Method of forming a semiconductor structure
By introducing a grinding stop layer and specific processes during the semiconductor structure formation process, the problems of large isolation layer area and inconsistent conductive plug height were solved, thereby improving the performance of the semiconductor structure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2022-09-28
- Publication Date
- 2026-06-19
AI Technical Summary
Existing technologies for forming semiconductor structures suffer from problems such as large isolation layer area, low integration density, and inconsistent conductive plug height, which affect the performance of the semiconductor structure.
During the semiconductor structure formation process, an additional grinding stop layer is formed, and through specific etching and planarization processes, the effective formation of the isolation structure and the high consistency of the conductive plugs are ensured.
By using a grinding stop layer, material consumption is reduced, ensuring the flatness of the semiconductor structure and the high consistency of the conductive plugs, thereby improving the overall performance of the semiconductor structure.
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Figure CN117832090B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Technology
[0002] As the integration density of semiconductor devices increases, the critical dimensions of transistors continue to shrink. However, with the rapid reduction in transistor size, the thickness of the first gate dielectric layer and the operating voltage cannot be changed accordingly, making it more difficult to suppress short-channel effects and increasing the channel leakage current of the transistor.
[0003] The gate of a FinFET (Fin Field-Effect Transistor) is structured in a forked 3D pattern resembling a fish fin. The channel of the FinFET protrudes from the substrate surface to form a first fin, and the gate covers the top and sidewalls of this first fin, thus creating an inversion layer on each side of the channel. This allows for control of the circuit's on / off state from both sides of the first fin. This design increases the gate's control over the channel region, effectively suppressing the short-channel effect of the transistor. However, the short-channel effect still exists in FinFETs.
[0004] Furthermore, to further reduce the impact of short-channel effects on semiconductor devices and lower channel leakage current, strained silicon technology has been introduced in the semiconductor technology field. The method of strained silicon technology includes: forming grooves in the first fins on both sides of the gate structure; and forming first source / drain doped regions in the grooves through an epitaxial growth process.
[0005] To prevent the first source-drain doped regions of different transistors from interconnecting, an isolation layer needs to be formed in the first fin. Simultaneously, to reduce the area of the isolation layer and increase the integration density of the formed semiconductor structure, the existing technology introduces SDB (Single Diffusion Break) technology.
[0006] However, existing methods still have many problems in the process of forming semiconductor structures. Summary of the Invention
[0007] The technical problem solved by this invention is to provide a method for forming a semiconductor structure to improve the performance of the final semiconductor structure.
[0008] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate having a first fin, the first fin including a plurality of device regions arranged along a first direction and at least one isolation region, the isolation region being located between adjacent device regions; forming a first dielectric layer and a first gate structure on the substrate, the first gate structure spanning the first fin and located on the isolation region, the first dielectric layer covering the sidewalls of the first gate structure; forming a mask structure on the first dielectric layer, the mask structure having a mask opening exposing the top surface of the first gate structure, the mask structure including a grinding stop layer and a grinding stop layer located on the grinding stop layer. A mask layer on the polishing stop layer; using the mask structure as a mask, a first etching process is used to remove a portion of the polishing stop layer, forming a blocking opening within the mask structure, the mask opening exposing the blocking opening; a blocking layer is formed within the blocking opening; after forming the blocking layer, using the mask structure as a mask, a second etching process is used to remove the first gate structure and a portion of the first fin covered by the first gate structure, forming an isolation opening within the first dielectric layer and the first fin; an initial isolation structure is formed within the isolation opening and on the mask structure; the initial isolation structure is planarized until the polishing stop layer is exposed, forming an isolation structure.
[0009] Optionally, the first etching process includes a wet etching process.
[0010] Optionally, the second etching process includes a wet etching process.
[0011] Optionally, the material of the grinding stop layer includes tantalum nitride.
[0012] Optionally, the material of the mask layer includes silicon oxide or silicon nitride.
[0013] Optionally, the material of the barrier layer includes silicon nitride.
[0014] Optionally, the process for forming the barrier layer includes atomic layer deposition.
[0015] Optionally, the process of forming the first dielectric layer and the first gate structure further includes: forming a plurality of second gate structures on the substrate, the second gate structures spanning the first fin, the second gate structures being located on the device region, and the first dielectric layer covering the sidewalls of the second gate structures.
[0016] Optionally, before forming the first gate structure and the second gate structure, the method further includes: forming a plurality of first source / drain doped layers in the first fin, wherein the first source / drain doped layers are located between adjacent first gate structures and second gate structures, or between adjacent second gate structures.
[0017] Optionally, before forming the first source / drain doped layer, the method further includes: forming a first dummy gate structure on the substrate, the first dummy gate structure spanning the first fin and located on the isolation region; and forming a plurality of second dummy gate structures on the substrate, the second dummy gate structures spanning the first fin and located on the device region.
[0018] Optionally, the method for forming the first source / drain doped layer includes: etching the first fin using the first pseudo-gate structure and the second pseudo-gate structure as masks to form a plurality of first source / drain openings in the first fin; and forming the first source / drain doped layer in the first source / drain openings.
[0019] Optionally, the method for forming the first gate structure and the plurality of second gate structures includes: removing the first dummy gate structure and forming a first gate opening in the first dielectric layer; forming the first gate structure in the first gate opening; removing the second dummy gate structure and forming a second gate opening in the first dielectric layer; and forming the second gate structure in the second gate opening.
[0020] Optionally, the material of the isolation structure includes silicon nitride.
[0021] Optionally, after forming the isolation structure, the method further includes: removing the polishing stop layer; forming a second dielectric layer on the first dielectric layer; and forming a conductive plug within the first dielectric layer and the second dielectric layer, the conductive plug being connected to the first source / drain doped layer.
[0022] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0023] In the method for forming the technical solution of the present invention, by additionally forming a polishing stop layer, when the initial isolation structure is planarized, the material of the polishing stop layer has a better polishing stop effect compared to the material of the initial isolation structure. The consumption of the polishing stop layer is less, and after the polishing stop layer is removed, the surface of the first dielectric layer is also relatively flat. When the second dielectric layer is subsequently formed on the first dielectric layer, the thickness of the second dielectric layer can be kept consistent throughout, and the height of the conductive plug connected to the first source / drain doped layer can be ensured to reach a preset height, thereby improving the performance of the finally formed semiconductor structure.
[0024] In addition, since the wet etching process used in the subsequent removal of the first gate structure has a relatively low selectivity for tungsten and titanium nitride etching, in order to avoid excessive damage to the polishing stop layer during the removal of the first gate structure, a first etching process is used to remove part of the polishing stop layer, forming a blocking opening in the mask structure, and forming a blocking layer in the blocking opening. This can protect the polishing stop layer and prevent excessive damage to the polishing stop layer during the subsequent removal of the first gate structure. Attached Figure Description
[0025] Figures 1 to 3 This is a schematic diagram of a semiconductor structure.
[0026] Figures 4 to 21 This is a schematic diagram of the steps in a semiconductor structure formation method according to an embodiment of the present invention. Detailed Implementation
[0027] As described in the background section, existing methods still have many problems in the process of forming semiconductor structures. These will be explained in detail below with reference to the accompanying drawings.
[0028] Figures 1 to 3 This is a schematic diagram of a semiconductor structure.
[0029] Please refer to Figure 1 The method includes: providing a substrate 100 having a first fin 101, the first fin 101 including a first device region A1, a second device region A2 and a first isolation region B1 arranged along a first direction X, the first isolation region B1 being located between adjacent first device regions A1 and second device regions A2; forming a first dielectric layer 102, a first gate structure 103 and a plurality of second gate structures 104 on the substrate 100, the first gate structure 103 spanning the first fin 101 and located on the first isolation region B1, the plurality of second gate structures 104 spanning the first fin 101 and respectively located on the first device region A1 and the second device region A2, the first dielectric layer 102 covering the sidewalls of the first gate structure 103 and the second gate structure 104; forming a mask structure 105 on the first dielectric layer 102, the mask structure 105 having a mask opening 106 exposing the top surface of the first gate structure 103.
[0030] Please refer to Figure 2 Using the mask structure 105 as a mask, a wet etching process is used to remove the first gate structure 103 and the portion of the first fin 101 covered by the first gate structure 103, forming an isolation opening 107 in the first dielectric layer 102 and the first fin 101.
[0031] Please refer to Figure 3 An initial isolation structure (not shown) is formed within the isolation opening 107 and on the mask structure 105; the initial isolation structure is planarized until the top surface of the mask structure 105 is exposed, thus forming an isolation structure 108.
[0032] In this embodiment, by forming the isolation structure 108, the problem of short circuits between the first source / drain doped layers (not shown) formed in adjacent first fins 101 can be effectively prevented, thus achieving an isolation effect.
[0033] In the above structure, the material of the mask structure 105 is the same material used to fill the cut trench during the gate cut-off process (not shown), and the material of the mask structure 105 is silicon oxide. The material of the initial isolation structure is silicon nitride. When the initial isolation structure is planarized using a chemical mechanical polishing (CMP) process, the mask structure 105 will serve as a polishing stop layer. However, since the polishing choices for silicon oxide and silicon nitride are relatively similar, a certain amount of silicon oxide will be consumed when it serves as the polishing stop layer for silicon nitride, resulting in a reduction in the remaining thickness of the mask structure 105. In subsequent process steps, a second dielectric layer (not shown) of the same material will be deposited on the mask structure 105, and a conductive plug (not shown) will be formed in the second dielectric layer, the mask structure 105, and the first dielectric layer 102. The conductive plug is connected to the first source / drain doped layer. Due to the reduced thickness of the mask structure 105, the overall thickness of the second dielectric layer and the mask structure 105 is smaller, resulting in a smaller height for the formed conductive plug. When the height of the conductive plug is small, it is easy to break the connection with the subsequently formed conductive layer, which in turn affects the performance of the final semiconductor structure.
[0034] Based on this, the present invention provides a method for forming a semiconductor structure. By additionally forming a polishing stop layer, when the initial isolation structure is planarized, the material of the polishing stop layer has a better polishing stopping effect compared to the material of the initial isolation structure. The consumption of the polishing stop layer is less, and after the polishing stop layer is removed, the surface of the first dielectric layer is also relatively flat. When the second dielectric layer is subsequently formed on the first dielectric layer, the thickness of the second dielectric layer can be kept consistent throughout, and the height of the conductive plug connected to the first source / drain doped layer can be ensured to reach a preset height, thereby improving the performance of the finally formed semiconductor structure.
[0035] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0036] Figures 4 to 21 This is a schematic diagram of the formation process of a semiconductor structure according to an embodiment of the present invention.
[0037] Please refer to Figure 4 and Figure 5 , Figure 5 yes Figure 4 Schematic diagram of the cross section along line AA. Figure 4 for Figure 5 A top view shows a substrate 200 having a first fin 201, the first fin 201 including a plurality of device regions arranged along a first direction X and at least one isolation region located between adjacent device regions.
[0038] In this embodiment, the plurality of device regions include: a first device region A1 and a second device region A2; at least one isolation region includes: a first isolation region B1, the first isolation region B1 being located between the first device region A1 and the second device region A2, and the first fin 101 extending from the first device region A1 to the second device region A2 and spanning the isolation region B1.
[0039] In this embodiment, the substrate 200 includes a first region I, a second region II, and a third region III arranged along a second direction Y. The second region II is located between the first region I and the third region III. The first direction X and the second direction Y are perpendicular. The substrate 200 also has a second fin 202, with the first fin 201 located on the first region I and the second fin 202 located on the third region III.
[0040] In this embodiment, the substrate 200 is made of silicon; in other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.
[0041] In this embodiment, the material of the first fin 201 is silicon; in other embodiments, the material of the first fin may also be germanium, silicon germanide, silicon carbide, gallium arsenide or indium gallium.
[0042] In this embodiment, the material of the second fin 202 is silicon; in other embodiments, the material of the first fin may also be germanium, silicon germanide, silicon carbide, gallium arsenide or indium gallium.
[0043] Please refer to Figure 6 , Figure 6 and Figure 5With the view orientation consistent, an isolation layer 203 is formed on the substrate 200, the isolation layer 203 covers part of the sidewall of the first fin 201, and the top surface of the isolation layer 203 is lower than the top surface of the first fin 201.
[0044] In this embodiment, the isolation layer 203 also covers part of the sidewall of the second fin 202, and the top surface of the isolation layer 203 is lower than the top surface of the second fin 202.
[0045] In this embodiment, the method for forming the isolation layer 203 includes: forming an initial isolation layer (not shown) on the substrate 200; etching away a portion of the initial isolation layer to form the isolation layer 203.
[0046] The insulating layer 203 is made of an insulating material, including silicon oxide or silicon oxynitride; in this embodiment, the insulating layer 203 is made of silicon oxide.
[0047] Please refer to Figure 7 , Figure 7 and Figure 4 With the view direction consistent, a first dummy gate structure 204 is formed on the substrate 200, the first dummy gate structure 204 spans the first fin 201, and the first dummy gate structure 204 is located on the isolation region; a plurality of second dummy gate structures 205 are formed on the substrate 200, the second dummy gate structures 205 span the first fin 201, and the second dummy gate structures 205 are located on the device region.
[0048] In this embodiment, the first pseudo-gate structure 204 and the second pseudo-gate structure 205 also span the second fin portion 202 respectively.
[0049] It should be noted that, in this embodiment, the first pseudo-gate structure 204 and the second pseudo-gate structure 205 are formed simultaneously using a global process. The first pseudo-gate structure 204 is located on the first isolation region B1, and a plurality of the second pseudo-gate structures 205 are respectively located on the first device region A1 and the second device region A2.
[0050] In this embodiment, both the first pseudo-gate structure 204 and the second pseudo-gate structure 205 include: a pseudo-gate first dielectric layer, and a pseudo-gate layer (not shown) located on the pseudo-gate first dielectric layer.
[0051] In this embodiment, the material of the first dielectric layer of the dummy gate is silicon oxide; in other embodiments, the material of the first dielectric layer of the dummy gate may also be silicon oxynitride.
[0052] In this embodiment, the pseudo-gate layer is made of polycrystalline silicon.
[0053] Please continue to refer to this. Figure 7 After forming the first pseudo-gate structure 204 and the second pseudo-gate structure 205, the method further includes forming sidewalls (not shown) on the sidewalls of the first pseudo-gate structure 204 and the second pseudo-gate structure 205, respectively.
[0054] In this embodiment, the sidewall is made of silicon nitride.
[0055] Please refer to Figure 8 The first fin 201 is etched using the first pseudo-gate structure 204 and the second pseudo-gate structure 205 as masks, and a plurality of first source / drain openings (not shown) are formed in the first fin 201; the first source / drain doped layer 206 is formed in the first source / drain openings.
[0056] In this embodiment, the process of forming the first source / drain doped layer 206 further includes: etching the second fin 202 using the first pseudo-gate structure 204 and the second pseudo-gate structure 205 as masks, forming a plurality of second source / drain openings (not shown) in the second fin 202; and forming the second source / drain doped layer 207 in the second source / drain openings.
[0057] In this embodiment, the method for forming the first source / drain doped layer 206 within the first source / drain opening includes: forming a first epitaxial layer (not shown) within the first source / drain opening using an epitaxial growth process; and incorporating first source / drain ions into the epitaxial layer using an in-situ doping process during the formation of the first epitaxial layer to form the first source / drain doped layer 206.
[0058] In this embodiment, the method for forming the second source / drain doped layer 207 within the second source / drain opening includes: forming a second epitaxial layer (not shown) within the first source / drain opening using an epitaxial growth process; and incorporating second source / drain ions into the epitaxial layer using an in-situ doping process during the formation of the second epitaxial layer to form the second source / drain doped layer 207.
[0059] In this embodiment, the first and second source / drain ions have opposite electrical types; the first source / drain ion is an N-type ion, and the second source / drain ion is a P-type ion. In other embodiments, the first source / drain ion may also be a P-type ion, and the second source / drain ion may be an N-type ion.
[0060] Please refer to Figure 9 After forming the first source / drain doped layer 206 and the second source / drain doped layer 207, a first dielectric layer 208 is formed on the substrate 200, the first dielectric layer 208 covering the sidewalls of the first dummy gate structure 204 and the second dummy gate structure 205.
[0061] In this embodiment, the method for forming the first dielectric layer 208 includes: forming an initial first dielectric layer (not shown) on the substrate 200, the initial first dielectric layer covering the first pseudo-gate structure 204 and the second pseudo-gate structure 205; performing planarization on the initial first dielectric layer until the top surfaces of the first pseudo-gate structure 204 and the second pseudo-gate structure 205 are exposed, thereby forming the first dielectric layer 208.
[0062] In this embodiment, the first dielectric layer 208 is made of silicon oxide; in other embodiments, the first dielectric layer may also be made of a low-K dielectric material (a low-K dielectric material refers to a dielectric material with a relative permittivity of less than 3.9) or an ultra-low-K dielectric material (an ultra-low-K dielectric material refers to a dielectric material with a relative permittivity of less than 2.5).
[0063] Please refer to Figure 10 Remove the first dummy gate structure 204 and form a first gate opening (not shown) in the first dielectric layer 208; form the first gate structure 209 in the first gate opening; remove the second dummy gate structure 205 and form a second gate opening (not shown) in the first dielectric layer 208; form the second gate structure 210 in the second gate opening.
[0064] In this embodiment, the first gate structure 209 and the second gate structure 210 are formed simultaneously using a global process. The first gate structure 209 is located on the first isolation region B1, and a plurality of the second gate structures 210 are respectively located on the first device region A1 and the second device region A2.
[0065] In this embodiment, both the first gate structure 209 and the second gate structure 210 include: a first gate dielectric layer, a work function layer located on the first gate dielectric layer, and a gate layer (not shown) located on the work function layer.
[0066] In this embodiment, the material of the first dielectric layer of the gate includes a high-k dielectric material.
[0067] The gate layer is made of a metal, including tungsten, aluminum, copper, titanium, silver, gold, lead, or nickel. In this embodiment, the gate layer is made of tungsten.
[0068] Please refer to Figures 11 to 13 , Figure 12 yes Figure 11 Schematic diagram of the cross section along line BB. Figure 13 yes Figure 11A cross-sectional view along the CC line shows that a polishing stop layer 211 and a first mask layer 212 are formed on the first dielectric layer 208. The polishing stop layer 211 and the first mask layer 212 have patterned openings 213 that expose a portion of the first dielectric layer 208, the first gate structure 209, and the second gate structure 210. The patterned openings 213 extend along the first direction X and are located on the second region II.
[0069] In this embodiment, the grinding stop layer 211 is made of titanium nitride.
[0070] In this embodiment, the first mask layer 212 is made of silicon oxide; in other embodiments, the first mask layer may also be made of silicon nitride.
[0071] Please refer to Figure 14 , Figure 14 and Figure 12 With the view direction consistent, using the grinding stop layer 211 and the first mask layer 212 as masks, the first dielectric layer 208, the first gate structure 209 and the second gate structure 210 are etched to form a cutting trench 214 on the second region II. The cutting trench 214 penetrates the first gate structure 209 and the second gate structure 210 along the first direction X.
[0072] In this embodiment, the cutting groove 214 is used to cut off the first gate structure 209 that spans the first fin 201 and the second fin 202, and the second gate structure 210 that spans the first fin 201 and the second fin 202, respectively.
[0073] It should be noted that during the etching of the first dielectric layer 208, the first gate structure 209, and the second gate structure 210, the first mask layer 212 will be consumed simultaneously.
[0074] Please refer to Figure 15 A partition material layer 215 is formed in the cutting groove 214 and on the grinding stop layer 211.
[0075] It should be noted that, in this embodiment, the barrier material layer 215 located on the polishing stop layer 211 is a mask layer, and the polishing stop layer 211 and the mask layer constitute a mask structure for subsequent removal of the first gate structure 209 located on the first region I.
[0076] Please refer to Figure 16 , Figure 16 and Figure 13With the view direction consistent, a mask opening 216 is formed in the mask structure to expose the top surface of the first gate structure 209; using the mask structure as a mask, a first etching process is used to remove part of the polishing stop layer 211, and a blocking opening 217 is formed in the mask structure, with the mask opening 216 exposing the blocking opening 217.
[0077] In this embodiment, since the wet etching process used in the subsequent removal of the first gate structure 209 has a relatively low selectivity for etching tungsten and titanium nitride, in order to avoid excessive damage to the polishing stop layer 211 during the removal of the first gate structure 209, a first etching process is used to remove part of the polishing stop layer 211, forming a blocking opening 217 in the mask structure. Subsequently, a blocking layer is formed in the blocking opening 217, which can play a blocking and protective role for the polishing stop layer 211, avoiding excessive damage to the polishing stop layer 211 during the subsequent removal of the first gate structure 209.
[0078] In this embodiment, the first etching process is a wet etching process.
[0079] Please refer to Figure 17 A barrier layer 218 is formed within the barrier opening 217.
[0080] In this embodiment, the barrier layer 218 is formed using an atomic layer deposition process.
[0081] In this embodiment, the barrier layer 218 is made of silicon nitride.
[0082] Please refer to Figure 18 After the barrier layer 218 is formed, the mask structure is used as a mask, and a second etching process is used to remove the first gate structure 209 and the portion of the first fin 201 covered by the first gate structure 209, forming an isolation opening 219 in the first dielectric layer 208 and the first fin 201.
[0083] In this embodiment, the second etching process is a wet etching process.
[0084] It should be noted that in this embodiment, the first mask layer 212 is also completely consumed during the process of removing the first gate structure 209 and part of the first fin 201.
[0085] Please refer to Figure 19 An initial isolation structure 220 is formed within the isolation opening 219 and on the mask structure.
[0086] In this embodiment, the initial isolation structure 220 is formed using a chemical vapor deposition process.
[0087] In this embodiment, the initial isolation structure 220 is made of silicon nitride.
[0088] Please refer to Figure 20 The initial isolation structure 220 is planarized until the grinding stop layer 211 is exposed, thus forming the isolation structure 221.
[0089] In this embodiment, the planarization process for the initial isolation structure 220 is performed using a chemical mechanical polishing process.
[0090] Please refer to Figure 21 After the isolation structure 221 is formed, the grinding stop layer 211 is removed; a second dielectric layer 222 is formed in the first dielectric layer 208; a conductive plug 223 is formed in the first dielectric layer 208 and the second dielectric layer 222, and the conductive plug 223 is connected to the first source / drain doped layer 206.
[0091] In this embodiment, by additionally forming a polishing stop layer 211, when the initial isolation structure 221 is planarized, the material of the polishing stop layer 211 has a better polishing stopping effect compared to the material of the initial isolation structure 221. The consumption of the polishing stop layer 211 is less, and after removing the polishing stop layer 211, the surface of the first dielectric layer 208 is also relatively flat. When the second dielectric layer 222 is formed on the first dielectric layer 208, the thickness of the second dielectric layer 222 can be kept consistent throughout, and the height of the conductive plug 223 connected to the first source / drain doped layer 206 can be ensured to reach a preset height, thereby improving the performance of the finally formed semiconductor structure.
[0092] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided having a first fin, the first fin including a plurality of device regions arranged along a first direction and at least one isolation region located between adjacent device regions; A first dielectric layer and a first gate structure are formed on the substrate. The first gate structure spans the first fin and is located on the isolation region. The first dielectric layer covers the sidewall of the first gate structure. A mask structure is formed on the first dielectric layer, the mask structure having a mask opening that exposes the top surface of the first gate structure, the mask structure including a polishing stop layer and a mask layer located on the polishing stop layer; Using the mask structure as a mask, a first etching process is used to remove part of the grinding stop layer, forming a blocking opening in the mask structure, and the mask opening exposes the blocking opening; A barrier layer is formed within the barrier opening; After the barrier layer is formed, the mask structure is used as a mask to remove the first gate structure and the portion of the first fin covered by the first gate structure using a second etching process, thereby forming an isolation opening in the first dielectric layer and the first fin. An initial isolation structure is formed within the isolation opening and on the mask structure; The initial isolation structure is planarized until the grinding stop layer is exposed, thus forming the isolation structure.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first etching process includes: wet etching process.
3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The second etching process includes: wet etching process.
4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the grinding stop layer includes tantalum nitride.
5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the mask layer includes silicon oxide or silicon nitride.
6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the barrier layer includes silicon nitride.
7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for forming the barrier layer includes atomic layer deposition.
8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the isolation structure includes silicon nitride.
9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process of forming the first dielectric layer and the first gate structure further includes: forming a plurality of second gate structures on the substrate, the second gate structures spanning the first fin, the second gate structures being located on the device region, and the first dielectric layer covering the sidewalls of the second gate structures.
10. The method for forming a semiconductor structure as described in claim 9, characterized in that, Before forming the first gate structure and the second gate structure, the method further includes: forming a plurality of first source / drain doped layers in the first fin, wherein the first source / drain doped layers are located between adjacent first gate structures and second gate structures, or between adjacent second gate structures.
11. The method for forming a semiconductor structure as described in claim 10, characterized in that, After forming the isolation structure, the method further includes: removing the polishing stop layer; forming a second dielectric layer on the first dielectric layer; and forming a conductive plug within the first dielectric layer and the second dielectric layer, wherein the conductive plug is connected to the first source / drain doped layer.
12. The method for forming a semiconductor structure as described in claim 10, characterized in that, Before forming the first source / drain doped layer, the method further includes: forming a first dummy gate structure on the substrate, the first dummy gate structure spanning the first fin and located on the isolation region; and forming a plurality of second dummy gate structures on the substrate, the second dummy gate structures spanning the first fin and located on the device region.
13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The method for forming the first source / drain doped layer includes: etching the first fin using the first pseudo-gate structure and the second pseudo-gate structure as masks, forming a plurality of first source / drain openings in the first fin; and forming the first source / drain doped layer in the first source / drain openings.
14. The method for forming a semiconductor structure as described in claim 12, characterized in that, The method for forming the first gate structure and a plurality of second gate structures includes: removing the first dummy gate structure and forming a first gate opening in the first dielectric layer; forming the first gate structure in the first gate opening; removing the second dummy gate structure and forming a second gate opening in the first dielectric layer; and forming the second gate structure in the second gate opening.