A GaN-based HEMT device and a manufacturing method thereof

Abstract

The application provides a GaN-based HEMT device and a manufacturing method thereof, which comprises the following steps: forming an epitaxial stack on a substrate, forming a gate, a drain and a source on the epitaxial stack, forming a shielding ring layer surrounding an active region of the device on the substrate, forming a first metal interconnection layer and a second metal interconnection layer to realize short connection between the substrate and the source, forming a passivation protection layer on the second metal interconnection layer, and forming a source and substrate shared pad, a drain pad and a gate pad based on the second metal interconnection layer and the passivation protection layer. In the GaN-based HEMT device and the manufacturing method thereof, the interconnection structure is formed in the chip to realize the short connection between the substrate and the source, and the substrate pad is not needed to be separately arranged to realize the grounding of the substrate, so that the proportion of the source pad and the drain pad to the chip area is improved, the current conduction capacity is improved, the parasitic parameters are further reduced, the current distribution uniformity is improved, the heat distribution of the device is improved, and the reliability of the device is improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to a GaN-based HEMT device and its fabrication method. Background Technology

[0002] Gallium nitride (GaN), a third-generation semiconductor material, has become an ideal candidate for high-voltage and high-frequency applications due to its wide bandgap and high electron saturation velocity. GaN semiconductors possess ultra-high critical breakdown electric fields, enabling higher power densities and making them highly suitable for fabricating high electron mobility transistors (HEMTs). They offer advantages such as high voltage tolerance, high frequency, high speed, and low on-resistance.

[0003] A schematic diagram of a traditional GaN-based HEMT device is shown below. Figure 1 As shown, a GaN layer 2' and an AlGaN layer 3' are formed on substrate 1' to form an AlGaN / GaN heterojunction. A source 4', a gate 5', and a drain 6' are formed on the AlGaN / GaN heterojunction, wherein the contact region between the source 4' and the drain 6' and the AlGaN / GaN heterojunction is an ohmic contact region 7'. To improve the device's electromagnetic interference immunity and ensure that the advantages of GaN-based devices at high frequencies and high power densities are effectively utilized in system applications, some patents propose a structure that adds a shielding ring around the active region of the device on the front side of the Si substrate, such as... Figure 2 As shown, the GaN-based device includes a substrate 1', a buffer layer 8', a HEMT layer 9', a source 4', a gate 5', a drain 6', and a shielding ring 10'. During packaging, the GaN-based device with the added shielding ring 10' needs to be soldered to the PCB board 11' using a flip-chip method to minimize parasitic inductance. A schematic diagram of the packaging scheme is shown below. Figure 3 As shown. The planar layout of the device pads (PADs) is as follows. Figure 4 As shown, the shielding ring 10' is disposed in the active region of the chip edge 17', the substrate pad 13' is connected to the shielding ring 10', and the source pad 14', gate pad 15', drain pad 16' and substrate pad 13' are isolated by an insulating layer. The substrate needs to be grounded separately through the substrate pad 13' and the substrate ground electrode 12', which occupies a large chip area, which is a disadvantage for GaN-based devices with high current density.

[0004] Therefore, how to provide a GaN-based HEMT device and its fabrication method to solve the problems in the prior art where GaN-based devices require separate substrate pads for grounding and occupy a large chip area has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a GaN-based HEMT device and its fabrication method, so as to solve the problems of GaN-based devices requiring separate substrate pads for grounding and occupying a large chip area.

[0006] To achieve the above and other related objectives, this invention provides a method for fabricating a GaN-based HEMT device, comprising the following steps:

[0007] A substrate is provided, an epitaxial stack is formed on the substrate, and a gate, a source, and a drain are formed on the epitaxial stack;

[0008] A first dielectric layer is formed above the epitaxial stack, the first dielectric layer covers the gate, the source and the drain, and a first conductive connection post is formed in the first dielectric layer, the first conductive connection post penetrates the first dielectric layer in the vertical direction and is connected to the top surface of the source.

[0009] An annular trench is formed, which penetrates the first dielectric layer and the epitaxial stack and extends to the surface of the substrate. The gate, the source, and the drain are all located in the region surrounded by the annular trench.

[0010] A first metal interconnect layer is formed above the first dielectric layer. The first metal interconnect layer is connected to the top surface of the first conductive connection pillar. A shielding ring layer is formed on the sidewall of the inner side of the annular trench. The top end of the shielding ring layer extends to the top surface of the first dielectric layer, and the bottom end of the shielding ring extends to the surface of the substrate.

[0011] A second dielectric layer is formed above the first dielectric layer and the substrate. The second dielectric layer covers the first metal interconnect layer and the shielding ring layer. A second conductive connection post and a third conductive connection post are formed in the second dielectric layer. The second conductive connection post penetrates the second dielectric layer in the vertical direction and connects to the first metal interconnect layer. The third conductive connection post penetrates the second dielectric layer in the vertical direction and connects to the shielding ring layer.

[0012] A second metal interconnect layer is formed above the second dielectric layer. The second metal interconnect layer includes an interconnect structure, which is connected to the top end of the second conductive connection post and the top end of the third conductive connection post.

[0013] A passivation protection layer is formed on the second metal interconnect layer, and a first opening, a second opening and a third opening are formed in the passivation protection layer. The portion of the second metal interconnect layer exposed by the first opening serves as a source pad shared with the substrate, the portion of the second metal interconnect layer exposed by the second opening serves as a drain pad, and the portion of the second metal interconnect layer exposed by the third opening serves as a gate pad.

[0014] Optionally, the shielding ring layer is stepped.

[0015] Optionally, the area of ​​the source pad shared with the substrate is larger than the area of ​​the gate pad, and the area of ​​the drain pad is larger than the area of ​​the gate pad.

[0016] Optionally, the top surface of the shielding ring layer is flush with the top surface of the first metal interconnect layer.

[0017] Optionally, the epitaxial stack includes a GaN channel layer and an AlGaN barrier layer located on the GaN channel layer.

[0018] The present invention also provides a GaN-based HEMT device, comprising:

[0019] Substrate;

[0020] An epitaxial stack is located on the substrate;

[0021] The gate, source, and drain are located on the epitaxial stack;

[0022] A first dielectric layer is located on the epitaxial stack. The first dielectric layer covers the gate, the source and the drain. A first conductive connection post is provided in the first dielectric layer. The first conductive connection post penetrates the first dielectric layer in the vertical direction and is connected to the top surface of the source.

[0023] A first metal interconnect layer is located on the first dielectric layer, and the first metal interconnect layer is connected to the top surface of the first conductive connection pillar.

[0024] A shielding ring layer is located outside the active region formed by the gate, the source, and the drain. The top end of the shielding ring layer extends to the top surface of the first dielectric layer, and the bottom end of the shielding ring layer extends to the surface of the substrate.

[0025] A second dielectric layer is located on the first dielectric layer and the substrate. The second dielectric layer covers the first metal interconnect layer and the shielding ring layer. The second dielectric layer is provided with a second conductive connection post and a third conductive connection post. The second conductive connection post penetrates the second dielectric layer in the vertical direction and connects to the first metal interconnect layer. The third conductive connection post penetrates the second dielectric layer in the vertical direction and connects to the shielding ring layer.

[0026] A second metal interconnect layer is located on the second dielectric layer. The second metal interconnect layer includes an interconnect structure, which is connected to the top end of the second conductive connection post and the top end of the third conductive connection post.

[0027] A passivation protection layer is located on the second metal interconnect layer. The passivation protection layer has a first opening, a second opening and a third opening. The portion of the second metal interconnect layer exposed by the first opening serves as a source pad shared with the substrate. The portion of the second metal interconnect layer exposed by the second opening serves as a drain pad. The portion of the second metal interconnect layer exposed by the third opening serves as a gate pad.

[0028] Optionally, the shielding ring layer is stepped.

[0029] Optionally, the area of ​​the source pad shared with the substrate is larger than the area of ​​the gate pad, and the area of ​​the drain pad is larger than the area of ​​the gate pad.

[0030] Optionally, the top surface of the shielding ring layer is flush with the top surface of the first metal interconnect layer.

[0031] Optionally, the epitaxial stack includes a GaN channel layer and an AlGaN barrier layer located on the GaN channel layer.

[0032] As described above, in the GaN-based HEMT device and fabrication method of the present invention, the substrate and the device source are short-circuited by forming an interconnect structure inside the chip, eliminating the need for separate substrate pads to ground the silicon substrate, thereby increasing the proportion of the source and drain pads to the chip area. Due to the increased proportion of the source and drain pad area, not only can the current conduction capability be improved and parasitic parameters be further reduced, but the current distribution uniformity can also be improved, which is beneficial to improving the thermal distribution of the device and improving the device reliability. Attached Figure Description

[0033] Figure 1 The diagram shows the structure of a traditional GaN-based HEMT device.

[0034] Figure 2 The diagram shows a structural schematic of a GaN-based HEMT device with a shielding ring.

[0035] Figure 3 The diagram shows a package schematic of a GaN-based HEMT device with a shielding ring.

[0036] Figure 4 The diagram shows a planar layout of the pads for a GaN-based HEMT device with a shielding ring.

[0037] Figure 5The diagram shows a process flow chart of the fabrication method of the GaN-based HEMT device of the present invention.

[0038] Figure 6 The diagram shows a method for fabricating a GaN-based HEMT device according to the present invention, in which an epitaxial stack is formed on a substrate, and a gate, source, and drain are formed on the epitaxial stack.

[0039] Figure 7 The diagram shows a first dielectric layer formed on an epitaxial stack and a first conductive connection pillar formed in the first dielectric layer in the fabrication method of the GaN-based HEMT device of the present invention.

[0040] Figure 8 The diagram shows a method for fabricating a GaN-based HEMT device according to the present invention, illustrating the formation of annular trenches.

[0041] Figure 9 The diagram shown illustrates the formation of the first metal interconnect layer and the shielding ring layer in the fabrication method of the GaN-based HEMT device of the present invention.

[0042] Figure 10 The diagram shows a method for fabricating a GaN-based HEMT device according to the present invention, in which a second dielectric layer is formed, and a second conductive connection pillar and a third conductive connection pillar are formed in the second dielectric layer.

[0043] Figure 11 The diagram shown illustrates the formation of a second metal interconnect layer on a second dielectric layer in the fabrication method of the GaN-based HEMT device of the present invention.

[0044] Figure 12 The diagram shows a planar layout of the pads for the GaN-based HEMT device of the present invention.

[0045] Component designation explanation

[0046] 1' Substrate

[0047] 2' GaN layer

[0048] 3' AlGaN layer

[0049] 4' source pole

[0050] 5' gate

[0051] 6' Drain

[0052] 7' Ohmic contact area

[0053] 8' Buffer Layer

[0054] 9' HEMT layer

[0055] 10' Shielding ring

[0056] 11' PCB board

[0057] 12' Substrate grounding electrode

[0058] 13' Substrate pad

[0059] 14' source pad

[0060] 15' gate pad

[0061] 16' Drain Pad

[0062] 17' Chip Edge

[0063] 1 Substrate

[0064] 2. Epitaxial stack

[0065] 200 buffer layers

[0066] 201 HEMT layer

[0067] 3 gate

[0068] 4 Source

[0069] 5 Drain

[0070] 6 Insulation layer

[0071] 7 First dielectric layer

[0072] 8 First conductive connection post

[0073] 9. Annular groove

[0074] 10 Shielding ring layers

[0075] 11 First metal interconnect layer

[0076] 12 Second dielectric layer

[0077] 13 Second conductive connection post

[0078] 14 Third conductive connection post

[0079] 15 Second metal interconnect layer

[0080] 150 interconnect structure

[0081] 16. Source and substrate share the same pad.

[0082] 17 Drain pad

[0083] 18 Gate pads

[0084] 19 Chip Edge

[0085] Steps S1 to S7 Detailed Implementation

[0086] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0087] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0088] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0089] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0090] This embodiment provides a method for fabricating a GaN-based HEMT device. Please refer to [link to relevant documentation]. Figure 5 The diagram shows the process flow of this method, which includes the following steps:

[0091] S1: A substrate is provided, an epitaxial stack is formed on the substrate, and a gate, a source and a drain are formed on the epitaxial stack;

[0092] S2: A first dielectric layer is formed above the epitaxial stack, the first dielectric layer covers the gate, the source and the drain, and a first conductive connection post is formed in the first dielectric layer, the first conductive connection post penetrates the first dielectric layer in the vertical direction and is connected to the top surface of the source.

[0093] S3: Form an annular trench that penetrates the first dielectric layer and the epitaxial stack and extends to the surface of the substrate. The gate, the source, and the drain are all located in the region surrounded by the annular trench.

[0094] S4: A first metal interconnect layer is formed above the first dielectric layer. The first metal interconnect layer is connected to the top surface of the first conductive connection pillar, and a shielding ring layer is formed on the sidewall of the inner side of the annular trench. The top end of the shielding ring layer extends to the top surface of the first dielectric layer, and the bottom end of the shielding ring extends to the surface of the substrate.

[0095] S5: A second dielectric layer is formed above the first dielectric layer and the substrate. The second dielectric layer covers the first metal interconnect layer and the shielding ring layer. A second conductive connection post and a third conductive connection post are formed in the second dielectric layer. The second conductive connection post penetrates the second dielectric layer in the vertical direction and connects to the first metal interconnect layer. The third conductive connection post penetrates the second dielectric layer in the vertical direction and connects to the shielding ring layer.

[0096] S6: A second metal interconnect layer is formed above the second dielectric layer. The second metal interconnect layer includes an interconnect structure, which is connected to the top end of the second conductive connection post and the top end of the third conductive connection post.

[0097] S7: A passivation protection layer is formed on the second metal interconnect layer, and a first opening, a second opening and a third opening are formed in the passivation protection layer. The portion of the second metal interconnect layer exposed by the first opening serves as a source pad shared with the substrate, the portion of the second metal interconnect layer exposed by the second opening serves as a drain pad, and the portion of the second metal interconnect layer exposed by the third opening serves as a gate pad.

[0098] First, please refer to Figure 6 Step S1: Provide a substrate 1, form an epitaxial stack 2 on the substrate, and form a gate 3, a source 4 and a drain 5 on the epitaxial stack 2.

[0099] As an example, the substrate 1 can be any suitable semiconductor material; in this embodiment, the substrate 1 is a silicon wafer.

[0100] As an example, the epitaxial stack 2 includes a buffer layer 200 and an HEMT layer 201 located above the buffer layer 200. The HEMT layer 201 includes a GaN channel layer and an AlGaN barrier layer located above the GaN channel layer.

[0101] As an example, the method for forming the epitaxial stack 2 includes physical vapor deposition, chemical vapor deposition or other suitable methods.

[0102] As an example, a method for forming a gate 3, a source 4, and a drain 5 on the epitaxial stack 2 includes:

[0103] (i) A gate metal layer is formed on the epitaxial stack 2, and then a mask layer is formed and patterned above the gate metal layer. Based on the patterned mask layer, a preset area of ​​the gate metal layer is etched away to form the gate 3.

[0104] As an example, the material of the gate metal layer can be any suitable gate material, but in this embodiment, TiN is preferred.

[0105] (ii) An insulating layer 6 is formed on the epitaxial stack 2, and then the insulating layer 6 is etched at a preset position to a preset depth to form a source groove and a drain groove.

[0106] As an example, the material of the insulating layer 6 includes silicon nitride, silicon dioxide, aluminum oxide or other suitable insulating materials, and silicon nitride is preferred in this embodiment.

[0107] (iii) A source-drain metal layer is formed above the insulating layer 6, the source-drain metal layer covers the insulating layer 6, the source groove and the drain groove, and then a mask layer is formed and patterned above the source-drain metal layer. Based on the patterned mask layer, the preset position of the source-drain metal layer is etched away, the source 4 is formed at the source groove, and the drain 5 is formed at the drain groove. The gate 3, the source 4 and the drain 5 are isolated from each other by the insulating layer 6.

[0108] As an example, the source / drain metal layer can be a single-layer structure or a multi-layer composite stacked structure. In this embodiment, the source / drain metal layer is a stacked structure of Ti layer, Al layer, Ti layer and TiN layer.

[0109] As an example, after forming the source 4 and the drain 5, a rapid annealing step is also included, through which the source ohmic contact and the drain ohmic contact are formed.

[0110] In some other embodiments, the fabrication order of the source, drain, and gate can be selected according to the actual situation. For example, the source and drain can be fabricated first, and then the gate can be fabricated; or the source, drain, and gate can be fabricated simultaneously, without being limited to this embodiment.

[0111] Next, please refer to Figure 7 Step S2 is executed: a first dielectric layer 7 is formed above the epitaxial stack 2. The first dielectric layer 7 covers the gate 3, the source 4 and the drain 5, and a first conductive connection post 8 is formed in the first dielectric layer 7. The first conductive connection post 8 penetrates the first dielectric layer 7 in the vertical direction and is connected to the top surface of the source 4.

[0112] As an example, the first dielectric layer 7 is prepared using existing deposition processes, including but not limited to silicon oxide.

[0113] As an example, a method for forming the first conductive connection post 8 includes forming a through hole in the first dielectric layer 7 by etching, laser drilling or other suitable methods, and then filling the through hole with conductive metal to form the first conductive connection post 8.

[0114] Next, please refer to Figure 8 Step S3 is executed: an annular trench 9 is formed, the annular trench 9 penetrates the first dielectric layer 7 and the epitaxial stack 2 and extends to the surface of the substrate 1, the gate 3, the source 4 and the drain 5 are all located in the area surrounded by the annular trench 9.

[0115] As an example, in actual manufacturing, semiconductor devices are typically composed of multiple semiconductor cells. Each semiconductor cell includes a source 4, a drain 5, a gate 3 located between the source 4 and the drain 5, and a corresponding active region. In this embodiment, when an array of multiple semiconductor cells forms a semiconductor device, adjacent semiconductor cells share the source 4 or the drain 5.

[0116] As an example, dry etching or wet etching is used to etch away the first dielectric layer 7 and the predetermined position of the epitaxial stack 2, and also includes etching away the predetermined position of the insulating layer 6 to form the annular trench 9.

[0117] As an example, the annular groove 9 is stepped, for use in the subsequent formation of a stepped shielding ring layer 10 (see below). Figure 9 ).

[0118] Next, please refer to Figure 9 Step S4: A first metal interconnect layer 11 is formed above the first dielectric layer 7. The first metal interconnect layer 11 is connected to the top surface of the first conductive connection post 8, and a shielding ring layer 10 is formed on the sidewall of the inner side of the annular trench 9. The top end of the shielding ring layer 10 extends to the top surface of the first dielectric layer 7, and the bottom end of the shielding ring layer 10 extends to the surface of the substrate 1.

[0119] As an example, the material of the first metal interconnect layer 11 includes copper, aluminum, nickel, gold, silver, titanium or other suitable conductive materials, and is formed by deposition, electroplating or other suitable processes. Since this embodiment sets up multiple semiconductor cells, the first metal interconnect layer 11 is connected to multiple sources 4 to form source bus.

[0120] As an example, the shielding ring layer 10 may be made of copper, aluminum, nickel, gold, silver, titanium or other suitable conductive materials, and may be formed by deposition, electroplating or other suitable processes.

[0121] As an example, the shielding ring layer 10 is arranged in a stepped shape above the substrate 1, the epitaxial stack 2 and the first dielectric layer 7, which is beneficial to forming an ohmic contact with the substrate 1 and reducing the contact resistance.

[0122] As an example, the top surface of the shielding ring layer 10 is flush with the top surface of the first metal interconnect layer 11.

[0123] As an example, the shielding ring 10 is disposed in the active region of the GaN-based HEMT device, which plays an electromagnetic shielding role, improves the device's ability to resist electromagnetic interference, and ensures that the advantages of high frequency and high power density of GaN-based HEMT device can be effectively utilized in system applications.

[0124] Next, please refer to Figure 10 Step S5: A second dielectric layer 12 is formed above the first dielectric layer 7 and the substrate 1. The second dielectric layer 12 covers the first metal interconnect layer 11 and the shielding ring layer 10. A second conductive connection post 13 and a third conductive connection post 14 are formed in the second dielectric layer 12. The second conductive connection post 13 penetrates the second dielectric layer 12 in the vertical direction and is connected to the first metal interconnect layer 11. The third conductive connection post 14 penetrates the second dielectric layer 12 in the vertical direction and is connected to the shielding ring layer 10.

[0125] As an example, the second dielectric layer 12 is prepared using existing deposition processes, including but not limited to silicon oxide.

[0126] As an example, a method for forming the second conductive connection post 13 and the third conductive connection post 14 includes forming a through-hole in the second dielectric layer 12 by etching, laser drilling or other suitable methods, and then filling the through-hole with conductive metal to form the second conductive connection post 13 and the third conductive connection post 14.

[0127] Next, please refer to Figure 11 Step S6: A second metal interconnect layer 15 is formed above the second dielectric layer 12. The second metal interconnect layer 15 includes an interconnect structure 150, which is connected to the top end of the second conductive connection post 13 and the top end of the third conductive connection post 14.

[0128] As an example, the second metal interconnect layer 15 may be made of copper, aluminum, nickel, gold, silver, titanium or other suitable conductive materials, and may be formed by deposition, electroplating or other suitable processes.

[0129] As an example, after the second metal interconnect layer 15 is formed, the substrate 1 is electrically connected to the source 4 through the shielding ring layer 10, the third conductive connection post 14, the interconnect structure 150, the second conductive connection post 13, the first metal interconnect layer 11 and the first conductive connection post 8. That is, the substrate is directly connected to the source through the internal interconnection of the device, so there is no need to set up a separate substrate pad to achieve substrate grounding, which reduces the difficulty of the packaging process.

[0130] Next, step S7 is performed: a passivation protection layer is formed on the second metal interconnect layer 15, and a first opening, a second opening and a third opening are formed in the passivation protection layer. The portion of the second metal interconnect layer 15 exposed by the first opening serves as a source pad 16 shared with the substrate, the portion of the second metal interconnect layer 15 exposed by the second opening serves as a drain pad 17, and the portion of the second metal interconnect layer 15 exposed by the third opening serves as a gate pad 18.

[0131] As an example, the second metal interconnect layer 15 includes at least three parts, wherein the first part is the interconnect structure 150, and the substrate and source common pad 16 is formed based on the interconnect structure 150; the second part is used to form the drain pad 17; and the third part is used to form the gate pad 18. That is, the portion of the interconnect structure 150 exposed by the first opening serves as the substrate and source common pad 16; the second portion of the second metal interconnect layer 15 exposed by the second opening serves as the drain pad 17, which is electrically connected to the drain 5; and the third portion of the second metal interconnect layer 15 exposed by the third opening serves as the gate pad 18, which is electrically connected to the gate 3.

[0132] As an example, ideally, the opening of the passivation protection layer could be consistent with the second metal interconnect layer 15, but due to limitations in the precision and reliability of the packaging process and factors such as the soldering method, the pad size is smaller than the second metal interconnect layer 15.

[0133] For example, please refer to Figure 12 The diagram shows a planar layout of the substrate and source shared pad 16, drain pad 17, and gate pad 18 in this embodiment. The shielding ring layer 10 is disposed around the active region of the chip edge 19. The substrate and source shared pad 16, the drain pad 17, and the gate pad 18 are located within the active region. Since the substrate 1 is connected to the source 4 inside the device, it is not necessary to separately ground the substrate pad.

[0134] As an example, compared to Figure 4In existing technologies, substrate pads are set separately, and the source and drain pad areas account for about half of the total pad area. This invention is equivalent to "allocating" the area of ​​the substrate pads to the source and drain pads, so that the area of ​​the source and substrate shared pad 16 is larger than the area of ​​the gate pad 18, and the area of ​​the drain pad 17 is larger than the area of ​​the gate pad 18. The source and drain pad areas can reach three-quarters or more of the total pad area, increasing the proportion of the source and drain pads to the chip area, improving the current conduction capability of the source and drain pads, further reducing parasitic parameters introduced by packaging; and improving the uniformity of current distribution, which is beneficial to improving the thermal distribution of the device and improving the device reliability.

[0135] Thus, a GaN-based HEMT device has been fabricated. Please refer to [link / reference]. Figures 11 to 12The system includes a substrate 1, an epitaxial stack 2, a gate 3, a source 4, a drain 5, a first dielectric layer 7, a first metal interconnect layer 11, a shielding ring layer 10, a second dielectric layer 12, a second metal interconnect layer 15, and a passivation protection layer. The epitaxial stack 2 is located on the substrate 1; the gate 3, the source 4, and the drain 5 are located on the epitaxial stack 2; the first dielectric layer 7 is located on the epitaxial stack 2, covering the gate 3, the source 4, and the drain 5, and a first conductive connection post 8 is provided in the first dielectric layer 7. The first conductive connection post 8 penetrates the first dielectric layer 7 in the vertical direction and is connected to the top surface of the source electrode 4; the first metal interconnect layer 11 is located on the first dielectric layer 7 and is connected to the top surface of the first conductive connection post 8; the shielding ring layer 10 is located outside the active region formed by the gate electrode 3, the source electrode 4, and the drain electrode 5, with the top end of the shielding ring layer 10 extending to the top surface of the first dielectric layer 7 and the bottom end of the shielding ring layer 10 extending to the surface of the substrate 1; the second dielectric layer 12 is located on the first dielectric layer 7 and the substrate 1. The second dielectric layer 7 covers the first metal interconnect layer 11 and the shielding ring layer 10. The second dielectric layer 12 has a second conductive connection post 13 and a third conductive connection post 14. The second conductive connection post 13 penetrates the second dielectric layer 12 vertically and connects to the first metal interconnect layer 11. The third conductive connection post 14 penetrates the second dielectric layer 12 vertically and connects to the shielding ring layer 10. The second metal interconnect layer 15 is located on the second dielectric layer 12 and includes an interconnect structure 150. The interconnect structure 150 is connected to the top ends of the second conductive connection post 13 and the third conductive connection post 14. The passivation protection layer is located on the second metal interconnect layer 15 and has a first opening, a second opening, and a third opening. The portion of the second metal interconnect layer 15 exposed by the first opening serves as a source pad 16 shared with the substrate. The portion of the second metal interconnect layer 15 exposed by the second opening serves as a drain pad 17. The portion of the second metal interconnect layer 15 exposed by the third opening serves as a gate pad 18.

[0136] As an example, the substrate 1 can be any suitable semiconductor material; in this embodiment, the substrate 1 is a silicon wafer.

[0137] In the example, the epitaxial stack 2 includes a buffer layer 200 and a HEMT layer 201 located above the buffer layer 200. The HEMT layer 201 includes a GaN channel layer and an AlGaN barrier layer located above the GaN channel layer.

[0138] As an example, an insulating layer 6 is also included, which is used to isolate the gate 3, the drain 4 and the source 5.

[0139] As an example, a semiconductor device is composed of multiple semiconductor cells. Each semiconductor cell includes a source 4, a drain 5, a gate 3 located between the source 4 and the drain 5, and a corresponding active region. In this embodiment, when an array of multiple semiconductor cells forms a semiconductor device, adjacent semiconductor cells share the source 4 or share the drain 5.

[0140] As an example, the shielding ring layer 10 is arranged in a stepped shape above the substrate 1, the epitaxial stack 2 and the first dielectric layer 7, which is beneficial to forming an ohmic contact with the substrate 1 and reducing the contact resistance.

[0141] As an example, the top surface of the shielding ring layer 10 is flush with the top surface of the first metal interconnect layer 11.

[0142] As an example, the shielding ring 10 is disposed in the active region of the GaN-based HEMT device, which plays an electromagnetic shielding role, improves the device's ability to resist electromagnetic interference, and ensures that the advantages of high frequency and high power density of GaN-based HEMT device can be effectively utilized in system applications.

[0143] As an example, the substrate 1 is electrically connected to the source 4 through the shielding ring layer 10, the third conductive connection post 14, the interconnect structure 150, the second conductive connection post 13, the first metal interconnect layer 11 and the first conductive connection post 8. That is, the substrate is directly connected to the source through the internal interconnection of the device, without the need to set up a separate substrate pad to achieve substrate grounding, thus reducing the difficulty of the packaging process.

[0144] As an example, the second metal interconnect layer includes at least three parts, wherein the first part is the interconnect structure 150, and the substrate and source shared pad 16 is set based on the interconnect structure 150; the second part is used to set the drain pad 17; and the third part is used to set the gate pad 18. That is, the part of the interconnect structure 150 exposed by the first opening serves as the substrate and source shared pad 16; the second part of the second metal interconnect layer 15 exposed by the second opening serves as the drain pad 17, which is electrically connected to the drain 5; and the third part of the second metal interconnect layer 15 exposed by the third opening serves as the gate pad 18, which is electrically connected to the gate 3.

[0145] As an example, the shielding ring layer 10 is disposed around the active region of the chip edge 19. The substrate and source common pad 16, the drain pad 17 and the gate pad 18 are located in the active region. The area of ​​the source and substrate common pad 16 is larger than the area of ​​the gate pad 18, and the area of ​​the drain pad 17 is larger than the area of ​​the gate pad 18.

[0146] As an example, compared to Figure 4 In existing technologies, substrate pads are set separately, and the source and drain pad areas account for about half of the total pad area. This invention is equivalent to "allocating" the area of ​​the substrate pads to the source and drain pads, so that the source and drain pad areas can reach three-quarters or more of the total pad area. This increases the proportion of the source and drain pads to the chip area, improves the current conduction capability of the source and drain pads, and can further reduce parasitic parameters introduced by packaging. In addition, it can improve the uniformity of current distribution, which is beneficial to improve the thermal distribution of the device and improve the reliability of the device.

[0147] In summary, the GaN-based HEMT device and fabrication method of this invention achieves short-circuiting between the substrate and the device source by forming an interconnect structure inside the chip, eliminating the need for separate substrate pads for substrate grounding. This increases the proportion of the source and drain pads to the chip area, which not only improves current conduction capability and further reduces parasitic parameters, but also improves current distribution uniformity, thus improving device thermal distribution and reliability. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0148] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a GaN-based HEMT device, characterized in that, Includes the following steps: A substrate is provided, an epitaxial stack is formed on the substrate, and a gate, a source, and a drain are formed on the epitaxial stack; A first dielectric layer is formed above the epitaxial stack, the first dielectric layer covers the gate, the source and the drain, and a first conductive connection post is formed in the first dielectric layer, the first conductive connection post penetrates the first dielectric layer in the vertical direction and is connected to the top surface of the source. An annular trench is formed, which penetrates the first dielectric layer and the epitaxial stack and extends to the surface of the substrate. The gate, the source, and the drain are all located in the region surrounded by the annular trench. A first metal interconnect layer is formed above the first dielectric layer. The first metal interconnect layer is connected to the top surface of the first conductive connection pillar. A shielding ring layer is formed on the sidewall of the inner side of the annular trench. The top end of the shielding ring layer extends to the top surface of the first dielectric layer, and the bottom end of the shielding ring extends to the surface of the substrate. A second dielectric layer is formed above the first dielectric layer and the substrate. The second dielectric layer covers the first metal interconnect layer and the shielding ring layer. A second conductive connection post and a third conductive connection post are formed in the second dielectric layer. The second conductive connection post penetrates the second dielectric layer in the vertical direction and connects to the first metal interconnect layer. The third conductive connection post penetrates the second dielectric layer in the vertical direction and connects to the shielding ring layer. A second metal interconnect layer is formed above the second dielectric layer. The second metal interconnect layer includes an interconnect structure, which is connected to the top end of the second conductive connection post and the top end of the third conductive connection post. A passivation protection layer is formed on the second metal interconnect layer, and a first opening, a second opening and a third opening are formed in the passivation protection layer. The portion of the second metal interconnect layer exposed by the first opening serves as a source pad shared with the substrate, the portion of the second metal interconnect layer exposed by the second opening serves as a drain pad, and the portion of the second metal interconnect layer exposed by the third opening serves as a gate pad.

2. The method for fabricating a GaN-based HEMT device according to claim 1, characterized in that: The shielding ring layer is stepped.

3. The method for fabricating a GaN-based HEMT device according to claim 1, characterized in that: The area of ​​the source pad shared with the substrate is larger than the area of ​​the gate pad, and the area of ​​the drain pad is larger than the area of ​​the gate pad.

4. The method for fabricating a GaN-based HEMT device according to claim 1, characterized in that: The top surface of the shielding ring layer is flush with the top surface of the first metal interconnect layer.

5. The method for fabricating a GaN-based HEMT device according to claim 1, characterized in that: The epitaxial stack includes a GaN channel layer and an AlGaN barrier layer located on the GaN channel layer.

6. A GaN-based HEMT device, characterized in that, include: Substrate; An epitaxial stack is located on the substrate; The gate, source, and drain are located on the epitaxial stack; A first dielectric layer is located on the epitaxial stack. The first dielectric layer covers the gate, the source and the drain. A first conductive connection post is provided in the first dielectric layer. The first conductive connection post penetrates the first dielectric layer in the vertical direction and is connected to the top surface of the source. A first metal interconnect layer is located on the first dielectric layer, and the first metal interconnect layer is connected to the top surface of the first conductive connection pillar. A shielding ring layer is located outside the active region formed by the gate, the source, and the drain. The top end of the shielding ring layer extends to the top surface of the first dielectric layer, and the bottom end of the shielding ring layer extends to the surface of the substrate. A second dielectric layer is located on the first dielectric layer and the substrate. The second dielectric layer covers the first metal interconnect layer and the shielding ring layer. The second dielectric layer is provided with a second conductive connection post and a third conductive connection post. The second conductive connection post penetrates the second dielectric layer in the vertical direction and connects to the first metal interconnect layer. The third conductive connection post penetrates the second dielectric layer in the vertical direction and connects to the shielding ring layer. A second metal interconnect layer is located on the second dielectric layer. The second metal interconnect layer includes an interconnect structure, which is connected to the top end of the second conductive connection post and the top end of the third conductive connection post. A passivation protection layer is located on the second metal interconnect layer. The passivation protection layer has a first opening, a second opening and a third opening. The portion of the second metal interconnect layer exposed by the first opening serves as a source pad shared with the substrate. The portion of the second metal interconnect layer exposed by the second opening serves as a drain pad. The portion of the second metal interconnect layer exposed by the third opening serves as a gate pad.

7. The GaN-based HEMT device according to claim 6, characterized in that: The shielding ring layer is stepped.

8. The GaN-based HEMT device according to claim 6, characterized in that: The area of ​​the source pad shared with the substrate is larger than the area of ​​the gate pad, and the area of ​​the drain pad is larger than the area of ​​the gate pad.

9. The GaN-based HEMT device according to claim 6, characterized in that: The top surface of the shielding ring layer is flush with the top surface of the first metal interconnect layer.

10. The GaN-based HEMT device according to claim 6, characterized in that: The epitaxial stack includes a GaN channel layer and an AlGaN barrier layer located on the GaN channel layer.

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