SiC MOSFET structure and fabrication method with current-conducting layer in JFET region

Abstract

The application discloses a SiC MOSFET structure with a JFET region provided with a flow guide layer and a preparation method thereof. The structure comprises the following steps: an N-drift region layer is arranged on the upper surface of an N+ substrate layer; two P-type base regions are arranged in the N-drift region layer at both ends of the device; a JFET region is formed between the two P-type base regions; two P+ body regions are arranged in the P-type base regions at both ends of the device; two N+ source regions are arranged in the P-type base regions and adjacent to the P+ body regions; two channel regions are arranged in the P-type base regions and adjacent to the N+ source regions; two flow guide layers are arranged in the JFET region and adjacent to the channel regions; a flow resistance layer is arranged in the JFET region between the two flow guide layers; two source electrodes are arranged on the P+ body regions and the N+ source regions at both ends of the device; a gate oxide layer is arranged on the two N+ source regions, the two channel regions, the two flow guide layers, the flow resistance layer and the JFET region; a gate electrode is arranged on the gate oxide layer; and a drain electrode is arranged on the lower surface of the N+ substrate layer. The application prolongs the short-circuit resistance time of the device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a SiC MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) structure and fabrication method with a current-conducting layer in the JFET (Field Effect Transistor) region. Background Technology

[0002] In the field of power electronics, SiC MOSFET power devices have developed rapidly and are widely used in new energy vehicles, electric vehicle charging stations, wind power generation, high-speed rail, and other fields. In these applications, the reliability challenges faced by SiC MOSFETs are even more pronounced, especially in terms of short-circuit reliability, as such failures occur very quickly but are extremely destructive. Firstly, SiC has a wider bandgap, allowing for higher doping concentrations in the drift region compared to silicon-based devices at the same voltage rating. Secondly, SiC chips are smaller and have higher current handling capabilities. Experimental tests show that the short-circuit withstand capability of Si MOSFETs can reach over 10 microseconds, while the short-circuit withstand capability of SiC MOSFETs is significantly lower due to gate oxide reliability and excessively high current density.

[0003] Currently, short-circuit testing is a crucial experiment for characterizing the reliability of SiC MOSFET devices. Power devices sometimes operate under short-circuit fault conditions. Typically, once a short circuit is detected, the external circuitry triggers a protection mechanism to shut down the circuit promptly. However, within the response time of the protection circuit, the device must be able to withstand a short circuit for a certain period. Therefore, improving the short-circuit withstand capability of SiC MOSFETs from a structural perspective has become a key issue.

[0004] In existing planar SiC MOSFET structures, the JFET region is uniformly N-type doped. When a short-circuit fault occurs, the short-circuit current is concentrated in the JFET region, and the junction temperature is also concentrated in the JFET region. This causes a positive feedback of short-circuit current and temperature rise, which leads to device failure, such as metal electrode melting and device thermal failure.

[0005] It is evident that the JFET region, serving as the current path during SiC MOSFET operation, is a key factor in addressing the issues of excessive short-circuit saturation density and concentrated junction temperature when the device is short-circuited. Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this invention provides a SiC MOSFET structure with a current-conducting layer in the JFET region and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0007] In a first aspect, embodiments of the present invention provide a SiC MOSFET structure with a current-conducting layer in the JFET region, the SiC MOSFET structure comprising:

[0008] N+ substrate layer;

[0009] The N-drift region layer is located on the upper surface of the N+ substrate layer;

[0010] Two P-type base regions are located on the N-drift region layers at both ends of the device; a JFET region is formed between the two P-type base regions;

[0011] Two P+ body regions are located on the P-type base regions at both ends of the device, respectively;

[0012] Two N+ source regions are located on the P-type base region and are each adjacent to one of the P+ body regions;

[0013] Two channel regions are located on the P-type base region and are each adjacent to one of the N+ source regions;

[0014] Two current-conducting layers are located within the JFET region and are respectively adjacent to one of the channel regions; the doping concentration of each current-conducting layer is greater than the doping concentration of the JFET region.

[0015] A current-blocking layer is located within the JFET region between the two current-conducting layers and is not adjacent to the two current-conducting layers; the doping concentration of the current-blocking layer is less than the doping concentration of the JFET region.

[0016] Two source electrodes are located on the P+ body region and part of the N+ source region at both ends of the device;

[0017] The gate oxide layer is located on two N+ source regions, two channel regions, two current conduction layers, a current blocking layer and a JFET region, and the two ends of the gate oxide layer are adjacent to two source electrodes;

[0018] The gate electrode is located on the gate oxide layer;

[0019] The drain electrode is located on the lower surface of the N+ substrate layer.

[0020] In one embodiment of the present invention, the ratio of the thickness of each guide layer to the thickness of the channel region is 1 / 2 to 2, and the thickness of each guide layer is less than the depth of the JFET region; the ratio of the length of each guide layer to the width of the JFET region is 1 / 12 to 1 / 3.

[0021] In one embodiment of the present invention, the ratio of the thickness of each guide layer to the thickness of the channel region is 1 / 2; the ratio of the length of each guide layer to the width of the JFET region is 1 / 12.

[0022] In one embodiment of the present invention, the ratio of the thickness of the current-blocking layer to the thickness of the channel region is 1 / 2 to 4, and the thickness of the current-blocking layer is less than the depth of the JFET region; the ratio of the length of the current-blocking layer to the width of the JFET region is 1 / 4 to 1 / 2.

[0023] In one embodiment of the present invention, the ratio of the thickness of the current-blocking layer to the thickness of the channel region is 1; the ratio of the length of the current-blocking layer to the width of the JFET region is 1 / 4.

[0024] Secondly, embodiments of the present invention provide a method for fabricating a SiC MOSFET structure with a current-conducting layer in the JFET region, characterized in that the fabrication method includes:

[0025] An N-drift region layer is epitaxially grown on the upper surface of an N+ substrate layer;

[0026] Ion implantation is performed at both ends of the device to form two P-type base regions; the two P-type base regions form a JFET region;

[0027] Ion implantation is performed at both ends of the device to form two P+ body regions;

[0028] Ion implantation is performed on the P-type base region adjacent to the P+ body region to form two N+ source regions; the difference in lateral diffusion junction depth between the P-type base region and the N+ source region forms a channel region;

[0029] Two current-carrying layers are formed by ion implantation in the JFET region adjacent to the channel region; the doping concentration of each current-carrying layer is greater than the doping concentration of the JFET region;

[0030] Ion implantation is performed in the JFET region between the two current-conducting layers to form a current-blocking layer; the doping concentration of the current-blocking layer is lower than the doping concentration of the JFET region.

[0031] Two source electrodes are formed by depositing source metal on the P+ body region and part of the N+ source region at both ends of the device;

[0032] A gate oxide layer is formed by depositing gate oxide metal on two N+ source regions, two channel regions, two guide layers, a choke layer, and a JFET region;

[0033] A gate metal is deposited in the middle region of the gate oxide layer to form a gate electrode;

[0034] Drain metal is deposited on the lower surface of the N+ substrate to form a drain electrode.

[0035] In one embodiment of the present invention, the ratio of the thickness of each guide layer to the thickness of the channel region is 1 / 2 to 2, and the thickness of each guide layer is less than the depth of the JFET region; the ratio of the length of each guide layer to the width of the JFET region is 1 / 12 to 1 / 3.

[0036] In one embodiment of the present invention, the ratio of the thickness of the current-blocking layer to the thickness of the channel region is 1 / 2 to 4, and the thickness of the current-blocking layer is less than the depth of the JFET region; the ratio of the length of the current-blocking layer to the width of the JFET region is 1 / 4 to 1 / 2.

[0037] The beneficial effects of this invention are:

[0038] This invention proposes a SiC MOSFET structure with a JFET region containing a current-conducting layer. Based on the conventional SiC MOSFET structure, it improves the JFET region structure of the SiC MOSFET, enhancing the short-circuit withstand capability of the SiC MOSFET from a device design perspective. Specifically, the JFET region is subdivided: two highly doped current-conducting layers (with a higher doping concentration than the JFET region) are added to the JFET region, and a lightly doped current-blocking layer (with a lower doping concentration than the JFET region) is added between the two current-conducting layers. When the device enters a short-circuit state, it operates in the saturation region. The PN junction formed by the JFET region and the P-type base region generates a large depletion layer, which mainly extends towards the less doped JFET region. The short-circuit current flows closer to the center of the JFET region. At this time, the highly doped current-conducting layer of the JFET region shunts the short-circuit current, while the current-blocking layer reduces the saturation current density of the JFET region. This effectively reduces the short-circuit current density in the central region of the JFET region, slows down temperature accumulation, and thus improves the short-circuit withstand time of the device.

[0039] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of a SiC MOSFET structure with a current-conducting layer in the JFET region provided by an embodiment of the present invention;

[0041] Figure 2 This is a schematic diagram comparing the current density of the JFET region under short-circuit conditions between a conventional SiC MOSFET structure and the structure proposed in this invention.

[0042] Figure 3 This is a schematic diagram comparing the short-circuit withstand time of a conventional SiC MOSFET structure and the structure proposed in this invention under short-circuit conditions.

[0043] Figure 4 This is a schematic diagram of the fabrication process of a SiC MOSFET structure with a current-conducting layer in the JFET region provided by an embodiment of the present invention;

[0044] Figure 5 (a)~ Figure 5 (i) is a schematic diagram of the fabrication process of the SiC MOSFET structure with a current-conducting layer in the JFET region provided in the embodiment of the present invention.

[0045] Explanation of reference numerals in the attached figures:

[0046] 1-N+ substrate layer; 2-N-drift region layer; 3-P-type base region; 4-JFET region; 5-P+ body region; 6-N+ source region; 7-channel region; 8-conducting layer; 9-resisting layer; 10-source electrode; 11-gate oxide layer; 12-gate electrode; 13-drain electrode. Detailed Implementation

[0047] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0048] In existing SiC MOSFET devices, the doping concentration in the JFET region and the drift region is kept consistent. This consistent doping concentration simplifies the fabrication process. However, to maintain the device's blocking characteristics, a typical drift region doping concentration of 5 × 10⁻⁶ is required for a 1200V SiC MOSFET device. 15 cm -3 ~1×10 17 cm -3 As the current channel during device operation, the JFET region is prone to short-circuit current and heat concentration under short-circuit conditions with the same doping concentration, which can lead to device degradation or thermal runaway and burnout. Therefore, reasonable modification of the JFET region is the key to increasing the short-circuit tolerance of the device.

[0049] Currently, most designs for SiC MOSFET devices focus on conduction characteristics, especially on-resistance, with little consideration given to short-circuit withstand capability. The most direct method to address short-circuit issues is to add a protective switch to the external circuitry. However, considering short-circuit withstand capability within the device itself requires design-level solutions, for which there are currently no readily available technical solutions. Simply reducing the doping concentration in the JFET region can lower the short-circuit saturation current, but this also severely impacts the device's conduction characteristics. Therefore, to improve the short-circuit withstand time of SiC MOSFET devices while minimizing the impact on on-resistance, a comprehensive consideration of the JFET region's characteristics is necessary. Addressing the issues of high saturation current density and concentrated short-circuit current in the JFET region of SiC MOSFETs during short circuits, this invention proposes a reasonable JFET region design scheme and provides a feasible fabrication method to reduce the concentration of short-circuit saturation current, slow down rapid device temperature rise, and thus improve the short-circuit withstand capability of SiC MOSFETs. Specifically:

[0050] Firstly, please see Figure 1 This invention provides a SiC MOSFET structure with a current-conducting layer in the JFET region, the SiC MOSFET structure comprising:

[0051] N+ substrate layer 1;

[0052] N-drift region layer 2 is located on the upper surface of N+ substrate layer 1;

[0053] Two P-type base regions 3 are located on the N-drift region layer 2 at both ends of the device; a JFET region 4 is formed between the two P-type base regions 3;

[0054] Two P+ body regions 5 are located on the P-type base regions 3 at both ends of the device;

[0055] Two N+ source regions 6 are located on the P-type base region 3 and are adjacent to a P+ body region 5 respectively;

[0056] Two channel regions 7 are located on the P-type base region 3 and are each adjacent to an N+ source region 6;

[0057] Two current-conducting layers 8 are located within the JFET region 4 and are adjacent to a channel region 7 respectively; the doping concentration of each current-conducting layer 8 is greater than the doping concentration of the JFET region 4; the upper surface of each current-conducting layer 8 coincides with the upper surface of the JFET region 4.

[0058] The current-blocking layer 9 is located in the JFET region 4 between the two current-conducting layers 8 and is not adjacent to the two current-conducting layers 8; the doping concentration of the current-blocking layer 9 is less than the doping concentration of the JFET region 4; the upper surface of the current-blocking layer 9 coincides with the upper surface of the JFET region 4.

[0059] Two source electrodes 10 are located on the P+ body region 5 and part of the N+ source region 6 at both ends of the device;

[0060] The gate oxide layer 11 is located on two N+ source regions 6, two channel regions 7, two current conduction layers 8, a current blocking layer 9 and a JFET region 4, and the two ends of the gate oxide layer 11 are adjacent to two source electrodes 10.

[0061] Gate electrode 12 is located on gate oxide layer 11;

[0062] Drain electrode 13 is located on the lower surface of N+ substrate layer 1.

[0063] In this embodiment of the invention, for example, the doping concentration of region 4 in a 1200V SiC MOSFET device JFET is 5×10⁻⁶. 15 cm -3 ~1×10 17 cm -3 The current-conducting layer 8 and the current-blocking layer 9 are determined according to the doping situation of JFET region 4. If the doping concentration of JFET region 4 is 5×10⁻⁶, then... 15 cm -3 Therefore, the doping concentration of the current-carrying layer 8 can be taken as 7 × 10⁸. 15 cm -3 Its doping concentration is greater than that of JFET region 4, while the doping concentration of the current blocking layer 9 can be 1×10⁻⁶. 15 cm -3 Its doping concentration is less than that of JFET region 4.

[0064] In embodiments of the present invention, such as Figure 1 As shown, the ratio of the thickness D1 of each current-conducting layer 8 to the thickness D of the channel region 7 is 1 / 2 to 2, and the thickness D1 of each current-conducting layer is less than the depth of the JFET region 4; the ratio of the length L1 of each current-conducting layer 8 to the width L of the JFET region 4 is 1 / 12 to 1 / 3. For the current-conducting layer 8: the short-circuit withstand time of the device decreases with the increase of the thickness D1 of the current-conducting layer 8; the short-circuit saturation current of the device increases with the increase of the length L1 of the current-conducting layer 8. In the embodiments of the present invention, as... Figure 1 As shown, the ratio of the thickness D2 of the choke layer 9 to the thickness D of the channel region 7 is 1 / 2 to 4, and the thickness D2 of the choke layer 9 is less than the depth of the JFET region 4; the ratio of the length L2 of the choke layer 9 to the width L of the JFET region 4 is 1 / 4 to 1 / 2. For the choke layer 9: the short-circuit withstand time of the device increases with the increase of the length L2 of the choke layer 9; the short-circuit saturation current of the device decreases with the increase of the thickness D2 of the choke layer 9. Therefore, in considering the short-circuit withstand time and conduction characteristics, the embodiments of the present invention need to comprehensively select appropriate device structure parameters.

[0065] A specific embodiment of the present invention is as follows: the doping concentration of region 4 in the JFET is 5 × 10⁴. 15 cm -3 The doping concentration of each current-conducting layer 8 is 7 × 10⁸. 15 cm -3 The ratio of the thickness D1 of each current-conducting layer 8 to the thickness D of the channel region 7 is 1 / 2, and the ratio of the length L1 of each current-conducting layer 8 to the width L of the JFET region 4 is 1 / 12; the doping concentration of the current-blocking layer 9 is 1×10⁻⁶. 15 cm -3 The ratio of the thickness D2 of the choke layer 9 to the thickness D of the channel region 7 is 1, and the ratio of the length L2 of the choke layer 9 to the width L of the JFET region 4 is 1 / 4.

[0066] To verify the advantages of the results proposed in this invention, experiments were conducted under the same structural parameters and voltage conditions. The results showed that, compared to conventional SiC MOSFET structures, the structure proposed in this invention has the following advantages: the saturation current density at the center of region 4 of the JFET region is effectively reduced by half, such as... Figure 2 As shown, Figure 2 The horizontal axis represents the center distance of the JFET in micrometers (μm), and the vertical axis represents the drain current in amperes (A). The conventional structure is the conventional SiC MOSFET structure, and the patented structure is the structure proposed in this invention. The short-circuit withstand time is improved by approximately 10%, such as... Figure 3 As shown, Figure 3 The horizontal axis represents the short-circuit withstand voltage time in microseconds (μs), and the vertical axis represents the drain current of the device in amperes (A). The traditional structure is the conventional SiC MOSFET structure, and the patented structure is the structure proposed in this invention.

[0067] As can be seen, the SiC MOSFET structure with a current-conducting layer in the JFET region proposed in this embodiment of the invention improves upon the conventional SiC MOSFET structure. The JFET region structure of the MOSFET improves the short-circuit withstand capability of SiC MOSFETs from the device design level. Specifically, the JFET region 4 is subdivided: two highly doped current-conducting layers 8 are added to the JFET region 4 (the doping concentration of the current-conducting layers 8 is greater than that of the JFET region 4), and a lightly doped current-blocking layer 9 is added between the two current-conducting layers 8 (the doping concentration of the current-blocking layer 9 is less than that of the JFET region 4). When the device enters the short-circuit state, the device operates in the saturation region. The PN junction formed by the JFET region 4 and the P-type base region 3 generates a large depletion layer. The depletion layer mainly extends towards the JFET region 4 with a lower doping concentration. The short-circuit current flows closer to the center of the JFET region 4. At this time, the highly doped current-conducting layers 8 of the JFET region 4 shunt the short-circuit current, while the current-blocking layer 9 can reduce the saturation current density of the JFET region 4, thereby effectively reducing the short-circuit current density in the central region of the JFET region 4, slowing down the temperature accumulation of the device, and thus improving the short-circuit withstand time of the device.

[0068] Secondly, please see Figure 4 This invention provides a method for fabricating a SiC MOSFET structure with a current-conducting layer in the JFET region, characterized in that the fabrication method includes:

[0069] S401. An N- drift region layer 2 is epitaxially grown on the upper surface of the N+ substrate layer 1.

[0070] An N- drift region layer 2 is grown on an N+ substrate layer 1 using MOCVD (Metal-Organic Chemical Vapor Deposition) process, such as... Figure 5 As shown in (a).

[0071] S402, Ion implantation is performed on the N-drift region layer 2 at both ends of the device to form two P-type base regions 3; the two P-type base regions 3 form a JFET region 4.

[0072] Using ion implantation, P-type ion implantation is performed on the N-drift region layer 2 at both ends of the device, such as through multiple boron ion implantations, to form two P-type base regions 3. Simultaneously, a JFET region 4 is formed between the two P-type base regions 3. At this point, the doping concentration of the JFET region 4 is consistent with that of the N-drift region layer 2. Figure 5 As shown in (b).

[0073] S403. Ion implantation is performed on the P-type base region 3 at both ends of the device to form two P+ body regions 5.

[0074] Using ion implantation technology, P-type ions are implanted into the P-type base regions 3 at both ends of the device, such as through multiple boron ion implantations, to form two P+ body regions 5. Figure 5 As shown in (c), in this embodiment of the invention, the P+ body region 5 is highly doped to eliminate the parasitic BJT (Bipolar Junction Transistor) effect.

[0075] S404. Ion implantation is performed on the P-type base region 3 adjacent to the P+ body region 5 to form two N+ source regions 6; the difference in lateral diffusion junction depth between the P-type base region 4 and the N+ source region 6 forms the channel region 7.

[0076] Using ion implantation technology, N-type ions, such as multiple phosphorus ion implantations, are performed on the P-type base region 3 adjacent to the P+ body region 5 to form two N+ source regions 6; simultaneously, the difference in lateral diffusion junction depth between the two P-type base regions 4 and one N+ source region 6 forms a channel region 7, such as... Figure 5 As shown in (c).

[0077] S405, Ion implantation is performed in the JFET region 4 adjacent to the channel region 7 to form two current-carrying layers 8; the doping concentration of each current-carrying layer 8 is greater than the doping concentration of the JFET region 4.

[0078] Using ion implantation technology, N-type ion implantation, such as multiple phosphorus ion implantations, is performed in the JFET region 4 adjacent to the channel region 7 to form two current-carrying layers 8, such as... Figure 5 As shown in (d), it can be seen that, in this embodiment of the invention, the doping concentration of each current-carrying layer 8 is required to be greater than the doping concentration of the JFET region 4.

[0079] In this embodiment of the invention, the ratio of the thickness D1 of each flow guide layer 8 to the thickness D of the channel region 7 is 1 / 2 to 2, and the thickness D1 of each flow guide layer is less than the depth of the JFET region 4; the ratio of the length L1 of each flow guide layer 8 to the width L of the JFET region 4 is 1 / 12 to 1 / 3.

[0080] S406. Ion implantation is performed in the JFET region 4 between the two current-conducting layers 8 to form a current-blocking layer 9; the doping concentration of the current-blocking layer 9 is less than the doping concentration of the JFET region 4.

[0081] Using ion implantation technology, N-type ion implantation, such as multiple phosphorus ion implantations, is performed in the JFET region 4 between the two current-carrying layers 8 to form a current-blocking layer 9. Figure 5 As shown in (e), it can be seen that the doping concentration of the current blocking layer 9 is less than the doping concentration of the JFET region 4 in this embodiment of the invention.

[0082] In this embodiment of the invention, the ratio of the thickness D2 of the current blocking layer 9 to the thickness D of the channel region 7 is 1 / 2 to 4, and the thickness D2 of the current blocking layer 9 is less than the depth of the JFET region 4; the ratio of the length L2 of the current blocking layer 9 to the width L of the JFET region 4 is 1 / 4 to 1 / 2.

[0083] S407. Two source electrodes 10 are formed by depositing source metal on the P+ body region 5 and part of the N+ source region 6 at both ends of the device.

[0084] Using electron beam evaporation, source metal, such as Al metal, is deposited on the P+ body region 5 and part of the N+ source region 6 at both ends of the device. The P-type base region 3 and the N+ source region 6 are then shorted to form the source electrode 10 of the device structure. Figure 5 As shown in (f).

[0085] S408, gate oxide metal is deposited on two N+ source regions 6, two channel regions 7, two guide layers 8, choke layer 9 and JFET region 4 to form gate oxide layer 11.

[0086] Gate oxide metal, such as Al2O3, is deposited on two N+ source regions 6, two channel regions 7, two conduction layers 8, a current-blocking layer 9, and a JFET region 4 using PECVD (Plasma Enhanced Chemical Vapor Deposition) to form gate oxide layer 11. Figure 5 As shown in (g).

[0087] S409. Deposit gate metal in the middle region of gate oxide layer 11 to form gate electrode 12.

[0088] Using an electron beam evaporation process, gate metal, such as Al metal, is deposited in the middle region of the gate oxide layer 11 to form the gate electrode 12. Figure 5 As shown in (h).

[0089] S410. Drain metal is deposited on the lower surface of N+ substrate 1 to form drain electrode 13.

[0090] Using electron beam evaporation, a drain metal, such as Al metal, is deposited on the lower surface of the N+ substrate layer 1 to form a drain electrode 13. Figure 5 As shown in (i).

[0091] The method for fabricating a SiC MOSFET structure with a current-conducting layer in the JFET region proposed in this invention eliminates the uniform doping method in the JFET region 4. Instead of directly reducing or increasing the doping concentration in the JFET region, a current-conducting layer 8 is added to improve conduction characteristics. This layer 8 allows the device to maintain a low on-resistance under normal switching characteristics, thereby reducing switching losses. A current-blocking layer 9 is added to improve short-circuit withstand capability. This layer effectively reduces the short-circuit saturation current in the JFET region during short-circuit faults, reducing heat concentration and increasing the short-circuit withstand time. In actual production, only a few more ion implantations are needed in the JFET region 4. Although this adds additional process steps, it does not introduce new process procedures, making the process simple to implement. Most importantly, the resulting SiC MOSFET structure is... In the MOSFET structure, two highly doped current-conducting layers 8 (with a higher doping concentration than the JFET region 4) are added to the JFET region 4. A lightly doped current-blocking layer 9 (with a lower doping concentration than the JFET region 4) is added between the two current-conducting layers 8 in the JFET region 4. When the device enters a short-circuit state, it operates in the saturation region. The PN junction formed by the JFET region 4 and the P-type base region 3 generates a large depletion layer. The depletion layer mainly extends towards the JFET region 4 with a lower doping concentration. The short-circuit current flows closer to the center of the JFET region 4. At this time, the highly doped current-conducting layers 8 of the JFET region 4 shunt the short-circuit current, while the current-blocking layer 9 can reduce the saturation current density of the JFET region 4. This effectively reduces the short-circuit current density in the central region of the JFET region 4, slows down the temperature accumulation of the device, and thus improves the short-circuit withstand time of the device.

[0092] As for the method embodiment of the second aspect, since it is basically similar to the structural embodiment of the first aspect, the description is relatively simple, and relevant details can be found in the description of the structural embodiment of the first aspect.

[0093] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0094] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the specification and accompanying drawings, will understand and implement other variations of the disclosed embodiments in carrying out the claimed invention. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. While certain measures are described in different embodiments, this does not mean that these measures cannot be combined to produce good results.

[0095] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A SiC MOSFET structure with a current-conducting layer in the JFET region, characterized in that, The SiC MOSFET structure includes: N+ substrate layer; The N-drift region layer is located on the upper surface of the N+ substrate layer; Two P-type base regions are located on the N-drift region layers at both ends of the device; a JFET region is formed between the two P-type base regions; Two P+ body regions are located on the P-type base regions at both ends of the device, respectively; Two N+ source regions are located on the P-type base region and are each adjacent to one of the P+ body regions; Two channel regions are located on the P-type base region and are each adjacent to one of the N+ source regions; Two current-conducting layers are located within the JFET region and are respectively adjacent to one of the channel regions; the doping concentration of each current-conducting layer is greater than the doping concentration of the JFET region. A current-blocking layer is located within the JFET region between the two current-conducting layers and is not adjacent to the two current-conducting layers; the doping concentration of the current-blocking layer is less than the doping concentration of the JFET region. Two source electrodes are located on the P+ body region and part of the N+ source region at both ends of the device; The gate oxide layer is located on two N+ source regions, two channel regions, two current conduction layers, a current blocking layer and a JFET region, and the two ends of the gate oxide layer are adjacent to two source electrodes; The gate electrode is located on the gate oxide layer; The drain electrode is located on the lower surface of the N+ substrate layer.

2. The SiC MOSFET structure with a current-conducting layer in the JFET region according to claim 1, characterized in that, The ratio of the thickness of each guide layer to the thickness of the channel region is 1 / 2 to 2, and the thickness of each guide layer is less than the depth of the JFET region; the ratio of the length of each guide layer to the width of the JFET region is 1 / 12 to 1 / 3.

3. The SiC MOSFET structure with a current-conducting layer in the JFET region according to claim 1, characterized in that, The thickness of each guide layer is 1 / 2 the thickness of the channel region; the length of each guide layer is 1 / 12 the width of the JFET region.

4. The SiC MOSFET structure with a current-conducting layer in the JFET region according to claim 1, characterized in that, The ratio of the thickness of the current-blocking layer to the thickness of the channel region is 1 / 2 to 4, and the thickness of the current-blocking layer is less than the depth of the JFET region; the ratio of the length of the current-blocking layer to the width of the JFET region is 1 / 4 to 1 / 2.

5. The SiC MOSFET structure with a current-conducting layer in the JFET region according to claim 1, characterized in that, The ratio of the thickness of the flow-blocking layer to the thickness of the channel region is 1; the ratio of the length of the flow-blocking layer to the width of the JFET region is 1 / 4.

6. A method for fabricating a SiC MOSFET structure with a current-conducting layer in the JFET region, characterized in that, The preparation method includes: An N-drift region layer is epitaxially grown on the upper surface of an N+ substrate layer; Ion implantation is performed at both ends of the device to form two P-type base regions; the two P-type base regions form a JFET region; Ion implantation is performed at both ends of the device to form two P+ body regions; Ion implantation is performed on the P-type base region adjacent to the P+ body region to form two N+ source regions; the difference in lateral diffusion junction depth between the P-type base region and the N+ source region forms a channel region; Two current-carrying layers are formed by ion implantation in the JFET region adjacent to the channel region; the doping concentration of each current-carrying layer is greater than the doping concentration of the JFET region; Ion implantation is performed in the JFET region between the two current-conducting layers to form a current-blocking layer; the doping concentration of the current-blocking layer is lower than the doping concentration of the JFET region. Two source electrodes are formed by depositing source metal on the P+ body region and part of the N+ source region at both ends of the device; A gate oxide layer is formed by depositing gate oxide metal on two N+ source regions, two channel regions, two guide layers, a choke layer, and a JFET region; A gate metal is deposited in the middle region of the gate oxide layer to form a gate electrode; Drain metal is deposited on the lower surface of the N+ substrate to form a drain electrode.

7. The method for fabricating a SiC MOSFET structure with a current-conducting layer in the JFET region according to claim 6, characterized in that, The thickness of each guide layer is 1 / 2 to 2 times the thickness of the channel region, and the thickness of each guide layer is less than the depth of the JFET region; the length of each guide layer is 1 / 12 to 1 / 3 times the width of the JFET region.

8. The method for fabricating a SiC MOSFET structure with a current-conducting layer in the JFET region according to claim 6, characterized in that, The ratio of the thickness of the current-blocking layer to the thickness of the channel region is 1 / 2 to 4, and the thickness of the current-blocking layer is less than the depth of the JFET region; the ratio of the length of the current-blocking layer to the width of the JFET region is 1 / 4 to 1 / 2.

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