MOSFET with embedded heterojunction diode and method of manufacturing the same

Abstract

The present disclosure provides a MOSFET with an embedded heterojunction diode and a manufacturing method thereof, the MOSFET comprising a metalized drain, an N-type substrate, an N+ buffer layer, a multi-layer N-epitaxial layer, a P-type body region, a JFET region, a P+ contact region, an N+ source region, a gate oxide layer, an N-type polysilicon gate, a silicon dioxide interlayer dielectric, a P-type polysilicon, and a metalized source; the JFET region is located in the middle of two P-type body regions; the P-type polysilicon is arranged in the middle of two N-type polysilicon gates, above the JFET region, and the P-type polysilicon and the JFET region form a heterojunction diode. The present disclosure sets the P-type polysilicon in the middle of the two N-type polysilicon gates to form a heterojunction diode with the JFET region, thereby reducing the area of a single silicon carbide MOSFET cell, increasing the channel density, increasing the current density, reducing the size of the entire MOSFET, and reducing the process cost.

Description

Technical Field

[0001] This disclosure relates to the field of power semiconductor device technology, and in particular to a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with an embedded heterojunction diode and its manufacturing method. Background Technology

[0002] Silicon carbide power devices have advantages such as low on-resistance, high switching frequency, and high operating junction temperature. In recent years, silicon carbide power devices have developed rapidly and have been successfully commercialized, and are widely used in inverters for new energy vehicles.

[0003] In the half-bridge circuit of an inverter, silicon carbide MOSFETs with embedded unipolar diodes are typically used. The embedded unipolar diodes are often Schottky diodes with low on-state voltage drop. However, embedding Schottky diodes increases the area of ​​a single silicon carbide MOSFET cell, reduces the channel density, and reduces the current density, which leads to an increase in the overall size of the MOSFET and increases the manufacturing cost. Summary of the Invention

[0004] The technical problem to be solved by this disclosure is to overcome the defects of existing silicon carbide MOSFETs with embedded Schottky diodes, such as large area of ​​individual silicon carbide MOSFET cells, small channel density, and small current density, which lead to larger overall MOSFET size and increased process cost. The disclosure provides a MOSFET with embedded heterojunction diodes and its manufacturing method.

[0005] This disclosure solves the above-mentioned technical problems through the following technical solution:

[0006] This disclosure provides a MOSFET with an embedded heterojunction diode, the MOSFET including a metallized drain, an N-type substrate, an N+ buffer layer, multiple N- epitaxial layers, a P-type body region, a JFET region, a P+ contact region, an N+ source region, a gate oxide layer, an N-type polysilicon gate, a silicon dioxide interlayer dielectric, a P-type polysilicon, and a metallized source.

[0007] The metallized drain, the N-type substrate, the N+ buffer layer, and the multiple N- epitaxial layers are stacked sequentially from bottom to top;

[0008] The two P-type body regions are located at the top of the uppermost N-epitaxial layer, and are distributed on the left and right sides of the uppermost N-epitaxial layer;

[0009] The JFET region is located in the uppermost N-epitaxial layer, between the two P-type body regions;

[0010] Above each of the P-type body regions are the P+ contact region and the N+ source region; wherein the N+ source region is close to the JFET region;

[0011] The gate oxide layers are respectively provided on both sides above the uppermost N-epitaxial layer;

[0012] The N-type polysilicon gate is disposed above the gate oxide layer on each side;

[0013] The P-type polysilicon is located in the middle of the two N-type polysilicon gates, above the JFET region, and the P-type polysilicon and the JFET region form the heterojunction diode;

[0014] The silicon dioxide interlayer dielectric is disposed above the gate oxide layer, the N-type polysilicon gate, and the P-type polysilicon.

[0015] The metallized source electrode is disposed above the P+ contact region, the N+ source region, and the silicon dioxide interlayer dielectric, and the metallized source electrode is connected to the P-type polysilicon.

[0016] Preferably, different doping concentrations of the P-type polysilicon correspond to different on-state voltage drops of the heterojunction diode.

[0017] Preferably, the doping concentration of the N-epipolar layers decreases sequentially from bottom to top.

[0018] Preferably, the semiconductor material used in the MOSFET is silicon carbide.

[0019] Preferably, the P-type polycrystalline silicon is deposited on the N-epitaxial layer by low-pressure chemical vapor deposition.

[0020] Preferably, the thickness of the P-type polycrystalline silicon is in the range of 0.1-1 μm.

[0021] Preferably, the doping concentration of the P-type polycrystalline silicon is 1e19-1e20 cm⁻¹. -3 .

[0022] Preferably, the metallized source electrode is protected with PI (polyimide) adhesive.

[0023] This disclosure also provides a method for manufacturing a MOSFET with an embedded heterojunction diode, the method being used to manufacture a MOSFET with an embedded heterojunction diode as described above, the method comprising:

[0024] An N+ buffer layer is grown on the surface of an N-type substrate;

[0025] Multiple N-epipolar layers are grown on the surface of the N+ buffer layer;

[0026] The N-epipolar layers are stacked sequentially from bottom to top.

[0027] Implantation windows for the P-type body region, P+ contact region, and N+ source region are formed on the topmost N-epitaxial layer using photomask lithography. Then, the P-type body region, the P+ contact region, and the N+ source region are formed by ion implantation and activation annealing, respectively.

[0028] The two P-type body regions are located at the top of the uppermost N-epitaxial layer and are distributed on the left and right sides of the uppermost N-epitaxial layer; the uppermost N-epitaxial layer is provided with a JFET region, which is located between the two P-type body regions.

[0029] A gate oxide layer is formed on the N-epitaxial layer by thermal oxidation, an N-type polysilicon gate is deposited, and a split gate structure is etched.

[0030] Each of the P-type body regions is provided with a P+ contact region and an N+ source region above it, and the N+ source region is close to the JFET region; the uppermost epitaxial layer is provided with gate oxide layers on both sides above it, and an N-type polysilicon gate is provided above the gate oxide layer on each side.

[0031] A P-type polysilicon is deposited in the middle of the N-type polysilicon gate, and the P-type polysilicon forms a heterojunction diode with the JFET region;

[0032] The P-type polysilicon is located above the JFET region;

[0033] A silicon dioxide interlayer dielectric is deposited around the split gate structure to encapsulate the N-type polysilicon gate and the P-type polysilicon, and exposes the surfaces of the P+ contact region and the N+ source region.

[0034] The silicon dioxide interlayer dielectric is disposed above the gate oxide layer, the N-type polysilicon gate, and the P-type polysilicon.

[0035] A metallized source electrode is formed on the surface of the P+ contact region and the N+ source region, and the metallized source electrode is connected to the P-type polysilicon.

[0036] The metallization source electrode is disposed above the P+ contact region, the N+ source region, and the silicon dioxide interlayer dielectric.

[0037] A metallized drain is formed on the back side of the N-type substrate by metallization.

[0038] Based on common knowledge in the field, the preferred conditions described can be combined arbitrarily to obtain various preferred embodiments of this disclosure.

[0039] The positive and progressive effects of this disclosure are as follows:

[0040] This disclosure reduces the area of ​​a single silicon carbide MOSFET cell, increases the channel density and current density, and reduces the overall size of the MOSFET by placing a P-type polysilicon at the midpoint between two N-type polysilicon gates to form a heterojunction diode with the JFET region. This reduces the process cost. In addition, the MOSFET with an embedded heterojunction diode has a smaller leakage current, achieving a lower on-state voltage drop and a higher reverse blocking voltage, improving device performance and reducing the risk of device failure. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of the MOSFET with an embedded heterojunction diode according to Embodiment 1 of this disclosure.

[0042] Figure 2 This is a schematic diagram of the freewheeling current path of the MOSFET with an embedded heterojunction diode in Embodiment 1 of this disclosure.

[0043] Figure 3 This is a flowchart of a method for manufacturing a MOSFET with an embedded heterojunction diode according to Embodiment 2 of this disclosure. Detailed Implementation

[0044] The present disclosure is further illustrated below by way of embodiments, but the present disclosure is not limited to the scope of the embodiments described herein.

[0045] Example 1

[0046] This embodiment provides a MOSFET with an embedded heterojunction diode, such as... Figure 1 As shown, the MOSFET includes a metallized drain 1, an N-type substrate 2, an N+ buffer layer 3, and multiple N- epitaxial layers.

[0047] The number of N-epitaxy layers can be set according to actual needs. Figure 1 As shown, the multilayer N-epitaxial layer includes 10 epitaxial layers, specifically, from bottom to top, it includes the first N-epitaxial layer 4, the second N-epitaxial layer 5, the third N-epitaxial layer 6, ... the tenth N-epitaxial layer 13 (wherein, the number of each N-epitaxial layer increases by 1 from bottom to top). Among them, the tenth N-epitaxial layer 13 is the topmost N-epitaxial layer.

[0048] The MOSFET also includes a P-type body region 14, a P+ contact region 15, an N+ source region 16, an N-type polysilicon gate 17, a gate oxide layer 18, a silicon dioxide interlayer dielectric 19, a P-type polysilicon 20, a metallized source 21, and a JFET region 22.

[0049] Metallized drain 1, N-type substrate 2, N+ buffer layer 3 and multilayer N- epitaxial layer are stacked sequentially from bottom to top;

[0050] Two P-type body regions 14 are located at the top of the tenth N-epipolar layer 13, and are distributed on the left and right sides of the tenth N-epipolar layer 13;

[0051] JFET region 22 is located in the tenth N-epitaxial layer 13, between the two P-type body regions 14;

[0052] Above each P-type body region 14 is a P+ contact region 15 and an N+ source region 16; wherein, the N+ source region 16 is close to the JFET region 22;

[0053] Gate oxide layers 18 are respectively provided on both sides above the tenth N-epipolar layer 13;

[0054] An N-type polysilicon gate 17 is provided above the gate oxide layer 18 on each side.

[0055] In practical implementation, by forming two N-type polysilicon gates, i.e., a split gate structure, the relative area between the gate and the source is reduced, and the overlapping part of the N-type polysilicon gate and the metallized drain is removed, thereby reducing the gate-drain capacitance. This enables faster switching speeds, lower switching losses, and improves the device's high-frequency figure of merit (FOM) and dynamic characteristics. It also reduces the ratio of reverse transfer capacitance to input capacitance, preventing the device from turning on by itself.

[0056] The P-type polysilicon 20 is located in the middle of the two N-type polysilicon gates 17, above the JFET region 22. The P-type polysilicon 20 and the JFET region 22 form a heterojunction diode.

[0057] The silicon dioxide interlayer dielectric 19 is disposed above the gate oxide layer 18, the N-type polysilicon gate 17, and the P-type polysilicon 20;

[0058] The metallized source 21 is disposed above the P+ contact region 15, the N+ source region 16 and the silicon dioxide interlayer dielectric 19, and the metallized source 21 is connected to the P-type polysilicon 20.

[0059] In the specific implementation, the semiconductor material used in the MOSFET is silicon carbide. P-type polysilicon 20 can be deposited on the N-epitaxial layer via low-pressure chemical vapor deposition. The thickness of the P-type polysilicon 20 ranges from 0.1 to 1 μm, and the doping concentration is 1e19-1e20 cm⁻¹. -3 The metallized source electrode 21 can be protected with PI adhesive.

[0060] In this design, a P-type polysilicon is placed between two N-type polysilicon gates to form a heterojunction diode with the JFET region. This reduces the area of ​​a single silicon carbide MOSFET cell, increases channel density and current density, reduces the overall MOSFET size, and lowers process costs. Furthermore, the MOSFET with an embedded heterojunction diode exhibits lower leakage current, resulting in a lower on-state voltage drop and a higher reverse blocking voltage, improving device performance and reducing the risk of device failure. The MOSFET also features extremely low reverse recovery charge, reducing reverse recovery losses, improving reverse recovery characteristics, achieving lower power loss, and increasing MOSFET integration density.

[0061] In one feasible approach, different doping concentrations of the P-type polysilicon 20 correspond to different on-state voltage drops of the heterojunction diode.

[0062] In this scheme, the anode region of the heterojunction diode can be made of P-type polysilicon with different doping concentrations to achieve different on-state voltage drops.

[0063] In one feasible approach, the doping concentration of the multilayer N-epitaxial layers decreases sequentially from bottom to top.

[0064] Specifically, multiple N-epitaxial layers are grown on top of an N-type substrate, and the concentration distribution of the epitaxial layers is optimized to make the concentration linear. The doping concentration of each epitaxial layer gradually decreases from bottom to top, with the first N-epitaxial layer 4 having the highest doping concentration and the tenth N-epitaxial layer 13 having the lowest doping concentration.

[0065] In this scheme, by setting the doping concentration of the multiple N-epitaxial layers to decrease sequentially from bottom to top, the electric field distribution can be optimized, improving the device's breakdown voltage capability. Due to the presence of the multiple N-epitaxial layers, the potential distribution near the bottom of the P-type body region is more uniform and has higher utilization, reducing local peak electric fields and increasing breakdown voltage. Simultaneously, the on-resistance is reduced, improving device performance.

[0066] The operating principle of the MOSFET with embedded heterojunction diode in this embodiment is as follows: In the conduction mode, the electrode connection of the MOSFET with embedded heterojunction diode is as follows: the metallized source is connected to a low potential, the metallized drain is connected to a high potential, and the N-type polysilicon gate is connected to a high potential. When the forward bias voltage applied to the gate electrode reaches the threshold voltage, an inversion channel is formed on the surface of the P-type body region. Electrons are injected from the N+ source region into the multilayer N- epitaxial layer through the inversion channel of the P-type body region, forming a forward conduction current.

[0067] In blocking mode, the electrode connections of this structure are as follows: the metallized source is connected to a low potential, the metallized drain is connected to a high potential, the N-type polysilicon gate electrode is connected to a low potential, and the PN junction formed by the P-type body region and multiple N-epitaxial layers withstands high voltage. Due to the presence of multiple N-epitaxial layers, the potential distribution near the bottom of the P-type body region is more uniform, with high utilization, reduced local peak electric field, and improved breakdown voltage. Simultaneously, the on-resistance is reduced, improving device performance.

[0068] In a half-bridge circuit, the switching transistor is on, the freewheeling transistor is off, and current flows through the switching transistor. Due to the split-gate structure, the device has lower gate-drain capacitance and lower switching losses. When the switching transistor switches from on to off, the freewheeling transistor continues to conduct, and the heterojunction diode in this structure begins to conduct. Figure 2 The diagram shows the freewheeling current path of the MOSFET with embedded heterojunction diode in this embodiment. The dashed line with arrows represents the current, which flows from the P-type polysilicon to the N-epitaxial layer below.

[0069] In this embodiment, by placing a P-type polysilicon in the middle of the two N-type polysilicon gates to form a heterojunction diode with the JFET region, the area of ​​a single silicon carbide MOSFET cell is reduced, the channel density is increased, the current density is increased, the overall size of the MOSFET is reduced, and the process cost is lowered. In addition, the MOSFET with an embedded heterojunction diode has a smaller leakage current, achieving a lower on-state voltage drop and a higher reverse blocking voltage, improving device performance and reducing the risk of device failure.

[0070] Example 2

[0071] This embodiment provides a method for manufacturing a MOSFET with an embedded heterojunction diode. This method is used to manufacture a MOSFET with an embedded heterojunction diode as described in Embodiment 1. Figure 3 As shown, the manufacturing method includes:

[0072] S101. An N+ buffer layer is grown on the surface of an N-type substrate;

[0073] S102. Grow multiple N-epitaxial layers on the surface of the N+ buffer layer;

[0074] Among them, multiple N-epipolar layers are stacked sequentially from bottom to top;

[0075] S103. On the topmost N-epitaxial layer, implantation windows for the P-type body region, P+ contact region and N+ source region are formed by photolithography using a mask, and then the P-type body region, P+ contact region and N+ source region are formed by ion implantation and activation annealing, respectively.

[0076] Among them, the two P-type body regions are located at the top of the uppermost N-epitaxial layer, distributed on the left and right sides of the uppermost N-epitaxial layer; the uppermost N-epitaxial layer contains a JFET region, which is located in the middle of the two P-type body regions;

[0077] Specifically, on the topmost N-epitaxial layer, photoresist is deposited and a mask is used to transfer the pattern onto the wafer through multiple photolithography processes to form the implantation windows of the P-type body region, P+ contact region, and N+ source region, respectively. Then, the P-type body region, P+ contact region, and N+ source region are formed by ion implantation and high-temperature annealing.

[0078] S104. A gate oxide layer is formed on the N-epitaxial layer by thermal oxidation, an N-type polysilicon gate is deposited, and a split gate structure is etched.

[0079] Each P-type body region has a P+ contact region and an N+ source region above it, with the N+ source region close to the JFET region; gate oxide layers are provided on both sides above the top epitaxial layer, and an N-type polysilicon gate is provided above each gate oxide layer.

[0080] S105. A heavily doped P-type polysilicon is deposited in the middle of the N-type polysilicon gate, and the P-type polysilicon forms a heterojunction diode with the JFET region.

[0081] Among them, the P-type polycrystalline silicon is located above the JFET region;

[0082] In the specific implementation process, P-type polycrystalline silicon with a thickness of 0.1-1 μm is deposited on the N-epitaxial layer by low-pressure chemical vapor deposition, and the doping concentration of the P-type polycrystalline silicon ranges from 1e19 to 1e20 cm⁻¹. -3 .

[0083] S106. A silicon dioxide interlayer dielectric is deposited around the split gate structure to encapsulate the N-type polysilicon gate and the P-type polysilicon, and the surfaces of the P+ contact region and the N+ source region are exposed.

[0084] The silicon dioxide interlayer dielectric is disposed above the gate oxide layer, the N-type polysilicon gate, and the P-type polysilicon.

[0085] S107. A metallized source electrode is formed on the surface of the P+ contact region and the N+ source region, and the metallized source electrode is connected to the P-type polysilicon.

[0086] The metallization source is located above the P+ contact region, the N+ source region, and the silicon dioxide interlayer dielectric.

[0087] S108. A metallized drain is formed on the back side of an N-type substrate by metallization.

[0088] In this embodiment, by placing a P-type polysilicon in the middle of the two N-type polysilicon gates to form a heterojunction diode with the JFET region, the area of ​​a single silicon carbide MOSFET cell is reduced, the channel density is increased, the current density is increased, the overall size of the MOSFET is reduced, and the process cost is lowered. In addition, the MOSFET with an embedded heterojunction diode has a smaller leakage current, achieving a lower on-state voltage drop and a higher reverse blocking voltage, improving device performance and reducing the risk of device failure.

[0089] While specific embodiments of this disclosure have been described above, those skilled in the art should understand that these are merely illustrative examples, and the scope of protection of this disclosure is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of this disclosure, but all such changes and modifications fall within the scope of protection of this disclosure.

Claims

1. A MOSFET with an embedded heterojunction diode, characterized in that, The MOSFET includes a metallized drain, an N-type substrate, an N+ buffer layer, multiple N- epitaxial layers, a P-type body region, a JFET region, a P+ contact region, an N+ source region, a gate oxide layer, an N-type polysilicon gate, a silicon dioxide interlayer dielectric, a P-type polysilicon, and a metallized source. The metallized drain, the N-type substrate, the N+ buffer layer, and the multiple N- epitaxial layers are stacked sequentially from bottom to top; The two P-type body regions are located at the top of the uppermost N-epitaxial layer, and are distributed on the left and right sides of the uppermost N-epitaxial layer; The JFET region is located in the uppermost N-epitaxial layer, between the two P-type body regions; Above each of the P-type body regions are the P+ contact region and the N+ source region; wherein the N+ source region is close to the JFET region; The gate oxide layers are respectively provided on both sides above the uppermost N-epitaxial layer; The N-type polysilicon gate is disposed above the gate oxide layer on each side; The P-type polysilicon is located in the middle of the two N-type polysilicon gates, above the JFET region, and the P-type polysilicon and the JFET region form the heterojunction diode; The silicon dioxide interlayer dielectric is disposed above the gate oxide layer, the N-type polysilicon gate, and the P-type polysilicon. The metallized source electrode is disposed above the P+ contact region, the N+ source region, and the silicon dioxide interlayer dielectric, and the metallized source electrode is connected to the P-type polysilicon.

2. The MOSFET with an embedded heterojunction diode as described in claim 1, characterized in that, The different doping concentrations of the P-type polycrystalline silicon correspond to the different on-state voltage drops of the heterojunction diode.

3. The MOSFET with an embedded heterojunction diode as described in claim 1, characterized in that, The doping concentration of the N-epitaxial layers decreases sequentially from bottom to top.

4. The MOSFET with an embedded heterojunction diode as described in claim 1, characterized in that, The MOSFET uses silicon carbide as its semiconductor material.

5. The MOSFET with an embedded heterojunction diode as described in any one of claims 1-4, characterized in that, The P-type polycrystalline silicon is formed by low-pressure chemical vapor deposition on the N-epitaxial layer.

6. The MOSFET with an embedded heterojunction diode as described in any one of claims 1-4, characterized in that, The thickness of the P-type polycrystalline silicon ranges from 0.1 to 1 μm.

7. The MOSFET with an embedded heterojunction diode as described in any one of claims 1-4, characterized in that, The doping concentration of the P-type polycrystalline silicon is 1e19-1e20 cm⁻¹. -3 .

8. The MOSFET with an embedded heterojunction diode as described in any one of claims 1-4, characterized in that, The metallized source electrode is protected with PI adhesive.

9. A method for manufacturing a MOSFET with an embedded heterojunction diode, characterized in that, The manufacturing method is used to manufacture a MOSFET with an embedded heterojunction diode as described in any one of claims 1-8, the manufacturing method comprising: An N+ buffer layer is grown on the surface of an N-type substrate; Multiple N-epipolar layers are grown on the surface of the N+ buffer layer; The N-epipolar layers are stacked sequentially from bottom to top. Implantation windows for the P-type body region, P+ contact region, and N+ source region are formed on the topmost N-epitaxial layer using photomask lithography. Then, the P-type body region, the P+ contact region, and the N+ source region are formed by ion implantation and activation annealing, respectively. The two P-type body regions are located at the top of the uppermost N-epitaxial layer and are distributed on the left and right sides of the uppermost N-epitaxial layer; the uppermost N-epitaxial layer is provided with a JFET region, which is located between the two P-type body regions. A gate oxide layer is formed on the N-epitaxial layer by thermal oxidation, an N-type polysilicon gate is deposited, and a split gate structure is etched. Each of the P-type body regions is provided with a P+ contact region and an N+ source region above it, and the N+ source region is close to the JFET region; the gate oxide layer is provided on both sides above the uppermost N-epitaxial layer, and the N-type polysilicon gate is provided above the gate oxide layer on each side. A P-type polysilicon is deposited in the middle of the N-type polysilicon gate, and the P-type polysilicon forms a heterojunction diode with the JFET region; The P-type polysilicon is located above the JFET region; A silicon dioxide interlayer dielectric is deposited around the split gate structure to encapsulate the N-type polysilicon gate and the P-type polysilicon, and exposes the surfaces of the P+ contact region and the N+ source region. The silicon dioxide interlayer dielectric is disposed above the gate oxide layer, the N-type polysilicon gate, and the P-type polysilicon. A metallized source electrode is formed on the surface of the P+ contact region and the N+ source region, and the metallized source electrode is connected to the P-type polysilicon. The metallization source electrode is disposed above the P+ contact region, the N+ source region, and the silicon dioxide interlayer dielectric. A metallized drain is formed on the back side of the N-type substrate by metallization.

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