Structure for improving breakdown voltage of ldmos and method of manufacturing the same

Abstract

The application provides a structure for improving the breakdown voltage of LDMOS, which comprises a substrate of a first conductive type, a terminal region and a cell region on the substrate, a buried layer of a second conductive type formed on the terminal region and the cell region, an epitaxial layer formed on the substrate, and a deep doped well of the second conductive type formed on the epitaxial layer; a shallow trench isolation is formed on the epitaxial layer to define an active region of the LDMOS device, and a deep trench isolation is formed on the epitaxial layer and the substrate to form an isolation between a high-voltage region and other devices; a body region of the first conductive type and a drift region of the second conductive type are formed on the terminal region and the cell region by ion implantation, and the body region and the drift region have a lateral spacing; a doped well of the second conductive type is formed on the deep doped well on the terminal region; wherein the deep doped well in the terminal region is not in contact with the drift region, and the deep doped well in the cell region is in contact with the drift region. The application can improve the overall breakdown voltage of the device, and the design cost is low.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a structure for improving the breakdown voltage of LDMOS and its manufacturing method. Background Technology

[0002] Due to their high voltage tolerance, high current drive capability, and extremely low power consumption, DMOS (Double-diffused MOS) is widely used in power management circuits. In planar LDMOS (Lateral DMOS) devices, as the application voltage continues to increase, the BV (breakdown voltage) of the LDMOS in the terminal isolation region and the LDMOS in the unit cell region differs significantly, resulting in a lower overall breakdown voltage of the device.

[0003] Existing LDMOS structures (such as) Figure 7 As shown in the figure, taking N-LDMOS as an example, the corresponding structures of each number are as follows: 100—P-type substrate, 101—N-type buried layer (NBL), 102—P-type epitaxial layer, 103—Deep N-type well (DNW), 104—Field plate dielectric layer / shallow trench isolation (STI), 105—Deep trench isolation (DTI), 106—N-type well implantation, 107—P-type well implantation, 108—N-type drift region implantation, 109—Gate polysilicon, 110—N-type heavily doped implantation, 111—P-type heavily doped implantation, 201—Gate insulating dielectric layer.

[0004] The drift regions of the LDMOS in the termination region and the LDMOS in the unit cell region use the same design, making it impossible to optimize the drift regions of the LDMOS in the termination region and the LDMOS in the unit cell region separately. To achieve optimal breakdown voltages for the termination isolation region and the unit cell region respectively, thereby improving the overall breakdown voltage of the device, the existing device structure still needs optimization.

[0005] To address the aforementioned issues, a novel structure and manufacturing method for improving the breakdown voltage of LDMOS are required. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a structure and manufacturing method for improving the breakdown voltage of LDMOS, which solves the problem that in the prior art, the drift region of the LDMOS in the terminal region and the drift region of the LDMOS in the unit cell region are designed in the same way, and it is impossible to separate and optimize the drift region of the LDMOS in the terminal region and the drift region of the LDMOS in the unit cell region.

[0007] To achieve the above and other related objectives, the present invention provides a structure for improving the breakdown voltage of LDMOS, comprising: A substrate of a first conductivity type has a terminal region and a unit cell region located in a high voltage region. A buried layer of a second conductivity type is formed on the terminal region and the unit cell region. An epitaxial layer is formed on the substrate. A deep doped well of the second conductivity type is formed on the epitaxial layer. Shallow trench isolation is formed on the epitaxial layer to define the active region of the LDMOS device, and deep trench isolation is formed on the epitaxial layer and the substrate to form isolation between the high voltage region and other devices; A body region of a first conductivity type and a drift region of a second conductivity type are formed on the terminal region and the unit cell region by ion implantation, with a lateral spacing between the body region and the drift region. A doped well of the second conductivity type is formed on the deep doped well on the terminal region. The deep doped well in the terminal region is not in contact with the drift region, while the deep doped well in the unit cell region is in contact with the drift region. A gate dielectric layer and a gate polysilicon layer located on the gate dielectric layer, and sidewalls located on the gate dielectric layer and the gate polysilicon layer, one end of the gate dielectric layer and the gate polysilicon layer extending to the body region, and the other end extending to the shallow trench isolation adjacent to the drift region; A heavily doped region is formed by ion implantation of a second conductivity type on the doped well, the body region, and the drift region; wherein the deep doped well, the doped well, and the heavily doped region on the terminal region serve as the lead-out structure of the buried layer, the heavily doped region on the drift region serves as the drain, and the heavily doped region on the body region serves as the source. The drift region doping concentration of the drain of the LDMOS in the unit cell region is greater than the drift region doping concentration of the drain of the LDMOS in the terminal region.

[0008] Preferably, the substrate is a silicon substrate.

[0009] Preferably, an NLDMOS device is formed on the substrate, wherein the first conductivity type of the NLDMOS device is P-type and the second conductivity type is N-type.

[0010] Preferably, a PLDMOS device is formed on the substrate, wherein the first conductivity type of the PLDMOS device is N-type and the second conductivity type is P-type.

[0011] Preferably, an LDMOS device is formed in the terminal region.

[0012] Preferably, two adjacent LDMOS devices in the terminal region and the unit cell region share the same body region.

[0013] Preferably, the material of the gate dielectric layer is silicon dioxide.

[0014] Preferably, the sidewall is made of silicon oxide.

[0015] Preferably, the structure further includes a body region extraction region located on the body region, formed by ion implantation of a first conductivity type.

[0016] The present invention also provides a method for manufacturing the above-described structure for improving the breakdown voltage of LDMOS, comprising: Step 1: Provide a substrate of a first conductivity type, the substrate having a terminal region and a unit cell region located in a high voltage region, forming a buried layer of a second conductivity type on the terminal region and the unit cell region, then forming an epitaxial layer on the substrate, and forming a deep doped well of the second conductivity type on the epitaxial layer; Step 2: A shallow trench isolation is formed on the epitaxial layer to define the active region of the LDMOS device, and a deep trench isolation is formed on the epitaxial layer and the substrate to form isolation between the high voltage region and other devices; Step 3: Using ion implantation, a body region of the first conductivity type and a drift region of the second conductivity type are formed on the terminal region and the unit cell region, with a lateral spacing between the body region and the drift region. A doped well of the second conductivity type is formed on the deep doped well on the terminal region. The deep doped well in the terminal region is not in contact with the drift region, while the deep doped well in the unit cell region is in contact with the drift region. Step 4: Form a gate dielectric layer and a gate polysilicon layer on the gate dielectric layer, and form sidewalls on the gate dielectric layer and the gate polysilicon layer. One end of the gate dielectric layer and the gate polysilicon layer extends to the body region, and the other end extends to the shallow trench isolation on the adjacent drift region. Step 5: Form heavily doped regions on the doped well, the body region, and the drift region using ion implantation of the second conductivity type; wherein, the deep doped well, the doped well, and the heavily doped region on the terminal region serve as the lead-out structure of the buried layer, the heavily doped region on the drift region serves as the drain, and the heavily doped region on the body region serves as the source, such that the drift region doping concentration of the drain of the LDMOS in the unit cell region is greater than the drift region doping concentration of the drain of the LDMOS in the terminal region.

[0017] Preferably, the substrate in step one is a silicon substrate.

[0018] Preferably, an NLDMOS device is formed on the substrate in step one, wherein the first conductivity type of the NLDMOS device is P-type and the second conductivity type is N-type.

[0019] Preferably, a PLDMOS device is formed on the substrate in step one, wherein the first conductivity type of the PLDMOS device is N-type and the second conductivity type is P-type.

[0020] Preferably, an LDMOS device is formed in the terminal region in step one.

[0021] Preferably, in step one, two adjacent LDMOS devices in the terminal region and the unit cell region share the same body region.

[0022] Preferably, the material of the gate dielectric layer in step four is silicon dioxide.

[0023] Preferably, the gate dielectric layer is formed in step four using a thermal oxidation method.

[0024] Preferably, the method for forming sidewalls on both sides of the gate polysilicon layer in step four includes: forming a sidewall material layer covering the gate polysilicon sidewalls; and etching back the sidewall material layer to form sidewalls on both sides of the gate polysilicon layer.

[0025] Preferably, the sidewall material in step four is silicon dioxide.

[0026] Preferably, step five further includes forming a body region extraction region located on the body region using ion implantation of a first conductivity type.

[0027] As described above, the structure and manufacturing method of the present invention for improving the breakdown voltage of LDMOS have the following beneficial effects: This invention only requires modification of the layout design to independently optimize the breakdown voltage of the terminal region and the unit cell region, thereby improving the overall breakdown voltage of the device and reducing design costs. Attached Figure Description

[0028] Figure 1 The diagram shown is a schematic representation of the process flow of the present invention. Figure 2 The diagram shows the formation of the buried layer and deep doped well according to the present invention. Figure 3 The diagram shows the forming region and drift region of the present invention. Figure 4 The diagram shown illustrates the structure of the present invention for improving the breakdown voltage of LDMOS. Figure 5The diagram shows a comparison of the potential distribution and impact ionization intensity of LDMOS in the prior art and LDMOS of the present invention. Figure 6 The diagram shows a simulation of the breakdown voltage of the LDMOS of the prior art and the LDMOS of the present invention. Figure 7 The diagram shown is a schematic of an existing LDMOS structure. Detailed Implementation

[0029] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. Example 1

[0030] Please see Figure 4 The present invention provides a structure for improving the breakdown voltage of LDMOS, comprising: A substrate 100 of the first conductivity type has a terminal region and a unit cell region located in a high voltage region. A buried layer 101 of the second conductivity type is formed on the terminal region and the unit cell region. An epitaxial layer 102 is formed on the substrate 100. A deep doped well 103 of the second conductivity type is formed on the epitaxial layer 102. In an embodiment of the present invention, the substrate 100 is a silicon substrate 100.

[0031] In an embodiment of the present invention, an NLDMOS device is formed on the substrate 100, wherein the first conductivity type of the NLDMOS device is P-type and the second conductivity type is N-type.

[0032] In an embodiment of the present invention, a PLDMOS device is formed on the substrate 100, wherein the first conductivity type of the PLDMOS device is N-type and the second conductivity type is P-type.

[0033] Shallow trench isolation 104 is formed on epitaxial layer 102 to define the active region of LDMOS device, and deep trench isolation 105 is formed on epitaxial layer 102 and substrate 100 to form isolation between high voltage region and other devices; the materials of shallow trench isolation 104 and deep trench isolation 105 are spin-coated glass (SOG), dense oxide (HDP-CVDOX) formed by high density plasma chemical vapor deposition, silicon dioxide (SiO2), or a dual filling of silicon dioxide and silicon nitride (SiN).

[0034] In an embodiment of the present invention, an LDMOS device is formed in the terminal region.

[0035] A first conductivity type body region 107 and a second conductivity type drift region 108 are formed on the terminal region and the unit cell region by ion implantation. There is a lateral spacing between the body region 107 and the drift region 108. A second conductivity type doped well 106 is formed on the deep doped well 103 on the terminal region. The doping of the deep doped well 103 is generally lighter than that of the doped well 106. The deep doped well 103 in the terminal region does not contact the drift region 108, while the deep doped well 103 in the unit cell region contacts the drift region 108. In an embodiment of the present invention, two adjacent LDMOS devices in the terminal region and the unit cell region share the same body region 107.

[0036] The gate dielectric layer 201 and the gate polysilicon layer 109 located on the gate dielectric layer 201, and the sidewalls located on the gate dielectric layer 201 and the gate polysilicon layer 109, one end of the gate dielectric layer 201 and the gate polysilicon layer 109 extends to the body region 107, and the other end extends to the shallow trench isolation 104 on the adjacent drift region 108; In an embodiment of the present invention, the material of the gate dielectric layer 201 is silicon dioxide.

[0037] In an embodiment of the present invention, the sidewall material is silicon oxide.

[0038] A heavily doped region 110 is formed by ion implantation of the second conductivity type on the doped well 106, body region 107, and drift region 108. The deep doped well 103, doped well 106, and heavily doped region 110 on the terminal region serve as the lead-out structure of the buried layer 101, the heavily doped region 110 on the drift region 108 serves as the drain, and the heavily doped region 110 on the body region 107 serves as the source. The doping concentration of the drift region 108 at the drain of the LDMOS in the unit cell region is greater than that at the drain of the LDMOS in the terminal region. This allows for independent optimization of the breakdown voltage of the terminal region and the unit cell region, thereby improving the overall breakdown voltage of the device.

[0039] In an embodiment of the invention, the structure further includes a body region extraction region 111 formed on the body region 107 by ion implantation of a first conductivity type.

[0040] Please see Figure 5 The diagram shows a comparison of the potential distribution and impact ionization intensity of the LDMOS in the prior art and the LDMOS of the present invention. It can be seen that the LDMOS structure of the present invention improves the potential distribution below the drain terminal of the unit cell region, reduces the impact ionization at that location, and improves the breakdown voltage of the LDMOS in the unit cell region, thereby improving the overall breakdown voltage of the device.

[0041] Please see Figure 6It shows a simulation diagram of the breakdown voltage of the prior art LDMOS and the LDMOS of the present invention. The overall breakdown voltage of the LDMOS device structure of the present invention is increased by about 25V. Example 2

[0042] Please see Figure 1 The present invention also provides a method for manufacturing the above-described structure for improving the breakdown voltage of LDMOS, comprising: Step 1, please refer to Figure 2 A substrate 100 of a first conductivity type is provided, having a terminal region and a unit cell region on the substrate 100, the terminal region and the unit cell region being located in a high voltage region, a buried layer 101 of a second conductivity type is formed on the terminal region and the unit cell region, an epitaxial layer 102 is then formed on the substrate 100, and a deep doped well 103 of the second conductivity type is formed on the epitaxial layer 102. In an embodiment of the present invention, the substrate 100 in step one is a silicon substrate 100.

[0043] In an embodiment of the present invention, an NLDMOS device is formed on the substrate 100 in step one, wherein the first conductivity type of the NLDMOS device is P-type and the second conductivity type is N-type.

[0044] In an embodiment of the present invention, a PLDMOS device is formed on the substrate 100 in step one, wherein the first conductivity type of the PLDMOS device is N-type and the second conductivity type is P-type.

[0045] In an embodiment of the present invention, an LDMOS device is formed in the terminal region in step one.

[0046] In an embodiment of the present invention, two adjacent LDMOS devices in the terminal region and primitive cell region in step one share the same body region 107.

[0047] Step 2: A shallow trench isolation 104 is formed on the epitaxial layer 102 to define the active region of the LDMOS device, and a deep trench isolation 105 is formed on the epitaxial layer 102 and the substrate 100 to form isolation between the high voltage region and other devices; the materials of the shallow trench isolation 104 and the deep trench isolation 105 are spin-coated glass (SOG), dense oxide (HDP-CVDOX) formed by high-density plasma chemical vapor deposition, silicon dioxide (SiO2), or a dual filling of silicon dioxide and silicon nitride (SiN).

[0048] Step 3: Using ion implantation, a first conductivity type body region 107 and a second conductivity type drift region 108 are formed on the terminal region and the unit cell region, respectively. There is a lateral spacing between the body region 107 and the drift region 108. A second conductivity type doped well 106 is formed on the deep doped well 103 in the terminal region. The doping of the deep doped well 103 is generally lighter than that of the doped well 106. Specifically, the deep doped well 103 in the terminal region does not contact the drift region 108, while the deep doped well 103 in the unit cell region does contact the drift region 108, forming a structure as shown in the diagram. Figure 3 The structure shown; Step 4: Form a gate dielectric layer 201 and a gate polysilicon layer 109 on the gate dielectric layer 201, forming sidewalls on the gate dielectric layer 201 and the gate polysilicon layer 109. One end of the gate dielectric layer 201 and the gate polysilicon layer 109 extends to the body region 107, and the other end extends to the shallow trench isolation 104 on the adjacent drift region 108, forming a... Figure 4 The structure shown; In an embodiment of the present invention, the material of the gate dielectric layer 201 in step four is silicon dioxide.

[0049] In an embodiment of the present invention, the gate dielectric layer 201 is formed in step four by thermal oxidation.

[0050] In an embodiment of the present invention, the method of forming sidewalls on both sides of the gate polysilicon layer 109 in step four includes: forming a sidewall material layer covering the gate polysilicon sidewalls; and etching back the sidewall material layer to form sidewalls on both sides of the gate polysilicon layer 109.

[0051] In an embodiment of the present invention, the material of the sidewall in step four is silicon oxide.

[0052] Step 5: Using ion implantation of the second conductivity type, a heavily doped region 110 is formed on the doped well 106, body region 107, and drift region 108. The deep doped well 103, doped well 106, and heavily doped region 110 on the terminal region serve as the lead-out structure of the buried layer 101; the heavily doped region 110 on the drift region 108 serves as the drain; and the heavily doped region 110 on the body region 107 serves as the source. This ensures that the doping concentration of the drift region 108 at the drain of the LDMOS in the unit cell region is greater than the doping concentration of the drift region 108 at the drain of the LDMOS device in the terminal region, forming a structure as shown below. Figure 4 The structure shown.

[0053] In an embodiment of the present invention, step five further includes forming a body region extraction region 111 located on the body region 107 by ion implantation of a first conductivity type.

[0054] Please see Figure 5The diagram shows a comparison of the potential distribution and impact ionization intensity of the LDMOS in the prior art and the LDMOS of the present invention. It can be seen that the LDMOS structure of the present invention improves the potential distribution below the drain terminal of the unit cell region, reduces the impact ionization at that location, and improves the breakdown voltage of the LDMOS in the unit cell region, thereby improving the overall breakdown voltage of the device.

[0055] Please see Figure 6 It shows a simulation diagram of the breakdown voltage of the prior art LDMOS and the LDMOS of the present invention. The overall breakdown voltage of the LDMOS device structure of the present invention is increased by about 25V.

[0056] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0057] In summary, this invention only requires modification to the layout design to independently optimize the breakdown voltage of the terminal region and the unit cell region, thereby improving the overall breakdown voltage of the device and reducing design costs. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0058] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A structure for improving the breakdown voltage of LDMOS, characterized in that, include: A substrate of a first conductivity type has a terminal region and a unit cell region located in a high voltage region. A buried layer of a second conductivity type is formed on the terminal region and the unit cell region. An epitaxial layer is formed on the substrate. A deep doped well of the second conductivity type is formed on the epitaxial layer. Shallow trench isolation is formed on the epitaxial layer to define the active region of the LDMOS device, and deep trench isolation is formed on the epitaxial layer and the substrate to form isolation between the high voltage region and other devices; A body region of a first conductivity type and a drift region of a second conductivity type are formed on the terminal region and the unit cell region by ion implantation, with a lateral spacing between the body region and the drift region. A doped well of the second conductivity type is formed on the deep doped well on the terminal region. The deep doped well in the terminal region is not in contact with the drift region, while the deep doped well in the unit cell region is in contact with the drift region. A gate dielectric layer and a gate polysilicon layer located on the gate dielectric layer, and sidewalls located on the gate dielectric layer and the gate polysilicon layer, one end of the gate dielectric layer and the gate polysilicon layer extending to the body region, and the other end extending to the shallow trench isolation adjacent to the drift region; A heavily doped region is formed by ion implantation of a second conductivity type on the doped well, the body region, and the drift region; wherein the deep doped well, the doped well, and the heavily doped region on the terminal region serve as the lead-out structure of the buried layer, the heavily doped region on the drift region serves as the drain, and the heavily doped region on the body region serves as the source. The drift region doping concentration of the drain of the LDMOS in the unit cell region is greater than the drift region doping concentration of the drain of the LDMOS in the terminal region.

2. The structure for improving LDMOS breakdown voltage according to claim 1, characterized in that: The substrate is a silicon substrate.

3. The structure for improving LDMOS breakdown voltage according to claim 1, characterized in that: An NLDMOS device is formed on the substrate, wherein the first conductivity type of the NLDMOS device is P-type and the second conductivity type is N-type.

4. The structure for improving LDMOS breakdown voltage according to claim 1, characterized in that: A PLDMOS device is formed on the substrate, wherein the first conductivity type of the PLDMOS device is N-type and the second conductivity type is P-type.

5. The structure for improving LDMOS breakdown voltage according to claim 1, characterized in that: One of the LDMOS devices is formed in the terminal region.

6. The structure for improving LDMOS breakdown voltage according to claim 1, characterized in that: The two adjacent LDMOS devices in the terminal region and the unit cell region share the same body region.

7. The structure for improving LDMOS breakdown voltage according to claim 1, characterized in that: The material of the gate dielectric layer is silicon dioxide.

8. The structure for improving LDMOS breakdown voltage according to claim 1, characterized in that: The sidewall is made of silicon dioxide.

9. The structure for improving LDMOS breakdown voltage according to claim 1, characterized in that: The structure also includes a body region extraction region located on the body region, formed by ion implantation of a first conductivity type.

10. A method for manufacturing a structure for improving the breakdown voltage of an LDMOS according to any one of claims 1 to 9, characterized in that, At least including: Step 1: Provide a substrate of a first conductivity type, the substrate having a terminal region and a unit cell region located in a high voltage region, forming a buried layer of a second conductivity type on the terminal region and the unit cell region, then forming an epitaxial layer on the substrate, and forming a deep doped well of the second conductivity type on the epitaxial layer; Step 2: A shallow trench isolation is formed on the epitaxial layer to define the active region of the LDMOS device, and a deep trench isolation is formed on the epitaxial layer and the substrate to form isolation for the termination region and the unit cell region; Step 3: Using ion implantation, a body region of the first conductivity type and a drift region of the second conductivity type are formed on the terminal region and the unit cell region, with a lateral spacing between the body region and the drift region. A doped well of the second conductivity type is formed on the deep doped well on the terminal region. The deep doped well in the terminal region is not in contact with the drift region, while the deep doped well in the unit cell region is in contact with the drift region. Step 4: Form a gate dielectric layer and a gate polysilicon layer on the gate dielectric layer, and form sidewalls on the gate dielectric layer and the gate polysilicon layer. One end of the gate dielectric layer and the gate polysilicon layer extends to the body region, and the other end extends to the shallow trench isolation on the adjacent drift region. Step 5: Form heavily doped regions on the doped well, the body region, and the drift region using ion implantation of the second conductivity type; wherein, the deep doped well, the doped well, and the heavily doped region on the terminal region serve as the lead-out structure of the buried layer, the heavily doped region on the drift region serves as the drain, and the heavily doped region on the body region serves as the source, such that the drift region doping concentration of the drain of the LDMOS in the unit cell region is greater than the drift region doping concentration of the drain of the LDMOS in the terminal region.

11. The method for manufacturing the structure for improving the breakdown voltage of LDMOS according to claim 10, characterized in that: The substrate mentioned in step one is a silicon substrate.

12. The method for manufacturing the structure for improving the breakdown voltage of LDMOS according to claim 10, characterized in that: An NLDMOS device is formed on the substrate in step one, wherein the first conductivity type of the NLDMOS device is P-type and the second conductivity type is N-type.

13. The method for manufacturing the structure for improving the breakdown voltage of LDMOS according to claim 10, characterized in that: A PLDMOS device is formed on the substrate in step one, wherein the first conductivity type of the PLDMOS device is N-type and the second conductivity type is P-type.

14. The method for manufacturing the structure for improving the breakdown voltage of LDMOS according to claim 10, characterized in that: In step one, an LDMOS device is formed in the terminal region.

15. The method for manufacturing the structure for improving the breakdown voltage of LDMOS according to claim 10, characterized in that: In step one, the two adjacent LDMOS devices in the terminal region and the unit cell region share the same body region.

16. The method for manufacturing the structure for improving the breakdown voltage of LDMOS according to claim 10, characterized in that: The material of the gate dielectric layer in step four is silicon dioxide.

17. The method for manufacturing the structure for improving the breakdown voltage of LDMOS according to claim 16, characterized in that: In step four, the gate dielectric layer is formed using a thermal oxidation method.

18. The method for manufacturing the structure for improving the breakdown voltage of LDMOS according to claim 10, characterized in that: Step four also includes: forming a sidewall material layer covering the sidewalls of the gate polysilicon layer; and etching back the sidewall material layer to form sidewalls located on both sides of the gate polysilicon layer.

19. The method for manufacturing the structure for improving the breakdown voltage of LDMOS according to claim 10, characterized in that: The material of the sidewall in step four is silicon dioxide.

20. The method for manufacturing the structure for improving the breakdown voltage of LDMOS according to claim 10, characterized in that: Step five also includes forming a body region extraction region located on the body region using ion implantation of the first conductivity type.

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