A CMOS APD device and its fabrication method

Abstract

The application provides a CMOS APD device and a preparation method thereof. The CMOS APD device comprises a first conductive type substrate, an isolation ring structure, an active region, a first conductive type doped region and a first conductive type contact region. The isolation ring structure comprises a first isolation ring and a second isolation ring which are embedded in the upper layer of the substrate and are arranged at intervals. The active region is located between the second isolation ring and comprises a first conductive type well region located in the upper layer of the substrate and a second conductive type doped layer located on the upper surface of the first conductive type well region. The doped region is located between the first isolation ring and the second isolation ring and has a bottom surface lower than that of the first conductive type well region. The contact region is located in the upper layer of the doped region. The application sets the doped region between the first isolation ring and the second isolation ring, the bottom surface of the doped region is lower than that of the first conductive type well region, and the doping concentration of the doped region and the first conductive type well region is higher than that of the substrate, thereby reducing the influence of temperature on the dark current of the device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a CMOS APD device and its fabrication method. Background Technology

[0002] An avalanche photodiode (APD) is a photodetector capable of achieving high sensitivity and high bandwidth. It utilizes avalanche breakdown to absorb light signals in the depletion layer, thereby generating a multiplied number of electrons and holes. The basic design technology of a complementary metal-oxide-semiconductor avalanche photodiode (CMOS APD) is similar to that of a conventional PN junction, but new design techniques are employed to effectively reduce dark current and improve the signal-to-noise ratio of optical communication systems. Operating in the linear region, CMOS APDs are widely used in the Internet of Things (IoT), CD-ROMs, DVDs, and Blu-ray discs due to their low voltage and low cost.

[0003] Isolation processes for CMOS APD devices can be divided into two types. One is Local Oxidation of Silicon (LOCOS), which uses silicon nitride as a mask to selectively oxidize silicon. In this process, a thick oxide layer, called the isolation or field oxide layer, is grown on all heavily doped silicon regions except for the active transistor region. However, when CMOS processes reach 0.25μm, LOCOS has drawbacks. First, the beak effect wastes space; second, the large height difference in surface topography necessitates a very thick interlayer dielectric (ILD), limiting the size of contact holes. The other type is Shallow Trench Isolation (STI) guard ring technology, which has advantages such as low process temperature, no beak effect, and good surface planarization, making it the main isolation technology for complementary metal-oxide-semiconductor (CMOS) devices. This design technology is widely used in CMOS manufacturing, but it can affect photocurrent when used in APDs.

[0004] In high-sensitivity sensors composed of CMOS APD devices operating in linear mode, the photoelectric effect and avalanche multiplication effect are used to detect and amplify optical signals. Recent research on CMOS APD devices has focused on designing low-dark-current APD devices using different APD structure design techniques, as well as research on large-scale APD arrays and their signal processing circuits. Both of these efforts require further optimization of CMOS APD device design techniques and performance, and further reduction of device dark current. Traditional APD device design techniques typically incorporate shallow trench isolation (STI) guard rings at both the anode and cathode sides for optimization, such as... Figure 1 The diagram shown is a cross-sectional view of a CMOS APD device. The CMOS APD device includes a substrate 01, an isolation ring structure 02, a first isolation ring 021, a first isolation trench 0211, a first isolation layer 0212, a second isolation ring 022, a second isolation trench 0221, a second isolation layer 0222, an active region 03, a second conductivity type well region 031, and a contact region 04. The drift distance of photogenerated electron carriers, the proper use of the STI guard ring, and the influence of temperature on dark current are ignored. Therefore, it is not possible to achieve the effect of ensuring that the photocurrent is detected while maintaining a low dark current.

[0005] Therefore, there is an urgent need to find a CMOS APD device that can ensure the photocurrent can be detected and reduce the effect of temperature on the dark current of the device. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a CMOS APD device and its fabrication method, so as to solve the problems of high temperature-dependent dark current and difficult-to-detect photocurrent in the prior art of CMOS APD devices.

[0007] To achieve the above and other related objectives, the present invention provides a CMOS APD device, comprising:

[0008] First conductivity type substrate;

[0009] The isolation ring structure includes a first isolation ring and a second isolation ring, both of which are embedded in the upper surface layer of the substrate, and the second isolation ring is spaced apart from the first isolation ring by a predetermined distance;

[0010] An active region is located between the second isolation rings. The active region includes a first conductivity type well region and a second conductivity type doped layer. The first conductivity type well region is located on the upper surface of the substrate. The second conductivity type doped layer is located on the upper surface of the first conductivity type well region. The sidewall of the second conductivity type doped layer is adjacent to the sidewall of the second isolation ring.

[0011] A first conductivity type doped region is located between the first isolation ring and the second isolation ring, and the bottom surface of the doped region is lower than the bottom surface of the first conductivity type well region;

[0012] The first type of conductive contact region is located on the upper surface of the doped region.

[0013] Optionally, the doping concentration of the substrate is in the range of 9 × 10⁻⁶. 11 cm -3 ~1.5×10 12 cm -3 .

[0014] Optionally, the bottom surface of the second isolation ring is higher than the bottom surface of the first isolation ring.

[0015] Optionally, the first isolation ring includes a first trench and a first isolation layer, and the second isolation ring includes a second trench and a second isolation layer.

[0016] Optionally, the doping concentration range of the first conductivity type well region is 5 × 10⁻⁶. 14 cm -3 ~2×10 15 cm -3 The thickness of the first conductivity type well region ranges from 0.8 μm to 1.2 μm, and the doping concentration of the second conductivity type doped layer ranges from 5 × 10⁻⁶. 18 cm -3 ~2×10 19 cm -3 The thickness of the second conductivity type doped layer ranges from 0.2 μm to 0.4 μm.

[0017] Optionally, the thickness of the doped region ranges from 3 μm to 4 μm, and the doping concentration of the doped region ranges from 5 × 10⁻⁶. 17 cm -3 ~2×10 18 cm -3 .

[0018] Optionally, the sidewalls of the doped region are spaced apart from the sidewalls of the first conductivity type well region.

[0019] Optionally, the CMOS APD further includes a cathode electrically connected to the second conductivity type doped layer and an anode electrically connected to the contact area, wherein the upper surface of the second conductivity type doped layer serves as the light receiving window of the CMOS APD device.

[0020] Optionally, the cathode is made of graphene, and the anode is made of graphene.

[0021] This invention also provides a method for fabricating a CMOS APD device, comprising the following steps:

[0022] Provide a substrate of a first conductivity type;

[0023] An isolation ring structure is formed on the upper surface of the substrate. The isolation ring structure includes a first isolation ring and a second isolation ring. The second isolation ring is spaced apart from the first isolation ring by a predetermined distance. The area between the second isolation rings is used as an active region.

[0024] A first conductivity type well region and a second conductivity type doped layer are sequentially formed in the active region. The first conductivity type well region is located on the upper surface of the active region, and the second conductivity type doped layer is located on the upper surface of the first conductivity type well region. The sidewall of the second conductivity type doped layer is adjacent to the sidewall of the second isolation ring.

[0025] A first conductivity type doped region is formed in the substrate between the first isolation ring and the second isolation ring, and the bottom surface of the doped region is lower than the bottom surface of the first conductivity type well region;

[0026] A first type of conductive contact region is formed on the upper surface layer of the doped region.

[0027] As described above, the CMOS APD device and its fabrication method of the present invention, by setting the doping concentration of the first conductivity type well region and the second conductivity type doped layer, specifically by using the heavily doped second conductivity type doped layer to reduce the vertical width of the depletion layer on the second conductivity type doped layer side of the PN junction, and by using the restriction of the second isolation ring to reduce the lateral width of the depletion layer, makes the potential barrier of the depletion layer higher and the energy band steeper, reducing the probability of interband tunneling of charge carriers, reducing diffusion current, and thus reducing the dark current of the device; by using the doped region located below the anode and having a deeper depth to absorb minority carriers of the substrate, reducing the number of diffused charge carriers in the substrate surrounding the active region entering the depletion layer, thereby reducing the dark current of the device; and by using the concentration difference between the substrate and the first conductivity type well region to form a potential barrier, further reducing the number of diffused charge carriers in the substrate entering the depletion layer, thereby reducing the influence of temperature on the dark current of the device, it has high industrial application value. Attached Figure Description

[0028] Figure 1 The diagram shows a cross-sectional structure of a CMOS APD device.

[0029] Figure 2 The diagram shown is a cross-sectional view of the CMOS APD device of the present invention.

[0030] Figure 3The diagram shown is a three-dimensional structural schematic of the CMOS APD device of the present invention.

[0031] Figure 4 The diagram shows the process flow of the fabrication method of the CMOS APD device of the present invention.

[0032] Figure 5 The diagram shows a cross-sectional structure of the substrate used in the fabrication method of the CMOS APD device of the present invention.

[0033] Figure 6 The diagram shows a cross-sectional structure after the formation of the first trench in the fabrication method of the CMOS APD device of the present invention.

[0034] Figure 7 The diagram shows a cross-sectional structure after the formation of the first isolation layer in the fabrication method of the CMOS APD device of the present invention.

[0035] Figure 8 The diagram shows a cross-sectional structure after the formation of the second isolation ring, which is a method for fabricating the CMOS APD device of the present invention.

[0036] Figure 9 The diagram shows a cross-sectional structure after forming a first conductivity type well region, which is a method for fabricating the CMOS APD device of the present invention.

[0037] Figure 10 The diagram shown is a cross-sectional view of the CMOS APD device fabrication method of the present invention after forming a second conductivity type doped layer.

[0038] Figure 11 The diagram shows a cross-sectional structure of the CMOS APD device fabrication method of the present invention after the formation of the doped region.

[0039] Figure 12 The diagram shows a cross-sectional structure of the CMOS APD device fabrication method of the present invention after the contact area is formed.

[0040] Explanation of icon numbers

[0041] 01 Substrate

[0042] 02 Isolation Ring Structure

[0043] 021 First Isolation Ring

[0044] 0211 First Isolation Trench

[0045] 0212 First Isolation Layer

[0046] 022 Second Isolation Ring

[0047] 0221 Second Isolation Trench

[0048] 0222 Second Isolation Layer

[0049] 03 Active Zone

[0050] 031 Second type of conductivity well region

[0051] 04 Contact Area

[0052] 1 Substrate

[0053] 2. Isolation ring structure

[0054] 21 First Isolation Ring

[0055] 211 First Isolation Trench

[0056] 212 First Isolation Layer

[0057] 22 Second Isolation Ring

[0058] 221 Second isolation trench

[0059] 222 Second Isolation Layer

[0060] 3 Active Region

[0061] 31 First type of conductivity well region

[0062] 32 Second conductivity type doped layer

[0063] 4 Doped Region

[0064] 41 Contact Area

[0065] 5 Cathode

[0066] 6 Anode Detailed Implementation

[0067] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0068] Please see Figures 2 to 12 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0069] Example 1

[0070] This embodiment provides a CMOS APD device, such as Figure 2 and Figure 3 The figures shown are a cross-sectional view of the CMOS APD device and a schematic diagram of the CMOS APD device. A three-dimensional structural diagram of an APD device includes: a substrate of a first conductivity type 1, an isolation ring structure 2, an active region 3, a doped region of a first conductivity type 4, and a contact region of a first conductivity type 41. The isolation ring structure 2 includes a first isolation ring 21 and a second isolation ring 22, both embedded in the upper surface of the substrate 1, with the second isolation ring 22 spaced a predetermined distance from the first isolation ring 21. The active region 3 is located between the second isolation rings 22, and includes a first conductivity type well region 31 and a second conductivity type doped layer 32. The first conductivity type well region 31 is located on the upper surface of the substrate 1, and the second conductivity type doped layer 32 is located on the upper surface of the first conductivity type well region 31, with the sidewall of the second conductivity type doped layer 32 adjacent to the sidewall of the second isolation ring 22. The doped region 4 is located between the first isolation ring 21 and the second isolation ring 22, with the bottom surface of the doped region 4 lower than the bottom surface of the first conductivity type well region 31. The contact region 41 is located on the upper surface of the doped region 4.

[0071] Specifically, the first conductivity type includes either N-type or P-type, and the second conductivity type includes either N-type or P-type, with the first conductivity type and the second conductivity type being opposite in nature. In this embodiment, the first conductivity type is P-type, and the second conductivity type is N-type.

[0072] Specifically, the substrate 1 is made of silicon, silicon germanium, silicon carbide, or other suitable semiconductor materials. In this embodiment, the substrate 1 is a silicon substrate.

[0073] Specifically, depending on the material of the substrate 1, the size and doping concentration of the first conductive type well region 31, the second conductive type doped layer 32, and the doped region 4 can be selected using simulation results.

[0074] As an example, the doping concentration of the substrate 1 ranges from 9 × 10⁻⁶. 11 cm -3 ~1.5×10 12 cm -3 In this embodiment, the doping concentration of the substrate 1 is 1.2 × 10⁻⁶. 12 cm -3 .

[0075] As an example, the bottom surface of the second isolation ring 22 is higher than the bottom surface of the first isolation ring 21, so that the photogenerated carriers in the depletion layer of the active region 3 can drift to the anode 6. Under the condition that the detection area remains unchanged, the detectability of the photocurrent generated by the incident light is guaranteed, while the dark current of the device is reduced.

[0076] As an example, the first isolation ring 21 includes a first isolation trench 211 and a first isolation layer 212, the first isolation layer 212 filling the first isolation trench 211, and the second isolation ring 22 includes a second isolation trench 221 and a second isolation layer 222, the second isolation layer 222 filling the second isolation trench 221.

[0077] Specifically, while ensuring device performance, and provided that the bottom surface of the second isolation trench 221 is lower than the contact surface between the first conductivity type well region 31 and the second conductivity type doped layer 32, the depth of the second isolation trench 221 can be set according to actual conditions, and is not limited here.

[0078] Specifically, the first isolation ring 21 is located outside the second isolation ring 22. The second isolation ring 22 is used to make the electric field distribution of the depletion layer in the active region 3 uniform, so that the electric field distribution of the depletion layer between the second conductivity type doped layer 32 and the first conductivity type well region 31 is uniform, and to prevent diffusion current from entering the depletion layer. This avoids edge breakdown at the edge of the active region 3 due to the lack of protection of the second isolation ring 22, which would cause the electric field of the depletion layer to be unevenly distributed and affect the performance of the device.

[0079] Specifically, since the sidewall of the second conductivity type well region 32 is adjacent to the sidewall of the second isolation ring 22, the second isolation ring 22 restricts the lateral width of the depletion layer in the active region 3. Here, lateral refers to the horizontal direction parallel to the upper surface of the substrate 1.

[0080] Specifically, the bottom surface of the second isolation trench 221 is lower than the contact surface between the first conductivity type well region 31 and the second conductivity type doped layer 32, so that the photogenerated carriers generated at the PN junction between the second conductivity type doped layer 32 and the first conductivity type well region 31 can drift to the anode 6, while preventing the edge of the PN junction from breaking down prematurely and affecting the performance of the device.

[0081] Specifically, provided that the device performance is guaranteed and the depth of the second isolation trench 221 is less than the depth of the first isolation trench 211, the depth of the first isolation trench 211 can be set according to the actual situation, and is not limited here. The depth here refers to the distance from the bottom surface of the first isolation trench 211 to the upper surface of the substrate 1.

[0082] Specifically, the material of the first isolation layer 212 includes silicon oxide, silicon nitride, or other suitable dielectric materials.

[0083] Specifically, the material of the second isolation layer 222 includes silicon oxide, silicon nitride, or other suitable dielectric materials.

[0084] As an example, the doping concentration range of the first conductivity type well region 31 is 5 × 10⁻⁶. 14 cm -3 ~2×10 15 cm -3 The thickness of the first conductivity type well region 31 ranges from 0.8 μm to 1.2 μm, and the doping concentration of the second conductivity type doped layer 32 ranges from 5 × 10⁻⁶. 18 cm -3 ~2×10 19 cm -3 The thickness of the second conductivity type doped layer 32 ranges from 0.2 μm to 0.4 μm. In this embodiment, the doping concentration of the first conductivity type well region 31 is 1.3 × 10⁻⁶. 15 cm -3 The thickness of the first conductivity type well region 31 is 1 μm, and the doping concentration of the second conductivity type doped layer 32 is 1.5 × 10⁻⁶. 19 cm -3 The thickness of the second conductivity type doped layer 32 is 0.3 μm. Here, the thickness of the first conductivity type well region 31 refers to the longitudinal distance between the upper surface of the first conductivity type well region 31 and the lower surface of the first conductivity type well region 31, and the thickness of the second conductivity type doped layer 32 refers to the longitudinal distance between the upper surface of the second conductivity type doped layer 32 and the lower surface of the second conductivity type doped layer 32.

[0085] Specifically, because the doping concentration of the second conductivity type doped layer 32 is relatively high, the longitudinal width of the depletion layer (space charge region) on the side of the PN junction of the second conductivity type doped layer 32 in the active region 3 is narrow. Consequently, the longitudinal width of the depletion layer in the active region 3 is narrow, the barrier height of the depletion layer is high, and the PN junction formed by the high doping concentration of the second conductivity type doped layer 32 and the low doping concentration of the first conductivity type well region 31 is a non-unilateral abrupt junction. The energy band of the depletion layer is steep, making it difficult for diffused carriers to tunnel between bands, thereby reducing the transit of diffused carriers and lowering the dark current of the device.

[0086] As an example, the depth of the doped region 4 ranges from 3 μm to 4 μm, and the doping concentration of the doped region 4 ranges from 5 × 10⁻⁶. 17 cm -3 ~2×10 18cm -3 Here, "depth" refers to the distance between the upper surface of the substrate 1 and the lower surface of the doped region 4. In this embodiment, the depth of the doped region 4 is 3.5 μm, and the doping concentration is 1.3 × 10⁻⁶. 18 cm -3 .

[0087] Specifically, the bottom surface of the doped region 4 is spaced apart from the lower surface of the substrate 1. While ensuring device performance, the distance between the bottom surface of the doped region 4 and the substrate 1 can be selected according to the actual situation, and is not limited here.

[0088] As an example, the sidewall of the doped region 4 is spaced apart from the sidewall of the first conductivity type well region 31 to prevent diffused carriers in the substrate 1 from entering the first conductivity type well region 31 through the doped region 4.

[0089] Specifically, while ensuring device performance, the distance between the sidewall of the doped region 4 and the sidewall of the first conductivity type well region 31 can be set according to the actual situation, and is not limited here.

[0090] As an example, the bottom surface of the contact area 41 is higher than the bottom surface of the first isolation ring 21.

[0091] Specifically, the contact area 41 is used to reduce the internal resistance of the device, which facilitates the detection of photogenerated carriers.

[0092] Specifically, to ensure device performance, the doping concentration of the contact area 41 can be set according to the actual situation, and is not limited here.

[0093] Specifically, while ensuring device performance, the thickness of the contact area 41 can be set according to actual conditions, and is not limited here. The thickness here refers to the distance between the upper surface and the lower surface of the contact area 41.

[0094] As an example, the CMOS APD also includes a cathode 5 electrically connected to the second conductivity type doped layer 32 and an anode 6 electrically connected to the contact region 41, wherein the upper surface of the second conductivity type doped layer 32 serves as the light receiving window of the CMOS APD device.

[0095] Specifically, when light is incident on the light receiving window, it is absorbed by the PN junction region (light absorption region) between the first conductivity type well region 31 and the second conductivity type doped layer 32, and photogenerated carriers (electron-hole pairs) are generated. The photogenerated carriers separate under the action of the built-in electric field to form electrons and holes. The electrons drift to the avalanche region under the action of the reverse external electric field to participate in multiplication.

[0096] Specifically, since the upper surface of the contact region 41 is flush with the upper surface of the second conductivity type doped layer 32, the contact region 41 is located on the upper surface of the doped region 4, the second conductivity type doped layer 32 is located on the upper surface of the first conductivity type well region 31, and the bottom surface of the doped region 4 is lower than the bottom surface of the first conductivity type well region 31, a potential barrier is formed between the doped region 4 and the substrate 1, reducing the diffusion of charge carriers in the substrate 1 to the depletion layer in the active region 3, and at the same time reducing the dark current of the device.

[0097] Specifically, when the temperature rises, the carrier concentration in the substrate 1 surrounding the active region 3 increases, resulting in an increase in the amount of diffused carriers in the device. The doped region 4 absorbs the carriers in the substrate 1 surrounding the active region 3, and the potential barrier formed by the concentration difference between the first conductivity type well region 31 and the substrate 1 reduces the number of carriers in the substrate 1 that diffuse into the depletion layer, thereby reducing the effect of temperature on the dark current of the device.

[0098] As an example, the cathode 5 may be made of graphene or other suitable materials, and the anode 6 may be made of graphene or other suitable materials. In this embodiment, both the anode 6 and the cathode 5 are made of graphene.

[0099] Specifically, since graphene is a transparent material, using graphene for both the cathode 5 and the anode 6 can avoid blocking incident light, reduce light loss, and at the same time reduce the capacitance of the device, making it easier to integrate the device.

[0100] In this embodiment, the CMOS APD device reduces the longitudinal width of the depletion layer near the PN junction between the second conductivity type doped layer 32 and the first conductivity type well region 31 by increasing the doping concentration of the second conductivity type doped layer 32. This results in a higher potential barrier and steeper band structure in the depletion layer, reducing the probability of interband tunneling of carriers, decreasing the transit of diffuse carriers, and lowering the dark current of the device. Furthermore, by utilizing the fact that the bottom surface of the doped region 4 is higher than the bottom surface of the first conductivity type well region 31, and the sidewalls of the doped region 4 are spaced apart from the sidewalls of the first conductivity type well region 31 by a predetermined distance, and the doping concentration of the substrate 1 is lower than that of the doped region 4 and the first conductivity type well region 31, the doped region 4 absorbs carriers from the substrate 1 surrounding the active region 3, reducing the number of diffuse carriers from the substrate 1 entering the depletion layer of the active region 3. The doping concentration difference between the first conductivity type well region 31 and the substrate 1 forms a potential barrier, further reducing the number of diffuse carriers from the substrate 1 entering the depletion layer of the active region 3, thereby reducing the influence of temperature on the dark current.

[0101] Example 2

[0102] This embodiment provides a method for fabricating a CMOS APD device, such as... Figure 4 The diagram shows a flowchart of the fabrication method for the CMOS APD device, including the following steps:

[0103] S1: Provides a substrate of a first conductivity type;

[0104] S2: An isolation ring structure is formed on the upper surface of the substrate. The isolation ring structure includes a first isolation ring and a second isolation ring. The second isolation ring is spaced apart from the first isolation ring by a preset distance. The area between the second isolation rings is used as an active region.

[0105] S3: A first conductivity type well region and a second conductivity type doped layer are sequentially formed in the active region. The first conductivity type well region is located on the upper surface of the active region, and the second conductivity type doped layer is located on the upper surface of the first conductivity type well region. The sidewall of the second conductivity type doped layer is adjacent to the sidewall of the second isolation ring.

[0106] S4: A first conductivity type doped region is formed in the substrate between the first isolation ring and the second isolation ring, and the bottom surface of the doped region is lower than the bottom surface of the first conductivity type well region;

[0107] S5: A first conductive contact region is formed on the upper surface layer of the doped region.

[0108] Please see Figures 5 to 8 The steps S1 and S2 are performed as follows: a first conductivity type substrate 1 is provided; an isolation ring structure 2 is formed on the upper surface of the substrate 1, the isolation ring structure 2 includes a first isolation ring 21 and a second isolation ring 22, and the area between the second isolation ring 22 and the first isolation ring 21 at a predetermined distance is used as an active region 3.

[0109] Specifically, such as Figure 5 The diagram shown is a cross-sectional view of the substrate 1. The thickness of the substrate 1 can be selected according to actual conditions while ensuring device performance, and is not limited here.

[0110] Specifically, the first isolation ring 21 includes a first isolation trench 221 located in the substrate 1 with an upward opening and a first isolation layer 212 filling the first isolation trench 221, and the second isolation ring 22 includes a second isolation trench 221 located in the substrate 1 with an upward opening and a second isolation layer 222 filling the second isolation trench 221.

[0111] Specifically, such as Figure 6 and Figure 7The diagrams shown are cross-sectional views of the first isolation trench 211 and the first isolation layer 212, respectively. The formation of the isolation ring structure 2 includes the following steps: forming a patterned first photoresist layer on the upper surface of the substrate 1; forming the first isolation trench 221 based on the patterned first photoresist layer, and forming the first isolation layer 212 in the first isolation trench 221; forming a patterned second photoresist layer on the upper surface of the substrate 1, forming the second isolation trench 221 based on the patterned second photoresist layer, and forming the second isolation layer 222 in the second isolation trench 221.

[0112] Specifically, without affecting device performance, during the formation of the isolation ring structure 2, the second isolation trench 221 can be formed first, and then the first isolation trench 221 can be formed.

[0113] Specifically, without affecting device performance, during the formation of the isolation ring structure 2, the first isolation trench 221 and the second isolation trench 221 can be formed simultaneously with the formation of the first isolation layer 212 and the second isolation layer 222.

[0114] Specifically, the method for forming the first isolation trench 221 includes dry etching, wet etching, or other suitable methods; the method for forming the second isolation trench 221 includes dry etching, wet etching, or other suitable methods.

[0115] Specifically, the method for forming the first isolation layer 212 includes chemical vapor deposition, physical vapor deposition, or other suitable methods; the method for forming the second isolation layer 222 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0116] Specifically, such as Figure 8 As shown, this is a cross-sectional structural diagram after the second isolation ring 22 is formed. The bottom surface of the second isolation ring 22 is higher than the bottom surface of the first isolation ring 21, so that the photogenerated carriers generated in the active region 3 can drift to the anode 6.

[0117] Please see again Figures 9 to 12Then, perform steps S3, S4, and S5: A first conductivity type well region 31 and a second conductivity type doped layer 32 are sequentially formed in the active region 3. The first conductivity type well region 31 is located on the upper surface of the active region 3, and the second conductivity type doped layer 32 is located on the upper surface of the first conductivity type well region 31, with the sidewall of the second conductivity type doped layer 32 adjacent to the sidewall of the second isolation ring 22; a first conductivity type doped region 4 is formed in the substrate 1 between the first isolation ring 21 and the second isolation ring 22, with the bottom surface of the doped region 4 lower than the bottom surface of the first conductivity type well region 31; a first conductivity type contact region 41 is formed on the upper surface of the doped region 4.

[0118] Specifically, such as Figure 9 and Figure 10 The figures shown are cross-sectional structural diagrams after the formation of the first conductivity type well region 31 and the second conductivity type doped layer 32, respectively. The formation of the first conductivity type well region 31 and the second conductivity type doped layer 32 includes the following steps: forming a patterned first masking layer (not shown) on the upper surface of the substrate 1, and forming the first conductivity type well region 31 based on the patterned first masking layer; forming the second conductivity type doped layer 32 on the upper surface layer of the first conductivity type well region 31 based on the patterned first masking layer.

[0119] Specifically, the first shielding layer can be a photoresist layer, a mask layer, or a composite layer of a photoresist layer and a mask layer. The appropriate layer can be selected based on the actual situation while ensuring device performance.

[0120] Specifically, the method for forming the first conductivity type well region 31 includes ion implantation or other suitable methods; the method for forming the second conductivity type doped layer 32 includes ion implantation or other suitable methods.

[0121] Specifically, such as Figure 11 and Figure 12 The figures show cross-sectional view of the doped region 4 after its formation and cross-sectional view of the contact region 41 after its formation. The formation of the doped region 4 includes the following steps: forming a patterned second shielding layer (not shown) on the upper surface of the substrate 1; forming the doped region 4 in the substrate 1 between the first isolation ring 21 and the second isolation ring 22 based on the patterned second shielding layer; and forming the contact region 41 on the upper surface of the doped region 4 based on the patterned second shielding layer.

[0122] Specifically, the second masking layer can be a photoresist layer, a mask layer, or a composite layer of a photoresist layer and a mask layer. The appropriate layer can be selected based on the actual situation while ensuring device performance.

[0123] Specifically, the method for forming the doped region 4 includes ion implantation or other suitable methods; the method for forming the contact region 41 includes ion implantation or other suitable methods.

[0124] Specifically, the doping concentration of the doped region 4 is higher than that of the substrate 1, and the doping concentration of the first conductivity type well region 31 is higher than that of the substrate 1.

[0125] Specifically, the sidewall of the formed doped region 4 is spaced at a predetermined distance from the sidewall of the first conductivity type well region 31.

[0126] Specifically, as the temperature increases, the carrier concentration in the substrate 1 increases, increasing the diffusion current in the device. Since the bottom surface of the doped region 4 is lower than the bottom surface of the first conductivity type well region 31, the doped region 4 absorbs minority carriers in the substrate 1 surrounding the active region 3, reducing the number of diffused carriers entering the active region 3. The doping concentration difference between the first conductivity type well region 31 and the substrate 1 forms a potential barrier, further reducing the number of carriers in the substrate entering the depletion layer in the active region 3. This can reduce the impact of temperature on the dark current of the device.

[0127] Specifically, such as Figure 2 and Figure 3 The figures shown are a cross-sectional view of the cathode 5 and the anode 6 after their formation and a three-dimensional view of the cathode 5 and the anode 6 after their formation. After the contact area 41 is formed, the method further includes the steps of forming the anode 6 electrically connected to the contact area 41 and the cathode 5 electrically connected to the second conductivity type doped layer 32.

[0128] Specifically, the method for forming the cathode 5 and the anode 6 is a conventional method, which will not be described in detail here.

[0129] The fabrication method of the CMOS APD device in this embodiment involves forming the doped region 4 in the substrate 1 between the first isolation ring 21 and the second isolation ring 22, with the bottom surface of the doped region 4 being lower than the bottom surface of the first conductivity type well region 31. The sidewalls of the first conductivity type well region 31 and the sidewalls of the doped region 4 are spaced apart by a predetermined distance. The doped region 4 absorbs minority carriers in the substrate 1, reducing the number of diffused carriers entering the depletion layer in the active region 3. At the same time, the potential barrier between the first conductivity type well region 31 and the substrate 1 further reduces the number of carriers in the substrate 1 diffusing into the depletion layer in the active region 3, thereby reducing the influence of temperature on the device's dark current.

[0130] In summary, the CMOS APD device and its fabrication method of the present invention reduce the longitudinal width of the depletion layer on the second conductivity type doped layer side of the PN junction by increasing the doping concentration of the second conductivity type doped layer in the active region. This reduces the longitudinal width of the depletion layer in the active region, raises the potential barrier of the depletion layer, and makes the band structure steeper, thereby reducing the probability of interband tunneling of charge carriers and reducing the transit of diffusion current, thus reducing the dark current of the device. Furthermore, a doped region with a higher concentration than the substrate is set between the first and second isolation rings around the active region, and the bottom surface of the doped region is lower than the bottom surface of the first conductivity type well region. This allows the doped region to absorb charge carriers from the substrate surrounding the active region, reducing the number of diffused charge carriers from the substrate entering the depletion layer. Simultaneously, the concentration difference between the first conductivity type well region and the substrate forms a potential barrier, further reducing the number of charge carriers between the first conductivity type well region and the doped region entering the depletion layer, thus reducing the influence of temperature on the device's dark current. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0131] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A CMOS APD device, characterized in that, include: a first conductivity type substrate having a doping concentration ranging from 9 x 1018to 1.5 x 1019cm-3 11 cm -3 -3to 1.5 x 1019cm-3 12 cm -3 ; The isolation ring structure includes a first isolation ring and a second isolation ring, both of which are embedded in the upper surface layer of the substrate, and the second isolation ring is spaced apart from the first isolation ring by a predetermined distance; An active region is located between the second isolation rings. The active region includes a first conductivity type well region and a second conductivity type doped layer. The first conductivity type well region is located on the upper surface of the substrate, and the second conductivity type doped layer is located on the upper surface of the first conductivity type well region. The sidewall of the second conductivity type doped layer is adjacent to the sidewall of the second isolation ring. The doping concentration of the first conductivity type well region is in the range of 5 × 10⁻⁶. 14 cm -3 ~2×10 15 cm -3 The doping concentration range of the second conductivity type doped layer is 5 × 10⁻⁶. 18 cm -3 ~2×10 19 cm -3 ; A first conductivity type doped region is located between the first isolation ring and the second isolation ring. The bottom surface of the doped region is lower than the bottom surface of the first conductivity type well region. The doping concentration range of the doped region is 5 × 10⁻⁶. 17 cm -3 ~2×10 18 cm -3 The sidewalls of the doped region are spaced apart from the sidewalls of the first conductivity type well region; The first type of conductive contact region is located on the upper surface of the doped region.

2. The CMOS APD device according to claim 1, characterized in that: The bottom surface of the second isolation ring is higher than the bottom surface of the first isolation ring.

3. The CMOS APD device according to claim 1, characterized in that: The first isolation ring includes a first trench and a first isolation layer, and the second isolation ring includes a second trench and a second isolation layer.

4. The CMOS APD device according to claim 1, characterized in that: The thickness of the first conductivity type well region ranges from 0.8 μm to 1.2 μm, and the thickness of the second conductivity type doped layer ranges from 0.2 μm to 0.4 μm.

5. The CMOS APD device according to claim 1, characterized in that: The depth range of the doped region is 3 μm to 4 μm.

6. The CMOS APD device according to claim 1, characterized in that: The CMOS APD also includes a cathode electrically connected to the second conductivity type doped layer and an anode electrically connected to the contact area, wherein the upper surface of the second conductivity type doped layer serves as the light receiving window of the CMOS APD device.

7. The CMOS APD device according to claim 6, characterized in that: The cathode is made of graphene, and the anode is made of graphene.

8. A method for fabricating a CMOS APD device, characterized in that, Includes the following steps: A substrate of a first conductivity type is provided, wherein the doping concentration of the substrate is in the range of 9 × 10⁻⁶. 11 cm -3 ~1.5×10 12 cm -3 ; An isolation ring structure is formed on the upper surface of the substrate. The isolation ring structure includes a first isolation ring and a second isolation ring. The second isolation ring is spaced apart from the first isolation ring by a predetermined distance. The area between the second isolation rings is used as an active region. A first conductivity type well region and a second conductivity type doped layer are sequentially formed in the active region. The first conductivity type well region is located on the upper surface of the active region, and the second conductivity type doped layer is located on the upper surface of the first conductivity type well region. The sidewall of the second conductivity type doped layer is adjacent to the sidewall of the second isolation ring. The doping concentration of the first conductivity type well region is in the range of 5 × 10⁻⁶. 14 cm -3 ~2×10 15 cm -3 The doping concentration range of the second conductivity type doped layer is 5 × 10⁻⁶. 18 cm -3 ~2×10 19 cm -3 ; A first conductivity type doped region is formed in the substrate between the first isolation ring and the second isolation ring, the bottom surface of the doped region being lower than the bottom surface of the first conductivity type well region, and the doping concentration of the doped region being 5 × 10⁻⁶. 17 cm -3 ~2×10 18 cm -3 The sidewalls of the doped region are spaced apart from the sidewalls of the first conductivity type well region; A first type of conductive contact region is formed on the upper surface layer of the doped region.

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