A dutycycle adaptive transmission driver circuit

Abstract

The application discloses a duty cycle adaptive sending driving circuit, and relates to the field of automobile LIN communication systems; an input end of the sending driving circuit is connected with an MCU; an output end of the sending driving circuit is connected with a receiving circuit through a LIN bus; the sending driving circuit is used for receiving a data signal output by the MCU and sending the data signal to the receiving circuit through the LIN bus; a duty cycle detection circuit is connected with the receiving circuit and a first control end of the sending driving circuit respectively; the duty cycle detection circuit is used for detecting a high level duration of the data signal received by the receiving circuit and controlling a number of capacitances of a capacitance array in the sending driving circuit according to the high level duration, so as to guarantee correct transmission of the data signal. The application can resist interference from an automobile internal environment and make data normally transmitted.

Description

Technical Field

[0001] This invention relates to the field of automotive LIN communication systems, and in particular to a duty cycle adaptive transmission drive circuit. Background Technology

[0002] In LIN systems, to reduce electromagnetic emissions at high frequencies, the signal transmission rate (SR) on the LIN bus is subject to high requirements. Typically, the SR needs to be designed to be small to minimize electromagnetic energy during signal transmission. Advanced CMOS technology has become the mainstream trend due to its low power consumption, high speed, and high integration density. However, the SR is greatly affected by process technology, temperature, voltage, and the load on the LIN bus, making it sensitive to changes in the duty cycle during LIN bus signal transmission, further deteriorating the duty cycle of the RX output signal. Relying solely on the inherent characteristics of the process technology carries significant risks to signal transmission, potentially leading to bit errors or data loss. Summary of the Invention

[0003] The purpose of this invention is to provide a duty cycle adaptive transmission drive circuit that can resist interference from the automotive interior environment and ensure normal data transmission.

[0004] To achieve the above objectives, the present invention provides the following solution:

[0005] A duty cycle adaptive transmission drive circuit includes: a transmission drive circuit, a duty cycle detection circuit, and a receiving circuit;

[0006] The input terminal of the transmitting drive circuit is connected to the MCU, and the output terminal of the transmitting drive circuit is connected to the receiving circuit through the LIN bus; the transmitting drive circuit is used to receive the data signal output by the MCU and send the data signal to the receiving circuit through the LIN bus.

[0007] The duty cycle detection circuit is connected to the first control terminal of the receiving circuit and the transmitting drive circuit respectively; the duty cycle detection circuit is used to detect the high-level duration of the data signal received by the receiving circuit, and control the number of capacitors connected to the capacitor array in the transmitting drive circuit according to the high-level duration to ensure the correct transmission of the data signal.

[0008] Optionally, the transmitting drive circuit includes: a bias current digital control circuit, an SR control circuit, a first switch, a second switch, a third switch, a capacitor array, and a drive transistor;

[0009] The input terminal of the bias current digital control circuit is connected to power supply 1, the control terminal of the bias current digital control circuit is connected to the MCU, and the output terminal of the bias current digital control circuit is connected to the input terminal of the first switching transistor, the input terminal of the second switching transistor, and the gate terminal of the driving transistor, respectively. The bias current digital control circuit is used to control the magnitude of the current transmitted to the gate terminal of the driving transistor, so as to control the charging rate of the gate terminal capacitor of the driving transistor.

[0010] The output terminal of the first switch is connected to the first input terminal of the SR control circuit, and the output terminal of the first switch is also connected to the ground terminal; the other end of the second switch is connected to the second input terminal of the SR control circuit, the input terminal of the third switch, and the input terminal of the capacitor array, respectively, and the output terminals of the third switch and the capacitor array are both connected to the ground terminal; the control terminal of the SR control circuit is connected to the MCU, and the SR control circuit is used to adjust the data signal transmission rate;

[0011] The control terminal of the capacitor array is connected to the duty cycle detection circuit, and the capacitor array is used to control the turn-off rate of the driving transistor.

[0012] The control terminals of the first switch, the second switch, and the third switch all serve as input terminals of the transmitting drive circuit, connected to the MCU, and receive data signals sent by the MCU.

[0013] The collector of the driving transistor serves as the output of the transmitting driving circuit and is connected to the receiving circuit via a LIN bus. The emitter of the driving transistor is grounded through resistor R2.

[0014] Optionally, the control method for the duty cycle detection circuit includes:

[0015] The duty cycle detection circuit detects whether the duration of the received high level is greater than a preset threshold and obtains the first detection result.

[0016] If the first detection result is yes, the duty cycle detection circuit controls the capacitor array in the transmitting drive circuit to reduce the number of capacitors connected.

[0017] If the first detection result is negative, the duty cycle detection circuit controls the capacitor array in the transmitting drive circuit to increase the number of capacitors connected.

[0018] Optionally, the transmitting drive circuit further includes an overcurrent protection circuit;

[0019] The input terminal of the overcurrent protection circuit is connected to the output terminal of the bias current digital control circuit; the output terminal of the overcurrent protection circuit is connected to the source of the drive transistor.

[0020] The overcurrent protection circuit is used to protect the transmitting drive circuit.

[0021] Optionally, the bias current digital control circuit includes multiple current mirror groups;

[0022] The current mirror groups are connected in parallel;

[0023] The input terminal of the current mirror group is connected to power supply 1; the output terminal of the current mirror group is connected to the overcurrent protection circuit; the control terminal of the current mirror group is connected to the MCU; the output terminal of the current mirror group is connected to the input terminal of the first switching transistor, the input terminal of the second switching transistor, and the input terminal of the overcurrent protection circuit, respectively.

[0024] Optionally, the current mirror assembly includes a current mirror and a current mirror switching transistor;

[0025] The input terminal of the current mirror is connected to power supply 1; the output terminal of the current mirror is connected to the input terminal of the current mirror switching transistor; the control terminal of the current mirror switching transistor is connected to the MCU; the output terminal of the current mirror switching transistor is connected to the input terminal of the first switching transistor, the input terminal of the second switching transistor, and the input terminal of the overcurrent protection circuit, respectively.

[0026] Optionally, the SR control circuit includes a first transistor and a second transistor;

[0027] The gate of the first transistor is connected to the gate of the second transistor; the source of the first transistor is connected to the capacitor array; the drain of the first transistor is connected to the output terminal of the first switch; the source of the second transistor is connected to the other end of the second switch; the control terminals of both the first and second transistors are connected to the MCU.

[0028] Optionally, the capacitor array includes a first capacitor group and multiple second capacitor groups;

[0029] The first capacitor bank and multiple second capacitor banks are connected in parallel; the input terminal of the first capacitor bank is connected to the input terminal of the third switching transistor; the output terminals of the first capacitor bank and multiple second capacitor banks are all connected to the ground terminal; the control terminals of multiple second capacitor banks are all connected to the duty cycle detection circuit.

[0030] Optionally, the first capacitor bank includes a first capacitor; the second capacitor bank includes a second capacitor and a capacitor switching transistor.

[0031] The input terminal of the capacitor switch is connected to the duty cycle detection circuit; the output terminal of the capacitor switch is connected to the input terminal of the second capacitor.

[0032] The output terminals of the second capacitor and the first capacitor are both connected to the ground terminal; the input terminal of the first capacitor is connected to the input terminal of the third switching transistor.

[0033] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0034] This invention discloses a duty cycle adaptive transmitting drive circuit. The input terminal of the transmitting drive circuit is connected to an MCU, and the output terminal is connected to a receiving circuit via a LIN bus. The transmitting drive circuit receives data signals output by the MCU and transmits these data signals to the receiving circuit via the LIN bus. A duty cycle detection circuit is connected to the first control terminals of both the receiving circuit and the transmitting drive circuit. The duty cycle detection circuit detects the high-level duration of the data signal received by the receiving circuit and controls the number of capacitors connected to the capacitor array in the transmitting drive circuit based on the high-level duration to ensure correct data signal transmission. This invention can resist interference from the automotive interior environment, ensuring normal data transmission. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a first schematic diagram of the duty cycle adaptive transmission drive circuit in an embodiment of the present invention;

[0037] Figure 2 This is a second schematic diagram of the duty cycle adaptive transmission drive circuit in an embodiment of the present invention;

[0038] Figure 3 This is a control flowchart of the duty cycle adaptive transmission drive circuit in an embodiment of the present invention. Detailed Implementation

[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] The purpose of this invention is to provide a duty cycle adaptive transmission drive circuit that can resist interference from the automotive interior environment and ensure normal data transmission. This circuit is mainly used in automotive LIN communication systems to resist interference from the automotive interior environment during signal data transmission and ensure normal data transmission.

[0041] This invention can withstand harsh environments with high and low voltage from the LIN bus, preventing circuit damage from interference. Simultaneously, the LIN bus signal SR is adjustable during signal transmission, meeting the needs of various LIN bus application scenarios. The TX driver circuit is designed with a duty cycle adaptive detection function. By setting a duty cycle detection threshold, it ensures that the circuit operates at its lowest SR, and under different processes, temperatures, voltages, and LIN bus loads, signal transmission remains normal, and the duty cycle variation of the RX output signal is controlled within the set threshold range.

[0042] This invention uses a duty cycle detection function to control the number of capacitors connected to the capacitor array in the TX circuit, thereby achieving correct signal transmission.

[0043] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0044] like Figure 1 As shown, the duty cycle adaptive transmission drive circuit of the present invention includes: a transmission drive circuit, a duty cycle detection circuit, and a receiving circuit.

[0045] The input terminal of the transmitting drive circuit is connected to the MCU, and the output terminal of the transmitting drive circuit is connected to the receiving circuit via the LIN bus. The transmitting drive circuit is used to receive the data signal output by the MCU and send the data signal to the receiving circuit via the LIN bus.

[0046] like Figure 2 As shown, the transmission drive circuit includes: a bias current digital control circuit 00, an SR control circuit 20, a first switch sw5, a second switch sw6, a third switch sw7, a capacitor array 30, and a drive transistor M3.

[0047] The input terminal of the bias current digital control circuit 00 is connected to the power supply 1, the control terminal of the bias current digital control circuit 00 is connected to the MCU, and the output terminal of the bias current digital control circuit 00 is connected to the input terminal of the first switching transistor sw5, the input terminal of the second switching transistor sw6, and the gate terminal of the driving transistor M3, respectively. The bias current digital control circuit 00 is used to control the magnitude of the current transmitted to the gate terminal of the driving transistor M3, so as to control the charging rate of the gate terminal capacitor of the driving transistor M3.

[0048] The bias current digital control circuit 00 controls the current levels I1 to I4 by controlling the number of current mirrors.

[0049] like Figure 2 As shown, the bias current digital control circuit 00 includes multiple current mirror groups.

[0050] The current mirror groups are connected in parallel.

[0051] The input terminal of the current mirror group is connected to the power supply 1; the output terminal of the current mirror group is connected to the overcurrent protection circuit 10; the control terminal of the current mirror group is connected to the MCU; the output terminal of the current mirror group is connected to the input terminal of the first switching transistor SW5, the input terminal of the second switching transistor SW6, and the input terminal of the overcurrent protection circuit 10, respectively.

[0052] The current mirror assembly includes a current mirror and a current mirror switch.

[0053] The input terminal of the current mirror is connected to the power supply 1; the output terminal of the current mirror is connected to the input terminal of the current mirror switching transistor; the control terminal of the current mirror switching transistor is connected to the MCU; the output terminal of the current mirror switching transistor is connected to the input terminal of the first switching transistor SW5, the input terminal of the second switching transistor SW6, and the input terminal of the overcurrent protection circuit 10, respectively.

[0054] like Figure 2 As shown, the first current mirror I1 and the first current mirror switch sw1 are connected to form the first current mirror group, the second current mirror I2 and the second current mirror switch sw2 are connected to form the second current mirror group, the third current mirror I3 and the third current mirror switch sw3 are connected to form the third current mirror group, and the fourth current mirror I4 and the fourth current mirror switch sw4 are connected to form the fourth current mirror group; the first current mirror group to the fourth current mirror group are connected in parallel to form the bias current digital control circuit 00.

[0055] The output terminal of the first switch sw5 is connected to the first input terminal of the SR control circuit 20, and the output terminal of the first switch sw5 is also connected to the ground terminal; the other end of the second switch sw6 is connected to the second input terminal of the SR control circuit 20, the input terminal of the third switch sw7, and the input terminal of the capacitor array 30, respectively, and the output terminals of the third switch sw7 and the capacitor array 30 are both connected to the ground terminal; the control terminal of the SR control circuit 20 is connected to the MCU, and the SR control circuit 20 is used to adjust the data signal transmission rate.

[0056] like Figure 2 As shown, the SR control circuit 20 includes a first transistor M1 and a second transistor M2.

[0057] The gate of the first transistor M1 is connected to the gate of the second transistor M2; the source of the first transistor M1 is connected to the capacitor array 30; the drain of the first transistor M1 is connected to the output terminal of the first switch sw5; the source of the second transistor M2 is connected to the other end of the second switch sw6; the gate of the first transistor M1 and the control terminal of the second transistor M2 are both connected to the MCU.

[0058] The SR control circuit 20 consists of a first transistor M1 and a first transistor M2. By default, M1 and M2 are not working. Under certain application requirements of the LIN system, the SR control circuit 20 uses the MCU control signal to close M1 and M2, thereby achieving faster SR switching during signal transmission to meet the system application requirements.

[0059] like Figure 2 As shown, the capacitor array 30 includes a first capacitor group and multiple second capacitor groups.

[0060] The first capacitor bank and multiple second capacitor banks are connected in parallel; the input terminal of the first capacitor bank is connected to the input terminal of the third switching transistor SW7; the output terminals of the first capacitor bank and multiple second capacitor banks are all connected to the ground terminal; the control terminals of multiple second capacitor banks are all connected to the duty cycle detection circuit.

[0061] When the data signal is high, the first switch SW5 and the second switch SW6 are open, the third switch SW7 is closed, and the capacitor array 30 is shorted to ground.

[0062] When the data signal is low, the first switch sw5 and the second switch sw6 are closed, the third switch sw7 is open, and the first capacitor group and multiple second capacitor groups are connected to the gate of the driver transistor M3.

[0063] Capacitor array 30 consists of C1 to CN.

[0064] The first capacitor bank includes a first capacitor C1; the second capacitor bank includes a second capacitor and a capacitor switching transistor. The second capacitors are C2...CN. The capacitor switching transistors are SW8...SWN.

[0065] The input terminal of the capacitor switch is connected to the duty cycle detection circuit; the output terminal of the capacitor switch is connected to the input terminal of the second capacitor.

[0066] The output terminals of the second capacitor and the first capacitor are both connected to the ground terminal; the input terminal of the first capacitor is connected to the input terminal of the third switching transistor SW7.

[0067] The first capacitor is the fixed capacitor connected to the circuit, and the multiple second capacitor groups are capacitors that can be controlled by a switch, and all have the same capacitance value.

[0068] Unlike the RC delay method, it mainly controls the charging and discharging rate of the gate capacitor of the drive transistor M3 by controlling the bias current of I1 to I5, which makes the structure simpler.

[0069] First, control the bias current digital control circuit at position 00 via the MCU, assuming position I1 is selected.

[0070] By controlling the bias current digital control circuit 00 through the MCU, the circuit can quickly switch to the SR high-speed range, meeting the automatic addressing application requirements of the LIN system circuit.

[0071] When the MCU transmits data signal at a high level, the first switch sw5 and the second switch sw6 are turned off, and the third switch sw7 is turned on. At this time, the capacitor array 30 is shorted to ground, and the bias current I1 charges the gate capacitor of the drive transistor M3, controlling the turn-on rate of the drive transistor M3, thereby controlling the LIN bus voltage from high to low SR.

[0072] When the transmitted data is at a low level, switches SW5 and SW6 are closed, and SW7 is open. The current of I5 is greater than the current of I1, and the discharge current is greater than the charging current. The gate capacitor of the driver transistor M3 and the capacitor array 30 first distribute the charge evenly, and then discharge, controlling the turn-off rate of the driver transistor M3, thereby controlling the SR of the LIN bus voltage from low to high. Reducing SR can effectively reduce electromagnetic emissions.

[0073] When the data signal sent by the MCU is high, the MCU controls the first switch sw5 and the second switch sw6 to disconnect, the MCU controls the capacitor array 30 to ground, and the MCU controls the bias current digital control circuit 00 to charge the gate terminal of the drive transistor M3, controlling the turn-on rate of the drive transistor M3. After the LIN bus voltage changes from high to low, the MCU sends a high-level data signal to the receiving circuit through the drive transistor M3. The duty cycle detection circuit controls the turn-on rate of the drive transistor M3 by detecting the timing of the first data output by the receiving circuit and controlling the number of capacitors connected in the capacitor array 30, so that the timing of the first data output by the receiving circuit is within a preset range.

[0074] When the data signal sent by the MCU is low, the MCU controls the first switch sw5 and the second switch sw6 to close, so that the SR control circuit 20 is connected to the driver transistor M3. The discharge current of the driver transistor M3 is greater than the charging current, and the closing rate of the driver transistor M3 is controlled, so that the LIN bus voltage changes from low to high. The MCU sends a low-level data signal to the receiving circuit through the driver transistor M3. The receiving circuit receives the low level and outputs low-level data based on the received low level.

[0075] like Figure 2 As shown, the transmitting drive circuit further includes an overcurrent protection circuit 10.

[0076] Power supply 1 is in the low-voltage range, with a typical operating voltage of 5V. Power supply 2 is in the high-voltage range, with a typical operating voltage of 13V.

[0077] The input terminal of the overcurrent protection circuit 10 is connected to the output terminal of the bias current digital control circuit 00; the output terminal of the overcurrent protection circuit 10 is connected to the source of the drive transistor M3.

[0078] Power supply 1 is connected to the bias current digital control circuit 00; the LIN bus is connected to power supply 2 through the load; the overcurrent protection circuit 10 is connected to the source of both the bias current digital control circuit 00 and the drive transistor M3. The load is a pull-up resistor.

[0079] The overcurrent protection circuit 10 is used to protect the circuit.

[0080] When the LIN bus is shorted to power supply 2, according to the virtual short and virtual open principle of the op-amp, the voltage at the R1 terminal will be equal to the voltage at the R2 terminal. The current flowing through the driver transistor M3 is determined by the voltage at the R2 terminal and the resistance value of R2. Therefore, when the LIN bus is shorted to power supply 2, the large current generated can flow to ground through the driver transistor M3 and resistor R2, thereby protecting the circuit from damage.

[0081] like Figure 2 As shown, the overcurrent protection circuit consists of an operational amplifier, a current source I6, and a resistor R1. The negative terminal of the operational amplifier is connected between the current source I6 and R1, and the positive terminal is connected between the driver transistor M3 and the resistor R2. The current of I6 can be adjusted by controlling the number of current mirrors through a switch. Under normal operation, the overcurrent protection circuit 10 will not be activated. Only when the LIN BUS line of the driver circuit is shorted to power supply 2 and the driver transistor M3 is turned on will a large current be generated on the LIN BUS line. At this time, the overcurrent protection function will be automatically activated. After processing by the operational amplifier OPA, the large current flows to ground through the driver transistor M3 and the resistor R2, thereby protecting the internal circuit of the chip.

[0082] The duty cycle detection circuit is connected to the first control terminal of the receiving circuit and the transmitting drive circuit respectively; the duty cycle detection circuit is used to detect the high-level duration of the data signal received by the receiving circuit, and control the number of capacitors connected to the capacitor array 30 in the transmitting drive circuit according to the high-level duration to ensure the correct transmission of the data signal.

[0083] The duty cycle detection circuit, implemented by digital circuitry, is affected by process technology, temperature, and load changes on the LIN bus. The duty cycle of the receiving circuit fluctuates greatly, which can lead to bit errors and signal loss. The duty cycle detection circuit controls the number of capacitor arrays 30 connected by detecting the high-level time of the output signal of the receiving circuit, thereby achieving correct data transmission.

[0084] The signal from the duty cycle detection circuit controls the capacitor array to adjust the duty cycle changes caused by variations in PVT and LIN bus load. This enables adaptive adjustment of the LIN bus transmission signal duty cycle.

[0085] The control method for the duty cycle detection circuit includes:

[0086] The duty cycle detection circuit detects whether the duration of the received high level is greater than a preset threshold, and obtains the first detection result.

[0087] If the first detection result is yes, the duty cycle detection circuit controls the capacitor array in the transmitting drive circuit to reduce the number of capacitors connected.

[0088] If the first detection result is negative, the duty cycle detection circuit controls the capacitor array in the transmitting drive circuit to increase the number of capacitors connected.

[0089] The MCU sends a data signal to the transmit driver circuit. When the data signal received by the transmit driver circuit is high, the MCU controls the transmit driver circuit to change the LIN bus voltage from high to low. Then, the MCU controls the transmit driver circuit to send a high-level data signal to the receive circuit. The receive circuit outputs high-level data based on the received high-level data signal. The duty cycle detection circuit controls the time after the transmit driver circuit drives the LIN bus voltage to change from high to low by detecting the high-level time of the high-level data output by the receive circuit, so that the time for the transmit driver circuit to output the high-level data signal is within a preset range.

[0090] The MCU sends a data signal to the transmit driver circuit. When the data signal received by the transmit driver circuit is low, the MCU controls the transmit driver circuit to change the LIN bus voltage from low to high. Then, the MCU controls the transmit driver circuit to send a low-level data signal to the receive circuit. The receive circuit outputs low-level data based on the received low-level data signal.

[0091] like Figure 3 As shown, the detection method steps include:

[0092] 1) The circuit enters normal operating mode.

[0093] 2) The MCU normally sends a 20kbps signal. At this time, the bias current digital control is in the default position, the SR control circuit switch is not enabled, the overcurrent protection module function is not activated, and the capacitor array is in the default position.

[0094] 3) Enable the duty cycle detection circuit to detect the duty cycle of the output signal of the receiving circuit.

[0095] 4) The duty cycle detection circuit detects the high-level time of the receiving circuit output and counts the high-level time.

[0096] 5) If the high-level counting time exceeds the predetermined range, the detection circuit outputs a control signal to reduce the number of capacitors connected to the capacitor array.

[0097] 6) If the high-level counting time exceeds the predetermined range, the detection circuit outputs a control signal to increase the number of capacitors connected to the capacitor array.

[0098] 7) If the high-level count is within the predetermined range, the number of switched capacitors remains unchanged and no switching is performed.

[0099] When the MCU does not send data, the bias current digital control circuit is in the default position, the SR control circuit switch is disabled, the overcurrent protection module function is not activated, the capacitor array is in the default position, the duty cycle detection circuit is disabled, and the function is turned off.

[0100] The duty cycle adaptive transmission drive circuit provided by this invention is characterized by:

[0101] (1) The transmit drive circuit (TXD) receives data from the MCU. The normal communication rate is 20kbps and the low communication rate is 10.4kbps. The data signal is directly connected to the MCU and transmitted to the TXD drive circuit.

[0102] (2) Includes overcurrent protection circuit. In case of abnormal situation where the LIN bus is shorted to power supply 2, the function start can effectively protect the internal circuit of the system from damage caused by the large current generated.

[0103] (3) Supports SR (slewrate) adaptive function. When working normally, the low SR setting can effectively reduce electromagnetic emission interference. To meet the requirements of LIN communication automatic addressing application, when the automatic addressing function is enabled, the high SR setting is selected by switch control. When automatic addressing ends, slewrate automatically switches back to the low rate setting.

[0104] (4) Includes a duty cycle detection circuit for the output transmission signal of the receiving circuit (RX). When the detected duty cycle exceeds a predetermined value, the detection circuit outputs a signal to control the capacitor array of the TX circuit and control the number of capacitors connected; thus realizing the duty cycle adaptive adjustment function during data signal transmission.

[0105] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0106] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A duty cycle adaptive transmission drive circuit, characterized in that, The duty cycle adaptive transmission drive circuit includes: a transmission drive circuit, a duty cycle detection circuit, and a receiving circuit; The input terminal of the transmitting drive circuit is connected to the MCU, and the output terminal of the transmitting drive circuit is connected to the receiving circuit through the LIN bus; the transmitting drive circuit is used to receive the data signal output by the MCU and send the data signal to the receiving circuit through the LIN bus. The transmitting drive circuit includes: a bias current digital control circuit, an SR control circuit, a first switch, a second switch, a third switch, a capacitor array, and a driving transistor; the input terminal of the bias current digital control circuit is connected to power supply 1, the control terminal of the bias current digital control circuit is connected to the MCU, and the output terminal of the bias current digital control circuit is connected to the input terminal of the first switch, the input terminal of the second switch, and the gate terminal of the driving transistor, respectively; the bias current digital control circuit is used to control the magnitude of the current transmitted to the gate terminal of the driving transistor, so as to control the charging rate of the gate terminal capacitor of the driving transistor; the output terminal of the first switch is connected to the first input terminal of the SR control circuit, and the output terminal of the first switch is also connected to ground; the other end of the second switch is connected to the SR control circuit... The second input terminal, the input terminal of the third switch, and the input terminal of the capacitor array are connected. The output terminals of the third switch and the capacitor array are both connected to ground. The control terminal of the SR control circuit is connected to the MCU, and the SR control circuit is used to adjust the data signal transmission rate. The control terminal of the capacitor array is connected to the duty cycle detection circuit, and the capacitor array is used to control the turn-off rate of the drive transistor. The control terminals of the first switch, the second switch, and the third switch all serve as input terminals of the transmitting drive circuit, connected to the MCU, and receive data signals transmitted by the MCU. The collector terminal of the drive transistor serves as the output terminal of the transmitting drive circuit, connected to the receiving circuit via the LIN bus, and the emitter of the drive transistor is grounded through resistor R2. The duty cycle detection circuit is connected to the first control terminal of the receiving circuit and the transmitting drive circuit respectively; the duty cycle detection circuit is used to detect the high-level duration of the data signal received by the receiving circuit, and control the number of capacitors connected to the capacitor array in the transmitting drive circuit according to the high-level duration to ensure the correct transmission of the data signal.

2. The duty cycle adaptive transmission drive circuit according to claim 1, characterized in that, The control method for the duty cycle detection circuit includes: The duty cycle detection circuit detects whether the duration of the received high level is greater than a preset threshold and obtains the first detection result. If the first detection result is yes, the duty cycle detection circuit controls the capacitor array in the transmitting drive circuit to reduce the number of capacitors connected. If the first detection result is negative, the duty cycle detection circuit controls the capacitor array in the transmitting drive circuit to increase the number of capacitors connected.

3. The duty cycle adaptive transmission drive circuit according to claim 1, characterized in that, The transmitting drive circuit also includes an overcurrent protection circuit; The input terminal of the overcurrent protection circuit is connected to the output terminal of the bias current digital control circuit; the output terminal of the overcurrent protection circuit is connected to the source of the drive transistor. The overcurrent protection circuit is used to protect the transmitting drive circuit.

4. The duty cycle adaptive transmission drive circuit according to claim 3, characterized in that, The bias current digital control circuit includes multiple current mirror groups; The current mirror groups are connected in parallel; The input terminal of the current mirror group is connected to power supply 1; the output terminal of the current mirror group is connected to the overcurrent protection circuit; the control terminal of the current mirror group is connected to the MCU; the output terminal of the current mirror group is connected to the input terminal of the first switching transistor, the input terminal of the second switching transistor, and the input terminal of the overcurrent protection circuit, respectively.

5. The duty cycle adaptive transmission drive circuit according to claim 4, characterized in that, The current mirror assembly includes a current mirror and a current mirror switching transistor; The input terminal of the current mirror is connected to power supply 1; the output terminal of the current mirror is connected to the input terminal of the current mirror switching transistor; the control terminal of the current mirror switching transistor is connected to the MCU; the output terminal of the current mirror switching transistor is connected to the input terminal of the first switching transistor, the input terminal of the second switching transistor, and the input terminal of the overcurrent protection circuit, respectively.

6. The duty cycle adaptive transmission drive circuit according to claim 5, characterized in that, The SR control circuit includes a first transistor and a second transistor; The gate of the first transistor is connected to the gate of the second transistor; the source of the first transistor is connected to the capacitor array; the drain of the first transistor is connected to the output terminal of the first switch; the source of the second transistor is connected to the other end of the second switch; the control terminals of both the first and second transistors are connected to the MCU.

7. The duty cycle adaptive transmission drive circuit according to claim 6, characterized in that, The capacitor array includes a first capacitor group and multiple second capacitor groups; The first capacitor bank and multiple second capacitor banks are connected in parallel; the input terminal of the first capacitor bank is connected to the input terminal of the third switching transistor; the output terminals of the first capacitor bank and multiple second capacitor banks are all connected to the ground terminal; the control terminals of multiple second capacitor banks are all connected to the duty cycle detection circuit.

8. The duty cycle adaptive transmission drive circuit according to claim 7, characterized in that, The first capacitor bank includes a first capacitor; the second capacitor bank includes a second capacitor and a capacitor switching transistor. The input terminal of the capacitor switch is connected to the duty cycle detection circuit; the output terminal of the capacitor switch is connected to the input terminal of the second capacitor. The output terminals of the second capacitor and the first capacitor are both connected to the ground terminal; the input terminal of the first capacitor is connected to the input terminal of the third switching transistor.

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