A management system, method, device and storage medium

Abstract

The application provides a management system, method, device and storage medium, relates to the technical field of computer equipment, and the system comprises a baseboard management controller, a CPU, a switching chip, an Ethernet controller, a network transformer, the CPU and the Ethernet controller constitute a first channel, which is used for troubleshooting a network interface, the Ethernet controller and the switching chip constitute a second channel, the baseboard management controller and the switching chip constitute a third channel, the switching chip and the network interface constitute a fourth channel through the network transformer, the baseboard management controller is used for transmitting data with the CPU through the first, second and third channels and transmitting data with a network interface side device through the third and fourth channels, the CPU is used for transmitting data with the network interface side device through the first, second and fourth channels, and the baseboard management controller and the CPU constitute an instruction channel. The application aims to improve the communication rate and convenience between the CPU and the baseboard management controller.

Description

Technical Field

[0001] This application relates to the field of computer equipment technology, and in particular to a management system, method, device and storage medium. Background Technology

[0002] To facilitate centralized management and use of white-box switch devices by end users, the industry widely adopts the IPMI Intelligent Platform Interface. The standardized design utilizing this interface facilitates unified system management, enabling centralized management of different hardware platforms. This unified platform interface leads to similar hardware designs, all of which include a CPU, BMC, and management network port components. The CPU, as the system's control center, requires an external management network port for data upload / download and network access services. Similarly, the core controller of the IPMI Intelligent Management Platform also needs to be connected to an external management network port to achieve remote management of the white-box switch devices. A typical hardware design scheme is as follows: Figure 1 As shown, the CPU chip controls the Ethernet controller via a PCIe interface. The Baseboard Management Controller (BMC) chip connects to the Ethernet controller via an NCSI interface. Both share a single MDI interface, which, after passing through a network transformer, shares a single panel management network interface on the control panel side. The Ethernet controller has an external Flash memory chip storing firmware, used for normal operation and storing MAC addresses.

[0003] This typical hardware design has the following problems: 1. The Ethernet controller's management interface is PCIe. When network interface problems occur, maintenance personnel can only connect to the CPU serial port and access the Ethernet controller's registers through the PCIe interface for troubleshooting. Troubleshooting depends on whether the CPU is powered on and working normally. The CPU is the only troubleshooting channel, resulting in poor product maintainability. 2. The NCSI interface speed is only 100Mbps, which limits the maximum speed of the network interface on the BMC side. In addition, the NCSI interface is proprietary, and the communication conversion protocol between NCSI and PCIe is complex. The CPU cannot communicate with the BMC through the Ethernet controller and needs to use an additional communication interface (such as LPC or USB) for communication. However, this additional communication interface has a slow communication speed and is relatively complex. Summary of the Invention

[0004] In view of this, this application provides a management system, method, apparatus, and storage medium. The aim is to improve the communication speed and convenience between the CPU and the baseboard management controller.

[0005] In a first aspect of this application, a management system is provided, the system comprising: a baseboard management controller, a CPU, a switching chip, an Ethernet controller, a network transformer, and a network interface;

[0006] The CPU is connected to the Ethernet controller to form a first channel;

[0007] The CPU is used to troubleshoot the network interface through the first channel;

[0008] The Ethernet controller is connected to the switching chip to form a second channel;

[0009] The baseboard management controller is connected to the switching chip to form a third channel;

[0010] The switching chip is connected to the network interface via the network transformer, forming a fourth channel;

[0011] The baseboard management controller is used to transmit data with the CPU through the first channel, the second channel and the third channel, and to transmit data with the device connected through the network interface through the third channel and the fourth channel;

[0012] The CPU is used to transmit data with devices connected through the network interface via the first channel, the second channel, and the fourth channel.

[0013] The baseboard management controller is connected to the CPU to form an instruction channel.

[0014] Optionally, the system further includes: a first logic device and a multiplexer;

[0015] The baseboard management controller is connected to the switching chip through the multiplexer to form a first management channel;

[0016] The first management channel is used by the baseboard management controller to manage the switching chip based on the first management channel;

[0017] The CPU is connected to the switching chip via the multiplexer, forming a second management channel;

[0018] The second management channel is used by the CPU to manage the switching chip based on the second management channel;

[0019] The baseboard management controller is connected to the first logic device to form a first control channel;

[0020] The first logic device is connected to the multiplexer to form a management and control channel;

[0021] The first control channel and the management control channel together constitute the first management control channel;

[0022] The first management control channel is used by the substrate management controller to control the port on / off of the multiplexer through the first management control channel, so as to control the on / off of the first management channel and the second management channel;

[0023] The CPU is connected to the first logic device to form a second control channel;

[0024] The second control channel and the management control channel together constitute the second management control channel;

[0025] The second management control channel is used by the CPU to control the port on / off of the multiplexer through the second management control channel, so as to control the on / off of the first management channel and the second management channel.

[0026] Optionally, if the system further includes a second logic device, the connection between the CPU in the second management channel and the multiplexer includes: the CPU being connected to the multiplexer via the second logic device.

[0027] Optionally, the system further includes: a first multiplexer;

[0028] The baseboard management controller is connected to the spatial location of the firmware of the switching chip through the first multiplexer, forming a first upgrade channel;

[0029] The first upgrade channel is used by the baseboard management controller to upgrade the firmware of the switching chip based on the first upgrade channel;

[0030] The CPU is connected to the firmware location of the switching chip via the first multiplexer, forming a second upgrade channel;

[0031] The second upgrade channel is used by the CPU to upgrade the firmware of the switching chip based on the second upgrade channel;

[0032] The first logic device is connected to the first multiplexer to form an upgrade control channel;

[0033] The first control channel and the upgrade control channel together constitute the first upgrade control channel;

[0034] The first upgrade control channel is used by the baseboard management controller to control the port on / off of the first multiplexer through the first upgrade control channel, so as to control the on / off of the first upgrade channel and the second upgrade channel;

[0035] The second control channel and the upgrade control channel together constitute the second upgrade control channel;

[0036] The second upgrade control channel is used by the CPU to control the on / off state of the port of the first multiplexer, thereby controlling the on / off state of the first upgrade channel and the second upgrade channel.

[0037] Optionally, the CPU in the second upgrade channel is connected to the first multiplexer, including: the CPU is connected to the first multiplexer through the second logic device.

[0038] Optionally, if the system further includes a second multiplexer, the first multiplexer in the first upgrade channel and the second upgrade channel is connected to the spatial location of the firmware of the switching chip, including: the first multiplexer is connected to the spatial location of the firmware of the switching chip through the second multiplexer;

[0039] The first logic device is connected to the second multiplexer to form an upgrade control sub-channel;

[0040] The first control channel and the upgrade control channel together constitute the first upgrade control channel, which includes: the first control channel, the upgrade control channel and the upgrade control sub-channel together constitute the first upgrade control channel;

[0041] The second control channel and the upgrade control channel together constitute the second upgrade control channel, which includes: the second control channel, the upgrade control channel and the upgrade control sub-channel together constitute the second upgrade control channel.

[0042] Optionally, the system further includes:

[0043] The firmware location of the switching chip is connected to the switching chip via the second multiplexer to form a firmware configuration channel;

[0044] The firmware configuration channel is used to configure the firmware of the switching chip when the switching chip is powered on.

[0045] In a second aspect of this application, a management method is provided, applied to the management system described in the first aspect of this application, the method comprising:

[0046] Based on the received execution information, determine the execution action corresponding to the execution information;

[0047] When the execution action characterizes the CPU to perform network interface fault diagnosis, the CPU performs fault diagnosis on the network interface through the first channel;

[0048] When the execution action characterization substrate management controller transmits data to the CPU, the substrate management controller transmits the data to the CPU through the first channel, the second channel, and the third channel;

[0049] When the execution action represents the baseboard management controller transmitting data to a device connected via a network interface, the baseboard management controller transmits the data to the device connected via the network interface through the third and fourth channels;

[0050] When the execution action represents the CPU transmitting data to a device connected through the network interface, the CPU transmits data to the device connected through the network interface via the first channel, the second channel, and the fourth channel.

[0051] In a third aspect of the embodiments of this application, this application provides an electronic device, including: a processor, a memory, and a computer program stored in the memory and running on the processor, wherein the computer program, when executed by the processor, implements the steps of a management method described in the second aspect of this application.

[0052] In a fourth aspect of the embodiments of this application, this application provides a computer non-volatile readable storage medium storing a computer program, which, when executed by a processor, implements the steps of a management method described in the second aspect of this application.

[0053] Compared with prior art, this application has the following advantages:

[0054] This application provides a management system comprising: a baseboard management controller, a CPU, a switching chip, an Ethernet controller, a network transformer, and a network interface; the CPU and the Ethernet controller are connected to form a first channel; the CPU troubleshoots the network interface through the first channel; the Ethernet controller and the switching chip are connected to form a second channel; the baseboard management controller and the switching chip are connected to form a third channel; the switching chip is connected to the network interface through the network transformer to form a fourth channel; the baseboard management controller transmits data with the CPU through the first, second, and third channels, and transmits data with devices connected through the network interface through the third and fourth channels; the CPU transmits data with devices connected through the network interface through the first, second, and fourth channels; the baseboard management controller and the CPU are connected to form an instruction channel. Therefore, this application introduces a switching chip into the existing management system, enabling the CPU to troubleshoot network interface faults by accessing the Ethernet controller via the PCIe interface, while also enabling faster data communication between the CPU and the baseboard management controller via the Ethernet controller and the switching chip. This simplifies data communication between the CPU and the baseboard management controller, effectively improves the communication rate between them, and also effectively improves the communication rate of the baseboard management controller's external interface (data communication between the baseboard management controller and devices connected via the network interface).

[0055] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0056] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0057] Figure 1 This is a schematic diagram of the structure of a management system in the prior art;

[0058] Figure 2 A schematic diagram of the structure of a management system provided in an embodiment of this application;

[0059] Figure 3 A schematic diagram of the structure of a management system including a first logic device is provided as an embodiment of this application;

[0060] Figure 4 A schematic diagram of the structure of a management system provided in this application embodiment, in which a second logic device is also included;

[0061] Figure 5 Another schematic diagram of a management system including a second logic device, provided as an embodiment of this application;

[0062] Figure 6 A schematic diagram of the structure of a management system including a first multiplexer, provided as an embodiment of this application;

[0063] Figure 7 Another schematic diagram of a management system provided in this application embodiment, including a first multiplexer;

[0064] Figure 8 A schematic diagram of the structure of a management system provided in this application embodiment, including a first multiplexer and a second logic device;

[0065] Figure 9 A schematic diagram of the structure of a management system including a second multiplexer, provided as an embodiment of this application;

[0066] Figure 10 A schematic diagram of the overall structure of a management system provided in an embodiment of this application;

[0067] Figure 11 A flowchart illustrating a management method provided in an embodiment of this application;

[0068] Figure 12 This is a schematic diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0069] The exemplary embodiments of this application will now be described in more detail with reference to the accompanying drawings.

[0070] To facilitate understanding, the relevant technical terms mentioned below will be explained:

[0071] CPU: (Center Processing Unit) Central processing unit;

[0072] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard.

[0073] CPLD: (Complex Programmable Logic Device)

[0074] FPGA: (Field Programmable Gate Array) Programmable array logic;

[0075] BMC: (Baseboard Management Controller)

[0076] Network Transformer;

[0077] RGMII: (Reduced Gigabit Media Independent Interface)

[0078] MDI: (Medium Dependent Interface) Media-dependent interface;

[0079] NCSI: (Network Controller Sideband Interface)

[0080] L2Switch: (Layer 2Switch) A Layer 2 switching chip;

[0081] LPC: (Low Pin Count Bus) LPC bus;

[0082] Firmware: firmware;

[0083] MUX: (Multiplexer) Multiplexer.

[0084] Figure 2 A schematic diagram of the structure of a management system provided in an embodiment of this application is shown below. Figure 2 As shown, the system includes: a baseboard management controller, a CPU, a switching chip, an Ethernet controller, a network transformer, and a network interface; the CPU is connected to the Ethernet controller to form a first channel; the CPU is used to troubleshoot the network interface through the first channel; the Ethernet controller is connected to the switching chip to form a second channel; the baseboard management controller is connected to the switching chip to form a third channel; the switching chip is connected to the network interface through the network transformer to form a fourth channel; the baseboard management controller is used to transmit data with the CPU through the first, second, and third channels, and to transmit data with devices connected through the network interface through the third and fourth channels; the CPU is used to transmit data with devices connected through the network interface through the first, second, and fourth channels; the baseboard management controller is connected to the CPU to form an instruction channel.

[0085] In this embodiment, the management system provided by this application includes a Baseboard Management Controller (BMC), a CPU, a switching chip, an Ethernet Controller, a Network Transformer, and a network interface. Figure 2 As shown, in a management system provided by this application, the CPU is connected to an Ethernet controller to form a first channel. This first channel includes, but is not limited to, data transmission via a PCIe interface. When a network interface malfunctions, the fault information is recorded in the relevant registers of the Ethernet controller. This first channel is used by the CPU to access the Ethernet controller's registers to troubleshoot the network interface malfunction.

[0086] In this management system, the Ethernet controller is further connected to the switching chip to form a second channel, which includes, but is not limited to, data transmission via an MDI interface. In this management system, the baseboard management controller is connected to the switching chip to form a third channel, which includes, but is not limited to, data transmission via an RGMII interface. In this management system, the switching chip is further connected to a network interface via a network transformer to form a fourth channel, which includes, but is not limited to, data transmission via an MDI interface.

[0087] For the various data channels described above, the first function of the first channel is for the CPU to access the Ethernet controller's registers to troubleshoot network interface faults. The second function of the first channel, together with the second and third channels, is for high-speed data transmission between the baseboard management controller and the CPU. The third function of the first channel, together with the second and fourth channels, is for high-speed data transmission between the CPU and devices connected via the network interface. Finally, the third and fourth channels are used together for high-speed data transmission between the baseboard management controller and devices connected via the network interface. Therefore, the management system provided in this application, by introducing a switching chip and the aforementioned data channels, not only achieves a convenient gigabit-speed communication path between the baseboard management controller and the CPU, but also connects the baseboard management controller's external interfaces (such as...) Figure 2 The speed of channel 2 shown has been increased to 1Gbps. The network interface includes, but is not limited to, Registered Jack 45 (RJ 45), and the switching chip includes, but is not limited to, a Layer 2 gigabit switching chip (L2Switch). The switching chip uses VLANs to enable the CPU and baseboard management controller to share the panel management network port, as well as dedicated data network communication between the CPU and the BMC. Figure 2(See Channel 3 shown). To enable dedicated data network communication between the CPU and the baseboard management controller, a dedicated VLAN needs to be configured. By default, Channel 1 and Channel 2 are placed in a separate VLAN to enable external network communication. The switching chip loads the firmware from the external Flash memory upon power-up; the firmware contains the corresponding configurations.

[0088] This application provides a management system comprising: a baseboard management controller, a CPU, a switching chip, an Ethernet controller, a network transformer, and a network interface; the CPU and the Ethernet controller are connected to form a first channel; the CPU troubleshoots the network interface through the first channel; the Ethernet controller and the switching chip are connected to form a second channel; the baseboard management controller and the switching chip are connected to form a third channel; the switching chip is connected to the network interface through the network transformer to form a fourth channel; the baseboard management controller transmits data with the CPU through the first, second, and third channels, and transmits data with devices connected through the network interface through the third and fourth channels; the CPU transmits data with devices connected through the network interface through the first, second, and fourth channels; the baseboard management controller and the CPU are connected to form an instruction channel, which includes, but is not limited to, transmitting data through a USB interface and an LPC interface. Therefore, this application introduces a switching chip into the existing management system, enabling the CPU to troubleshoot network interface faults by accessing the Ethernet controller via the PCIe interface, while also enabling faster data communication between the CPU and the baseboard management controller via the Ethernet controller and the switching chip. This simplifies data communication between the CPU and the baseboard management controller, effectively improves the communication rate between them, and also effectively improves the communication rate of the baseboard management controller's external interface (data communication between the baseboard management controller and devices connected via the network interface).

[0089] In conjunction with the above embodiments, in one implementation, this application also provides a management system. In this management system, the system further includes: a first logic device and a multiplexer; a baseboard management controller connected to the switching chip via the multiplexer to form a first management channel; the first management channel is used by the baseboard management controller to manage the switching chip based on the first management channel; a CPU connected to the switching chip via the multiplexer to form a second management channel; the second management channel is used by the CPU to manage the switching chip based on the second management channel; the baseboard management controller connected to the first logic device to form a first control channel; the first logic device connected to the multiplexer to form a management control channel; the first control channel and the management control channel together constitute a first management control channel; the first management control channel is used by the baseboard management controller to control the on / off state of the ports of the multiplexer through the first management control channel, thereby controlling the on / off state of the first management channel and the second management channel; the CPU connected to the first logic device to form a second control channel; the second control channel and the management control channel together constitute a second management control channel; the second management control channel is used by the CPU to control the on / off state of the ports of the multiplexer through the second management control channel, thereby controlling the on / off state of the first management channel and the second management channel.

[0090] In this embodiment, Figure 3 This is a schematic diagram illustrating the structure of a management system provided in an embodiment of this application, including a first logic device. In this embodiment, the management system provided in this application further includes a first logic device and a multiplexer, such as... Figure 3 As shown, in the case where the management system provided in this application further includes a first logic device and a multiplexer, the baseboard management controller is connected to the switching chip through the multiplexer to form a first management channel. This first management channel includes, but is not limited to, data transmission via an MDC / MDIO interface. Specifically, in this first management channel, the baseboard management controller is connected to one input / output port of the multiplexer (e.g., ...). Figure 3 The multiplexer uses port 2 in the multiplexer, and the multiplexer uses another input / output port (such as port 2 in the multiplexer). Figure 3 Port 3) of the multiplexer is connected to the switching chip. This first management channel enables the baseboard management controller to manage the switching chip via this channel, for example, by controlling the multiplexer to select the appropriate switching chip. Figure 3When ports 2 and 3 are connected, the baseboard management controller can manage the switching chip through the first management channel. Since fault information is recorded in the relevant registers of the switching chip when a network interface malfunctions, the baseboard management controller managing the switching chip through the first management channel means that it accesses the switching chip's registers to troubleshoot network interface faults. In other words, this management system can troubleshoot network interface faults not only through the CPU but also through the baseboard management controller.

[0091] In this embodiment, as Figure 3 As shown, the CPU is connected to the switching chip via a multiplexer, forming a second management channel. This second management channel includes, but is not limited to, data transmission via the MDC / MDIO interface. Within this second management channel, the CPU is connected to another input / output port of the multiplexer (e.g., ...). Figure 3 Port 1 of the multiplexer), and the multiplexer continues through another input / output port mentioned above (such as port 1). Figure 3 Port 3) of the multiplexer is connected to the switching chip. This second management channel enables the CPU to manage the switching chip, for example, by controlling the multiplexer to select the correct multiplexer. Figure 3 When ports 1 and 3 are connected, the CPU can manage the switching chip through the second management channel. Since fault information is recorded in the relevant registers of the switching chip when a network interface malfunctions, the CPU managing the switching chip through this second management channel means accessing the switching chip's registers to troubleshoot network interface faults. This means the management system can troubleshoot network interface faults not only through the CPU's access to the Ethernet controller's registers but also through the switching chip's registers, thus ensuring the stability of network interface fault troubleshooting. If the CPU cannot troubleshoot a network interface fault, the baseboard management controller will do so; if the CPU cannot troubleshoot a network interface fault by accessing either the Ethernet controller's registers or the switching chip's registers, the CPU will access the other of the two to troubleshoot the network interface fault.

[0092] In this embodiment, as Figure 3 As shown, the first and second management channels share a common interface in the connection from the multiplexer to the switching chip (e.g., from...). Figure 3(Port 3 of the multiplexer in the circuit is connected to the switching chip), and this interface includes, but is not limited to, the MDC / MDIO interface.

[0093] In this embodiment, as Figure 3 As shown, in this management system, the baseboard management controller is connected to the first logic device to form a first control channel. This first control channel includes, but is not limited to, data transmission via an I2C interface. The first logic device is further connected to a multiplexer to form a management control channel. The first control channel and the management control channel together constitute a first management control channel. This first management control channel is used by the baseboard management controller to output corresponding control signals to the multiplexer to control the on / off state of the multiplexer's ports, thereby controlling whether the first management channel or the second management channel is connected (i.e., whether the switching chip is managed by the baseboard management controller or by the CPU). Here, the first function of the first logic device is to issue corresponding control signals to control the on / off state of the corresponding ports in the multiplexer based on the information received from the baseboard management controller through the first control channel. For example, based on the information received from the baseboard management controller through the first control channel, it issues corresponding control signals to control the on / off state of the ports in the multiplexer. Figure 3 Ports 2 and 3 of the multiplexer are connected to enable the baseboard management controller to manage the switching chip, or to issue corresponding control signals based on information received from the baseboard management controller via the first control channel, such as... Figure 3 Ports 1 and 3 in the multiplexer are connected, thereby enabling the CPU to manage the switching chip.

[0094] In this embodiment, in the management system, the CPU is connected to the first logic device to form a second control channel. This second control channel is preferably a branch of the LPC instruction channel between the CPU and the baseboard management controller. This second control channel and the management control channel together constitute a second management control channel. This second management control channel is used by the CPU to output corresponding control signals to the multiplexer to control the on / off state of the multiplexer's ports, thereby controlling whether the first management channel or the second management channel is connected (i.e., whether the baseboard management controller or the CPU manages the switching chip). Here, the second function of the first logic device is to issue corresponding control signals based on the information received from the CPU via the second control channel to control the on / off state of the corresponding ports in the multiplexer. For example, based on the information received from the CPU via the second control channel, it issues corresponding control signals to control the on / off state of the ports in the multiplexer. Figure 3Ports 2 and 3 of the multiplexer are connected to enable the baseboard management controller to manage the switching chip, or to issue corresponding control signals based on information received from the CPU via the second control channel to control the switching chip. Figure 3 Ports 1 and 3 of the multiplexer are connected, enabling the CPU to manage the switching chip. Therefore, both the CPU and the baseboard management controller can switch between managing the switching chip (i.e., controlling whether the baseboard management controller or the CPU manages the switching chip), and both can manage the switching chip simultaneously. The first logic device is used to obtain corresponding control signals through logic processing. This first logic device includes, but is not limited to, a CPLD, and can be any logic device capable of obtaining control signals through logic processing.

[0095] In conjunction with the above embodiments, in one implementation, this application also provides a management system. In this management system, where a second logic device is further included, the connection between the CPU and the multiplexer in the second management channel includes: the CPU being connected to the multiplexer via the second logic device.

[0096] In this embodiment, since most of the interfaces on the CPU are PCIe interfaces, while there are fewer interfaces such as MDC, I2C, and SPI, in order to avoid the management system provided in this application occupying the already limited number of MDC, I2C, and SPI interfaces, resulting in other systems that need these interfaces not having these fewer interfaces to use, or causing other systems that need these interfaces to share these fewer interfaces with the management system provided in this application, leading to a complicated processing process, this application introduces a second logic device for interface conversion in the connection between the CPU and the multiplexer in the second management channel formed by the CPU connecting to the switching chip through the multiplexer. Figure 4 A schematic diagram of the structure of a management system provided in this application embodiment, in which a second logic device is also included, is shown below. Figure 4 As shown, in the case where the management system also includes a second logic device, another embodiment of the connection between the CPU and the multiplexer in the second management channel of the above embodiment is as follows: the CPU first connects to the second logic device, and then the CPU connects to one input / output port of the multiplexer (e.g., ...) through the second logic device. Figure 4The CPU connects to port 1) of the multiplexer in the CPU. The second logic device in this process performs interface conversion. This second logic device includes, but is not limited to, an FPGA; any logic device capable of interface conversion is acceptable. The interface through which the CPU first connects to the second logic device includes, but is not limited to, a PCIe interface. The interface through which the second logic device connects to the multiplexer includes, but is not limited to, an MDC / MDIO interface.

[0097] In this embodiment, Figure 5 Another structural schematic diagram of a management system provided in this application embodiment, including a second logic device, is shown below. Figure 5 As shown, the management system includes a baseboard management controller, a CPU, a switching chip, an Ethernet controller, a network transformer, a network interface, a first logic device, a second logic device, and a multiplexer, as well as a first channel, a second channel, a third channel, a fourth channel, an instruction channel, a first management channel where the baseboard management controller is connected to the switching chip via a multiplexer, a second management channel where the CPU is connected to the switching chip via a second logic device and a multiplexer, a first control channel, a management control channel, a first management control channel composed of the first control channel and the management control channel, a second control channel, and a second management control channel composed of the second control channel and the management control channel.

[0098] In conjunction with the above embodiments, in one implementation, this application also provides a management system. In this management system, the system further includes: a first multiplexer; when the management system includes a first multiplexer, the baseboard management controller is connected to the spatial location of the firmware of the switching chip through the first multiplexer to form a first upgrade channel; the first upgrade channel is used by the baseboard management controller to upgrade the firmware of the switching chip based on the first upgrade channel; the CPU is connected to the spatial location of the firmware of the switching chip through the first multiplexer to form a second upgrade channel; the second upgrade channel is used by the CPU to upgrade the firmware of the switching chip based on the second upgrade channel; the first logic device is connected to the first multiplexer to form an upgrade control channel; the first control channel and the upgrade control channel together constitute a first upgrade control channel; the first upgrade control channel is used by the baseboard management controller to control the on / off state of the port of the first multiplexer through the first upgrade control channel to control the on / off state of the first upgrade channel and the second upgrade channel; the second control channel and the upgrade control channel together constitute a second upgrade control channel; the second upgrade control channel is used by the CPU to control the on / off state of the port of the first multiplexer through the second upgrade control channel to control the on / off state of the first upgrade channel and the second upgrade channel.

[0099] In this embodiment, the management system provided in this application may further include a first multiplexer. By introducing the first multiplexer, both the baseboard management controller and the CPU can perform firmware upgrades on the firmware stored in the Flash memory attached to the switching chip. Specifically: Figure 6 A schematic diagram of a management system including a first multiplexer is provided as an embodiment of this application, as shown below. Figure 6 As shown, the baseboard management controller is connected to the firmware location of the switching chip via a first multiplexer, forming a first upgrade channel. This first upgrade channel includes, but is not limited to, data transmission via an I2C / SPI interface. Specifically, in this first upgrade channel, the baseboard management controller is connected to one input / output port of the first multiplexer (e.g., ...). Figure 6 The first multiplexer in the first input / output port (port 2) is connected to another input / output port (such as port 2 in the first input / output port). Figure 6 Port 3) of the first multiplexer is connected to the switching chip. This first upgrade channel enables the baseboard management controller to upgrade the firmware in the external Flash memory of the switching chip, for example, by controlling the first multiplexer to... Figure 6When ports 2 and 3 are connected, the baseboard management controller can upgrade the firmware in the external Flash memory of the switching chip through the first upgrade channel. Simultaneously, the CPU connects to the location of the switching chip's firmware via an introduced first multiplexer, forming a second upgrade channel. This second upgrade channel includes, but is not limited to, data transmission via an I2C / SPI interface. In this second upgrade channel, the CPU is connected to one input / output port of the first multiplexer (e.g., ...). Figure 6 The first multiplexer in the first input / output port (port 1), while the first multiplexer continues through another input / output port (such as port 1). Figure 6 Port 3) of the first multiplexer is connected to the switching chip. The second upgrade channel enables the CPU to upgrade the firmware in the external Flash memory of the switching chip, for example, by controlling the first multiplexer to... Figure 6 When port 1 and port 3 are connected, the CPU can upgrade the firmware in the external Flash memory of the switching chip through the second upgrade channel. This allows both the CPU and the baseboard management controller to upgrade the firmware in the external Flash memory of the switching chip.

[0100] In this embodiment, as Figure 6 As shown, the first logic device is connected to the first multiplexer to form an upgrade control channel, and together with the first control channel described above, forms the first upgrade control channel. This first upgrade control channel is used by the baseboard management controller to output corresponding control signals to the first multiplexer to control the on / off state of the ports of the first multiplexer, thereby controlling whether the first upgrade channel or the second upgrade channel is connected (i.e., whether the baseboard management controller upgrades the firmware in the external Flash of the switching chip, or whether the CPU upgrades the firmware in the external Flash of the switching chip). Here, the third function of the first logic device is to issue corresponding control signals to control the on / off state of the corresponding ports in the first multiplexer based on the information received from the baseboard management controller via the first control channel. For example, based on the information received from the baseboard management controller via the first control channel, it issues corresponding control signals to control the on / off state of the ports in the first multiplexer. Figure 6 Ports 2 and 3 of the first multiplexer are connected, thereby enabling the baseboard management controller to upgrade the firmware in the external Flash memory of the switching chip, or to issue corresponding control signals based on the information received by the baseboard management controller through the first control channel to control, for example... Figure 6Ports 1 and 3 in the first multiplexer are connected to enable the CPU to upgrade the firmware in the Flash memory attached to the switching chip.

[0101] In this embodiment, in the management system, such as Figure 6 As shown, the second upgrade control channel is formed by the second control channel and the upgrade control channel described in the above embodiment. This second upgrade control channel is used by the CPU to output corresponding control signals to the first multiplexer to control the on / off state of the ports of the first multiplexer, thereby controlling whether the first upgrade channel or the second upgrade channel is connected (i.e., whether the firmware in the Flash memory of the switching chip is upgraded by the baseboard management controller or by the CPU). Here, the fourth function of the first logic device is to issue corresponding control signals to control the on / off state of the corresponding ports in the first multiplexer based on the information received from the CPU via the second control channel. For example, based on the information received from the CPU via the second control channel, it issues corresponding control signals to control the on / off state of the ports. Figure 6 Ports 2 and 3 of the first multiplexer are connected, thereby enabling the baseboard management controller to upgrade the firmware in the external Flash memory of the switching chip, or to issue corresponding control signals based on information received by the CPU through the second control channel to control... Figure 6 Ports 1 and 3 in the first multiplexer are connected to enable the CPU to upgrade the firmware in the Flash memory attached to the switching chip.

[0102] In conjunction with the above embodiments, in one implementation, this application also provides a management system. In this management system, the CPU in the second upgrade channel is connected to the first multiplexer, including: the CPU is connected to the first multiplexer via the second logic device.

[0103] In this embodiment, since most of the interfaces on the CPU are PCIe interfaces, while there are fewer interfaces such as MDC, I2C, and SPI, in order to avoid the management system provided in this application occupying the already limited number of MDC, I2C, and SPI interfaces, resulting in other systems that need these interfaces not having these fewer interfaces to use, or causing other systems that need these interfaces to share these fewer interfaces with the management system provided in this application, leading to a complicated processing process, this application also uses the aforementioned second logic device in the connection between the CPU and the first multiplexer in the second upgrade channel, where the CPU is connected to the firmware location of the switching chip through the first multiplexer. This second logic device is also used for interface conversion. Figure 7 Another schematic diagram of a management system provided in this application embodiment, including a first multiplexer, is shown below. Figure 7 As shown, another embodiment of the connection between the CPU and the first multiplexer in the second upgrade channel is as follows: the CPU first connects to the second logic device, and then the CPU connects to one input / output port of the first multiplexer (such as...) through the second logic device. Figure 7 The CPU connects to port 1) of the first multiplexer in the CPU. The second logic device in this process performs interface conversion; this second logic device includes, but is not limited to, an FPGA, or any logic device capable of interface conversion. Furthermore, the interface through which the CPU connects to the second logic device includes, but is not limited to, a PCIe interface, and the interface through which the second logic device connects to the first multiplexer includes, but is not limited to, an I2C / SPI interface.

[0104] In this embodiment, when the CPU connects to the first multiplexer, it first connects to the second logic device. Similarly, when the CPU connects to the multiplexer described in the above embodiment, it also first connects to the second logic device. In both embodiments, the CPU shares a single interface with the second logic device when connecting to the first multiplexer and when connecting to the multiplexer. Specifically... Figure 8 As shown, Figure 8 This application provides a schematic diagram of a management system including a first multiplexer and a second logic device. The second management channel from the CPU to the multiplexer and the second upgrade channel from the CPU to the first multiplexer share the interface connection from the CPU to the second logic device (e.g., ...). Figure 8 (The second management / upgrade channel is shown in the diagram).

[0105] In conjunction with the above embodiments, in one implementation, this application also provides a management system. In this management system, the management system may further include a second multiplexer. When the management system includes a second multiplexer, the first multiplexer in the first upgrade channel and the second upgrade channel is connected to the spatial location of the firmware of the switching chip, including: the first multiplexer is connected to the spatial location of the firmware of the switching chip through the second multiplexer; the first logic device is connected to the second multiplexer to form an upgrade control sub-channel; the first control channel and the upgrade control channel together constitute a first upgrade control channel, including: the first control channel, the upgrade control channel, and the upgrade control sub-channel together constitute a first upgrade control channel; the second control channel and the upgrade control channel together constitute a second upgrade control channel, including: the second control channel, the upgrade control channel, and the upgrade control sub-channel together constitute a second upgrade control channel.

[0106] In this embodiment, the CPU and the baseboard management controller can not only manage the switching chip, but also upgrade the firmware in the external Flash memory of the switching chip. Therefore, to better distinguish whether the CPU and the baseboard management controller are specifically managing the switching chip or upgrading the firmware in the external Flash memory of the switching chip, this application further introduces a second multiplexer. This second multiplexer is used to control the connection between the CPU and the Flash memory location of the switching chip, to control the connection between the baseboard management controller and the Flash memory location of the switching chip, and to control the connection between the Flash memory location and the switching chip. Specifically: as shown... Figure 9 As shown, the first upgrade channel and the second upgrade channel constructed in the above embodiments both involve the same channel connecting the first multiplexer to the spatial location of the firmware of the switching chip. For this channel, another implementation method is provided in this embodiment: the first multiplexer is connected to the spatial location of the firmware of the switching chip through the second multiplexer. Specifically, the first multiplexer connects to the firmware of the switching chip through an input / output port (such as...). Figure 9 Port 3 of the first multiplexer and one input / output port of the second multiplexer (e.g., ...) Figure 9 Connect port 1 of the second multiplexer in the middle, and then connect the other input / output port of the second multiplexer (such as...). Figure 9 The port 3 of the second multiplexer in the circuit is connected to the spatial location of the firmware of the switching chip.

[0107] Meanwhile, the first logic device is connected to the second multiplexer to form an upgrade control sub-channel. The function of this upgrade control sub-channel is to control the on / off state of each port of the second multiplexer, so as to control whether the first multiplexer is connected to the space where the firmware of the switching chip is located, thereby realizing the firmware upgrade of the firmware Flash of the switching chip.

[0108] At this point, for the first upgrade control channel configured in the above embodiment for controlling the firmware Flash upgrade of the switching chip by the baseboard management controller, another implementation is provided in this embodiment: the first control channel, the upgrade control channel, and the aforementioned upgrade control sub-channel together constitute the first upgrade control channel. In this embodiment, the first control channel is used by the baseboard management controller to send information through the first control channel. In this embodiment, the first logic device is used to issue a corresponding control signal to control the on / off state of the corresponding port in the first multiplexer based on the information received by the baseboard management controller sent through the first control channel, and to issue a corresponding control signal to control the on / off state of the corresponding port in the second multiplexer based on the information received by the baseboard management controller sent through the first control channel. In this embodiment, the upgrade control channel is used to output a corresponding control signal to the first multiplexer through the upgrade control channel to control the on / off state of the port of the first multiplexer. In this embodiment, the upgrade control sub-channel is used to output a corresponding control signal to the second multiplexer through the upgrade control sub-channel to control the on / off state of the port of the second multiplexer. For example, as... Figure 9 As shown, when the baseboard management controller wants to upgrade the firmware in the external Flash memory of the switching chip, it sends corresponding information through the first control channel. The first logic device obtains the corresponding control signals for the first multiplexer and the second multiplexer based on this information. The first logic device sends the control signal for the first multiplexer to the first multiplexer through the upgrade control channel to connect ports 2 and 3 in the first multiplexer. At the same time, the first logic device sends the control signal for the second multiplexer to the second multiplexer through the upgrade control sub-channel to connect ports 1 and 3 in the second multiplexer. Ultimately, the baseboard management controller can upgrade the firmware in the external Flash memory of the switching chip through the first upgrade channel.

[0109] At this point, for the second upgrade control channel configured in the above embodiment for controlling the firmware Flash upgrade of the switching chip by the CPU, another implementation is provided in this embodiment: the second control channel, the upgrade control channel, and the above-mentioned upgrade control sub-channel together constitute the second upgrade control channel. In this embodiment, the second control channel is used by the CPU to send information through the second control channel. In this embodiment, the first logic device is used to issue a corresponding control signal to control the on / off state of the corresponding port in the first multiplexer according to the information received by the CPU sent through the second control channel, and is used to issue a corresponding control signal to control the on / off state of the corresponding port in the second multiplexer according to the information received by the CPU sent through the second control channel. In this embodiment, the upgrade control channel is used to output a corresponding control signal to the first multiplexer through the upgrade control channel to control the on / off state of the port of the first multiplexer. In this embodiment, the upgrade control sub-channel is used to output a corresponding control signal to the second multiplexer through the upgrade control sub-channel to control the on / off state of the port of the second multiplexer. For example, as shown... Figure 9 As shown, when the CPU wants to upgrade the firmware in the external Flash memory of the switching chip, it sends corresponding information through the second control channel. The first logic device obtains the corresponding control signals for the first multiplexer and the second multiplexer based on this information. The first logic device sends the control signal for the first multiplexer to the first multiplexer through the upgrade control channel to connect ports 1 and 3 in the first multiplexer. At the same time, the first logic device sends the control signal for the second multiplexer to the second multiplexer through the upgrade control sub-channel to connect ports 1 and 3 in the second multiplexer. Ultimately, the CPU can control the firmware in the external Flash memory of the switching chip to upgrade through the second upgrade channel.

[0110] In conjunction with the above embodiments, in one implementation, this application also provides a management system. In this management system, the spatial location of the firmware of the switching chip is connected to the switching chip via a second multiplexer to form a firmware configuration channel; the firmware configuration channel is used to configure the firmware of the switching chip when the switching chip is powered on.

[0111] In this embodiment, when the management system provided in this application includes a second multiplexer, such as... Figure 10As shown, the spatial location of the switching chip's firmware is connected to the switching chip via a second multiplexer, forming a firmware configuration channel. This firmware configuration channel is used to configure the switching chip's firmware when it is powered on. Specifically, in this firmware configuration channel, the spatial location of the switching chip's firmware is connected to one of the input / output ports of the second multiplexer (e.g., ...). Figure 10 The second multiplexer in the circuit is connected to port 3), and the switching chip is connected to another input / output port of the second multiplexer (such as port 3). Figure 10 The second multiplexer in the circuit connects to port 2). For example, as shown... Figure 9 and Figure 10 As shown, after the baseboard management controller controls the CPU to upgrade the firmware in the Flash memory of the switching chip, it restores the connection between the firmware location of the switching chip and the switching chip, thereby enabling the switching chip to perform firmware configuration during subsequent power-on. At this time, the baseboard management controller sends corresponding information through the first control channel. The first logic device obtains the corresponding control signal for the second multiplexer based on the information. The first logic device sends the control signal for the second multiplexer to the second multiplexer through the upgrade control sub-channel to control the connection between ports 2 and 3 in the second multiplexer and to control the disconnection of port 1 in the second multiplexer, so that the firmware configuration channel between the switching chip and the firmware location of the switching chip can be connected, thereby enabling the switching chip to perform firmware configuration during subsequent power-on.

[0112] The management system provided in this application embodiment uses a gigabit switching chip as the core of the management system in terms of hardware, which has at least one RGMII interface data channel (e.g., Figure 10 The third channel in the middle) and two MDI interface data channels (such as Figure 10 The second and fourth channels in the middle), have one MDC / MDIO interface configuration management channel (such as Figure 10 The multiplexer in the middle connects to the first / second management channel of the switching chip, and an I2C / SPI interface Flash loading channel (such as...). Figure 10 The second multiplexer in the circuit connects to the switching chip. The BMC connects to the switching chip via the RGMII interface, providing a data communication channel. The BMC connects to the switching chip via the MDC / MDIO interface for configuration and management. The BMC connects to the external Flash memory of the switching chip via the I2C / SPI interface for firmware upgrades. On the CPU side, an I2C / SPI interface is extended via the FPGA (e.g.,...). Figure 10 The second upgrade channel extended from the second logic device in the middle) and the MDC / MDIO interface (such as Figure 10The second management channel, extended from the second logic device, connects to the switching chip after passing through a multiplexer and a first multiplexer. This enables redundant backup design of the management and firmware upgrade links for the switching chip and its external Flash memory. Similarly, the CPU provides an MDI interface to connect to the switching chip as a data communication channel. Communication data between the BMC and CPU resides within the switching chip, allowing for multiple path forwarding. This provides gigabit management paths for both the BMC and CPU, and also enables gigabit communication between them. Logically, the first logic device controls the switching of each multiplexer to achieve manual or automatic switching of the switching chip's management configuration and firmware upgrades in the external Flash memory.

[0113] In this embodiment, both the CPU and BMC provide an MDC / MDIO interface (e.g., Figure 10 The first and second management channels (connected to multiplexers respectively) are used to manage and configure the switching chip. Two MDC / MDIO channels on the CPU and BMC sides are connected to the multiplexer. Under the logic control of the first logic device, the multiplexer switches and connects the channels, enabling automatic and manual switching of switching chip management. Switching chip access management does not require the CPU or BMC to configure the Layer 2 switching chip; the chip configuration is loaded automatically from the external Flash memory. Here, access management mainly refers to the CPU and BMC gaining control over switching information, accessing the switching chip's registers, and synchronizing port link status information for easier maintenance. Figure 3 and Figure 10 As shown, the CPU uses the PCIe interface (such as...) Figure 10The interface connecting the CPU and the second logic device is connected to the second logic device. The analog output MDC / MDIO interface of the second logic device is connected to input 1 of the multiplexer. Simultaneously, the MDC / MDIO interface output by the BMC is connected to input 2 of the multiplexer, and output 3 of the multiplexer is connected to the MDC / MDIO interface of the switching chip. The CPU reads and writes the registers of the first logic device through the interface corresponding to the second control channel to control the multiplexer. The high and low level changes of the multiplexer's control pins determine the input and output of the multiplexer. Specifically, it can be defined that when the control pin of the multiplexer input through the management control channel is logic high, the MDC / MDIO on the second logic device side is selected, i.e., ports 1 and 3 of the multiplexer are connected; when the control pin of the multiplexer input through the management control channel is logic low, the MDC / MDIO on the substrate management controller side is selected, i.e., ports 2 and 3 of the multiplexer are connected. The BMC and the first logic device are connected via an interface (preferably I2C) corresponding to the first control channel. The BMC acts as the I2C master device, reading and writing to the registers of the first logic device through the first control channel to control the multiplexer. The high and low level changes of the multiplexer's control pins determine its input and output. Both the BMC and the CPU can gain control of the switching chip. If either the CPU or the BMC malfunctions, the registers of the first logic device can be manually written to regain control of the switching chip.

[0114] In this embodiment, as Figure 10 As shown, both the CPU and BMC provide one I2C / SPI interface (e.g. Figure 10 The first and second upgrade channels (in the system) are connected to the external Flash memory of the switching chip for upgrading the firmware in the external Flash. Under logic control, the CPU and BMC can automatically and manually switch the upgrade channels of the external Flash memory of the switching chip. Specifically, as shown... Figure 9 and Figure 10 As shown, the CPU uses the PCIe interface (such as...) Figure 10 The interface connecting the CPU and the second logic device is connected to the second logic device. The analog output I2C / SPI interface of the second logic device is connected to input 1 of the first multiplexer. Simultaneously, the I2C / SPI interface output by the BMC is connected to input 2 of the first multiplexer. Output 3 of the first multiplexer is connected to input 1 of the second multiplexer. Port 2 of the second multiplexer is connected to the I2C / SPI interface of the switching chip, and port 3 of the second multiplexer is connected to the external Flash memory of the switching chip. The first logic device outputs two control ports (such as...). Figure 9The upgrade control channel is connected to the first multiplexer, and the upgrade control sub-channel is connected to the second multiplexer, respectively, for selection. The BMC connects to the first and second multiplexers via an I2C interface (e.g., ...). Figure 9 The CPU reads and writes the registers of the first logic device through the first control channel, thereby controlling the upgrade control channel to output control signals to the first multiplexer and controlling the upgrade control sub-channel to output control signals to the second multiplexer. Correspondingly, the CPU uses the LPC interface (such as...) Figure 9 The second control channel reads and writes the registers of the first logic device to achieve the same control upgrade as described above. The control upgrade control channel outputs control signals to the first multiplexer, and the control upgrade control sub-channel outputs control signals to the second multiplexer. Both the BMC and the CPU can acquire control to upgrade the external Flash of the switching chip. End users can acquire upgrade control over the external Flash of the switching chip by writing to the registers of the first logic device as needed.

[0115] Based on the same inventive concept, in the second aspect of the embodiments of this application, such as Figure 11 As shown, this application provides a management method applied to a management system provided in the first aspect of this application, the method comprising:

[0116] S1: Determine the execution action corresponding to the received execution information;

[0117] S2: When the execution action indicates that the CPU is performing network interface fault diagnosis, the CPU performs fault diagnosis on the network interface through the first channel;

[0118] S3: When the execution action characterization substrate management controller transmits data to the CPU, the substrate management controller transmits data to the CPU through the first channel, the second channel and the third channel;

[0119] S4: When the execution action indicates that the baseboard management controller transmits data to a device connected via a network interface, the baseboard management controller transmits the data to the device connected via the network interface through the third channel and the fourth channel;

[0120] S5: When the execution action represents the CPU transmitting data to a device connected through the network interface, the CPU transmits data to the device connected through the network interface through the first channel, the second channel, and the fourth channel.

[0121] Optionally, the method further includes:

[0122] When the execution action indicates that the baseboard management controller manages the switching chip, the baseboard management controller manages the switching chip based on the first management channel;

[0123] When the execution action represents the CPU managing the switching chip, the CPU manages the switching chip based on the second management channel;

[0124] When the execution action represents the switching of the management of the switching chip by the baseboard management controller, the baseboard management controller controls the port on / off of the multiplexer through the first management control channel to control the on / off of the first management channel and the second management channel;

[0125] When the execution action represents the switching of the CPU control over the management of the switching chip, the CPU controls the port on / off of the multiplexer through the second management control channel to control the on / off of the first management channel and the second management channel.

[0126] Optionally, the method further includes:

[0127] When the execution action indicates that the baseboard management controller is upgrading the firmware of the switching chip, the baseboard management controller upgrades the firmware of the switching chip based on the first upgrade channel;

[0128] When the execution action indicates that the CPU is upgrading the firmware of the switching chip, the CPU upgrades the firmware of the switching chip based on the second upgrade channel;

[0129] When the execution action represents the switching of the firmware upgrade of the switching chip controlled by the baseboard management controller, the baseboard management controller controls the port on / off of the first multiplexer through the first upgrade control channel to control the on / off of the first upgrade channel and the second upgrade channel.

[0130] When the execution action represents the switching of the firmware upgrade of the switching chip controlled by the CPU, the CPU controls the port on / off of the first multiplexer through the second upgrade control channel to control the on / off of the first upgrade channel and the second upgrade channel.

[0131] Based on the same inventive concept, in a third aspect of the embodiments of this application, such as Figure 12As shown, this application provides an electronic device 1200, which includes a processor 1201, a memory 1202, and a computer program stored in the memory and running on the processor. When the computer program is executed by the processor, it implements the steps in the extended memory frequency modulation method as described in the first aspect of this application.

[0132] Based on the same inventive concept, in a fourth aspect of the embodiments of this application, this application provides a computer non-volatile readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of the extended memory frequency modulation method described in the first aspect of this application.

[0133] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer non-volatile readable storage medium or transmitted from one computer non-volatile readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer non-volatile readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid state disks (SSDs)).

[0134] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0135] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0136] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A management system, characterized in that, The system includes: a baseboard management controller, a CPU, a switching chip, an Ethernet controller, a network transformer, and a network interface; The CPU is connected to the Ethernet controller to form a first channel; The CPU is used to troubleshoot the network interface through the first channel; The Ethernet controller is connected to the switching chip to form a second channel; The baseboard management controller is connected to the switching chip to form a third channel; The switching chip is connected to the network interface via the network transformer, forming a fourth channel; The baseboard management controller is used to transmit data with the CPU through the first channel, the second channel and the third channel, and to transmit data with the device connected through the network interface through the third channel and the fourth channel; The CPU is used to transmit data with devices connected through the network interface via the first channel, the second channel, and the fourth channel. The baseboard management controller is connected to the CPU to form an instruction channel.

2. The system according to claim 1, characterized in that, The system also includes: a first logic device and a multiplexer; The baseboard management controller is connected to the switching chip through the multiplexer to form a first management channel; The first management channel is used by the baseboard management controller to manage the switching chip based on the first management channel; The CPU is connected to the switching chip via the multiplexer, forming a second management channel; The second management channel is used by the CPU to manage the switching chip based on the second management channel; The baseboard management controller is connected to the first logic device to form a first control channel; The first logic device is connected to the multiplexer to form a management and control channel; The first control channel and the management control channel together constitute the first management control channel; The first management control channel is used by the substrate management controller to control the port on / off of the multiplexer through the first management control channel, so as to control the on / off of the first management channel and the second management channel; The CPU is connected to the first logic device to form a second control channel; The second control channel and the management control channel together constitute the second management control channel; The second management control channel is used by the CPU to control the port on / off of the multiplexer through the second management control channel, so as to control the on / off of the first management channel and the second management channel.

3. The system according to claim 2, characterized in that, If the system further includes a second logic device, the connection between the CPU in the second management channel and the multiplexer includes: the CPU being connected to the multiplexer via the second logic device.

4. The system according to claim 3, characterized in that, The system also includes: a first multiplexer; The baseboard management controller is connected to the spatial location of the firmware of the switching chip through the first multiplexer, forming a first upgrade channel; The first upgrade channel is used by the baseboard management controller to upgrade the firmware of the switching chip based on the first upgrade channel; The CPU is connected to the firmware location of the switching chip via the first multiplexer, forming a second upgrade channel; The second upgrade channel is used by the CPU to upgrade the firmware of the switching chip based on the second upgrade channel; The first logic device is connected to the first multiplexer to form an upgrade control channel; The first control channel and the upgrade control channel together constitute the first upgrade control channel; The first upgrade control channel is used by the baseboard management controller to control the port on / off of the first multiplexer through the first upgrade control channel, so as to control the on / off of the first upgrade channel and the second upgrade channel; The second control channel and the upgrade control channel together constitute the second upgrade control channel; The second upgrade control channel is used by the CPU to control the on / off state of the port of the first multiplexer, thereby controlling the on / off state of the first upgrade channel and the second upgrade channel.

5. The system according to claim 4, characterized in that, The CPU in the second upgrade channel is connected to the first multiplexer, including: the CPU is connected to the first multiplexer through the second logic device.

6. The system according to claim 5, characterized in that, In the case where the system further includes a second multiplexer, the first multiplexer in the first upgrade channel and the second upgrade channel is connected to the spatial location of the firmware of the switching chip, including: the first multiplexer is connected to the spatial location of the firmware of the switching chip through the second multiplexer. The first logic device is connected to the second multiplexer to form an upgrade control sub-channel; The first control channel and the upgrade control channel together constitute the first upgrade control channel, which includes: the first control channel, the upgrade control channel and the upgrade control sub-channel together constitute the first upgrade control channel; The second control channel and the upgrade control channel together constitute the second upgrade control channel, which includes: the second control channel, the upgrade control channel and the upgrade control sub-channel together constitute the second upgrade control channel.

7. The system according to claim 6, characterized in that, The system also includes: The firmware location of the switching chip is connected to the switching chip via the second multiplexer to form a firmware configuration channel; The firmware configuration channel is used to configure the firmware of the switching chip when the switching chip is powered on.

8. A management method, characterized in that, Applied to the management system according to any one of claims 1 to 7, the method comprises: Based on the received execution information, determine the execution action corresponding to the execution information; When the execution action characterizes the CPU to perform network interface fault diagnosis, the CPU performs fault diagnosis on the network interface through the first channel; When the execution action characterization substrate management controller transmits data to the CPU, the substrate management controller transmits the data to the CPU through the first channel, the second channel, and the third channel; When the execution action represents the baseboard management controller transmitting data to a device connected via a network interface, the baseboard management controller transmits the data to the device connected via the network interface through the third and fourth channels; When the execution action represents the CPU transmitting data to a device connected through the network interface, the CPU transmits data to the device connected through the network interface via the first channel, the second channel, and the fourth channel.

9. An electronic device, characterized in that, include: A processor, a memory, and a computer program stored in the memory and running on the processor, wherein the computer program, when executed by the processor, implements the steps of a management method as described in claim 8.

10. A computer-defined non-volatile readable storage medium, characterized in that, The computer non-volatile readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the management method as described in claim 8.

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