Buffered oxide etch and its use in gate oxide sidewall modification
Patent Information
- Application Number
- CN202311566112.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-22
- Publication Date
- 2026-09-04
- Estimated Expiration
- 2043-11-22
AI Technical Summary
在工艺缩减中降低栅氧化层厚度可以有效地提高晶体管性能,然而薄的氧化层会加重电流遂穿效应并降低氧化层可靠性,同时存在缺陷的氧化层也会导致电路漏电,造成电子元器件的失效,因此对栅氧厚度和侧壁的修饰蚀刻在CMOS器件制造过程中是十分重要的一道工序
本发明提供的蚀刻液,通过合理调配氢氟酸和氟化铵,保证蚀刻速率的稳定,通过加入表面活性剂,既降低了蚀刻液的表面张力,同时也获得了一种低泡的药液,可以保证栅氧表面和侧壁的蚀刻清洗效果;加入增稠剂进一步增加栅氧和蚀刻液作用界面处的粘度,起到平缓局部蚀刻,修饰侧壁形貌。
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Figure CN117844485B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of etching solution technology, specifically relating to a buffered oxide etching solution and its application in the modification of the sidewall of the gate oxide layer. Background Technology
[0002] Functional electronic chemicals refer to specialized chemicals used in the electronics industry. They are commonly used in the cleaning and etching processes during the manufacturing of integrated circuit structures. Chemicals used in wet cleaning and etching processes have high requirements for quality, strong functionality, and high product precision.
[0003] With the rapid development of integrated circuits, the size of processes such as MOS devices is constantly decreasing. Gate oxide layers are often used in transistors to ensure good threshold voltage and current. Reducing the thickness of the gate oxide layer enhances the current drive capability of the transistor and improves its speed and power characteristics. Reducing the gate oxide layer thickness in process shrinkage can effectively improve transistor performance. However, a thin oxide layer can aggravate the current tunneling effect and reduce the reliability of the oxide layer. At the same time, a defective oxide layer can also lead to circuit leakage and cause electronic component failure. Therefore, the modification and etching of gate oxide thickness and sidewalls is a very important process in the manufacturing of CMOS devices. Summary of the Invention
[0004] This invention provides a buffered oxide etchant and its application in the modification of the sidewalls of the gate oxide layer. When etching the surface and sidewalls of the gate oxide layer, it can suppress excessive lateral etching while modifying the sidewall morphology.
[0005] To achieve the above objectives, the present invention adopts the following technical solution: a buffer oxide etching solution, which, by mass percentage, contains 0.1-5% hydrofluoric acid, 15-35% ammonium fluoride, 0.01-1% surfactant and 0.01-2% thickener, with the balance being water; wherein the surfactant is isomeric alcohol polyoxyethylene ether; and the thickener is symmetrical polyol ether.
[0006] Furthermore, both the hydrofluoric acid and ammonium fluoride mentioned are electronic-grade products.
[0007] Furthermore, the isomeric alcohol polyoxyethylene ether is any one or more of isomeric octyl alcohol polyoxyethylene ether, isomeric decaol polyoxyethylene ether, isomeric undecaol polyoxyethylene ether, and isomeric tridecaol polyoxyethylene ether.
[0008] Furthermore, the symmetrical polyol ether is any one or more of ethylene glycol ether, propylene glycol ether, butylene glycol ether, and hexanediol ether.
[0009] Furthermore, the water mentioned is ultrapure water. Furthermore, the etching solution contains 1-3% hydrofluoric acid, 18-28% ammonium fluoride, 0.05-0.5% surfactant and 0.1-1% thickener.
[0010] The present invention also relates to the application of the etchant in the etching and sidewall modification of the gate oxide layer.
[0011] The present invention has the following beneficial effects: The etching solution provided by this invention ensures a stable etching rate by rationally adjusting hydrofluoric acid and ammonium fluoride. By adding a surfactant, the surface tension of the etching solution is reduced, and a low-foaming solution is obtained, which can ensure the etching and cleaning effect on the gate oxide surface and sidewalls. The addition of a thickener further increases the viscosity at the interface between the gate oxide and the etching solution, which can smooth local etching and modify the sidewall morphology.
[0012] This etching solution has low surface tension and is not prone to foaming. It can etch and modify the surface and sidewalls of gate oxide layers of any thickness while suppressing excessive lateral corrosion. Attached Figure Description
[0013] Figure 1 This is a front view of the structure to be etched, where 1 is photoresist, 2 is gate oxide layer, and 3 is silicon substrate.
[0014] Figure 2 This is a front view after etching. Dimension 4 in the figure represents the measurement dimension, reflecting the degree of lateral corrosion. The sidewalls are oblique straight lines, which are used to smooth the ideal sidewall morphology.
[0015] Figure 3 This is another front view after etching. Figure 5 shows the structural morphology of the gate oxide sidewall after excessive etching, which is a concave curve. Detailed Implementation
[0016] The embodiments of the present invention will now be described in detail with reference to examples.
[0017] The components and their contents in the examples and comparative examples are shown in Table 1.
[0018] Table 1
[0019] After the etching solution is prepared and thoroughly mixed, its surface tension is measured using a surface tension meter. The PFA bottle containing the cleaning solution is placed in a low-temperature constant-temperature bath and heated to 23°C. After the temperature stabilizes for a period of time, the bottle containing the cleaning solution is then... Figure 1 The wafer with the structure shown was immersed in the etching solution and etched for 2 minutes; after etching, the results were measured by SEM. Figure 2 The width at position 4 is the remaining width dimension of the gate oxide, which is finally determined by... Figure 3The morphology and surface residue of the sidewall were determined at position 5. The test data of the above embodiments and comparative examples are shown in Table 2 below.
[0020] Table 2
[0021] The specific embodiments of the present invention have been described in detail above, but are merely examples, and the present invention is not limited to the specific embodiments described above. For those skilled in the art, any equivalent modifications and substitutions to the present invention are also within the scope of the present invention. Therefore, all equivalent changes and modifications made without departing from the spirit and scope of the present invention should be covered within the scope of the present invention.
Claims
1. A buffered oxide etching solution, characterized in that: By mass percentage, the etching solution contains 0.1-5% hydrofluoric acid, 15-35% ammonium fluoride, 0.01-1% surfactant, and 0.01-2% thickener, with the balance being water; wherein the surfactant is any one or more of isooctanol polyoxyethylene ether, isodecyl alcohol polyoxyethylene ether, isoundecanol polyoxyethylene ether, and isotridecyl alcohol polyoxyethylene ether; and the thickener is any one or more of ethylene glycol ether, propylene glycol ether, butanediol ether, and hexanediol ether.
2. The etching solution according to claim 1, characterized in that: Both the hydrofluoric acid and ammonium fluoride mentioned are electronic grade products.
3. The etching solution according to claim 1, characterized in that: The water mentioned is ultrapure water.
4. The etching solution according to any one of claims 1 to 3, characterized in that: By mass percentage, the etching solution contains 1-3% hydrofluoric acid, 18-28% ammonium fluoride, 0.05-0.5% surfactant and 0.1-1% thickener.
5. The application of the etchant according to any one of claims 1 to 4 in the etching and sidewall modification of the gate oxide layer.
Citation Information
Patent Citations
Low-foam and uniform-etching etching liquid
CN114350367A
Etchant composition for copper-containing metal film and etching method using the same
KR1020140122614A