Array substrate, electronic reader and manufacturing method of array substrate

Abstract

An array substrate, an electronic reader and a manufacturing method of the array substrate, the array substrate is used in the electronic reader, and the array substrate comprises a substrate and a driving circuit layer, a passivation layer, a planarization layer and a pixel electrode layer which are sequentially stacked on the substrate; wherein the planarization layer has a first thickness at a first position and a second thickness at other positions, the first thickness is greater than the second thickness, so that the parasitic capacitance generated by the pixel electrode layer and the driving circuit layer at the first position is reduced compared with other positions. According to the scheme, the planarization layer with the first thickness is arranged at the first position, and the planarization layer with the second thickness is arranged at other positions, the first thickness is greater than the second thickness, the parasitic capacitance at the first position is reduced, and the stress of the substrate is small, so that the warping is not easy to occur, and the overall performance and display effect of the electronic reader are not affected.

Description

Technical Field

[0001] This application relates to the field of e-reader technology, specifically to an array substrate, an e-reader, and a method for manufacturing the array substrate. Background Technology

[0002] With technological advancements and urbanization, e-readers, characterized by their thinness, portability, low power consumption, and eye-friendly features, are gradually replacing paper and even some LCD displays. This achieves efficient paperless and electricity-free operation, representing a future trend towards intelligentization in many fields.

[0003] With increasing demands for e-reader quality, such as high-temperature operation (above 50°C), high resolution, color display, large size, and efficient production, higher requirements are being placed on TFT backplane technology. Significant parasitic capacitance is generated between the pixel electrodes and the metal traces of other metal layers, thus affecting the overall performance and display effect of the e-reader. Summary of the Invention

[0004] The purpose of this application is to provide an array substrate, an e-reader, and a method for manufacturing the array substrate, thereby solving the problem that large parasitic capacitance affects the overall performance and display effect of the e-reader.

[0005] To achieve the objectives of this application, the following technical solution is provided:

[0006] In a first aspect, the present invention provides an array substrate for an e-reader, comprising: a substrate; a driving circuit layer disposed on the substrate; a passivation layer stacked on the driving circuit layer; a planarization layer stacked on the passivation layer; and a pixel electrode layer stacked on the planarization layer; wherein the planarization layer has a first thickness at a first location and a second thickness at other locations, the first thickness being greater than the second thickness, so that the parasitic capacitance generated by the pixel electrode layer and the driving circuit layer at the first location is reduced compared to that at other locations.

[0007] In one embodiment, the driving circuit layer includes a first metal layer, an insulating layer, a semiconductor layer, and a second metal layer, wherein the first metal layer, the insulating layer, the semiconductor layer, and the second metal layer are sequentially stacked on the substrate; at the first location, the first metal layer includes a first trace and a second trace spaced apart, the semiconductor layer includes a first structure, and the second metal layer includes a third trace; the first trace, the first structure, and the third trace overlap in a direction perpendicular to the substrate, and the pixel electrode layer covers the planarization layer at the first location.

[0008] In one embodiment, the first metal layer further includes a fourth trace at a second location. At the second location, the semiconductor layer further includes a second structure. The second metal layer also includes a fifth trace and a sixth trace spaced apart. A portion of each of the fifth trace and the sixth trace is stacked on both ends of the second structure, and another portion of each is stacked on the insulating layer. The fourth trace and the second structure overlap in a direction perpendicular to the substrate. In a direction opposite to the fifth trace and the sixth trace, the second structure extends beyond the fourth trace by a first distance, the first distance being 1.0 μm-4.0 μm. The fourth trace does not overlap with the fifth trace and the sixth trace in a direction perpendicular to the substrate.

[0009] In one embodiment, the semiconductor layer further includes a first dopant and a second dopant, the first dopant and the second dopant being stacked on the second structure and respectively located at both ends of the second structure, a portion of the fifth trace being stacked on the first dopant, and a portion of the sixth trace being stacked on the second dopant; the first dopant extends towards the second dopant from the fifth trace by a second distance, and the second dopant extends towards the first dopant from the sixth trace by a third distance, the second distance and the third distance being both 0.4μm-0.8μm.

[0010] In one embodiment, the planarization layer has a first hole at a third position, the third position being spaced apart from the first position, the pixel electrode layer covering the inner wall of the first hole and extending to the passivation layer, at the third position, the first metal layer further includes a first electrode plate, the second metal layer further includes a second electrode plate, and the first electrode plate and the second electrode plate overlap in a direction perpendicular to the substrate.

[0011] In one embodiment, the insulating layer has a second hole at a fourth position, the planarization layer has a third hole at the fourth position, and the passivation layer has a fourth hole at the fourth position. The second hole, the third hole, and the fourth hole are connected. At the fourth position, the first metal layer further includes a third electrode plate, and the second metal layer further includes a fourth electrode plate. The fourth electrode plate covers the inner wall of the second hole and is connected to the third electrode plate. The pixel electrode layer covers the inner walls of the third hole and the fourth hole and is connected to the fourth electrode plate.

[0012] In one embodiment, the pixel electrode layer includes a third metal layer and a conductive layer, the third metal layer and the conductive layer being stacked sequentially on the planarization layer, and the coverage area of ​​the conductive layer being larger than the coverage area of ​​the third metal layer.

[0013] In a second aspect, the present invention also provides an e-reader comprising an array substrate as described in any of the various embodiments of the first aspect.

[0014] Thirdly, the present invention also provides a method for fabricating an array substrate, the method comprising: forming a driving circuit layer on the substrate; forming a passivation layer on the driving circuit layer; forming a planarization layer on the passivation layer; forming a pixel electrode layer on the planarization layer; wherein the planarization layer has a first thickness at a first location and a second thickness at other locations, the first thickness being greater than the second thickness, so that the parasitic capacitance generated by the pixel electrode layer and the driving circuit layer at the first location is reduced compared to other locations.

[0015] In one embodiment, the fabrication method further includes: forming a third hole in the planarization layer at a fourth position on the array substrate; forming a fourth hole in the passivation layer through the third hole; covering the inner walls of the third hole and the fourth hole with the pixel electrode layer and connecting it to the driving circuit layer.

[0016] By setting a planarization layer with a first thickness at a first position and a second thickness at other positions, where the first thickness is greater than the second thickness, the distance between the pixel electrode layer and the driving circuit layer at the first position is greater than the distance at other positions. This reduces the parasitic capacitance of the pixel electrode layer and the driving circuit layer at the first position, thereby improving the overall performance and display effect of the e-reader. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a top view of an array substrate according to one embodiment;

[0019] Figure 2 It is along Figure 1 Cross-sectional structural diagrams of AA, BB, CC, DD, and EE;

[0020] Figure 3 yes Figure 2 Enlarged view of the local structure at point C;

[0021] Figures 4-12 This is a cross-sectional structural diagram of each step in a method for fabricating an array substrate according to one embodiment.

[0022] Explanation of reference numerals in the attached figures:

[0023] 100-Array substrate;

[0024] 10-Substrate;

[0025] 20-Driver circuit layer, 21-First metal layer, 211-First trace, 212-Second trace, 213-Fourth trace, 214-First electrode plate, 215-Third electrode plate, 216-Scan line; 22-Insulating layer, 221-Second hole; 23-Semiconductor layer, 231-First structure, 232-Second structure, 233-First dopant, 234-Second dopant, 235-Channel, L1-First distance, L2-Second distance, L3-Third distance; 24-Second metal layer, 241-Third trace, 242-Fifth trace, 243-Sixth trace, 244-TFT switch, 245-Second electrode plate, 246-Fourth electrode plate, 247-Data line;

[0026] 30 - Passivation layer, 31 - Fourth hole;

[0027] 40 - Planarization layer, 41 - First hole, 42 - Third hole, H1 - First thickness, H2 - Second thickness;

[0028] 50 - Pixel electrode layer, 51 - Third metal layer, 52 - Conductive layer. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] It should be noted that when a component is said to be "fixed" to another component, it can be directly on the other component or it can be in a middle component. When a component is said to be "connected" to another component, it can be directly connected to the other component or it may be in a middle component.

[0031] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items.

[0032] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0033] This invention provides an e-reader, including an array substrate 100 as described in this embodiment. The e-reader can be a color e-reader or a monochrome e-reader. It comprises an upper substrate (not shown), an electrophoretic layer (not shown), and the array substrate 100 as described in this embodiment. The upper substrate and the array substrate 100 control the movement of charged particles in the electrophoretic layer by changing the pixel voltage. A TFT switch 244 is integrated on the array substrate 100. The pixel voltage on this side can be precisely controlled by the TFT switch 244 to move and concentrate the charged particles in the electrophoretic layer in the display area. The image is then generated by reflecting ambient light or by applying additional light to the surface. This e-reader, using the array substrate 100 as described in this embodiment, reduces parasitic capacitance, thereby improving the overall performance and display effect of the e-reader.

[0034] Please refer to Figure 1 and Figure 2 This invention provides an array substrate 100 for an e-reader, comprising a substrate 10 and a driving circuit layer 20 and a passivation layer 30 (not on the substrate 10) sequentially stacked on the substrate 10. Figure 1 (shown in), planarization layer 40 (not shown in) Figure 1 (as shown in the image) and pixel electrode layer 50.

[0035] Optionally, the substrate 10 may be composed of materials such as glass and quartz, and other structures on the substrate 10 (e.g., a buffer layer). For example, the substrate 10 may be made of glass, which has a low coefficient of thermal expansion, low density, and high chemical stability, to ensure that the deformation and warping of the glass substrate 10 are smaller during processing and use, and that it is less prone to material decomposition and appearance changes when subjected to corrosion from various acidic or alkaline chemical agents or gases. Optionally, the thickness of the substrate 10 may be 0.3 mm to 0.7 mm, specifically 0.3 mm, 0.4 mm, 0.5 mm, 0.6 mm, 0.7 mm, etc., without limitation.

[0036] Optionally, the driving circuit layer 20 includes a first metal layer 21 and an insulating layer 22 (not on) Figure 1 (As shown in the figure), semiconductor layer 23 and second metal layer 24, the first metal layer 21, insulating layer 22, semiconductor layer 23 and second metal layer 24 are sequentially stacked on the substrate 10.

[0037] Optionally, the first metal layer 21 is stacked on the substrate 10 for carrying signal current, common current, or other control current, etc., without limitation. Optionally, the first metal layer 21 can be made of metals such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper, or a combination structure of the above-mentioned thin films can be used, without limitation.

[0038] Optionally, the insulating layer 22 covers the first metal layer 21, so that the first metal layer 21 is insulated from the semiconductor layer 23 and the second metal layer 24, respectively. The insulating layer 22 can be made of inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride, and there are no restrictions.

[0039] Optionally, the semiconductor layer 23 is disposed between the insulating layer 22 and the second metal layer 24 to form a switch or change the capacitance. The semiconductor layer 23 is usually an island structure, and the material can be amorphous silicon, polycrystalline silicon, metal oxide, etc., without limitation.

[0040] Optionally, the second metal layer 24 is stacked on the semiconductor layer 23 or the insulating layer 22 to carry data current, common current, or other control current, etc., without limitation. Optionally, the material used for the second metal layer 24 is similar to the material of the first metal layer 21 mentioned above, which can be referred to for reference only and will not be described again.

[0041] Optionally, the passivation layer 30 covers the entire substrate 10 and is stacked on the driving circuit layer 20. The passivation layer 30 is used to cover the second metal layer 24 and the semiconductor layer 23 to provide insulation protection for the second metal layer 24 and the semiconductor layer 23. At the same time, the passivation layer 30 isolates the second metal layer 24 from the semiconductor layer 23 and the planarization layer 40. Optionally, the passivation layer 30 can be made of inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride, without limitation.

[0042] Optionally, a planarization layer 40 is stacked on the passivation layer 30, and the first position of the planarization layer 40 ( Figure 2The pixel electrode layer 50 (as shown in positions AA and BB) has a first thickness H1, and other positions have a second thickness H2. The first thickness H1 is greater than the second thickness H2, so that the parasitic capacitance generated by the pixel electrode layer 50 and the driving circuit layer 20 at the first position is reduced compared to other positions. Optionally, the first thickness H1 can be 1μm (micrometer) to 3μm, specifically 1μm, 1.5μm, 2μm, 2.5μm, and 3μm, etc., without limitation. Optionally, the difference between the first thickness H1 and the second thickness H2 can be 0.1μm (micrometer) to 1.0μm, specifically 0.1μm, 0.2μm, 0.3μm, 0.4μm, 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, and 1.0μm, without limitation. Optionally, the planarization layer 40 can be made of organic photoresist material, which can be either positive or negative photoresist, without limitation. Optionally, the thickness of the passivation layer 30 can be 0.05μm-0.6μm, specifically 0.05μm, 0.1μm, 0.15μm, 0.2μm, 0.25μm, 0.3μm, 0.35μm, 0.4μm, 0.45μm, 0.5μm, 0.55μm, and 0.6μm, etc., without limitation.

[0043] The pixel electrode layer 50 includes a third metal layer 51 and a conductive layer 52 (not in the image). Figure 1 As shown in the figure, the third metal layer 51 is stacked on the planarization layer 40 and generates a first parasitic capacitance with the first metal layer 21 and a second parasitic capacitance with the second metal layer 24 at the first position; the conductive layer 52 is stacked on the third metal layer 51 and connected to the third metal layer 51.

[0044] Optionally, the third metal layer 51 is made of an opaque metallic material to protect the drive circuit layer 20 from excessive leakage current caused by exposure to ambient light. Specific materials include molybdenum, aluminum, aluminum-nickel alloys, molybdenum-tungsten alloys, chromium, and copper, without limitation. Optionally, the conductive layer 52 can be made of a transparent conductive material or a low-resistivity opaque conductive material, specifically indium tin oxide or indium zinc oxide, without limitation. Optionally, when the conductive layer 52 is made of an opaque conductive material, the third metal layer 51 is not required, and the conductive layer 52 is directly electrically connected to the second metal layer 24.

[0045] By providing a planarization layer 40 with a first thickness H1 at a first location and providing planarization layers 40 with a second thickness H2 at other locations, the distance between the third metal layer 51 and the first metal layer 21 and the second metal layer 24 at the first location is increased, thereby reducing the parasitic capacitance at the first location. The planarization layer 40 will generate stress on the substrate due to factors such as temperature, tension and impurity effects. In the prior art, the method of thickening the planarization layer 40 as a whole is usually used to reduce parasitic capacitance. However, the stress is large due to the thickness of the planarization layer 40. In this invention, the planarization layer 40 with a first thickness H1 is only provided at the first location, so that the substrate 10 is less stressed by the planarization layer 40, and is less likely to warp, thereby affecting the overall performance and display effect of the e-reader.

[0046] Please refer to Figure 1 and Figure 2 The pixel electrode layer 50 covers the planarization layer 40 at a first position. At the first position, the first metal layer 21 includes a first trace 211 and a second trace 212 spaced apart. The first trace 211 and the second trace 212 are signal traces used to transmit signals input or output from a certain interface of the array substrate 10. The first trace 211 is used to generate a third parasitic capacitance with the aforementioned third metal layer 51, and the second trace 212 is used to generate a first parasitic capacitance with the third metal layer 51. The second metal layer 24 includes a third trace 241, which is used to generate a first parasitic capacitance with the third metal layer 51. The metal layer 51 generates a second parasitic capacitance; the third trace 241 has a common voltage for providing a common voltage for the storage capacitors of the array substrate 100; the semiconductor layer 23 includes a first structure 231, which is an island structure; the first trace 211, the first structure 231 and the third trace 241 overlap in a direction perpendicular to the substrate 10 and generate a fourth parasitic capacitance between the first trace 211 and the third trace 241. The first structure 231 is used to increase the distance between the first trace 211 and the third trace 241 to reduce the fourth parasitic capacitance.

[0047] Optionally, the coverage area of ​​the first structure 231 may be greater than or equal to the area of ​​overlap between the first trace 211 and the third trace 241, so as to minimize the fourth parasitic capacitance.

[0048] By setting a first structure 231 and an insulating layer 22 between the first trace 211 and the third trace 241, compared to setting an insulating layer 22 only between the first trace 211 and the third trace 241, this solution retains the first structure 231 between the first trace 211 and the third trace 241, increases the distance between the first trace 211 and the third trace 241, and reduces the fourth parasitic capacitance.

[0049] Please refer to Figure 1 and Figure 2 The first metal layer 21 also includes a second location ( Figure 2 The fourth trace 213 (located at position CC) is used to connect to the scan line 216, which is used to transmit the scan signal. Optionally, the scan signal includes different first and second signals. For example, the first signal is a voltage less than a threshold voltage, and the second signal is a voltage greater than the threshold voltage.

[0050] At the second location, the semiconductor layer 23 further includes a second structure 232. The first structure 231 is an island-shaped structure. The fourth trace 213 and the second structure 232 overlap in a direction perpendicular to the substrate 10, so that the first signal and the second signal through the fourth trace 213 can control the movement direction of charge carriers in the second structure 232, allowing the second structure 232 to switch between a first state and a second state. For example, the first state is when the conductivity of the second structure 232 is less than a preset value, and the second state is when the conductivity of the second structure 232 is greater than or equal to the preset value.

[0051] The second metal layer 24 also includes a fifth trace 242 and a sixth trace 243 spaced apart. The fifth trace 242 is used to connect to a data line 247, which is used to transmit data signals of the display content. The sixth trace 243 is used to connect to the pixel electrode layer 50 and transmit data signals to the pixel electrode layer 50 to control the voltage on the pixel electrode layer 50.

[0052] The fifth trace 242 and the sixth trace 243 each have a portion stacked on both ends of the second structure 232, and another portion of each is stacked on the insulating layer 22. When the second structure 232 is in the first state, no data signal passes between the fifth trace 242 and the sixth trace 243; when the second structure 232 is in the second state, a data signal passes between the fifth trace 242 and the sixth trace 243.

[0053] The fourth trace 213, the second structure 232, the fifth trace 242, and the sixth trace 243 together form the TFT switch 244. When the scan signal is the first signal, the second structure 232 is in the first state, and the TFT switch 244 is in the off state. At this time, no data signal passes between the fifth trace 242 and the sixth trace 243. When the scan signal is the second signal, the second structure 232 is in the second state, and the TFT switch 244 is in the on state. At this time, a data signal passes between the fifth trace 242 and the sixth trace 243.

[0054] In the direction opposite to the fifth trace 242 and the sixth trace 243, the second structure 232 extends out of the fourth trace 213 by a first distance L1, the first distance L1 being 1.0μm-4.0μm. The fourth trace 213 does not overlap with the fifth trace 242 and the sixth trace 243 in the direction perpendicular to the substrate 10.

[0055] By setting a fourth trace 213, a second structure 232, and a fifth trace 242 and a sixth trace 243 spaced apart at a second position, the fourth trace 213 is connected to the scan line 216 and is aligned with the second structure 232. The fifth trace 242 is connected to the data line 247 and the sixth trace 243 is connected to the pixel electrode layer 50. The fifth trace 242 and the sixth trace 243 are partially stacked at both ends of the second structure 232 to form a TFT switch 244 for transmitting the data signal of the data line 247 to the pixel electrode layer 50. Meanwhile, the fourth trace 213 does not overlap with the fifth trace 242 and the sixth trace 243 in the direction perpendicular to the substrate 10, and in the opposite direction of the fifth trace 242 and the sixth trace 243, the second structure 232 extends out of the fourth trace 213 by a first distance L1, so that no parasitic capacitance is generated between the fourth trace 213 and the fifth trace 242 and the sixth trace 243 and no backlight phenomenon occurs, thereby realizing the miniaturization of the TFT switch 244.

[0056] Please refer to Figure 3 The semiconductor layer 23 further includes a first dopant 233 and a second dopant 234, which are stacked on the second structure 232 and located at opposite ends of the second structure 232. A portion of the fifth trace 242 is stacked on the first dopant 233, and a portion of the sixth trace 243 is stacked on the second dopant 234. The first dopant 233 extends a second distance L2 toward the second dopant 234 from the fifth trace 242, and the second dopant 234 extends a third distance L3 toward the first dopant 233 from the sixth trace 243. Both the second distance L2 and the third distance L3 are 0.4 μm to 0.8 μm.

[0057] Optionally, a channel 235 is formed on the portion of the first dopant 233 and the second dopant 234 that is not in contact with the aforementioned second structure 232. The length of the channel 235 is equal to the minimum distance between the first dopant 233 and the second dopant 234 in the direction parallel to the substrate 10. Optionally, when the length of the channel 235 is less than a critical value, the first dopant 233 and the second dopant 234 are prone to short circuits; when the length of the channel 235 is greater than the critical value, the conductivity of the channel 235 is low and cannot meet the performance requirements of the e-reader.

[0058] Optionally, the first dopant 233 and the second dopant 234 are amorphous silicon, polycrystalline silicon, or metal oxides doped with positive ions. For example, the first dopant 233 and the second dopant 234 are doped with n... + Amorphous silicon with ions n + -a-Si.

[0059] Traditionally, the fifth trace 242 completely covers the first dopant 233, and the sixth trace 243 completely covers the second dopant 234. At operating temperatures of 50°C and above, charge carriers in the first dopant 233 and the second dopant 234 easily escape into the fifth trace 242 and the sixth trace 243 due to the influence of the electric field, causing a decrease in the conductivity of the first dopant 233 and the second dopant 234, and this process is irreversible.

[0060] This invention, by setting the first dopant 233 to extend a fifth trace 242 at a second distance L2 toward the second dopant 234, and the second dopant 234 to extend a sixth trace 243 at a third distance L3 toward the first dopant 233, ensures the effective length of the channel 235 and the electrical properties of the TFT switch 244, while preventing charge carriers in the first dopant 233 and the second dopant 234 from escaping into the fifth trace 242 and the sixth trace 243 at higher temperatures. This maintains the stability of the first dopant 233 and the second dopant 234 and extends the service life of the e-reader.

[0061] Please refer to Figure 1 and Figure 2 The planarization layer 40 is in the third position ( Figure 2 A first hole 41 is provided at the position shown in DD. A third position is provided at an interval from the first position. A third metal layer 51 and a conductive layer 52 cover the inner wall of the first hole 41 and extend to the passivation layer 30. Optionally, the cross-sectional shape of the first hole 41 can be rectangular, trapezoidal, arc-shaped, etc., without limitation.

[0062] At the third position, the first metal layer 21 further includes a first electrode plate 214, and the second metal layer 24 further includes a second electrode plate 245. The second electrode plate 245 is electrically connected to the aforementioned third trace 241, and the first electrode plate 214 is electrically connected to the third metal layer 51. The first electrode plate 214 and the second electrode plate 245 overlap in a direction perpendicular to the substrate 10. The first electrode plate 214, the second electrode plate 245, and the third metal layer 51 are used to generate a storage capacitor. Optionally, the coverage area of ​​the first electrode plate 214 and the coverage area of ​​the second electrode plate 245 are equal to the bottom wall area of ​​the first hole 41.

[0063] By opening a first hole 41 at the third position in the planarization layer 40, and providing a first electrode plate 214 and a second electrode plate 245 at the third position, the first electrode plate 214 is electrically connected to the third metal layer 51, and a storage capacitor is generated between the first electrode plate 214, the second electrode plate 245 and the third metal layer 51. By opening the first hole 41, the distance between the third metal layer 51 and the second electrode plate 245 is reduced, thereby increasing the storage capacitor at the third position.

[0064] Please refer to Figure 2 Insulating layer 22 is in the fourth position ( Figure 2 A second hole 221 is provided at the position shown in EE. A third hole 42 is provided at the fourth position of the planarization layer 40, and a fourth hole 31 is provided at the fourth position of the passivation layer 30. The second hole 221, the third hole 42, and the fourth hole 31 are connected. Optionally, the maximum diameter of the fourth hole 31 is less than or equal to the minimum diameter of the third hole 42. Optionally, the inner walls of the second hole 221, the third hole 42, and the fourth hole 31 can be stepped, so that when the metal layer and the conductive layer 52 cover the inner walls of the holes, they have a supporting structure and are not prone to warping or even separation due to large stress. Optionally, the cross-sectional shape of the second hole 221, the third hole 42, and the fourth hole 31 is similar to that of the first hole 41 mentioned above, and will not be described again.

[0065] At the fourth position, the first metal layer 21 further includes a third electrode plate 215, and the second metal layer 24 further includes a fourth electrode plate 246. The fourth electrode plate 246 covers the inner wall of the second hole 221 and is connected to the third electrode plate 215. The pixel electrode layer 50 covers the inner walls of the third hole 42 and the fourth hole 31 and is connected to the fourth electrode plate 246. The third electrode plate 215 is connected to the first electrode plate 214, and the third metal layer 51 at the fourth position is connected to the third metal layer 51 at the second position. The voltage stored in the storage capacitor at the second position is transmitted to the conductive layer 52 through the third electrode plate 215 and the third metal layer 51 to generate a corresponding pixel voltage. Optionally, the shape of the third metal layer 51 at the fourth position matches the inner wall shape of the third hole 42 and the fourth hole 31, and the third metal layer 51 covers the inner walls of the third hole 42 and the fourth hole 31 and the fourth electrode plate 246. The conductive layer 52 covers the third metal layer 51.

[0066] By setting the second hole 221, the third hole 42 and the fourth hole 31, the third substrate 10, the fourth substrate 10 and the pixel electrode layer 50 can be connected through the second hole 221, the third hole 42 and the fourth hole 31. The voltage stored in the storage capacitor at the second position is transmitted to the conductive layer 52 through the third electrode plate 215 and the third metal layer 51 to generate the corresponding pixel voltage, thereby controlling the movement of charged particles in the electrophoretic layer.

[0067] Please refer to Figure 2The conductive layer 52 has a larger coverage area than the third metal layer 51 to ensure a sufficiently large display area. Optionally, the third metal layer 51 only covers the locations where the first metal layer 21 and the second metal layer 24 exist, to generate storage capacitance or parasitic capacitance and conduct current to the conductive layer 52. Optionally, the conductive layer 52 covers the entire array substrate 100, with adjacent scan lines 216 and adjacent data lines 247 as boundaries. There is a spacing distance between the conductive layer 52 and the adjacent scan lines 216 and adjacent data lines 247, which is 0.1μm-1.0μm, specifically 0.1μm, 0.2μm, 0.3μm, 0.4μm, 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, 1.0μm, etc., without limitation.

[0068] By setting the coverage area of ​​the conductive layer 52 to be larger than that of the third metal layer 51, the array substrate 100 is ensured to have a sufficiently large display area, enabling the e-reader to have higher brightness and display effect.

[0069] Please refer to Figures 4-12 This invention also provides a method for fabricating an array substrate 100, which includes techniques such as cleaning, film formation, photoresist coating, exposure, development, stripping, and etching. Optionally, metal materials are typically formed using sputtering, and non-metals are typically formed using chemical vapor deposition (CVD). Optionally, metal etching is typically performed using wet etching, and non-metal etching is performed using dry etching. The fabrication method in this invention includes:

[0070] Please refer to Figures 4-7 A driving circuit layer 20 is formed on the substrate 10, that is, a first metal layer 21 is sequentially formed and patterned, an insulating layer 22 is patterned, a second metal layer 24 is patterned, and a semiconductor layer 23 is patterned on the substrate 10.

[0071] Taking the process of forming the first metal layer 21 and patterning it as an example, please refer to... Figure 4 After the substrate 10 is cleaned, a first metal layer 21 of a certain thickness is sputtered to form it. Then, positive photoresist (not shown) is coated on the first metal layer 21, and the areas of the first metal layer 21 that need to be removed are exposed. The photoresist exposed to the light will dissolve in the developer after contacting it, while the areas not exposed to the light will have photoresist left to continue covering the first metal layer 21. Subsequently, the first metal layer 21 that needs to be removed is wet-etched using an etching solution. Finally, the substrate 10 is placed in a stripping solution to remove the remaining photoresist. Through the above process, scan lines 216, first traces 211, second traces 212, fourth traces 213, first electrode 214, and third electrode 215 are formed on the substrate 10.

[0072] Optionally, a negative photoresist can be coated on the first metal layer 21. The portion of the negative photoresist exposed to light will not dissolve in the developer, while the portion not exposed to light will dissolve in the developer and expose the first metal layer 21 to be etched.

[0073] Optionally, the forming process of the insulating layer 22, the second metal layer 24 and the semiconductor layer 23 is similar to that of the first metal layer 21, and can be referred to without further explanation.

[0074] Please refer to Figure 8 A passivation layer 30 is formed on the driving circuit layer 20. Optionally, the formation process of the passivation layer 30 is similar to that of the first metal layer 21, which can be referred to and will not be described in detail here.

[0075] Please refer to Figure 9 A planarization layer 40 is formed on the passivation layer 30. The planarization layer 40 has a first thickness H1 at a first location and a second thickness H2 at other locations, where the first thickness H1 is greater than the second thickness H2. Optionally, the formation process of the planarization layer 40 is similar to that of the first metal layer 21, and will not be described in detail here.

[0076] Please refer to Figures 11-12 A pixel electrode layer 50 is formed on the planarization layer 40, specifically, a third metal layer 51 is sequentially formed and patterned on the planarization layer 40, and a conductive layer 52 is formed and patterned. After patterning, the third metal layer 51 generates different capacitances at different locations compared to the first metal layer 21 and the second metal layer 24 of the driving circuit layer 20. Optionally, the formation processes of the third metal layer 51 and the conductive layer 52 are similar to those of the first metal layer 21, and will not be elaborated further.

[0077] By using the manufacturing method of this embodiment, the driving circuit layer 20, passivation layer 30, planarization layer 40 and pixel electrode layer 50 are sequentially stacked on the substrate 10, and corresponding metal traces, semiconductor structures, metal plates and vias are formed in each layer. This allows the array substrate 100 to control the pixel electrodes to drive charged particles in the electrophoretic layer to move and gather in the display area, and then generate an image by reflecting ambient light or applying additional light to the surface. At the same time, it also meets the performance requirements of e-readers such as small parasitic capacitance, large storage capacitance and low leakage current.

[0078] Please refer to Figures 8-10 The manufacturing method in this embodiment of the invention further includes:

[0079] A third hole 42 is formed in the planarization layer 40 at the fourth position of the array substrate 100, and a fourth hole 31 is formed in the passivation layer 30 through the third hole 42. Finally, the pixel electrode layer 50 is covered on the inner walls of the second hole 221 and the third hole 42 and connected to the driving circuit layer 20.

[0080] The specific process can be as follows: After the substrate 10 is cleaned, a passivation layer 30 of a certain thickness is formed by vapor phase chemical deposition. Then, a planarization layer 40 of a certain thickness is deposited on the passivation layer 30 by vapor phase chemical deposition. Next, a positive photoresist is coated on the planarization layer 40. The photoresist of the planarization layer 40 includes a completely removed area, a partially removed area, and a retained area. The completely removed area corresponds to the first hole 41 and the third hole 42 of the planarization layer 40, the retained area corresponds to the first position, and the partially removed area corresponds to other positions. After exposure, development, etching, and stripping treatments are performed on the passivation layer 30, the planarization layer 40 forms the first hole 41, the third hole 42, the first thickness H1, and the second thickness H2 on the substrate 10.

[0081] After the substrate 10 is cleaned, the passivation layer 30 is coated with photoresist, exposed, developed, etched and stripped through the third hole 42, and the passivation layer 30 forms a fourth hole 31 on the substrate 10.

[0082] Finally, a third metal layer 51 and a conductive layer 52 are sequentially formed on the inner walls of the planarization layer 40, the first hole 41, the third hole 42 and the fourth hole 31, as well as on the fourth electrode plate 246 exposed in the fourth hole 31 at the third position. The operation steps are similar to those of the first metal layer 21 described above, and can be referred to without further explanation.

[0083] Optionally, negative photoresist can also be coated on the planarization layer 40, passivation layer 30, third metal layer 51 and conductive layer 52. The operation steps are similar to those for coating negative photoresist on the first metal layer 21, and can be referred to without further explanation.

[0084] By first creating a third hole 42 on the planarization layer 40, and then creating a fourth hole 31 through the third hole to the passivation layer 30, the second metal layer 24 is not affected by chemical agents such as developing solution during the fabrication of the planarization layer 40, thus ensuring the normal operation of the drive circuit layer 20.

[0085] In the description of the embodiments of this application, it should be noted that the orientation or positional relationship of the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and other indicators are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0086] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Those skilled in the art will understand that all or part of the processes for implementing the above embodiments and equivalent variations made in accordance with the claims of this application are still within the scope of this application.

Claims

1. An array substrate for use in an e-reader, characterized in that, include: substrate; A driving circuit layer is disposed on the substrate; A passivation layer is stacked on the driving circuit layer; A planarization layer is stacked on the passivation layer; A pixel electrode layer is stacked on the planarization layer; The planarization layer has a first thickness at a first location and a second thickness at other locations, wherein the first thickness is greater than the second thickness, so that the parasitic capacitance generated by the pixel electrode layer and the driving circuit layer at the first location is reduced compared to other locations; the driving circuit layer includes a first metal layer, an insulating layer, a semiconductor layer, and a second metal layer, which are sequentially stacked on the substrate; at the first location, the first metal layer includes a first trace and a second trace spaced apart, the semiconductor layer includes a first structure, and the second metal layer includes a third trace, wherein the first trace, the first structure, and the third trace overlap in a direction perpendicular to the substrate; the pixel electrode layer... The electrode layer covers the planarization layer at the first position; the first metal layer further includes a fourth trace at a second position. At the second position, the semiconductor layer further includes a second structure. The second metal layer further includes a fifth trace and a sixth trace spaced apart. A portion of each of the fifth trace and the sixth trace is stacked at both ends of the second structure, and another portion of each is stacked on the insulating layer. The fourth trace and the second structure overlap in a direction perpendicular to the substrate. In the direction opposite to the fifth trace and the sixth trace, the second structure extends beyond the fourth trace by a first distance, the first distance being 1.0 μm-4.0 μm. The fourth trace does not overlap with the fifth trace and the sixth trace in a direction perpendicular to the substrate.

2. The array substrate according to claim 1, characterized in that, The semiconductor layer further includes a first dopant and a second dopant, which are stacked on the second structure and located at opposite ends of the second structure. A portion of the fifth trace is stacked on the first dopant, and a portion of the sixth trace is stacked on the second dopant. The first dopant extends a second distance toward the second dopant from the fifth trace, and the second dopant extends a third distance toward the first dopant from the sixth trace. Both the second distance and the third distance are 0.4 μm to 0.8 μm.

3. The array substrate according to claim 1, characterized in that, The planarization layer has a first hole at a third position, the third position being spaced apart from the first position. The pixel electrode layer covers the inner wall of the first hole and extends to the passivation layer. At the third position, the first metal layer further includes a first electrode plate, and the second metal layer further includes a second electrode plate. The first electrode plate and the second electrode plate overlap in a direction perpendicular to the substrate.

4. The array substrate according to claim 1, characterized in that, The insulating layer has a second hole at the fourth position, the planarization layer has a third hole at the fourth position, and the passivation layer has a fourth hole at the fourth position. The second hole, the third hole, and the fourth hole are connected. At the fourth position, the first metal layer further includes a third electrode plate, and the second metal layer further includes a fourth electrode plate. The fourth electrode plate covers the inner wall of the second hole and is connected to the third electrode plate. The pixel electrode layer covers the inner walls of the third hole and the fourth hole and is connected to the fourth electrode plate.

5. The array substrate according to claim 1, characterized in that, The pixel electrode layer includes a third metal layer and a conductive layer, which are stacked sequentially on the planarization layer. The coverage area of ​​the conductive layer is larger than that of the third metal layer.

6. An e-reader, characterized in that, The array substrate includes any one of claims 1 to 5.

7. A method for fabricating an array substrate, characterized in that, A method for manufacturing an array substrate as described in any one of claims 1 to 5, the method comprising: A driving circuit layer is formed on the substrate; A passivation layer is formed on the driving circuit layer; A planarization layer is formed on the passivation layer; A pixel electrode layer is formed on the planarization layer; The planarization layer has a first thickness at a first location and a second thickness at other locations, wherein the first thickness is greater than the second thickness, so that the parasitic capacitance generated by the pixel electrode layer and the driving circuit layer at the first location is reduced compared to other locations.

8. The method for fabricating an array substrate according to claim 7, characterized in that, Also includes: A third hole is formed in the planarization layer at the fourth position of the array substrate; A fourth hole is formed on the passivation layer through the third hole; The pixel electrode layer covers the inner walls of the third and fourth holes and is connected to the driving circuit layer.

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