Voltage regulator circuit and corresponding apparatus

Abstract

A circuit includes: a power supply node receiving a supply voltage; an output node providing a regulated voltage; a startup circuit arrangement coupled to the power supply node circuit arrangement; a current generator circuit arrangement coupled to the startup circuit arrangement and generating a current circuit arrangement; a bandgap node coupled to the bandgap circuit arrangement to receive a bandgap voltage; a multiplier circuit arrangement coupled to the bandgap node and the current generator circuit arrangement to receive a current and apply scaling to the current; a first transistor providing a threshold voltage drop across a first transistor node and a second transistor node; a first resistive element between the first transistor and the bandgap node; a second resistive element coupled between ground and a second node of the first transistor; and an operational amplifier receiving a pre-regulated voltage as a function of the bandgap voltage, the threshold voltage across the first transistor, and the voltage drop across the first and second resistive elements.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Italian patent application No. 102022000020610, filed on October 6, 2022, which is incorporated herein by reference. Technical Field

[0003] This manual relates to voltage regulator circuits and methods.

[0004] One or more embodiments can be applied to proportionally reduce the input voltage for low-voltage sensitive circuitry (e.g., bandgap circuits, operational amplifier circuits, and digital circuits). Background Technology

[0005] In low quiescent, high-voltage low-dropout regulators (LDOs), nanopower pre-regulators with ultra-low quiescent current under zero load are desired.

[0006] For example, its quiescent current consumption (currently referred to as shutdown current) can represent a relevant portion of the LDO's total current, especially in shutdown mode (e.g., when the enable signal EN is at a first logic level, such as logic level "0").

[0007] In medium- and high-voltage applications, pre-regulators can be used to proportionally reduce the input voltage and precisely bias low-voltage load circuitry such as bandgap, operational amplifiers, undervoltage lockout, comparators, PLLs, and digital components with thousands or more gates.

[0008] To reduce bias current, it is desirable to reduce silicon area.

[0009] Known architectures for reducing bias current involve several circuits and components, such as Zener diodes, uniform resistors, and current generators, which have a related impact on area footprint. Summary of the Invention

[0010] The purpose of one or more embodiments is to help overcome the above-mentioned disadvantages.

[0011] According to one or more embodiments, this objective can be achieved via a circuit having the features set forth in the appended claims.

[0012] One or more embodiments may relate to a corresponding voltage regulator device.

[0013] The claims are an integral part of the technical teachings provided herein with reference to the embodiments.

[0014] One or more embodiments help to reduce the area occupied by the circuit device.

[0015] In one or more embodiments, the high input voltage pre-regulator involves low static power consumption.

[0016] One or more embodiments provide a more compact solution.

[0017] One or more embodiments use a reduced number of resistors and electronic components.

[0018] One or more embodiments can help save silicon area and power consumption. Attached Figure Description

[0019] One or more embodiments will now be described by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0020] Figure 1 This is an example diagram of a voltage regulator that includes a pre-regulator circuit;

[0021] Figure 2 yes Figure 1 Example circuit of the load circuit device of the pre-regulator circuit;

[0022] Figure 3 This is an example diagram of the pre-regulator architecture;

[0023] Figure 4 This is an example diagram of a circuit based on this disclosure;

[0024] Figure 5 This is an example diagram of a variant circuit based on this disclosure;

[0025] Figure 6 This is an example diagram of a circuit based on this disclosure;

[0026] Figure 7 yes Figure 6 A sample image;

[0027] Figure 8A and Figure 8B This is an example diagram of a voltage signal in one or more embodiments;

[0028] Figure 9 This is an example diagram of the current signal in one or more embodiments;

[0029] Figure 10A and Figure 10B This is an example diagram of a voltage signal in one or more embodiments;

[0030] Figure 11A , Figure 11B , Figure 11C and Figure 11D This is an example diagram showing the voltage signal value distribution of the circuit according to this disclosure under various operating conditions; and

[0031] Figure 12 , Figure 13 , Figure 14 and Figure 15 This is an example diagram showing the distribution of current signal values ​​under various operating conditions of the circuit according to this disclosure.

[0032] Unless otherwise indicated, corresponding numbers and symbols in different figures generally refer to the corresponding parts.

[0033] These figures are drawn to clearly illustrate relevant aspects of the embodiments and are not necessarily drawn to scale.

[0034] The edges of features drawn in the diagram do not necessarily indicate the end of the feature's range. Detailed Implementation

[0035] In the following description, one or more specific details are shown to provide a thorough understanding of examples of embodiments of this specification. Embodiments may be obtained without one or more of these specific details, or by utilizing other methods, components, materials, etc. In other instances, known structures, materials, or operations have not been shown or described in detail so as not to obscure certain aspects of the embodiments.

[0036] References to “embodiment” or “one embodiment” within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as “in an embodiment” or “in one embodiment” that may appear at one or more points in this specification do not necessarily refer to the same embodiment.

[0037] Furthermore, specific conformations, structures, or properties can be combined in any suitable manner in one or more embodiments.

[0038] The accompanying drawings are simplified and not drawn to exact scale.

[0039] In the figures attached to this document, similar parts or elements are indicated by similar reference numerals / numbers unless the context otherwise indicates, and for the sake of brevity, the corresponding descriptions for each figure will not be repeated.

[0040] Reference numerals used herein are provided for convenience only and therefore do not limit the scope of protection or the scope of embodiments.

[0041] For simplicity, the same reference symbols may be used in the following detailed description to designate both nodes / lines in a circuit and signals that may appear at that node or line.

[0042] like Figure 1 As illustrated, the device 100 includes:

[0043] Low differential pressure regulator 10, which includes a voltage regulator configured to draw from a capacitor C, such as a loaded capacitor. IN Such a power source receives the supply voltage at the power supply node V. IN ,

[0044] Enable node EN, which is configured to activate voltage regulation.

[0045] The ground node GND is configured to be coupled to ground.

[0046] Output node V OUT It is configured to be coupled to a load capacitor C, etc. OUT Such a load,

[0047] Adjust node ADJ, which is configured, for example, to be coupled to output node V via voltage dividers R1 and R2. OUT Configure the ADJ to set the output node to a portion of the output voltage, for example, determined by the resistor ratio (e.g., such as R1 / R2);

[0048] The power good or feedback node PG monitors the voltage at the adjustment node ADJ to indicate the status of the output voltage.

[0049] like Figure 2 As illustrated, the pre-regulator 12 can be coupled to load circuitry such as bandgap circuitry 14, operational amplifier circuitry 16, digital components 18, and comparator 19 to provide a pre-regulated voltage PRE to them.

[0050] For example, in automotive applications, the pre-regulator input voltage is 40 volts.

[0051] You can consider setting the PRE using CMOS process parameters, such as 5V, 3.3V, 1.8V, and 1.2V.

[0052] like Figure 3 As illustrated, coupled to load R L C L Traditional high-voltage pre-regulator architectures include:

[0053] Voltage clamping circuit device DZ, R sup (For example, having a name called R) sup The 5V Zener diode of the start-up resistor is coupled to the power supply node V. IN ,

[0054] Current generator circuit block 13, which is coupled to voltage clamping circuit devices DZ and R sup ,

[0055] The low-voltage bandgap 14 is coupled to the current generator circuit block 13.

[0056] Operational amplifier 16 includes a first (e.g., non-inverting) input node +, a second (e.g., negative) input node -, and an output node O1. The first (e.g., non-inverting) input node + is coupled to a low-voltage bandgap 14. The second (e.g., negative) input node - is coupled to the output node PRE via a feedback branch including resistive voltage dividers R1 and R2. The output node O1 is coupled to the gate node of a high-voltage transistor HVMOS (e.g., an n-channel or p-channel power MOS).

[0057] like Figure 4 As illustrated, the pre-regulator circuit 40 according to this disclosure includes:

[0058] Power supply node V IN It is configured to receive the power supply voltage.

[0059] Starting circuit 42, such as a current generator or a resistive element,

[0060] An independent current source 44, such as a high-voltage power supply, is configured to provide a first current I1 and a second current I2, as discussed below.

[0061] A voltage multiplier circuit 46 (e.g., active or passive) is coupled to an operational amplifier 48 and to resistors R0 and R1 in series with transistor Q0 (e.g., a diode-connected BJT or MOS transistor).

[0062] Operational amplifier 48 (e.g., in a buffer configuration) includes a first input node -, a second input node +, and an output node O1. The first input node - is coupled to an independent current source 44, the second input node + is coupled to the output node PRE, the output node O1 is coupled to a power transistor HVMOS (e.g., an n-channel transistor), and operational amplifier 48 is coupled to a current generator I. B01 The current generator I B01 Configured to provide it with a bias current I B01 ;

[0063] A bandgap voltage node (BDG) is configured to be coupled to a bandgap circuit device to receive the bandgap voltage (BDG).

[0064] like Figure 4 As illustrated, the current generator 44 is configured to generate a first current I1 and a second current I2, which can be represented as:

[0065]

[0066]

[0067] in:

[0068] ΔV BE This is a voltage proportional to absolute temperature (PTAT), such as that provided by the Caprio unit.

[0069] R0 is the value of the resistance in the resistor branch.

[0070] N is a (e.g., programmable) scaling factor for current generator 44.

[0071] like Figure 4 As illustrated, the voltage at reference node PRE0 between voltage multiplier circuit block 46 and operational amplifier 48 is at a voltage level given by the sum of the bandgap voltage BDG and (e.g., active) voltage multiplier circuit 46. For example, the voltage at reference node PRE0 is a voltage independent of high impedance and temperature.

[0072] like Figure 4 As illustrated, the voltage at the pre-adjusted output node PRE is essentially equal to the voltage at the reference node PRE0, and is ultimately affected only by any non-ideal offset in the operational amplifier 48.

[0073] like Figure 4 As illustrated, the pre-regulation voltage PRE helps to supply voltage to the output load R. L C L It provides current and maintains a voltage level that is independent of temperature.

[0074] For example, an active voltage multiplier can help obtain a pre-regulated voltage level PRE (e.g., about 3.3V above PRE0) from a bandgap voltage (e.g., about 1.3V).

[0075] like Figure 4 and Figure 5 As illustrated, the power transistor HVMOS can be an n-channel or p-channel transistor.

[0076] For example, at the supply voltage V IN In applications close to the pre-regulator voltage, a p-channel solution may be preferred.

[0077] like Figure 6 As illustrated, the independent current source 44 includes a Caprio cell structure known per se. The Caprio cell, as discussed on page 95 of Serdijn, Verhoeven & van Roermund, “Analog IC Techniques for Low-Voltage Low Power Electronics” – (1995), may be suitable for use in one or more embodiments.

[0078] like Figure 6 As illustrated, the startup circuit device 42 includes a startup resistor Rsup to turn on the Caprio unit 44.

[0079] like Figure 6 As illustrated, the Caprio unit includes:

[0080] Current mirrors M5 and M6 are coupled to the power supply node V via the start-up resistor Rsup. IN It is configured to perform voltage clamping at other stages.

[0081] The active load pair (e.g., p-channel MOSFETs) M3-M2 and M4-M1, which have a mirror ratio of 1 to N in a cascaded configuration, are configured to protect low-voltage components from high input voltages (e.g., in the range of 40 volts to 100 volts).

[0082] like Figure 6 and Figure 7 As illustrated, the Caprio cell comprises a quadruple of bipolar transistors Q1, Q2, Q3, Q4 (e.g., 5V NPN bipolar transistors) and resistor R0, wherein:

[0083] In the quadruple of bipolar transistors Q1, Q2, Q3, and Q4, the first bipolar transistor Q1 has a first emitter area, for example, approximately three times the area of ​​the second emitter area.

[0084] In the quadruple of bipolar transistors Q1, Q2, Q3, and Q4, the second bipolar transistor Q2 has a second emitter area; for example, per unit emitter area,

[0085] The emitter area of ​​the third bipolar transistor Q3 is three times that of the second emitter area and equal to the first emitter area.

[0086] The fourth bipolar transistor Q4 includes a fourth emitter area equal to the second emitter area of ​​the second bipolar transistor Q2.

[0087] like Figure 6 As illustrated, at least one current generator IB 01 Coupled to Caprio units Q4, Q3, Q2, Q1, and R0, this at least one current generator IB 01 This includes a fifth bipolar transistor Q5 (e.g., having a fifth unit emitter area) and a bias resistor element Ra, which is used to apply a suitable current I3 (e.g., about 60 nA, where 1 nA = 1 nanoamp = 10 NA). - 9 A) Bias operational amplifier 48.

[0088] like Figure 6As illustrated, the bias current I3 is a function of the current generated from the Caprio cell.

[0089] like Figure 6 As illustrated, the PTAT voltage ΔV across resistor R0 BE It can be represented as:

[0090]

[0091] in:

[0092] @300K (27℃) is the thermal voltage.

[0093] k is the Boltzmann constant.

[0094] T is the temperature measured in Kelvin.

[0095] q is the electron charge.

[0096] AE Q3 It is the area of ​​the third bipolar transistor.

[0097] AE Q1 It is the area of ​​the first bipolar transistor.

[0098] AE Q2 That is the area of ​​the second bipolar transistor.

[0099] AE Q4 That is the area of ​​the fourth bipolar transistor.

[0100] For example, at room temperature (i.e., a temperature T of approximately 300 K), the PTAT voltage ΔV BE It can be represented as:

[0101] ΔV BE (@300K)=0.026*ln9=0.05712V.

[0102] For example, the threshold voltage ΔV BE Substituting the room temperature value (@300K) into the expressions for the first current I1 and the second current I2, and in the exemplary case where the scaling factor N of the current generator N is a unitary value, their values ​​can be calculated as follows:

[0103]

[0104] For example, the first current I1 and the second current I2 have approximately 30nA (1nA = 10nA). -9 In an exemplary scenario where the value is 1 nanoampere, the resistor R0 can be designed to have a resistance value of R0 = 952 kΩ.

[0105] like Figure 6 As illustrated, the current I3 used to bias operational amplifier 48 can be determined by the following expression:

[0106]

[0107] in

[0108] Ra is the resistance of a bias resistor.

[0109] VBE Q1 It is the base-emitter voltage of the first bipolar transistor.

[0110] VBE Q5 It is the base-emitter voltage of the fifth bipolar transistor.

[0111] For example, to obtain a bias current I3 of approximately 60 nA, the current generator IB can be used. 01 The resistance Ra is set to a value of approximately 476 kΩ.

[0112] like Figure 7 As illustrated, the bandgap voltage received at the bandgap voltage node V (BDG) can be expressed as:

[0113]

[0114] in

[0115] VBE Q0 It is the PTAT voltage ΔV BE complementary quantities,

[0116] R1 is the resistor between the bandgap voltage node BDG and the diode-connected transistor (e.g., BJT) Q0.

[0117] For example, resistor R1 can be a function of resistor R0, such as R1 = 2 * N * R0, where N depends on the technology; this can help provide a voltage with the desired temperature profile at the bandgap node BDG.

[0118] For example, considering a resistance value R1 of approximately 24 MΩ, then VBE is obtained. Q0 = 0.533 volts.

[0119] For example, the bandgap voltage received at the bandgap voltage node BDG can be at a voltage level of about 1.31V at room temperature.

[0120] like Figure 6 As illustrated, the reference voltage PRE0 at reference node PRE0 can be expressed as:

[0121] V(PRE0)=V(BDG)+2*(V TH+V OVDRV )=V(BDG)+VGS M0A +VGS M0B =2V GS

[0122] in

[0123] V TH It is the threshold voltage of the transistor pair M0A and M0B connected by a diode.

[0124] VGS M0A +VGS M0B It is the sum of the voltage thresholds of the diode-connected transistor pairs M0A and M0B, and

[0125] V OVDRV It is the voltage overdrive of these MOS transistors.

[0126] For example, in the technology used, the voltage threshold thermal coefficient (TC) of a PMOS transistor at a temperature may be approximately: Vth(TC)PMOS = -1.1mV / ℃.

[0127] For example, overdrive voltage V OVDRV This can be achieved by setting the ratio of width to length (e.g., To design in order to balance the threshold voltage V at temperature TH The negative change.

[0128] like Figure 6 As illustrated, the second current I2 (which is a function of the first current I1) flows through the diode-connected transistor M. 0A and M 0B This depends on the PTAT voltage ΔV BE This causes its temperature to rise.

[0129] Therefore, the reference voltage PRE0 can be considered as a temperature-independent voltage (e.g., except in cases of temperature drift).

[0130] like Figure 6 As illustrated, a set of current generators IB 01 IB 02 ..., IB 0N It can be coupled to Caprio units Q1, Q2, Q3, Q4 to provide bias current supply to the corresponding set of load circuits 16, 18, 19 coupled to the pre-regulated voltage level PRE.

[0131] For example, this group of current generators IB 01 IB 02 ..., IB 0NThe current generators in the diagram may each include a series of bipolar transistors Q6, ..., QN, which have a first transistor terminal coupled to the Caprio unit 44 and coupled to corresponding resistive elements Rb, ..., R N The second transistor terminal, and the third transistor terminal coupled to the corresponding load in the group of loads 16, 18, 19.

[0132] For example, this group of current generators IB 01 IB 02 ..., IB 0N The j-th current generator in the array can be configured to provide a corresponding current Ij, which can be represented as:

[0133]

[0134] in

[0135] Rj is the resistance of the j-th biased resistive element.

[0136] VBE Q1 It is the base-emitter voltage of the first bipolar transistor.

[0137] VBE QN It is the base-emitter voltage of the Nth bipolar transistor.

[0138] like Figure 6 and Figure 7 As illustrated, transistor M can be used 0A and M 0B The diode connection is used to replace the diffusion or polysilicon resistor R2.

[0139] For example, transistors M connected around these diodes can be used in a manner known per se. 0A and M 0B The virtual structure is used to make the two transistors M 0A and M 0B Process diffusion between them is minimized because their matching layout can improve performance.

[0140] like Figure 8A and Figure 8B As shown, using the circuit 40 according to this disclosure, the drift of the pre-adjustment voltage PRE and the drift of the bandgap BDG can be limited, for example, to about 60 mV, or 1.8%, within the temperature range [-40°C, 160°C].

[0141] As illustrated herein, circuit 40 includes:

[0142] Power supply node V IN It is configured to receive power from power supply C IN V INReceived power supply voltage V IN ;

[0143] Output node PRE, which is configured to couple to load R L C L To provide the regulated voltage PRE;

[0144] The starting circuit device 42 is coupled to the power supply node V. IN The startup circuit is configured to provide a startup voltage as a function of the supply voltage in order to receive the supply voltage.

[0145] A current generator circuit 44 is coupled to a startup circuit to receive a startup voltage. The current generator circuit is configured to generate a first current I1 having a first current intensity and a second current I2 having a second current intensity, wherein the second current intensity of the second current I2 is a function of the first current intensity of the first current I1.

[0146] A bandgap node (BDG) is configured to be coupled to a bandgap circuit device to receive a bandgap voltage.

[0147] Multiplier circuit 46, coupled to a bandgap node and to a current generator circuit, receives a second current I2. Multiplier circuit 46 is configured to apply a scaling factor N to the second current to provide a scaled version of the second current at the bandgap node. The scaled version of the second current I2 has a current intensity scaled by an integer scaling factor N relative to the first current I1.

[0148] A first diode-connected transistor (e.g., BJT) Q0 has a current flow path passing between a first transistor node and a second transistor node. The first transistor Q0 has a control node coupled to the first transistor node and coupled to a bandgap node, and has a second transistor node coupled to a current generator circuit device. The first transistor is configured to provide a threshold voltage drop across the first transistor node and the transistor node.

[0149] The first resistive element R1 is located between the first switch / transistor and the bandgap node;

[0150] The second resistive element R0 involved is coupled to the second node of the first transistor Q0;

[0151] The second transistor, HVMOS, has a control node and a power supply node V. IN The current flow path between the output node PRE and the output node, and

[0152] Operational amplifier 48 has a first input node PRE0 coupled to current generator circuitry 44 and multiplier circuitry 46. The first input node PRE0 of operational amplifier 48 is configured to receive a pre-regulated voltage PRE0 as a function of bandgap voltage BDG, a threshold voltage across first transistor Q0, and a voltage drop across first resistive element R1 and second resistive element R0. The operational amplifier includes a second input node PRE0 coupled via a feedback branch to an output node OI, which has an output node OI coupled to a control node of second transistor HVMOS and is configured to provide a regulated voltage based on the pre-regulated voltage PRE0 to the output node of the circuit.

[0153] As illustrated herein, the startup circuit device 42 includes a connection to the supply voltage node V. IN The starting resistive element Rsup, and the current generator circuit device includes a plurality of transistors M2, M3, M4, M5, M6 arranged in a current mirror cascade, the plurality of transistors being coupled to the starting resistive element and the supply voltage node, wherein the transistors in the plurality of current transistors have corresponding transistor areas that are proportional to each other, and the current mirror cascade provides a mirror ratio equal to an integer scaling factor N.

[0154] As illustrated herein, the current generator circuit 44 includes a Caprio unit comprising a quadruple of Caprio unit switches (e.g., BJT and / or MOSFET transistors) Q1, Q2, Q3, and Q4.

[0155] For example:

[0156] The first Caprio cell switch (e.g., transistor) Q1 in the quadruple of switches in the Caprio cell includes a first area.

[0157] The second Caprio cell switch (e.g., transistor) Q2 in the quadruple of switches in the Caprio cell comprises a unit area.

[0158] The third Caprio cell switch (e.g., transistor) Q3 in the quadruple of switches in the Caprio cell includes a third area equal to the first area, and

[0159] The fourth Caprio cell switch (e.g., transistor) Q4 in the quadruple of switches in the Caprio cell includes a fourth area equal to the unit area of ​​the second switch in the quadruple of switches.

[0160] As illustrated herein, the current generator circuit 44 is configured to generate a first current intensity of a first current I1 and a second current intensity of a second current I2, wherein the first current intensity of the first current I1 is expressed as:

[0161]

[0162] The second current intensity of the second current I2 is expressed as follows:

[0163]

[0164] in

[0165] N is an integer scaling factor, and

[0166] R0 is the resistance of the second resistive element.

[0167] As illustrated herein, operational amplifier 48 includes bias circuitry I. B01 Furthermore, the bias circuitry includes a bias current generator configured to provide a bias current I to the operational amplifier. B01 .

[0168] As illustrated herein, a bias current generator is coupled to a current generator circuit to receive a first current I1. The bias current generator includes a fifth transistor Q5 coupled to a bias resistive element Ra, wherein the fifth transistor Q5 has a unit area.

[0169] As illustrated in this article, the multiplier circuit assembly includes a diode-connected transistor M. 0A M 0B In a pair of diode-connected transistors, the diode-connected transistors in the pair have the same transistor area.

[0170] As illustrated herein, the voltage regulator device 100 includes:

[0171] Power supply C IN V IN It is configured to provide a power supply voltage V IN ;

[0172] At least one load R L C L It is configured to receive regulated voltage PRE, V OUT ;

[0173] Bandgap circuit device 14, configured to generate bandgap voltage BDG, and

[0174] The circuit 40 according to this disclosure has a power supply node, a bandgap node and an output node, the power supply node being coupled to a power source, the bandgap node being coupled to a bandgap circuit device to receive a bandgap voltage, and the output node being coupled to at least one load to provide it with a regulated voltage.

[0175] As illustrated in this article, at least one load R L C L It includes at least one circuit selected from bandgap circuit 14, comparator circuit 16 and operational amplifier circuit 18.

[0176] like Figure 9 As illustrated, the quiescent current level I may vary with temperature. For example, at a normal supply voltage level and without any load C... L In the case of R, the static current level I can vary within a range of several nanoamperes.

[0177] like Figure 10A and Figure 10B The illustration shows various curves, each corresponding to a pre-regulated voltage value as a function of temperature for a specific value of the supply voltage (e.g., in the range between 5 volts and 40 volts).

[0178] like Figure 10A and Figure 10B As illustrated, the pre-regulation voltage PRE and the bandgap value BDG vary within a finite range and can be considered essentially constant at temperature.

[0179] like Figure 11A , Figure 11B , Figure 11C , Figure 11D As illustrated, at a fixed temperature of 27°C, when the supply voltage V is changed... IN (For example, in) Figure 11A The illustrated 5V and Figure 11D At the illustrated range of 40V, various distributions of the pre-regulation voltage PRE showed a standard deviation of approximately 0.22%, therefore the results are essentially consistent with the supply voltage V. IN The value is irrelevant.

[0180] Figures 12 to 15 This indicates that at a fixed temperature (e.g., approximately 27°C), with zero load and supply voltage V... IN Variation within a given range (e.g., in) Figure 12 The illustrated 5V and Figure 15 The current consumption (e.g., quiescent current I) at the illustrated range of 40V.

[0181] Table I below summarizes the average value (in nanoamperes) of the quiescent current I as a function of the supply voltage level VIN at a constant temperature (e.g., 27°C).-9 A).

[0182] Table I

[0183] <![CDATA[V IN [V]]> I[nA] 5 168 12 226 24 325 40 460

[0184] Since the quiescent current consumption of the internal pre-regulator is one of the major contributors to the total LDO power consumption, the proposed circuitry and apparatus help to reduce it.

[0185] It should be understood that the various individual implementation options illustrated throughout the accompanying figures are not necessarily intended to be used in the same combinations illustrated in the figures. Therefore, one or more embodiments may employ these (otherwise non-mandatory) options individually and / or in different combinations relative to the combinations illustrated in the accompanying figures.

[0186] Without prejudice to the fundamental principles and without departing from the scope of protection, details and embodiments may vary, even significantly, relative to what has been described by way of example only. The scope of protection is defined by the appended claims.

Claims

1. A circuit comprising: A power supply node, the power supply node being configured to receive a power supply voltage from a power source; An output node, configured to be coupled to a load to provide a regulated voltage; A startup circuit device coupled to the power supply node to receive the power supply voltage, the startup circuit device being configured to provide a startup voltage as a function of the power supply voltage; A current generator circuit device coupled to the startup circuit device to receive the startup voltage, the current generator circuit device being configured to generate a first current having a first current intensity and a second current having a second current intensity, wherein the second current intensity of the second current is a function of the first current intensity of the first current. A bandgap node configured to be coupled to a bandgap circuit device to receive a bandgap voltage; A multiplier circuit device coupled to the bandgap node and the current generator circuit device to receive the second current, the multiplier circuit device being configured to apply scaling to the second current by an integer scaling factor N, thereby providing a scaled version of the second current at the bandgap node, the scaled version of the second current having a current intensity scaled relative to the first current intensity by the integer scaling factor N; A first transistor having a first current flow path passing between a first transistor node and a second transistor node, the first transistor having a first control node coupled to the first transistor node and the bandgap node, the first transistor having a second transistor node coupled to the current generator circuit device, and the first transistor being configured to provide a threshold voltage drop across the first transistor node and the second transistor node. A first resistive element, wherein the first resistive element is located between the first transistor and the bandgap node; A second resistive element is coupled between ground and the second transistor node; The second transistor has a second control node and a second current flow path passing between the power supply node and the output node; as well as An operational amplifier having a first input node coupled to a current generator circuit and a multiplier circuit, wherein the first input node of the operational amplifier is configured to receive a pre-regulated voltage as a function of the bandgap voltage, the threshold voltage across the first transistor, and the voltage drop across the first resistive element and the second resistive element; the operational amplifier including a second input node coupled to the output node via a feedback branch; the operational amplifier having an operational amplifier output coupled to a second control node of the second transistor and configured to provide the regulated voltage based on the pre-regulated voltage to the output node of the circuit.

2. The circuit according to claim 1, wherein: The startup circuit device includes a startup resistive element coupled to the power supply node; and The current generator circuitry includes a plurality of transistors arranged in a current mirror cascade, the plurality of transistors being coupled to the start-up resistive element and the power supply node, wherein the transistors in the plurality of transistors have corresponding transistor areas proportional to each other, and the current mirror cascade provides a mirror ratio equal to the integer scaling factor N.

3. The circuit according to claim 1, wherein the current generator circuit device includes a Caprio unit, the Caprio unit including a quadruple of Caprio unit switches, wherein: The first Caprio unit switch in the quadruple of the Caprio unit switch in the Caprio unit includes a first area; The second Caprio unit switch in the quadruple of the Caprio unit switch in the Caprio unit includes a unit area; The third Caprio unit switch in the quadruple of the Caprio unit switch in the Caprio unit includes a third area equal to the first area; and The fourth Caprio unit switch in the quadruple of the Caprio unit switches in the Caprio unit includes a fourth area equal to the unit area of ​​the second Caprio unit switch in the quadruple of the Caprio unit switches.

4. The circuit according to claim 3, wherein: The operational amplifier includes a bias circuit device; The bias circuitry includes a bias current generator configured to provide a bias current to the operational amplifier. and The bias current generator is coupled to the current generator circuitry to receive the first current, and the bias current generator includes a fifth switch coupled to a bias resistive element, wherein the fifth switch has the unit area.

5. The circuit of claim 1, wherein the current generator circuit is configured to generate a first current intensity of the first current and a second current intensity of the second current, wherein the first current intensity of the first current is expressed as: The second current intensity is expressed as follows: Where N is the integer scaling factor, ΔV BE It is a voltage proportional to absolute temperature, and R0 is the resistance of the second resistive element.

6. The circuit according to claim 1, wherein: The operational amplifier includes a bias circuit device; and The bias circuitry includes a bias current generator configured to provide bias current to the operational amplifier.

7. The circuit of claim 1, wherein the multiplier circuit arrangement comprises a pair of diode-connected transistors, wherein the diode-connected transistors in the pair of diode-connected transistors have the same transistor area.

8. A voltage regulator device, comprising: A power source, configured to provide a supply voltage; At least one load, the at least one load being configured to receive an regulated voltage; A bandgap circuit device configured to generate a bandgap voltage; as well as The circuit includes: A power supply node, the power supply node being configured to receive the supply voltage from the power source; An output node, configured to be coupled to a load, to provide the regulated voltage; A startup circuit device coupled to the power supply node to receive the power supply voltage, the startup circuit device being configured to provide a startup voltage as a function of the power supply voltage; A current generator circuit device coupled to the startup circuit device to receive the startup voltage, the current generator circuit device being configured to generate a first current having a first current intensity and a second current having a second current intensity, wherein the second current intensity of the second current is a function of the first current intensity of the first current. A bandgap node, configured to be coupled to a bandgap circuit device to receive the bandgap voltage; A multiplier circuit device coupled to the bandgap node and the current generator circuit device to receive the second current, the multiplier circuit device being configured to apply scaling to the second current by an integer scaling factor N, thereby providing a scaled version of the second current at the bandgap node, the scaled version of the second current having a current intensity scaled relative to the first current intensity by the integer scaling factor N; A first transistor having a first current flow path passing between a first transistor node and a second transistor node, the first transistor having a first control node coupled to the first transistor node and the bandgap node, the first transistor having a second transistor node coupled to the current generator circuit device, and the first transistor being configured to provide a threshold voltage drop across the first transistor node and the second transistor node. A first resistive element, wherein the first resistive element is located between the first transistor and the bandgap node; A second resistive element is coupled between ground and the second transistor node; A second transistor having a second control node and a second current flow path passing between the power supply node and the output node; and An operational amplifier having a first input node coupled to a current generator circuit and a multiplier circuit, wherein the first input node of the operational amplifier is configured to receive a pre-regulated voltage as a function of the bandgap voltage, the threshold voltage across the first transistor, and the voltage drop across the first resistive element and the second resistive element; the operational amplifier including a second input node coupled to the output node via a feedback branch; the operational amplifier having an operational amplifier output coupled to a second control node of the second transistor and configured to provide the regulated voltage based on the pre-regulated voltage to the output node of the circuit; The power supply node is coupled to the power source, the bandgap node is coupled to the bandgap circuit device to receive the bandgap voltage, and the output node is coupled to the at least one load to provide the regulated voltage thereto.

9. The voltage regulator device of claim 8, wherein the at least one load comprises at least one load circuit selected from the following circuits: a second bandgap circuit, a comparator circuit, or an operational amplifier circuit.

10. The voltage regulator device according to claim 8, wherein: The startup circuit device includes a startup resistive element coupled to the power supply node; and The current generator circuitry includes a plurality of transistors arranged in a current mirror cascade, the plurality of transistors being coupled to the start-up resistive element and the power supply node, wherein the transistors in the plurality of transistors have corresponding transistor areas proportional to each other, and the current mirror cascade provides a mirror ratio equal to the integer scaling factor N.

11. The voltage regulator device according to claim 8, wherein the current generator circuit device includes a Caprio unit, the Caprio unit including a quadruple of Caprio unit switches, wherein: The first Caprio unit switch in the quadruple of the Caprio unit switch in the Caprio unit includes a first area; The second Caprio unit switch in the quadruple of the Caprio unit switch in the Caprio unit includes a unit area; The third Caprio unit switch in the quadruple of the Caprio unit switch in the Caprio unit includes a third area equal to the first area; and The fourth Caprio unit switch in the quadruple of the Caprio unit switches in the Caprio unit includes a fourth area equal to the unit area of ​​the second Caprio unit switch in the quadruple of the Caprio unit switches.

12. The voltage regulator device according to claim 11, wherein: The operational amplifier includes a bias circuit device; The bias circuitry includes a bias current generator configured to provide a bias current to the operational amplifier. and The bias current generator is coupled to the current generator circuitry to receive the first current, and the bias current generator includes a fifth switch coupled to a bias resistive element, wherein the fifth switch has the unit area.

13. The voltage regulator device of claim 8, wherein the current generator circuit is configured to generate a first current intensity of the first current and a second current intensity of the second current, the first current intensity of the first current being expressed as: The second current intensity is expressed as follows: Where N is the integer scaling factor, ΔV BE It is a voltage proportional to absolute temperature, and R0 is the resistance of the second resistive element.

14. The voltage regulator device according to claim 8, wherein: The operational amplifier includes a bias circuit device; and The bias circuitry includes a bias current generator configured to provide bias current to the operational amplifier.

15. The voltage regulator device of claim 8, wherein the multiplier circuit device comprises a pair of diode-connected transistors, wherein the diode-connected transistors in the pair of diode-connected transistors have the same transistor area.

16. A circuit comprising: Power supply input nodes; Regulated voltage output node; A startup circuit device coupled to the power supply input node and including a startup voltage output; A current generator circuit device coupled to the start-up voltage output, the current generator circuit device having a first current output and a second current output, wherein the second current intensity of the second current output is a function of the first current intensity of the first current output; Bandgap voltage node; A multiplier circuit device coupled to a second current output of the current generator circuit device, and an integer-scaled second current output coupled to the bandgap voltage node, the integer-scaled second current output having a current intensity scaled relative to the first current intensity of the first current output by an integer scaling factor N. A first transistor having a first current flow path passing between a first transistor node and a second transistor node, the first transistor having a first control node coupled to the first transistor node and the bandgap voltage node, the first transistor having a second transistor node coupled to the current generator circuit device, and the first transistor providing a threshold voltage drop across the first transistor node and the second transistor node. A first resistive element, wherein the first resistive element is located between the first transistor and the bandgap voltage node; A second resistive element is coupled between ground and the second transistor node; The second transistor has a second control node and a second current flow path passing between the power supply input node and the regulated voltage output node; as well as Operational amplifier, the operational amplifier comprising: A first input node, coupled to the current generator circuitry and the multiplier circuitry, wherein the first input node of the operational amplifier is configured to receive a pre-adjusted voltage as a function of the bandgap voltage of the bandgap voltage node, the threshold voltage across the first transistor, and the voltage drop across the first resistive element and the second resistive element. A second input node, the second input node being coupled to the regulated voltage output node via a feedback branch; and The operational amplifier output is coupled to the second control node of the second transistor and to the regulated voltage output node.

17. The circuit according to claim 16, wherein: The startup circuit device includes a startup resistive element coupled to the power supply input node; and The current generator circuitry includes a plurality of transistors arranged in a current mirror cascade, the plurality of transistors being coupled to the start-up resistive element and the power supply input node, wherein the transistors in the plurality of transistors have corresponding transistor areas proportional to each other, and the current mirror cascade has a mirror ratio equal to the integer scaling of the integer scaling of the second current output.

18. The circuit of claim 16, wherein the current generator circuit device includes a Caprio unit, the Caprio unit including a quadruple of Caprio unit switches, wherein: The first Caprio unit switch in the quadruple of the Caprio unit switch in the Caprio unit includes a first area; The second Caprio unit switch in the quadruple of the Caprio unit switch in the Caprio unit includes a unit area; The third Caprio unit switch in the quadruple of the Caprio unit switch in the Caprio unit includes a third area equal to the first area; and The fourth Caprio unit switch in the quadruple of the Caprio unit switches in the Caprio unit includes a fourth area equal to the unit area of ​​the second Caprio unit switch in the quadruple of the Caprio unit switches.

19. The circuit according to claim 16, wherein: The operational amplifier includes a bias circuit device; and The bias circuit device includes a bias current generator with a bias current output.

20. The circuit of claim 16, wherein the multiplier circuit arrangement comprises a pair of diode-connected transistors, wherein the diode-connected transistors in the pair of diode-connected transistors have the same transistor area.

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