Electronic device having a voltage linear regulator and method of operation thereof

Abstract

The present disclosure relates to an electronic device having a voltage linear regulator and a method of operating the same. The present disclosure relates to a device having a supply input to receive a supply voltage, a switched mode power supply comprising an output at which the supply voltage is generated, and a voltage linear regulator to supply power to a load, the regulator receiving the supply voltage, the regulator comprising two transistors coupled between the supply input, the output of the power supply and an output node of the regulator, respectively. When the current drawn by the load is below a threshold, the output current delivered to the load is equal to the current flowing through the transistors, and therefore, when the current drawn by the load is above the threshold, the output current is equal to the current flowing through the transistors plus the current flowing through the transistors.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to French patent application No. 2210179 entitled “Dispositifélectronique”, filed on October 10, 2022, which is incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This disclosure generally relates to electronic devices and methods, and more specifically to devices including voltage linear regulators and methods of operating thereof. Background Technology

[0004] In electronic devices, a linear regulator is a voltage regulator based on an active component that operates in its linear region or a passive component (such as a Zener diode) that operates in its reverse region.

[0005] Low dropout (LDO) voltage regulators are a type of voltage linear regulator that can regulate the output voltage even when the supply voltage is close to the output voltage. Summary of the Invention

[0006] One embodiment addresses all or some of the shortcomings of known electronic devices.

[0007] One embodiment provides an electronic device, including:

[0008] The first power supply input terminal is configured to receive the first power supply voltage;

[0009] A first switch-mode power supply, including a first output terminal, the first switch-mode power supply being configured to generate a second supply voltage at the first output terminal; and

[0010] A voltage linear regulator configured to supply power to a load included in a device, the regulator being configured to receive first and second supply voltages, the regulator comprising:

[0011] A first transistor is coupled between a first power supply input terminal and the output node of the regulator; and

[0012] The second transistor is coupled between the output terminal of the first switch-mode power supply and the output node of the regulator.

[0013] The regulator is configured such that when the current drawn by the load is below a threshold, a first output current delivered to the load from the regulator's output node is equal to a third current flowing through the second transistor, and such that when the current is above the threshold, the first output current is equal to the sum of a fourth current flowing through the first transistor and a third current flowing through the second transistor, wherein the fourth current is non-zero.

[0014] Another embodiment provides a method for controlling an electronic device, the electronic device comprising:

[0015] The first power supply input terminal receives the first power supply voltage;

[0016] A first switch-mode power supply includes a first output terminal, at which the first switch-mode power supply generates a second supply voltage; and

[0017] A voltage linear regulator that supplies power to a load included in a device, the regulator receiving first and second supply voltages, the regulator comprising:

[0018] A first transistor is coupled between a first power supply input terminal and the output node of the regulator; and

[0019] The second transistor is coupled between the output terminal of the first switch-mode power supply and the output node of the regulator.

[0020] When the current drawn by the load is below the threshold, the first output current delivered to the load by the output node of the regulator is equal to the third current flowing through the second transistor, and when the current is above the threshold, the first output current is equal to the sum of the fourth current flowing through the first transistor and the third current flowing through the second transistor, wherein the fourth current is non-zero.

[0021] According to an embodiment, the regulator is configured such that when the current drawn by the load is higher than a threshold, the greater the drawn current, the greater the fourth current flowing through the first transistor.

[0022] According to an embodiment, the regulator includes:

[0023] An error amplifier is configured to receive a setpoint voltage and a voltage representing the output voltage of the regulator as inputs, and is configured to generate an error voltage.

[0024] A voltage-to-current converter includes an input configured to receive an error voltage, and generates a fifth current at a second output of the converter, and generates a sixth current at a third output of the converter; and

[0025] A first gate drive circuit drives a first transistor, and a second gate drive circuit drives a second transistor. The converter is configured to deliver a fifth current to the first drive circuit and a sixth current to the second drive circuit.

[0026] According to an embodiment, the regulator includes a voltage divider bridge, the input of which is coupled to the output node of the regulator, and the output of which is coupled to the input of an amplifier in such a manner as to deliver a voltage representing the output voltage.

[0027] According to an embodiment, the converter includes a third transistor coupled between a first node and a node for applying a reference voltage, the third transistor being configured to be controlled by an error voltage, and the converter includes a fourth transistor coupling the first node to a second output terminal and at least one fifth transistor coupling the first node to a third output terminal.

[0028] According to an embodiment, the first node and the third output are coupled via a set of at least two fifth transistors connected in parallel.

[0029] According to an embodiment, the second gate drive circuit includes a sixth transistor, which is diode-coupled between the second output terminal of the converter and the output terminal of the first switch-mode power supply, and the drive terminal of the sixth transistor is coupled to the output terminal of the second drive circuit.

[0030] According to an embodiment, the second driving circuit includes:

[0031] The seventh transistor, a diode coupled between an input configured to receive setpoint current and the output of the first switch-mode power supply; and

[0032] The eighth transistor is coupled between the second output terminal of the converter and the output terminal of the first switch-mode power supply, and the drive terminal of the eighth transistor is coupled to the drive terminal of the seventh transistor.

[0033] According to an embodiment, the first gate drive circuit includes a diode-connected ninth transistor, the ninth transistor and a resistor being coupled between a first output terminal of the converter and a first input terminal of the device, and the drive terminal of the ninth transistor being coupled to the output terminal of the first drive circuit.

[0034] According to an embodiment, the first gate driving circuit includes:

[0035] The tenth transistor, a diode, is connected between the input configured to receive setpoint current and the first input of the device, and

[0036] The eleventh transistor is coupled between the first output terminal of the converter and the first input terminal of the device, and the drive terminal of the tenth transistor is coupled to the drive terminal of the eleventh transistor.

[0037] According to an embodiment, the first driving circuit includes:

[0038] The twelfth transistor is coupled between the first output of the converter and the first input of the device;

[0039] A first switch is coupled between the drive terminal of the twelfth transistor and the input terminal configured to receive setpoint current; and

[0040] The second switch is coupled between the drive terminal of the twelfth transistor and the first input terminal of the device.

[0041] According to an embodiment, the device includes at least one second switch-mode power supply, and for each second switch-mode power supply includes a second transistor coupled between the output terminal and the output node of the corresponding second switch-mode power supply, and the regulator is configured such that the current flowing through only one of the second transistors is non-zero at any given time. Attached Figure Description

[0042] The foregoing features and advantages, as well as others, will be described in detail below with reference to the accompanying drawings, in a description of specific embodiments given in an illustrative rather than limiting manner, wherein:

[0043] Figure 1 An embodiment of an electronic device including a voltage linear regulator is illustrated;

[0044] Figure 2 An embodiment of a voltage linear regulator is illustrated;

[0045] Figure 3 A more detailed illustration is provided. Figure 2 Part of the embodiments;

[0046] Figure 4 A more detailed illustration is provided. Figure 2 Another part of the embodiments; and

[0047] Figure 5 A more detailed illustration is provided. Figure 2 Another part of the embodiments. Detailed Implementation

[0048] Similar features in the various figures are indicated by similar reference numerals. In particular, common structural and / or functional features between the various embodiments may have the same reference numerals and may be provided with exactly the same structure, size, and material properties.

[0049] For clarity, only detailed illustrations and descriptions are provided for operations and elements useful for understanding the embodiments described herein.

[0050] Unless otherwise stated, when referring to two elements connected together, it means that there is no direct connection between them except for the conductor, and when referring to two elements coupled together, it means that the two elements can be connected or they can be coupled via one or more other elements.

[0051] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers (such as the terms “front,” “back,” “top,” “bottom,” “left,” “right,” etc.) or relative position qualifiers (such as the terms “above,” “below,” “higher,” “lower,” etc.) or orientation qualifiers (such as “horizontal,” “vertical,” etc.), refer to the orientation shown in the figures.

[0052] Unless otherwise stated, the expressions “approximately,” “about,” “substantially,” and “about” indicate within 10%, and preferably within 5%.

[0053] Figure 1 An embodiment of an electronic device 10 including a voltage linear regulator 12 is illustrated. The voltage regulator 12 is a low-dropout voltage regulator or an LDO regulator.

[0054] Regulator 12 is configured to energize load 14. Load 14 is, for example, an analog circuit. Load 14 is, for example, a logic circuit. Load 14 is, for example, an analog circuit controlling a switch-mode power supply (SMPS).

[0055] Regulator 12 includes an output terminal at which an output voltage VOUT is generated. Voltage VOUT is the power supply voltage of circuit 14. The output terminal is coupled to (preferably connected to) the power supply input terminal of circuit 14.

[0056] Device 10 can, for example, operate in a low-power mode. To ensure low power, regulator 12 can be powered by at least two voltage sources, at least one of which has a value less than the supply voltage of device 10. The voltage sources deliver different supply voltages. Regulator 12 generates an output voltage VOUT from one of the supply voltages. The regulator generates a current IOUT at its output.

[0057] exist Figure 1 In this example, regulator 12 is coupled to three power supplies. Therefore, regulator 12 can be powered by one or more of these voltage sources. Depending on the load 14 and the power consumed by the load 14, the regulator's power supply voltage can come from one or more of these sources.

[0058] Regulator 12 is powered, for example, by the supply voltage VDD of device 10. Voltage VDD is, for example, higher than 3V, and for example, equal to 5V. In other words, regulator 12 includes a power supply input coupled to (preferably connected to) node 16 for applying voltage VDD. Therefore, the regulator receives a current IBAT at its input.

[0059] The regulator 12 is powered, for example, by at least one voltage generated by a switch-mode power supply. Figure 1In this example, the device includes two switch-mode power supplies 18 and 20. Therefore, each of power supplies 18 and 20 includes an output coupled to (preferably connected to) the power supply input of regulator 12. For example, power supplies 18 and 20 are down-converting power supplies.

[0060] Power supply 18 generates a supply voltage VBUCK1 at its output terminal, which is coupled to (preferably connected to) regulator 12. Regulator 12 therefore receives voltage VBUCK1 at its supply input terminal. Similarly, power supply 18 generates a current IBUCK1 at its output terminal. Regulator 12 therefore receives current IBUCK1 at its supply input terminal. Similarly, power supply 20 generates a supply voltage VBUCK2 at its output terminal, which is coupled to (preferably connected to) regulator 12. Regulator 12 therefore receives voltage VBUCK2 at its supply input terminal. Similarly, power supply 20 generates a current IBUCK2 at its output terminal. Regulator 12 therefore receives current IBUCK2 at its supply input terminal. Voltages VBUCK1 and VBUCK2 are, for example, lower than the supply voltage VDD, for example, lower than 3.3V.

[0061] Power supplies 18 and 20 are preferably different. Power supplies 18 and 20 are configured, for example, to supply different ranges of voltage or current.

[0062] Device 10 is preferably configured such that only one of power supplies 18 and 20 can be active at any given time. In other words, if regulator 12 is powered by power supply 18, then the regulator is not powered by power supply 20. Similarly, if regulator 12 is powered by power supply 20, then the regulator is not powered by power supply 18. Therefore, device 10 is configured such that regulator 12 does not simultaneously receive non-zero currents IBUCK1 and IBUCK2.

[0063] Device 10 is configured such that current IOUT is equal to the sum of current IBAT and current IBUCK, and current IBUCK corresponds to current IBUCK1 or current IBUCK2 depending on whether power supply 18 or 20 supplies power to the regulator.

[0064] The current IBAT is configured to be determined by the following equation: IBAT = β * IBUCK - IOS, where IOS is a constant value and β is a variable, for example, depending on the current used by the load. Preferably, the larger the current requested by the load, the higher the value of β.

[0065] During regulator operation, such as in low-power mode, when the value β causes the value of the β*IBUCK term to be lower than the value of the constant IOS, the value of the current IBAT is zero. The value of the current IBAT cannot be negative. Therefore, the current IOUT is equal to the current IBUCK.

[0066] During regulator operation, such as in low-power mode, the current IBAT is non-zero when the value β makes the value of the β*IBUCK term higher than the value of the constant IOS. Therefore, the current IOUT depends on the values ​​of current IBAT and current IBUCK. The value VOUT depends on the values ​​of voltage VDD and voltage VBUCK. Therefore, the regulator is powered by either power supply 18 or 20, which supplies the supply voltage VDD and delivers the voltage VBUCK.

[0067] Therefore, when the load current is below the threshold, the regulator is powered by a switch-mode power supply, and when the load current is above the threshold, the regulator is powered by a switch-mode power supply and the supply voltage source VDD. Preferably, the larger the load current, the larger the portion of the current IOUT that is composed of the current IBAT.

[0068] Figure 2 An embodiment of the voltage linear regulator 12 is illustrated.

[0069] The regulator 12 includes an error amplifier 22. Amplifier 22 is, for example, an operational amplifier. Amplifier 22 includes a first input, for example, a positive input (+), at which a setpoint voltage VREF and a current IREF are delivered. Therefore, the first input is coupled to (preferably connected to) a node for applying the voltage VREF. Amplifier 22 includes a second input, for example, a negative input (-), at which a loop voltage VFB is applied. The loop voltage depends on the output voltage VOUT, for example, and is proportional to the output voltage VOUT.

[0070] The regulator 12 includes a voltage-to-current converter (VI converter) 24. The converter 24 includes an input coupled to (preferably connected to) the output of the amplifier 22. The converter 24 includes at least two outputs, each delivering a current representing the voltage received by the converter 24 as an input.

[0071] Regulator 12 includes gate drive circuits 26, 28, and 30. Regulator 12 includes as many gate drive circuits as possible, corresponding to the power supply for regulator 12. In other words, in Figure 1 In the example, regulator 12 includes gate drive circuitry 30 associated with a source of voltage VDD and gate drive circuitry 26 and 28 associated with power supplies 18 and 20, respectively.

[0072] The drive circuits 26, 28, and 30 are each configured to receive the current generated by the converter 24. Therefore, each circuit 26, 28, and 30 includes an input that is coupled to (preferably connected to) the output of the converter 24.

[0073] Preferably, converter 24 is configured such that the current supplied to gate drive circuits 26 and 28 (i.e., the gate drive circuits associated with switch-mode power supplies 18 and 20) is n times higher than the current supplied to gate drive circuit 30 (i.e., the drive circuit associated with the source of the supply voltage VDD). The value n is preferably an integer, such as a positive number, for example, greater than two.

[0074] Each gate drive circuit is configured to receive its associated supply voltage. Therefore, circuits 26 and 28 receive voltages VBUCK1 and VBUCK2, respectively, and circuit 30 receives voltage VDD. In other words, circuit 26 includes a supply input coupled (preferably connected to) a node for applying voltage VBUCK1 (e.g., the output of power supply 18). Circuit 28 includes a supply input coupled (preferably connected to) a node for applying voltage VBUCK2 (e.g., the output of power supply 20). Circuit 30 includes a supply input coupled (preferably connected to) a node for applying voltage VDD.

[0075] Each gate drive circuit 26, 28, and 30 generates the gate drive voltage of the transistor. Circuit 26 generates the gate drive voltage VGBUCK1 for transistor 32. Circuit 28 generates the gate drive voltage VGBUCK2 for transistor 34. Circuit 30 generates the gate drive voltage VGAT for transistor 36.

[0076] Transistor 32 and transistor 38 are connected in series between the node for applying voltage VBUCK1 and the output node 40, generating the output voltage VOUT of regulator 12 at the output node 40. Transistor 34 and transistor 42 are connected in series between the node for applying voltage VBUCK2 and the output node 40. Transistor 36 is connected between the node for applying voltage VDD and the output node 40.

[0077] Transistors 32, 34, 36, 38, and 42 are, for example, insulated-gate field-effect transistors (MOSFETs). For example, transistors 32, 34, 36, 38, and 42 are P-channel transistors.

[0078] One conductive terminal (e.g., the source) of transistor 32 is coupled to a node for applying voltage VBUCK1, preferably connected to that node, and another conductive terminal (e.g., the drain) of transistor 32 is coupled to node 44, preferably connected to node 44. One conductive terminal (e.g., the source) of transistor 38 is coupled to node 40, preferably connected to node 40, and another conductive terminal (e.g., the drain) of transistor 38 is coupled to node 44, preferably connected to node 44. The body of transistor 32 is coupled to a node for applying voltage VBUCK1, for example, preferably connected to that node. The body of transistor 38 is coupled to node 40, for example, preferably connected to node 40.

[0079] One conductive terminal (e.g., the source) of transistor 34 is coupled to, preferably connected to, a node for applying voltage VBUCK2, and another conductive terminal (e.g., the drain) of transistor 34 is coupled to, preferably connected to, node 46. One conductive terminal (e.g., the source) of transistor 42 is coupled to, preferably connected to, node 40, and another conductive terminal (e.g., the drain) of transistor 42 is coupled to, preferably connected to, node 44. The body of transistor 34 is coupled to, for example, a node for applying voltage VBUCK2, and preferably connected to that node. The body of transistor 42 is coupled to, for example, node 40, and preferably connected to, node 40.

[0080] One conductive terminal (e.g., the source) of transistor 36 is coupled to a node for applying voltage VDD, preferably connected to that node, and another conductive terminal (e.g., the drain) of transistor 36 is coupled to node 40, preferably connected to node 40.

[0081] The current flowing through transistor 36 (i.e., the current from the node used to apply voltage VDD to node 40) is current IBAT. The current flowing through transistors 34 and 42 (i.e., the current from the node used to apply voltage VBUCK2 to node 40) is current IBUCK2. The current flowing through transistors 32 and 44 (i.e., the current from the node used to apply voltage VBUCK1 to node 40) is current IBUCK1.

[0082] The output current IOUT (i.e., the current delivered at the output of regulator 12) corresponds to the sum of currents IBAT, IBUCK1 and IBUCK2, and currents IBUCK1 and IBUCK2 cannot be non-zero at the same time.

[0083] The regulator 12 includes control circuitry (not shown). The control circuitry is configured to generate control voltages for transistors 38 and 42.

[0084] The regulator 12 includes, for example, a capacitor 48 coupled between node 40 and a node (e.g., ground) for applying a reference voltage GND. In other words, one terminal of the capacitor 48 is coupled to node 40, preferably connected to node 40, and the other terminal of the capacitor 48 is coupled to the node for applying the voltage GND, preferably connected to that node.

[0085] The regulator includes two resistors, 50 and 52. Resistors 50 and 52 form a voltage divider bridge that generates voltage VFB. Resistors 50 and 52 are connected in series between node 40 and the node for applying voltage GND. One terminal of resistor 50 is coupled to node 40, preferably connected to node 40, and the other terminal of resistor 50 is coupled to node 54, preferably connected to node 54, generating voltage VFB at node 54. One terminal of resistor 52 is coupled to node 54, preferably connected to node 54, and the other terminal of resistor 52 is coupled to the node for applying voltage GND, preferably connected to that node. Node 54 is coupled to the second input terminal of amplifier 22, preferably connected to the second input terminal of amplifier 22. Therefore, node 40 corresponds to the input node of the voltage divider bridge, and node 54 corresponds to the output node of the voltage divider bridge.

[0086] Figure 3 A more detailed illustration is provided. Figure 2 This is part of an embodiment. More precisely, Figure 3 The diagram shows... Figure 2 An embodiment of the VI converter 24.

[0087] The converter 24 includes an input 56 that is coupled to (preferably connected to) the output of the amplifier 22.

[0088] The converter includes transistor 58. Transistor 58 is, for example, a MOSFET transistor, or an N-channel transistor. Transistor 58 is controlled by an input voltage (i.e., the voltage delivered by amplifier 22 at node 56). The drive terminal of transistor 58 is coupled to node 56, preferably connected to node 56.

[0089] The converter includes a resistor 60. Resistor 60 is connected in series with transistor 58 between node 62 and the node used to apply the reference voltage GND. In other words, one conductive terminal (e.g., the drain) of transistor 58 is coupled to node 62, preferably connected to node 62, and another conductive terminal (e.g., the source) of transistor 58 is coupled to node 64, preferably connected to node 64. Current IG flows through transistor 58 and resistor 60.

[0090] Node 62 is coupled to output node 66 of converter 24. Converter 24 delivers current IMBAT via output 66. Current IMBAT is supplied... Figure 2 The current of the drive circuit 30.

[0091] Converter 24 includes transistors 68 and 70. Transistors 68 and 70 are preferably MOSFET transistors, such as N-channel transistors. Transistors 68 and 70 are connected in series between node 62 and output terminal 66. In other words, one conductive terminal (e.g., drain) of transistor 68 is coupled to output terminal 66, preferably connected to output terminal 66, and the other conductive terminal (e.g., source) of transistor 68 is coupled to node 72, preferably connected to node 72. One conductive terminal (e.g., drain) of transistor 70 is coupled to node 72, preferably connected to node 72, and the other conductive terminal (e.g., source) of transistor 70 is coupled to node 62, preferably connected to node 62.

[0092] Node 62 is coupled to output node 74 of converter 24. Converter 24 delivers current IMBUCK1 via output 74. Current IMBUCK1 is supplied... Figure 2 The current of the drive circuit 26.

[0093] The converter 24 includes transistors 76 and a collection of transistors 78. The transistors 76 and the collection 78 are, for example, MOSFET transistors, or N-channel transistors. The collection 78 comprises n transistors connected in parallel. In other words, the drains of the transistors in the collection 78 are coupled to each other, preferably connected, and the sources of the transistors in the collection 78 are coupled to each other, preferably connected. Additionally, the drive terminals of the transistors in the collection 78 are coupled to each other, preferably connected.

[0094] Transistor 76 and assembly 78 are connected in series between node 62 and output terminal 74. In other words, one conductive terminal (e.g., drain) of transistor 76 is coupled to output terminal 74, preferably connected to output terminal 74, and the other conductive terminal (e.g., source) of transistor 76 is coupled to node 80, preferably connected to node 80. One conductive terminal (e.g., drain, i.e., the drain of the transistor in assembly 78) of assembly 78 is coupled to node 80, preferably connected to node 80, and the other conductive terminal (e.g., source 78) of assembly 78 is coupled to node 62, preferably connected to node 62.

[0095] Node 62 is coupled to output node 82 of converter 24. Converter 24 delivers current IMBUCK2 via output 82. Current IMBUCK2 is supplied... Figure 2 The current of the drive circuit 28.

[0096] Converter 24 includes transistor 84 and a transistor set 86. The transistors in transistor 84 and set 86 are, for example, MOSFET transistors, or N-channel transistors. The transistor set 86 includes several transistors connected in parallel, preferably as many as in set 78, preferably n transistors. In other words, the drains of the transistors in set 86 are coupled to each other, preferably connected, and the sources of the transistors in set 86 are coupled to each other, preferably connected. Additionally, the drive terminals of the transistors in set 86 are coupled to each other, preferably connected.

[0097] Transistor 84 and assembly 86 are connected in series between node 62 and output terminal 82. In other words, one conductive terminal (e.g., the source) of transistor 84 is coupled to output terminal 82, preferably connected to output terminal 82, and the other conductive terminal (e.g., the drain) of transistor 84 is coupled to node 88, preferably connected to node 88. One conductive terminal (e.g., the source of the transistors in assembly 86) of assembly 86 is coupled to node 88, preferably connected to node 88, and the other conductive terminal (e.g., the drain of the transistors in assembly 86) of assembly 86 is coupled to node 62, preferably connected to node 62.

[0098] The drive terminals of transistors 68, 76, and 84 are coupled to each other, and preferably connected to each other. Transistors 68, 76, and 84 are controlled by a voltage VCAS. The voltage VCAS is a common-source, common-gate voltage, configured such that the source voltages of transistors 68, 76, and 84 are exactly the same.

[0099] Transistor 70, along with clusters 78 and 86, are controlled by voltages generated by a control circuit (not shown) via regulator 12. During operation of converter 24, a drive voltage for transistor 70 turns it on, for example, equal to voltage VDD. During operation of converter 24, a drive voltage for cluster 78 or 86 corresponding to the switch-mode power supply supplying regulator 12 turns that cluster on, for example, equal to voltage VDD. A drive voltage for the other cluster turns it off, for example, significantly equal to 0V.

[0100] Preferably, the transistors in group 78 are identical to each other. Preferably, the transistors in group 86 are identical to each other. Preferably, the transistors in group 78 are identical to the transistors in group 86. Preferably, transistor 70 is identical to the transistors in groups 78 and 86.

[0101] Therefore, currents IMBUCK1 and IMBUCK2 are n times higher than current IBAT. The control voltages of sets 78 and 86 prevent currents IMBUCK1 and IMBUCK2 from being non-zero during the same operating period.

[0102] During the operation of device 10, the current IG is equal to the sum of the current IMBAT and the currents IMBUCK1 and IMBUCK2, with one of the currents IMBUCK1 and IMBUCK2 being zero. Therefore, the non-zero current among the currents IMBUCK1 and IMBUCK2 is equal to n / (n+1)IG, while the current IMBAT is equal to 1 / (n+1)IG.

[0103] Figure 4 A more detailed illustration is provided. Figure 2 Another part of the embodiments. More precisely, Figure 4 An embodiment of circuit 89 is illustrated. Circuit 89 corresponds to circuits 26 and 28 (i.e., the gate drive circuits of transistors 32 and 34, in other words, the gate drive circuits associated with supply voltages VBUCK1 and VBUCK2). Regulator 12 therefore includes two circuits 89. More generally, regulator 12 includes, for example, as many circuits 89 as possible from the supply voltage from the switch-mode power supply.

[0104] Circuit 89 includes an input terminal 90, at which a supply voltage VBUCK is applied. Depending on whether circuit 89 corresponds to circuits 26 or 28, the supply voltage VBUCK corresponds to either voltage VBUCK1 or VBUCK2. Circuit 89 also includes an input terminal 92, at which a current IMBUCK is supplied. This current IMBUCK corresponds to either current IMBUCK1 or current IMBUCK2. In other words, input terminal 92 is coupled to, and preferably connected to, the output terminal of circuit 24 associated with the supply voltage VBUCK. Circuit 89 includes an input terminal 94, at which a setpoint current IREF is supplied. The current IREF is, for example, determined by... Figure 2 The control circuit, not shown, is described. The current IREF is approximately constant, for example, during the operation of circuit 89. Circuit 89 includes an output terminal 96 at which a voltage VGBUCK is generated, which corresponds to either voltage VGBUCK1 or voltage VGBUCK2.

[0105] Circuit 89 includes transistor 98. Transistor 98 is, for example, a MOSFET transistor, or a P-channel transistor. Transistor 98 is coupled between input terminal 90 and input terminal 94. In other words, one conducting terminal (e.g., drain) of transistor 98 is coupled to input terminal 94, preferably connected to input terminal 94, and another conducting terminal (e.g., source) of transistor 98 is coupled to input terminal 90, preferably connected to input terminal 90. The driving terminal of transistor 98 is coupled to node 100, preferably connected to node 100. Transistor 98 is, for example, diode-connected. Node 100 is coupled to input terminal 94, for example, preferably connected to input terminal 94.

[0106] Circuit 89 includes transistor 102. Transistor 102 is, for example, a MOSFET transistor, or a P-channel transistor. Transistor 102 is coupled between input terminal 90 and input terminal 92. In other words, one conducting terminal (e.g., drain) of transistor 102 is coupled to input terminal 92, preferably connected to input terminal 92, and another conducting terminal (e.g., source) of transistor 102 is coupled to input terminal 90, preferably connected to input terminal 90. The driving terminal of transistor 102 is coupled to node 100, preferably connected to node 100.

[0107] Circuit 89 includes transistor 104. Transistor 104 is, for example, a MOSFET transistor, or a P-channel transistor. Transistor 104 is coupled between input terminal 90 and input terminal 92. Transistor 104 is coupled in parallel to transistor 102. In other words, one conducting terminal (e.g., drain) of transistor 104 is coupled to input terminal 92, preferably connected to input terminal 92, and another conducting terminal (e.g., source) of transistor 104 is coupled to input terminal 90, preferably connected to input terminal 90. The driving terminal of transistor 104 is coupled to input terminal 96, preferably connected to input terminal 96.

[0108] Preferably, the surface area of ​​transistor 32 or 34 corresponding to circuit 89 is equal to m times the surface area of ​​transistor 104, where m is a constant value, preferably a positive integer value.

[0109] The current IBUCK is equal to α times the current IC flowing through transistor 104. When transistor 32 or 34 is in saturation, the value α is equal to m.

[0110] Preferably, transistors 98 and 102 are identical. Therefore, the current IMBUCK is equal to the sum of the current IC and the current IREF.

[0111] Figure 5 A more detailed illustration is provided. Figure 2 Another part of the embodiments. More precisely, Figure 5 An embodiment of circuit 30 (i.e., the gate drive circuit of transistor 36, in other words, the gate drive circuit associated with the supply voltage VDD) is illustrated.

[0112] Circuit 30 includes an input terminal 106 at which a supply voltage VDD is applied. Circuit 30 also includes an input terminal 108 at which a current IMBAT is supplied. In other words, input terminal 108 is coupled to, and preferably connected to, the output terminal of circuit 24 associated with the supply voltage VDD. Circuit 30 includes an input terminal 110 at which a setpoint current IREF is supplied. The current IREF is, for example, determined by... Figure 2The control circuit, not shown, is described. The current IREF is approximately constant, for example, during the operation of circuit 30. Circuit 30 includes an output terminal 112, at which a voltage VGBAT is generated.

[0113] Circuit 30 includes transistor 114. Transistor 114 is, for example, a MOSFET transistor, or a P-channel transistor. Transistor 114 is coupled between input terminal 106 and input terminal 110. In other words, one conducting terminal (e.g., drain) of transistor 114 is coupled to input terminal 110, preferably connected to input terminal 110, and another conducting terminal (e.g., source) of transistor 114 is coupled to input terminal 106, preferably connected to input terminal 106. The driving terminal of transistor 114 is coupled to node 116, preferably connected to node 116. Transistor 114 is, for example, diode-connected. Node 116 is coupled to input terminal 110, for example, preferably connected to input terminal 110.

[0114] Circuit 30 includes transistor 118. Transistor 118 is, for example, a MOSFET transistor, or a P-channel transistor. Transistor 118 is coupled between input terminal 106 and input terminal 108. In other words, one conducting terminal (e.g., drain) of transistor 118 is coupled to input terminal 108, preferably connected to input terminal 108, and another conducting terminal (e.g., source) of transistor 118 is coupled to input terminal 106, preferably connected to input terminal 106. The driving terminal of transistor 118 is coupled to node 116, preferably connected to node 116.

[0115] Circuit 30 includes transistor 120. Transistor 120 is, for example, a MOSFET transistor, or a P-channel transistor. Transistor 120 is coupled between input terminal 106 and input terminal 108. Transistor 120 is connected in parallel with transistor 118. In other words, one conducting terminal (e.g., drain) of transistor 120 is coupled to input terminal 108, preferably connected to input terminal 108, and the other conducting terminal (e.g., source) of transistor 120 is coupled to input terminal 106, preferably connected to input terminal 106. The driving terminal of transistor 120 is coupled to input terminal 110 via switch 122. Additionally, the driving terminal of transistor 120 is coupled to input terminal 106 via switch 124. In other words, one terminal of switch 122 is coupled to the driving terminal of transistor 120, preferably connected to the driving terminal of transistor 120, and the other terminal of switch 122 is coupled to node 116, preferably connected to node 116. Similarly, one terminal of switch 124 is coupled to the drive terminal of transistor 120, preferably connected to the drive terminal of transistor 120, and the other terminal of switch 124 is coupled to input terminal 106, preferably connected to input terminal 106. Switches 122 and 124 are, for example, defined by... Figure 2The control circuit described is not shown.

[0116] Circuit 30 includes, for example, a transistor 126 and a resistor 128 connected in series between input terminals 106 and 108. Transistor 128 is, for example, a MOSFET transistor, or a P-channel transistor. One terminal of resistor 128 is coupled to input terminal 106, preferably connected thereto, and the other terminal of resistor 128 is coupled to node 130, preferably connected thereto. One conducting terminal (e.g., the source) of transistor 126 is coupled to node 130, preferably connected thereto, and the other conducting terminal (e.g., the drain) of transistor 126 is coupled to input terminal 108, preferably connected thereto. A drive terminal of transistor 126 is coupled to output terminal 112, preferably connected thereto, at which a voltage VGBAT is applied. Output terminal 112 is further coupled to input terminal 108 (preferably connected thereto), such that transistor 126 is diode-connected.

[0117] Preferably, the surface area of ​​transistor 36 is m times the surface area of ​​transistor 126. Transistor 36 is always in a saturated state. Therefore, current IBAT is m times the value of current ICB, which is the current flowing through transistor 126. Additionally, current IMBAT is equal to the sum of current ICB and a multiple of current IREF, where p is a constant value defined by circuit 24.

[0118] Therefore, the current IBAT is configured to be determined by the following equation: IBAT = β * IBUCK - IOS, where β equals And iOS equals

[0119] When the load uses low current, the current IOUT is equal to the current IBUCK, and the IBAT portion of the current IOUT is zero.

[0120] When the voltage drop is high, that is, when the voltage difference between VBUCK and the regulated voltage is high, the value α becomes equal to the value m, and the current IOUT is equal to the sum of the current IBAT and the current IBUCK, where the current IBAT is non-zero and the current IBUCK is equal to n times the current IBAT. Therefore, most of the current IOUT is delivered by the switch-mode power supply that generates IBUCK.

[0121] When the voltage drop decreases, transistor 32 or 34, corresponding to the switching-mode power supply that generates non-zero current, enters the transistor region. Therefore, the value α becomes less than the value m. Consequently, the current IBUCK becomes less than n times the current IBAT.

[0122] The more the voltage drop decreases, the more the transistor enters the transistor region, and the value α becomes increasingly lower than the value m. Therefore, the ratio of current IBUCK to current IBAT decreases until it becomes less than 1. Current IBUCK becomes less than current IBAT. Therefore, most of the current IOUT comes from current IBAT.

[0123] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these embodiments can be combined, and other variations will readily conceive of them. In particular, while the described embodiments include two switch-mode power supplies, it should be understood that the device may include a single switch-mode power supply or a greater number of switch-mode power supplies.

[0124] Furthermore, although the described embodiments include transistor 70 and sets 78 and 86, transistor 70 can be replaced by sets of transistors connected in parallel (preferably identical), such as sets 78 and 86. Thus, sets 78 and 86 would include n times more transistors than set 70.

[0125] Finally, based on the functional descriptions provided above, the actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art.

Claims

1. An electronic device, comprising: The first power supply input terminal is configured to receive the first power supply voltage; A first switch-mode power supply includes a first output terminal, wherein the first switch-mode power supply is configured to generate a second supply voltage at the first output terminal; as well as A voltage linear regulator configured to supply power to a load included in a device, the voltage linear regulator being configured to receive a first supply voltage and a second supply voltage, the voltage linear regulator comprising: A first transistor is coupled between a first power supply input terminal and the output node of a voltage linear regulator; and The second transistor is coupled between the output terminal of the first switch-mode power supply and the output node of the voltage linear regulator. The voltage linear regulator is configured as follows: In response to a second current drawn by the load falling below a threshold, a first output current is delivered from the output node of the voltage linear regulator to the load, this first output current being equal to the third current flowing through the second transistor; and In response to the second current being higher than a threshold, the first output current is set to be equal to the sum of the fourth current flowing through the first transistor and the third current flowing through the second transistor, wherein the fourth current is non-zero.

2. The device of claim 1, wherein the voltage linear regulator is further configured to increase the fourth current flowing through the first transistor in response to a second current drawn by the load being higher than a threshold, based on the increase in the drawn current.

3. The device according to claim 1, wherein the voltage linear regulator comprises: An error amplifier is configured to receive the setpoint voltage and the voltage representing the output node of the voltage linear regulator as inputs, and is configured to generate an error voltage. A voltage-to-current converter includes an input configured to receive an error voltage, and generates a fifth current at a second output of the converter and a sixth current at a third output of the converter. as well as A first gate drive circuit that drives a first transistor and a second gate drive circuit that drives a second transistor, wherein the converter is configured to deliver a fifth current to the first gate drive circuit and a sixth current to the second gate drive circuit.

4. The device of claim 3, wherein the voltage linear regulator includes a voltage divider bridge, the input of which is coupled to the output node of the voltage linear regulator, and the output of which is coupled to the input of the amplifier in a manner that delivers a voltage representing the output node.

5. The device of claim 3, wherein the converter includes a third transistor coupled between a first node and a node for applying a reference voltage, the third transistor being configured to be controlled by an error voltage, and the converter includes a fourth transistor coupling the first node to a second output and at least one fifth transistor coupling the first node to a third output.

6. The device of claim 5, wherein the first node and the third output are coupled via a set of at least two fifth transistors connected in parallel.

7. The device of claim 5, wherein the second gate drive circuit includes a sixth transistor with a diode connected between the third output terminal of the converter and the output terminal of the first switch-mode power supply, the drive terminal of the sixth transistor being coupled to the output terminal of the second gate drive circuit.

8. The device of claim 7, wherein the second gate drive circuit comprises: The seventh transistor, a diode, is connected between the input configured to receive setpoint current and the output of the first switch-mode power supply. as well as The eighth transistor is coupled between the third output terminal of the converter and the output terminal of the first switch-mode power supply, and the drive terminal of the eighth transistor is coupled to the drive terminal of the seventh transistor.

9. The device of claim 3, wherein the first gate drive circuit includes a diode-connected ninth transistor, the ninth transistor and a resistor being coupled between a second output terminal of the converter and a first power supply input terminal of the device, and the drive terminal of the ninth transistor being coupled to the output terminal of the first gate drive circuit.

10. The device of claim 9, wherein the first gate drive circuit comprises: The tenth transistor, a diode, is connected between the input configured to receive setpoint current and the device's first power supply input. The eleventh transistor is coupled between the second output terminal of the converter and the first power supply input terminal of the device, and the drive terminal of the tenth transistor is coupled to the drive terminal of the eleventh transistor.

11. The device of claim 10, wherein the first gate drive circuit comprises: The twelfth transistor is coupled between the second output terminal of the converter and the first power supply input terminal of the device; The first switch is coupled between the drive terminal of the twelfth transistor and the input terminal configured to receive the setpoint current; as well as The second switch is coupled between the drive terminal of the twelfth transistor and the first power supply input terminal of the device.

12. The device of claim 1, wherein the device includes at least one second switch-mode power supply, and for each second switch-mode power supply includes another second transistor coupled between the output terminal and the output node of the corresponding second switch-mode power supply, and the voltage linear regulator is configured such that the current flowing through only one of the second transistors is non-zero each time.

13. A method for controlling an electronic device, the method comprising: The first power supply voltage is received from the first power supply input terminal; The second supply voltage is generated at the first output terminal of the first switch-mode power supply. The load included in the device is powered by a voltage linear regulator; A voltage linear regulator receives a first supply voltage and a second supply voltage. The voltage linear regulator includes a first transistor coupled between a first supply input terminal and an output node of the voltage linear regulator, and a second transistor coupled between a first output terminal of a first switch-mode power supply and an output node of the voltage linear regulator. as well as In response to the second current drawn by the load being lower than a threshold, a first output current is delivered from the output node of the voltage linear regulator to the load, which is equal to the third current flowing through the second transistor; or In response to the second current being higher than a threshold, the first output current is set to be equal to the sum of the fourth current flowing through the first transistor and the third current flowing through the second transistor, wherein the fourth current is non-zero.

14. The method of claim 13, further comprising, in response to a second current drawn by the load exceeding a threshold, increasing a fourth current flowing through the first transistor by a voltage linear regulator based on the increase in the drawn current.

15. The method of claim 13, further comprising: The error amplifier of the voltage linear regulator receives the setpoint voltage and the voltage representing the output node of the voltage linear regulator as inputs; The error voltage is generated by the error amplifier; The error voltage is received at the input of the voltage-to-current converter; A fifth current is generated at the second output terminal of the converter; A sixth current is generated at the third output terminal of the converter; The first transistor is driven by the first gate driving circuit; The second transistor is driven by the second gate drive circuit; as well as The converter delivers the fifth current to the first gate drive circuit and the sixth current to the second gate drive circuit.

16. The method of claim 15, further comprising delivering a voltage representing an output node by the output of a voltage divider bridge of a voltage linear regulator, the input of which is coupled to the output node of the voltage linear regulator, and the output of which is coupled to the input of an amplifier.

17. The method of claim 15, further comprising: The first node is coupled to the node for applying the reference voltage by the third transistor of the converter; the third transistor is controlled by the error voltage. The first node is coupled to the second output terminal by the fourth transistor of the converter; as well as The first node is coupled to the third output by at least one fifth transistor of the converter.

18. The method of claim 17, further comprising coupling the first node and the third output via a set of at least two fifth transistors connected in parallel.

19. The method of claim 15, further comprising a third output terminal of a sixth transistor coupled to a first output terminal of a first switch-mode power supply connected by a diode of a second gate drive circuit, wherein the drive terminal of the sixth transistor is coupled to the output terminal of the second gate drive circuit.

20. The method of claim 19, further comprising: The seventh transistor, connected by the diode of the second gate drive circuit, couples the input terminal receiving the setpoint current to the output terminal of the first switch-mode power supply. as well as The third output terminal of the converter is coupled to the output terminal of the first switch-mode power supply by the eighth transistor of the second gate drive circuit, and the drive terminal of the eighth transistor is coupled to the drive terminal of the seventh transistor.

21. The method of claim 15, further comprising a ninth transistor connected by a diode of the first gate drive circuit and a second output terminal of a resistor-coupled converter and a first power supply input terminal of the device, wherein the drive terminal of the ninth transistor is coupled to the output terminal of the first gate drive circuit.

22. The method of claim 21, further comprising: The tenth transistor, coupled to the diode of the first gate drive circuit, is configured to receive the setpoint current input and the first power supply input of the device. as well as The second output terminal of the converter is coupled to the first power supply input terminal of the device by the eleventh transistor of the first gate drive circuit, and the drive terminal of the tenth transistor is coupled to the drive terminal of the eleventh transistor.

23. The method of claim 22, further comprising: The second output terminal of the converter is coupled to the first power supply input terminal of the device by the twelfth transistor of the first gate drive circuit; The first switch of the first gate drive circuit couples the drive terminal of the twelfth transistor to the input terminal configured to receive the setpoint current. as well as The drive terminal of the twelfth transistor is coupled to the first power supply input terminal of the device by the second switch of the first gate drive circuit.

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