Circuit for multiplexing adjustment of electrical parameters of a pin chip

Abstract

The application relates to a circuit for multiplexing pin trimming of a chip electrical parameter, comprising a voltage reduction chip, an input capacitor, an input power supply, a load, an output capacitor and a control end, wherein the voltage reduction chip comprises a trimming code generation module, a linear voltage reduction module, an input end, an output end, a ground end and an enable end; the input end of the voltage reduction chip is connected to the positive pole of the input capacitor and the positive pole of the input power supply; the output end of the voltage reduction chip is connected to the positive pole of the output capacitor and one end of the load; the ground end is connected to the ground; the enable end of the voltage reduction chip is connected to the control end; the control end is used for sending an enable control signal to the enable end of the voltage reduction chip; the negative pole of the input power supply, the negative pole of the input capacitor, the negative pole of the output capacitor and the other end of the load are all connected to the ground. The circuit for multiplexing pin trimming of a chip electrical parameter can realize trimming of the chip electrical parameter through multiplexing of the enable pin, saves two pins, and thus can reduce the generation and test cost.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically to a circuit for adjusting chip electrical parameters using multiplexed pins. Background Technology

[0002] To obtain more accurate electrical parameters, tuning circuits are often incorporated into the chip's circuit design. Different tuning schemes can affect the chip's production cost and testing efficiency.

[0003] like Figure 1 The image shows the existing use of I. 2 A circuit diagram for adjustment using C. The step-down chip 111 has six ports: IN, OUT, GND, EN, SCL, and SDA. The IN port is connected to the positive terminal of the input capacitor 102 and the positive terminal of the input power supply 103. The OUT port is connected to the positive terminal of the output capacitor 105 and one end of the output load 104. The GND port is connected to ground. The EN (enable) port, SCL (clock line), and SDA (bidirectional data line) are connected to the output terminals of the microcontroller 107. The negative terminals of the output capacitor 102, the input power supply 103, the output capacitor 105, and the other end of the output load 104 are all connected to ground. Existing adjustment circuits use I... 2 The C read / write code method writes the code into I. 2 C decoding module 203, and reads register data from this module, compares it with the written data, and determines the correctness of the write operation. 2 The C decoding module 203 adjusts the electrical parameters of the lower proportional resistor 405, the reference voltage 401, the upper proportional resistor 406, and the current limiting module 403 in the linear buck module 202 according to the written encoding, so as to obtain different voltage and current parameters of the output terminal OUT, thereby achieving different output specifications and maintaining the consistency of the same specification output.

[0004] However, the existing tuning circuit requires signals to be applied through three pins: EN, SCL, and SDA, in order to read and write chip data. This requires more pins during testing, increasing production and testing costs. Summary of the Invention

[0005] The purpose of this invention is to provide a circuit for adjusting the electrical parameters of a chip by multiplexing pins. By multiplexing the enable pin EN and applying different voltages and pulse signals to the enable pin, the encoding verification and writing functions are realized to adjust the electrical parameters of the chip. This saves two pins, thus reducing the production and testing costs.

[0006] To achieve the above objectives, this invention provides a circuit for multiplexing pin-adjusted chip electrical parameters, comprising a step-down chip, an input capacitor, an input power supply, a load, an output capacitor, and a control terminal. The step-down chip includes an adjustment code generation module, a linear step-down module, an input terminal, an output terminal, a ground terminal, and an enable terminal. The input terminal of the step-down chip is connected to the positive terminal of the input capacitor and the positive terminal of the input power supply. The output terminal of the step-down chip is connected to the positive terminal of the output capacitor and one end of the load. The ground terminal is connected to ground. The enable terminal of the step-down chip is connected to the control terminal, which is used to send an enable control signal to the enable terminal of the step-down chip. The negative terminals of the input power supply, the input capacitor, the output capacitor, and the other end of the load are all connected to ground.

[0007] Further, the tuning code generation module includes an enable module, a single-wire decoding module, a test mode selection module, a write instruction module, a verification module, a one-time programming module, a verification NMOS transistor, and a verification resistor. The input terminals of the enable module, the test mode selection module, the single-wire decoding module, and the second input terminal of the write instruction module are all connected to the enable terminal of the buck converter chip. The output terminal of the enable module is connected to the linear buck converter module. The output terminal of the single-wire decoding module is connected to the first input terminal of the verification module and the first input terminal of the one-time programming module, respectively. The first input terminal of the test mode selection module... The output terminal is connected to the second input terminal of the verification module; the second output terminal of the test mode selection module is connected to the second input terminal of the primary programming module, and the third input terminal of the test mode selection module is connected to the first input terminal of the write instruction module; the output terminal of the write instruction module is connected to the third input terminal of the primary programming module; the primary programming module has four output terminals respectively connected to the linear buck module; the source and substrate of the verification NMOS transistor are both connected to ground, the drain of the verification NMOS transistor is connected to one end of the verification resistor, and the other end of the verification resistor is connected to the input terminal of the buck chip.

[0008] Further, the linear buck module includes a reference voltage generation module, an error amplification module, a current limiting module, a buck PMOS transistor, a lower proportional resistor, and an upper proportional resistor. The input terminal of the reference voltage generation module is connected to the second output terminal of the primary programming module, and the output terminal of the reference voltage generation module is connected to the inverting input terminal of the error amplification module. The first terminal of the upper proportional resistor is connected to the output terminal, and the second terminal is connected to the first terminal of the lower proportional resistor, with the second terminal of the lower proportional resistor connected to ground. The non-inverting input terminal of the error amplification module is connected to the second terminal of the upper proportional resistor and the first terminal of the lower proportional resistor, respectively. The enable input terminal of the error amplification module is connected to the output terminal of the enable module. The output terminal of the error amplification module is connected to the input terminal of the current limiting module. The output terminal of the current limiting module is connected to the gate of the buck PMOS transistor. The source and substrate of the buck PMOS transistor are connected to the input terminal of the buck chip, and the drain of the buck PMOS transistor is connected to the output terminal of the buck chip.

[0009] Furthermore, the test selection module includes an input detection NMOS transistor, a first current source, a first Schmitt trigger, a first D flip-flop, a second D flip-flop, a first AND gate, a second AND gate, and a third AND gate. The source of the input detection NMOS transistor is connected to the enable terminal, the gate and substrate of the input detection NMOS transistor are connected to ground, the drain of the input detection NMOS transistor is connected to the negative terminal of the first current source and the input terminal of the first Schmitt trigger, the positive terminal of the first current source is connected to the input terminal of the buck converter chip, the output terminal of the first Schmitt trigger is connected to the CLK terminal of the first D flip-flop, and the Q terminal of the first D flip-flop is connected to the second input terminal of the first AND gate and the second input terminal of the third AND gate, respectively. The D terminal of the first D flip-flop is connected to the QN terminal of the first D flip-flop to form a first node. The first node is connected to the CLK terminal of the second D flip-flop and the second input terminal of the second AND gate. The Q terminal of the second D flip-flop is connected to the first input terminal of the second AND gate and the first input terminal of the third AND gate. The D terminal and the QN terminal of the second D flip-flop are interconnected to form a second node. The second node is connected to the first input terminal of the first AND gate. The output terminal of the first AND gate forms the first output terminal of the test mode selection module. The output terminal of the second AND gate forms the second output terminal of the test mode selection module. The output terminal of the third AND gate forms the third output terminal of the test mode selection module.

[0010] Furthermore, the single-wire decoding module may include a first inverter, a first pull-down NMOS transistor, a second current source, a pulse width capacitor, a comparator, and three to eighteenth D flip-flops. The input terminal of the first inverter is connected to the enable terminal, and the output terminal of the first inverter is connected to the gate of the pull-down NMOS transistor and the CLK terminal of the three to eighteenth D flip-flops, respectively. The drain of the first pull-down NMOS transistor is connected to the negative terminal of the second current source, the positive terminal of the pulse width capacitor, and the positive input terminal of the comparator, respectively. The source of the first pull-down NMOS transistor is connected to ground. The negative terminal of the pulse capacitor is connected to the input terminal of the step-down chip; the negative terminal of the comparator is connected to the internal reference voltage; the output terminal of the comparator is connected to the D terminal of the third D flip-flop; the third to the eighteenth D flip-flops are arranged sequentially, and for any one of the fourth to the seventeenth D flip-flops, the D terminal of the D flip-flop is connected to the Q terminal of the preceding D flip-flop, and the Q terminal of the D flip-flop is connected to the D terminal of the following D flip-flop; all the Q terminals of the third to the eighteenth D flip-flops form the output terminal of the single-wire decoding module.

[0011] Furthermore, the write instruction module includes an input PMOS transistor, a third current source, a second Schmitt trigger, a second inverter, a debouncing filter, and a fourth AND gate. The source and substrate of the input PMOS transistor are connected to the enable terminal, the gate of the input PMOS transistor is connected to the input terminal of the buck converter chip, the drain of the input PMOS transistor is connected to the positive terminal of the third current source and the input terminal of the second Schmitt trigger, the negative terminal of the third current source is connected to ground, the output terminal of the second Schmitt trigger is connected to the input terminal of the second inverter, the output terminal of the second inverter is connected to the input terminal of the debouncing filter, the output terminal of the debouncing filter is connected to the first input terminal of the fourth AND gate, the second input terminal of the fourth AND gate is connected to the third output terminal of the test mode selection module, and the output terminal of the fourth AND gate forms the output terminal of the write instruction module.

[0012] Furthermore, the enable module includes a fourth current source, a second pull-down NMOS transistor, and a third Schmitt trigger. The gate of the second pull-down NMOS transistor is connected to the enable terminal, the source and substrate of the second pull-down NMOS transistor are connected to ground, the drain of the second pull-down NMOS transistor is connected to the negative terminal of the fourth current source and the input terminal of the third Schmitt trigger, respectively, and the output terminal of the third Schmitt trigger is formed as the output terminal of the enable module.

[0013] Furthermore, the verification module may include a fifth AND gate, first to fifth AND gates, and third to tenth inverters. The input of the third inverter is connected to the Q terminal of the fourth D flip-flop, the input of the fourth inverter is connected to the Q terminal of the sixth D flip-flop, the first input of the second AND gate is connected to the Q terminal of the third D flip-flop, the second input of the second AND gate is connected to the output of the third inverter, the third input of the second AND gate is connected to the Q terminal of the fifth D flip-flop, and the fourth input of the second AND gate is connected to the output of the fourth inverter; the input of the fifth inverter is connected to... The Q input of the eighth D flip-flop is connected to the Q input of the sixth inverter, the first input of the third AND gate is connected to the Q input of the seventh D flip-flop, the second input of the third AND gate is connected to the output of the fifth inverter, the third input of the third AND gate is connected to the Q input of the ninth D flip-flop, the fourth input of the third AND gate is connected to the output of the sixth inverter; the input of the seventh inverter is connected to the Q input of the eleventh D flip-flop, the input of the eighth inverter is connected to the Q input of the thirteenth D flip-flop, and the first input of the fourth AND gate is connected to the output of the seventh inverter. The fourth AND gate's second input is connected to the Q terminal of the twelfth D flip-flop; its third input is connected to the output of the eighth inverter; and its fourth input is connected to the Q terminal of the fourteenth D flip-flop. The ninth inverter's input is connected to the Q terminal of the fifteenth D flip-flop; the tenth inverter's input is connected to the Q terminal of the seventeenth D flip-flop; the fifth AND gate's first input is connected to the output of the ninth inverter; its second input is connected to the Q terminal of the sixteenth D flip-flop; and its third input is connected to the output of the tenth inverter. The fourth input of the fifth quad AND gate is connected to the Q terminal of the eighteenth D flip-flop; the first input of the first quad AND gate is connected to the output of the second quad AND gate; the second input of the first quad AND gate is connected to the output of the third quad AND gate; the third input of the first quad AND gate is connected to the output of the fourth quad AND gate; the fourth input of the first quad AND gate is connected to the output of the fifth quad AND gate; the output of the first quad AND gate is connected to the first input of the fifth binary AND gate; the second input of the fifth binary AND gate is connected to the first output of the test mode selection module; and the output of the fifth binary AND gate forms the output of the verification module.

[0014] Furthermore, the primary programming module includes a first fuse unit to a sixteenth fuse unit arranged in sequence, wherein the first input terminals of the first fuse unit to the sixteenth fuse unit are all connected to the output terminal of the write instruction module; the second input terminals of the first fuse unit to the sixteenth fuse unit are all connected to the second output terminal of the test mode selection module; the third input terminal of the first fuse unit is connected to the Q terminal of the third D flip-flop; the output terminal of the first fuse unit forms the fourth output terminal of the primary programming module; the second fuse unit to the sixteenth fuse unit correspond one-to-one with the fourth D flip-flop to the eighteenth D flip-flop, and for each of the second fuse unit to the sixteenth fuse unit, the third input terminal of the fuse unit is connected to the output terminal of the previous fuse unit and the Q terminal of the corresponding D flip-flop of the fuse unit.

[0015] Furthermore, each fuse unit includes a sixth AND gate, a current NMOS transistor, a fifth current source, a fuse, an eleventh inverter, and a signal selector. The second input terminal of the sixth AND gate forms the first input terminal of the fuse unit. The output terminal of the sixth AND gate is connected to the gate of the current NMOS transistor. The source and substrate of the current NMOS transistor are connected to ground. The drain of the current NMOS transistor, the positive terminal of the fifth current source, the input terminal of the eleventh inverter, and one end of the fuse are interconnected. The other end of the fuse is connected to the input terminal of the step-down chip. The negative terminal of the fifth current source is connected to ground. The output terminal of the eleventh inverter is connected to the first input terminal of the signal selector. The second input terminal of the signal selector and the first input terminal of the sixth AND gate together form the third input terminal of the fuse unit. The third input terminal of the signal selector forms the second input terminal of the fuse unit. The output terminal of the signal selector forms the output terminal of the fuse unit.

[0016] The circuit for adjusting the electrical parameters of a chip using multiplexed pins of the present invention achieves test mode selection, encoding verification, and writing functions by multiplexing the enable pin EN and applying signals with different positive and negative levels and pulse widths to the EN pin. Since the EN pin is multiplexed, the chip can save two test adjustment pins, making the test peripheral simple and efficient and saving the use of peripheral components. At the same time, it can also reduce the chip packaging cost. Attached Figure Description

[0017] Figure 1 In order to use the existing technology I 2 A circuit diagram for C to be adjusted;

[0018] Figure 2 This is a circuit for adjusting the electrical parameters of a chip using multiplexed pins according to an embodiment of the present invention;

[0019] Figure 3 This is a waveform diagram of the enable terminal EN and the input terminal IN according to an exemplary embodiment of the present invention.

[0020] Figure 4 A circuit diagram of a test mode selection module according to an embodiment of the present invention;

[0021] Figure 5 This is a circuit diagram of a single-line decoding module according to an embodiment of the present invention;

[0022] Figure 6 This is a circuit diagram of the write instruction module according to an embodiment of the present invention;

[0023] Figure 7 This is a circuit diagram of an enable module according to an embodiment of the present invention;

[0024] Figure 8 This is a circuit diagram of a code verification module according to an embodiment of the present invention;

[0025] Figure 9 This is a circuit diagram of a primary programming module according to an embodiment of the present invention;

[0026] Figure 10 This is a circuit diagram of a fuse unit according to an embodiment of the present invention. Detailed Implementation

[0027] The preferred embodiments of the present invention are given below with reference to the accompanying drawings and described in detail.

[0028] like Figure 2 As shown, this embodiment of the invention provides a circuit for multiplexing pin-adjusted chip electrical parameters, including a step-down chip 101, an input capacitor 102, an input power supply 103, a load 104, an output capacitor 105, and a control terminal 106. The step-down chip 101 includes an adjustment code generation module 201, a linear step-down module 202, an input terminal IN, an output terminal OUT, a ground terminal GND, and an enable terminal EN. The input terminal IN is connected to the positive terminal of the input capacitor 102 and the positive terminal of the input power supply. The output terminal OUT is connected to the positive terminal of the output capacitor 105 and one end of the load 104. The ground terminal GND is connected to ground. The enable terminal EN is connected to the control terminal 106, which is used to receive external enable control signals. The negative terminals of the input power supply 103, the input capacitor 102, the output capacitor 105, and the other end of the load 104 are all connected to ground.

[0029] The adjustment code generation module 201 is configured to enter different test modes based on the signal from the enable terminal EN, perform a jump response on the input current at the input terminal IN after the code verification is correct, and output an adjustment signal to the linear buck module 202 so as to achieve different output voltage and current specifications at the output terminal OUT. Specifically, as shown in the example... Figure 2As shown, the tuning code generation module 201 includes an enable module 301, a single-wire decoding module 302, a test mode selection module 303, a write instruction module 304, a verification module 305, a one-time programming module 306, a verification NMOS transistor 307, and a verification resistor 308. The input terminal of the enable module 301 is connected to the enable terminal EN, and the input signal of the enable module 301 is EN, while the output signal is ON. The input terminal of the single-wire decoding module 302 is connected to the enable terminal EN, and its input signal is EN, while its output signal is BIT<15:0> (i.e., a 16-bit parallel encoded signal). The test mode selection module 303 includes one input terminal and three output terminals. Its input terminal is connected to the enable terminal EN and is used to receive the input signal EN. The first output terminal of the test mode selection module 303 is used to output the first signal CodeCheck, the second output terminal is used to output the second signal SoftProg, and the third output terminal is used to output the third signal FlashEN. The write instruction module 304 has two inputs. The first input module 304 has one input and one output. Its first input is connected to the third output of the test mode selection module 303 to receive the third signal FlashEN. The output of the write instruction module 304 is used to output the signal Trim. The verification module 305 has two inputs and one output. Its first input is connected to the output of the single-wire decoding module 302 to receive the signal BIT<15:0>. Its second input is connected to the first output of the test mode selection module 303 to receive the first signal CodeCheck. The output of the verification module 305 outputs the signal GTN. The one-time programming module 306 has three inputs and four outputs. Its first input is connected to the output of the single-wire decoding module 302 to receive the signal BIT<15:0>. Its second input is connected to the second output of the test mode selection module 303 to receive the second signal SoftProg. Its third input is connected to the output of the write instruction module 304 to receive the signal Trim. The first output of the one-time programming module 306 outputs the signal TR1. <0> The second output terminal outputs signal TR2<6:1>, the third output terminal outputs signal TR3<12:7>, and the fourth output terminal outputs signal TR4<14:13>. The four output terminals of the primary programming module 306 are respectively connected to the linear buck module 202. The gate of the verification NMOS transistor 307 is connected to the output terminal of the verification module 305 to receive the signal GTN. The source and substrate of the verification NMOS transistor 307 are both connected to ground. The drain of the verification NMOS transistor 307 is connected to one end of the verification resistor 308, and the other end of the verification resistor 308 is connected to the input terminal IN of the buck chip 101.

[0030] The linear buck module 202 includes a reference voltage generation module 401, an error amplification module 402, a current limiting module 403, a buck PMOS transistor 404, a lower proportional resistor 405, and an upper proportional resistor 406. The input terminal of the reference voltage generation module 401 is connected to the second output terminal of the primary programming module 306 to receive the signal TR2<6:1>. The output terminal of the reference voltage generation module 401 is connected to the inverting input terminal of the error amplification module 402 to output the reference voltage VREF. The first terminal of the upper proportional resistor 406 is connected to the output terminal OUT, the second terminal is connected to the first terminal of the lower proportional resistor 405, and the second terminal of the lower proportional resistor is connected to ground. The error amplification module 402... The non-inverting input terminals of the two resistors are connected to the second terminal of the upper proportional resistor 406 and the first terminal of the lower proportional resistor 405, respectively, to receive the signal FB. The enable input terminal of the error amplifier module 402 is connected to the output terminal of the enable module 301 to receive the signal EN. The output terminal of the error amplifier module 402 is connected to the input terminal of the current limiting module 403 to output the signal VEA to the current limiting module 403. The output terminal of the current limiting module 403 is connected to the gate of the buck PMOS transistor 404 to output the signal GTP to the gate. The source and substrate of the buck PMOS transistor 404 are connected to the input terminal IN of the buck chip 101, and the drain of the buck PMOS transistor 404 is connected to the output terminal OUT of the buck chip 101. Both the upper proportional resistor 406 and the lower proportional resistor 405 are variable resistor modules with an encoding input terminal. The resistance value can be changed by the signal input through the encoding input terminal. Specifically, the encoding input terminal of the upper proportional resistor 406 is connected to the third output terminal of the primary programming module 306 to receive the signal TR3<12:7>, and the encoding input terminal of the lower proportional resistor 405 is connected to the first output terminal of the primary programming module 306 to receive the signal TR1. <0> .

[0031] In some embodiments, the association between encoding and level is: 1 represents a high level "IN", and 0 represents a low level "ground". The signals output by the primary programming module 306 are set as follows: Signal TR1 <0> 1 bit, modulate the output OUT version, when TR1 <0> When TR1 is 0, the output is the 3.3V version. <0> When set to 1, the output is 1.2V; signal TR2<6:1>, 6 bits, adjusts the output VREF voltage accuracy of the internal reference voltage generation module 401; signal TR3<12:7>, 6 bits, adjusts the voltage accuracy of the output terminal OUT; signal TR4<14:13>, 2 bits, adjusts the output current limit value. The one-time programming module 306 can also output signal TR <15> When TR <15> When the value is 1, the firmware function of the primary programming module 306 is disabled.

[0032] By inputting the signal EN to the enable terminal EN via the control terminal 106, the operation of the buck converter chip 101 can be controlled. For example... Figure 3As shown, the signal EN is a level that changes over time. The test mode selection module 303 is set to count negative voltage pulses of the signal EN (see section A) and enter different test modes according to the counting results. The negative voltage level is -1V and the holding time is 30us. When the EN signal receives a negative voltage pulse and its level remains at 2V, the first signal CodeCheck output by the test mode selection module 303 is at a high level, while the second signal SoftProg and the third signal FlashEN are at a low level. At this time, the first test mode is entered, and the test mode selection module 303 enables the code verification module 305, thus activating it. When the EN signal receives two negative voltage pulses and its level remains at 2V, the second signal SoftProg output by the test mode selection module 303 is at a high level, while the first signal CodeCheck and the third signal FlashEN are at a low level. At this time, the second test mode is entered. The output code of the single-wire decoding module 302 is transmitted to the linear buck module 202 via the primary programming module 306, thereby adjusting the linear buck module 202 and achieving different output voltage and current specifications at the output terminal OUT. When the EN signal receives three negative voltage pulses and its level remains at 2V, the third signal FlashEN output by the test mode selection module 303 is at a high level, while the first signal CodeCheck and the second signal SoftProg are at a low level. At this time, the third test mode is entered, and the instruction writing module 304 begins operation. The single-wire decoding module 302 identifies the input signal as 1 or 0 based on the high-level width of the 5V high-level and 2V low-level pulse signals (see section B). The frequency of the EN input code is 50kHz, meaning each cycle of the high and low levels takes 20µs. When the high level is maintained for 10µs (i.e., 50% duty cycle), the single-wire decoding module 302 determines the input code of the EN signal as 1; when the high level is maintained for 2µs (i.e., 10% duty cycle), the single-wire decoding module 302 determines the input code of the EN signal as 0. When the level of the EN signal is 7V (see section C), the Trim signal output by the write instruction module 304 is high. When the EN signal > 1.5V, the ON signal output by the enable module 301 is high, and the buck chip 101 starts working, enabling output functionality.When CodeCheck is high, the code verification module 305 determines whether the output code (i.e., output signal) BIT<15:0> of the single-wire decoding module 302 can be correctly decoded. If the code of BIT<15:0> is correct, the signal GTN output by the code verification module 305 changes from low to high, and the code verification NMOS transistor 307 is turned on. At this time, a current path is generated from the input terminal IN through the code verification resistor 308 and the code verification NMOS transistor 307 to ground. Before the code verification module 305 receives the correct code, the input current of the input terminal IN is 10nA. After the code verification module 305 receives the correct code, the input current of the input terminal IN is 180uA. Therefore, this method can be used to determine whether the input code can be correctly decoded by the buck chip 101. When the signal Trim output by the instruction writing module 304 is high, the primary programming module 306 will solidify the output code BIT<15:0> of the single-wire decoding module 302 into the circuit.

[0033] like Figure 4As shown, in some embodiments, the test mode selection module 303 may include an input detection NMOS transistor 501, a first current source 502, a first Schmitt trigger 503, a first D flip-flop 504, a second D flip-flop 505, a first AND gate 506, a second AND gate 507, and a third AND gate 508. The source of the input detection NMOS transistor 501 is connected to the enable terminal EN (i.e., the source is the input terminal of the test mode selection module 303), the gate and substrate of the input detection NMOS transistor 501 are connected to ground, and the drain of the input detection NMOS transistor 501 is connected to the negative terminal of the first current source 502 and the input terminal of the first Schmitt trigger 503. The positive terminal of the first current source 502 is connected to the input terminal IN of the step-down chip 101. The output terminal of the first Schmitt trigger 503 is connected to the CLK terminal (i.e., clock signal input terminal) of the first D flip-flop 504. The Q terminal of the first D flip-flop 504 is used to output signal Q0. The Q terminal of the first D flip-flop 504 is connected to the second input terminal of the first AND gate 506 and the second input terminal of the third AND gate 508, respectively. The D terminal (i.e., signal input terminal) of the first D flip-flop 504 is connected to the QN terminal of the first D flip-flop 504. The output terminal (i.e., the output terminal used to output the inverted signal of Q0) is connected to form the first node Q0N. The first node Q0N is connected to the CLK terminal of the second D flip-flop 505 and the second input terminal of the second AND gate 507, respectively. The Q terminal of the second D flip-flop 505 is used to output the signal Q1 and is connected to the first input terminal of the second AND gate 507 and the first input terminal of the third AND gate 508, respectively. The D terminal of the second D flip-flop 505 and the QN terminal of the second D flip-flop 505 are connected to each other to form the second node Q1N. The second node Q1N is connected to the first input terminal of the first AND gate 506. The output terminal of the first AND gate 506 forms the first output terminal of the test mode selection module 303 and is used to output the first signal CodeCheck. The output terminal of the second AND gate 507 forms the second output terminal of the test mode selection module 303 and is used to output the second signal SoftProg. The output terminal of the third AND gate 508 forms the third output terminal of the test mode selection module 303 and is used to output the third signal FlashEN.

[0034] like Figure 3As shown, when the signal EN is -1, the input of the first Schmitt trigger 503 is pulled low to 0V, and its output is high. When the signal EN is a negative voltage pulse signal of 2V to -1V, the input signal at the CLK terminal of the first D trigger 504 is a positive voltage pulse signal of 0V to 5V. After the triggering and counting output of the first D trigger 504 and the second D trigger 505, under the action of the first AND gate 506, the second AND gate 507 and the third AND gate 508, it can be obtained that when the signal EN includes a negative voltage pulse and enters the first test mode, the first signal CodeCheck changes from low level to high level. At this time, the step-down chip 101 is in the verification encoding mode, according to the input terminal I... The current monitoring result of N determines whether the 16-bit encoding of EN meets the decoding requirements. When the signal EN includes two negative voltage pulses to enter the second test mode, the second signal SoftProg jumps from low level to high level. At this time, the buck chip 101 is in soft programming mode. Different 16-bit encodings input to the signal EN can obtain different current and voltage specifications output by the output terminal OUT. When the signal EN includes three negative voltage pulses to enter the third test mode, the third signal FlashEN jumps from low level to high level. At this time, the buck chip 101 is in write-and-harden mode, which can harden the 16-bit encoding verified by the second test mode into the internal circuit of the buck chip 101.

[0035] like Figure 5As shown, in some embodiments, the single-wire decoding module 302 may include a first inverter 601, a first pull-down NMOS transistor 602, a second current source 603, a pulse width capacitor 604, a comparator 605, and a third D flip-flop 606 to an eighteenth D flip-flop 621. The input terminal of the first inverter 601 is connected to the enable terminal EN (i.e., the input terminal of the first inverter 601 is the input terminal of the single-wire decoding module 302). The output terminal of the first inverter 601 is connected to the gate of the pull-down NMOS transistor 602 and the CLK terminals of the third D flip-flop 606 to the eighteenth D flip-flop 621, respectively. The drain of the first pull-down NMOS transistor 602 is connected to the negative terminal of the second current source 603, the positive terminal of the pulse width capacitor 604, and the positive input terminal of the comparator 605, respectively. The source and substrate of the first pull-down NMOS transistor 602 are connected to ground. The positive terminal of the second current source 603 is connected to the input terminal IN of the step-down chip 101. The pulse capacitor 605... The negative terminal of 04 is connected to ground; the negative input terminal of comparator 605 is connected to the internal reference voltage VREF (i.e., the reference voltage generated by reference voltage generation module 401); the output terminal of comparator 605 is used to output the signal DATA and is connected to the D terminal of the third D flip-flop 606; the third D flip-flop 606 to the eighteenth D flip-flop 621 are arranged sequentially, and for any one of the fourth D flip-flop 606 to the seventeenth D flip-flop 620, the D terminal of the D flip-flop is connected to the Q terminal of the preceding D flip-flop, and the Q terminal of the D flip-flop is connected to the D terminal of the following D flip-flop. All the Q terminals of the third to eighteenth D flip-flops 606-621 together form the output terminal of the single-wire decoding module 302, which is used to output the signal BIT<15:0>. That is to say, the third D flip-flop to the eighteenth D flip-flop 621 are connected sequentially; specifically, the Q terminal of the third D flip-flop 606 outputs the signal BIT. <0> It is connected to the D terminal of the fourth D flip-flop 607, and the Q terminal of the fourth D flip-flop 607 is used to output the bit signal. <1> And it is connected to the D terminal of the fifth D flip-flop, and so on; the D terminal of the seventeenth D flip-flop 620 receives the signal BIT output from the Q terminal of the sixteenth D flip-flop. <13> The Q output signal BIT of the seventeenth D flip-flop 620 <14> It is connected to the D terminal of the eighteenth D flip-flop 621.

[0036] like Figure 3As shown, in segment B, the signal EN is a 2V to 5V pulse signal. When the high level of signal EN reaches 10µs, the first pull-down NMOS transistor 602 is turned off, and the charging of the second current source 603 is sufficient for the positive input signal of comparator 605 to rise above the internal reference voltage VREF, that is, the output signal DATA of comparator 605 is high. When the high level of EN is only 2µs, the time for the first pull-down NMOS transistor 602 to be turned off is insufficient for the charging of the second current source 603 to raise the positive input signal of comparator 605. The voltage rises above VREF (i.e., the positive input signal is below the internal reference voltage VREF), so the output signal DATA of comparator 605 is low. Each low level of signal EN causes the third D flip-flop 606 to the eighteenth D flip-flop 621 to read the level state at the D terminal, and each high level of signal EN causes the third D flip-flop 606 to the eighteenth D flip-flop 621 to output the level state read at the D terminal from the Q terminal. Thus, the serial encoding of signal EN is processed by 16 pulses and then output in parallel on BIT<15:0>.

[0037] like Figure 6 As shown, in some embodiments, the write instruction module 304 may include an input PMOS transistor 701, a third current source 702, a second Schmitt trigger 703, a second inverter 709, a debouncing filter 704, and a fourth AND gate 705. The source and substrate of the input PMOS transistor 701 are connected to the enable terminal EN (the source and substrate are the input terminals of the write instruction module 304), the gate of the input PMOS transistor 701 is connected to the input terminal IN, and the drain of the input PMOS transistor 701 is connected to the positive terminal of the third current source 702 and the input terminal of the second Schmitt trigger 703, respectively. The negative terminal of the third current source 702 is connected to ground. The output terminal of the second Schmitt trigger 703 is connected to the input terminal of the second inverter 709. The output terminal of the second inverter 709 is connected to the input terminal of the debounce filter 704. The output terminal of the debounce filter 704 is connected to the first input terminal of the fourth AND gate 705. The second input terminal of the fourth AND gate 705 is connected to the third output terminal of the test mode selection module 303 to receive the third signal FlashEN. The output terminal of the fourth AND gate 705 is formed as the output terminal of the write instruction module 304 for outputting the signal Trim.

[0038] like Figure 3As shown, in segment C, when the voltage of signal EN is 7V and held for 500us, the drain of input PMOS transistor 701 is pulled high. After passing through the second Schmitt trigger 703 and the second inverter 709, the input of debounce filter 704 is high. When the high level of input to debounce filter 704 exceeds 100ns, its output is high. If the signal FlashEN at the second input of the fourth AND gate 705 is high at this time, the output signal Trim of the fourth AND gate 705 is high.

[0039] like Figure 7 As shown, in some embodiments, the enable module 301 may include a fourth current source 706, a second pull-down NMOS transistor 707, and a third Schmitt trigger 708. The gate of the second pull-down NMOS transistor 707 is connected to the enable terminal EN, the source and substrate of the second pull-down NMOS transistor are connected to ground, and the drain of the second pull-down NMOS transistor 707 is connected to the negative terminal of the fourth current source 706 and the input terminal of the third Schmitt trigger 708. The output terminal of the third Schmitt trigger 708 forms the output terminal of the enable module 301, used to output the signal ON. When the signal EN is greater than 1.5V, the second pull-down NMOS transistor 707 is turned on, the input of the third Schmitt trigger 708 is pulled low, its output signal ON is high, and the buck chip 101 is in the working state.

[0040] like Figure 8As shown, in some embodiments, the verification module 305 may include a fifth AND gate 801, first four AND gates 802 to fifth four AND gates 806, and third inverters 807 to tenth inverters 814. The input of the third inverter 807 is connected to the Q terminal of the fourth D flip-flop 607 to receive the BIT signal. <1> The input of the fourth inverter 808 is connected to the Q output of the sixth D flip-flop to receive the bit signal. <3> The first input terminal of the second quad AND gate 803 is connected to the Q terminal of the third D flip-flop 606 to receive the bit signal. <0> The second input of the second quad AND gate 803 is connected to the output of the third inverter 807, and the third input of the second quad AND gate 803 is connected to the Q input of the fifth D flip-flop to receive the bit signal. <2> The fourth input of the second quad AND gate 803 is connected to the output of the fourth inverter 808; the input of the fifth inverter 809 is connected to the Q input of the eighth D flip-flop to receive the bit signal. <5> The input of the sixth inverter 810 is connected to the Q output of the tenth D flip-flop to receive the bit signal. <7> The first input terminal of the third AND gate 804 is connected to the Q terminal of the seventh D flip-flop 606 to receive the bit signal. <4> The second input of the third quad AND gate 804 is connected to the output of the fifth inverter 809, and the third input of the third quad AND gate 804 is connected to the Q input of the ninth D flip-flop to receive the bit signal. <6> The fourth input of the third AND gate 804 is connected to the output of the sixth inverter 810; the input of the seventh inverter 811 is connected to the Q input of the eleventh D flip-flop to receive the bit signal. <8> The input of the eighth inverter 812 is connected to the Q output of the thirteenth D flip-flop to receive the bit signal. <10> The first input of the fourth quad-AND gate 805 is connected to the output of the seventh inverter 811, and the second input of the fourth quad-AND gate 805 is connected to the Q input of the twelfth D flip-flop to receive the bit signal. <9> The third input of the fourth quad-AND gate 805 is connected to the output of the eighth inverter 812, and the fourth input of the fourth quad-AND gate 805 is connected to the Q input of the fourteenth D flip-flop to receive the bit signal. <11> The input of the ninth inverter 813 is connected to the Q output of the fifteenth D flip-flop to receive the BIT signal. <12> The input of the tenth inverter 814 is connected to the Q output of the seventeenth D flip-flop to receive the bit signal. <14> The first input of the fifth quadruple AND gate 806 is connected to the output of the ninth inverter 813, and the second input of the fifth quadruple AND gate 806 is connected to the Q input of the sixteenth D flip-flop to receive the bit signal. <13> The third input of the fifth quad-AND gate 806 is connected to the output of the tenth inverter 814, and the fourth input of the fifth quad-AND gate 806 is connected to the Q input of the eighteenth D flip-flop to receive the bit signal. <15> ;The first input terminal of the first quad AND gate 802 is connected to the output terminal of the second quad AND gate 803, the second input terminal of the first quad AND gate 802 is connected to the output terminal of the third quad AND gate 804, the third input terminal of the first quad AND gate 802 is connected to the output terminal of the fourth quad AND gate 805, and the fourth input terminal of the first quad AND gate 802 is connected to the output terminal of the fifth quad AND gate 806. The output terminal of the first quad AND gate 802 is connected to the first input terminal of the fifth binary AND gate 801, and the second input terminal of the fifth binary AND gate 801 is connected to the first output terminal of the test mode selection module 303 to receive the CodeCheck signal. The output terminal of the fifth binary AND gate 801 forms the output terminal of the code verification module 305 for outputting the GTN signal. Since a high level represents 1 and a low level represents 0, from the circuit logic above, it can be seen that when the input code BIT<15:0> is 1010101001010101, the output of the first quad AND gate 802 is high. If CodeCheck is also high at this time, then the output of the fifth binary AND gate 801 is high.

[0041] like Figure 9 As shown, in some embodiments, the primary programming module 306 may include a first fuse unit 901 to a sixteenth fuse unit 916, wherein the first input terminals of the first fuse units 901 to the sixteenth fuse unit 916 are all connected to the output terminal of the write instruction module 304 to receive the signal Trim; the second input terminals of the first fuse units 901 to the sixteenth fuse unit 916 are all connected to the second output terminal of the test mode selection module 303 to receive the signal SoftProg; and the third input terminal of the first fuse unit 901 is connected to the Q terminal of the third D flip-flop 606 to receive the signal BIT. <0> The output terminal of the first fuse unit 901 is configured as the fourth output terminal of the primary programming module 306, used to output signal TR. <0> The third input terminal of the second fuse unit 901 is connected to the Q terminal of the fourth D flip-flop 607 and the output terminal of the first fuse unit 901, respectively, to receive the signal BIT. <1> and TR <0> Similarly, the third input terminal of the fifteenth fuse unit 915 is connected to the Q terminal of the seventeenth D flip-flop 620 and the output terminal of the fourteenth fuse unit, respectively, to receive the signal BIT. <14> and TR <13> The third input terminal of the sixteenth fuse unit 916 is connected to the Q terminal of the eighteenth D flip-flop 621 and the output terminal of the fifteenth fuse unit 915, respectively, to receive the signal BIT. <15> and TR <14> The output terminal of the sixteenth fuse unit 916 outputs signal TR. <15> When SoftProg is high and Trim is low, the output signal level of each fuse unit is consistent with the BIT signal input to each fuse unit; when SoftProg is low and Trim is high, the output signal level of the fuse unit is the state after the fuse has solidified.

[0042] like Figure 10 As shown, in some embodiments, each fuse unit includes: a sixth AND gate 921, a current NMOS transistor 917, a fifth current source 918, a fuse 919, an eleventh inverter 922, and a signal selector 920. The second input terminal of the sixth AND gate 921 forms the first input terminal of the fuse unit, which is connected to the output terminal of the write instruction module 304 for receiving the signal Trim. The output terminal of the sixth AND gate 921 is connected to the gate of the current NMOS transistor 917. The source and substrate of the current NMOS transistor 917 are connected to ground. The drain of the current NMOS transistor 917, the positive terminal of the fifth current source 918, the input terminal of the eleventh inverter 922, and one end of the fuse 919 are interconnected to form a third node FUSEB. The other end of the fuse 919 is connected to the step-down chip 101. The input terminal IN of the fifth current source 918 is connected to ground. The output terminal of the eleventh inverter 922 is connected to the first input terminal of the signal selector 920 for outputting the signal FUSE. The second input terminal of the signal selector 920 and the first input terminal of the sixth AND gate 921 together form the third input terminal of the fuse unit. They are all connected to the Q terminal of the D flip-flop corresponding to the fuse unit to receive the BIT signal. The third input terminal of the signal selector 920 forms the second input terminal of the fuse unit, which is connected to the second output terminal of the test mode selection module 303 to receive the signal SoftProg. The signal SoftProg is used to control the selection of one of the signals FUSE and BIT. The output terminal of the signal selector 920 forms the output terminal of the fuse unit to output the TR signal. When both Trim and BIT are high, the current-carrying NMOS transistor 917 is turned on. A current path exists from the input terminal IN through fuse 919, NMOS transistor 917, and ground. Since both fuse 919 and NMOS transistor 917 are low-impedance devices at this time, this path carries a large current (commonly 60mA in designs). The heat generated by this current in fuse 919 melts it, making it high-impedance, and FUSEB is pulled down to a low level. When Trim is high and BIT is low, NMOS transistor 917 is open, fuse 919 is not blown, and FUSEB is still pulled up to a high level by fuse 919. In other words, when Trim is high, the level state of BIT is fixed in the FUSE signal.

[0043] The circuit for adjusting the electrical parameters of a chip using multiplexed pins in this embodiment of the invention achieves test mode selection, encoding verification, and writing functions by multiplexing the enable pin EN and adding signals with different positive and negative levels and pulse widths to the EN pin. Since the EN pin is multiplexed, the chip can save two test adjustment pins, making the test peripheral simple and efficient and saving the use of peripheral components. At the same time, it can also reduce the chip packaging cost.

[0044] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of the invention. Various variations can be made to the above embodiments of the present invention. That is, all simple and equivalent changes and modifications made based on the claims and description of this invention fall within the protection scope of the claims of this patent. All aspects not described in detail in this invention are conventional technical content.

Claims

1. A circuit for adjusting chip electrical parameters using multiplexed pins, characterized in that, The system includes a step-down chip, an input capacitor, an input power supply, a load, an output capacitor, and a control terminal. The step-down chip includes a trimming code generation module, a linear step-down module, an input terminal, an output terminal, a ground terminal, and an enable terminal. The input terminal of the step-down chip is connected to the positive terminal of the input capacitor and the positive terminal of the input power supply. The output terminal of the step-down chip is connected to the positive terminal of the output capacitor and one end of the load. The ground terminal is connected to ground. The enable terminal of the step-down chip is connected to the control terminal, which is used to send an enable control signal to the enable terminal of the step-down chip. The negative terminals of the input power supply, the input capacitor, the output capacitor, and the other end of the load are all connected to ground. The tuning code generation module includes an enable module, a single-wire decoding module, a test mode selection module, a write instruction module, a verification module, a one-time programming module, a verification NMOS transistor, and a verification resistor. The input terminals of the enable module, the test mode selection module, the single-wire decoding module, and the second input terminal of the write instruction module are all connected to the enable terminal of the buck converter chip. The output terminal of the enable module is connected to the linear buck converter module. The output terminal of the single-wire decoding module is connected to the first input terminal of the verification module and the first input terminal of the one-time programming module, respectively. The first output terminal of the test mode selection module... The first input terminal of the test mode selection module is connected to the second input terminal of the verification module; the second output terminal of the test mode selection module is connected to the second input terminal of the primary programming module, and the third input terminal of the test mode selection module is connected to the first input terminal of the write instruction module; the output terminal of the write instruction module is connected to the third input terminal of the primary programming module; the primary programming module has four output terminals respectively connected to the linear buck module; the source and substrate of the verification NMOS transistor are both connected to ground, the drain of the verification NMOS transistor is connected to one end of the verification resistor, and the other end of the verification resistor is connected to the input terminal of the buck chip.

2. The circuit for adjusting chip electrical parameters using multiplexed pins according to claim 1, characterized in that, The linear buck module includes a reference voltage generation module, an error amplification module, a current limiting module, a buck PMOS transistor, a lower proportional resistor, and an upper proportional resistor. The input terminal of the reference voltage generation module is connected to the second output terminal of the primary programming module, and the output terminal of the reference voltage generation module is connected to the inverting input terminal of the error amplification module. The first terminal of the upper proportional resistor is connected to the output terminal, and the second terminal is connected to the first terminal of the lower proportional resistor, which is connected to ground. The non-inverting input terminal of the error amplification module is connected to both the second terminal of the upper proportional resistor and the first terminal of the lower proportional resistor. The enable input terminal of the error amplification module is connected to the output terminal of the enable module. The output terminal of the error amplification module is connected to the input terminal of the current limiting module. The output terminal of the current limiting module is connected to the gate of the buck PMOS transistor. The source and substrate of the buck PMOS transistor are connected to the input terminal of the buck chip, and the drain of the buck PMOS transistor is connected to the output terminal of the buck chip.

3. The circuit for adjusting chip electrical parameters using multiplexed pins according to claim 1, characterized in that, The test mode selection module includes an input detection NMOS transistor, a first current source, a first Schmitt trigger, a first D flip-flop, a second D flip-flop, a first AND gate, a second AND gate, and a third AND gate. The source of the input detection NMOS transistor is connected to the enable terminal, the gate and substrate of the input detection NMOS transistor are connected to ground, the drain of the input detection NMOS transistor is connected to the negative terminal of the first current source and the input terminal of the first Schmitt trigger, the positive terminal of the first current source is connected to the input terminal of the buck converter chip, the output terminal of the first Schmitt trigger is connected to the CLK terminal of the first D flip-flop, and the Q terminal of the first D flip-flop is connected to the second input terminals of the first AND gate and the second input terminals of the third AND gate, respectively. The D terminal of a first D flip-flop is connected to the QN terminal of a second D flip-flop to form a first node. The first node is connected to the CLK terminal of a second D flip-flop and the second input terminal of a second AND gate. The Q terminal of the second D flip-flop is connected to the first input terminal of a second AND gate and the first input terminal of a third AND gate. The D terminal and the QN terminal of the second D flip-flop are interconnected to form a second node, which is connected to the first input terminal of a first AND gate. The output terminal of the first AND gate forms the first output terminal of the test mode selection module. The output terminal of the second AND gate forms the second output terminal of the test mode selection module. The output terminal of the third AND gate forms the third output terminal of the test mode selection module.

4. The circuit for adjusting chip electrical parameters using multiplexed pins according to claim 1, characterized in that, The single-wire decoding module may include a first inverter, a first pull-down NMOS transistor, a second current source, a pulse width capacitor, a comparator, and three to eighteenth D flip-flops. The input terminal of the first inverter is connected to the enable terminal, and the output terminal of the first inverter is connected to the gate of the pull-down NMOS transistor and the CLK terminal of the three to eighteenth D flip-flops, respectively. The drain of the first pull-down NMOS transistor is connected to the negative terminal of the second current source, the positive terminal of the pulse width capacitor, and the positive input terminal of the comparator, respectively. The source of the first pull-down NMOS transistor is connected to ground. The positive terminal of the second current source is connected to... The input terminal of the step-down chip is connected to the negative terminal of the pulse capacitor; the negative input terminal of the comparator is connected to the internal reference voltage; the output terminal of the comparator is connected to the D terminal of the third D flip-flop; the third to the eighteenth D flip-flops are arranged sequentially, and for any one of the fourth to the seventeenth D flip-flops, the D terminal of the D flip-flop is connected to the Q terminal of the preceding D flip-flop, and the Q terminal of the D flip-flop is connected to the D terminal of the following D flip-flop; all the Q terminals of the third to the eighteenth D flip-flops together form the output terminal of the single-wire decoding module.

5. The circuit for adjusting chip electrical parameters using multiplexed pins according to claim 1, characterized in that, The write instruction module includes an input PMOS transistor, a third current source, a second Schmitt trigger, a second inverter, a debouncing filter, and a fourth AND gate. The source and substrate of the input PMOS transistor are connected to the enable terminal, the gate of the input PMOS transistor is connected to the input terminal of the buck converter, the drain of the input PMOS transistor is connected to the positive terminal of the third current source and the input terminal of the second Schmitt trigger, the negative terminal of the third current source is connected to ground, the output terminal of the second Schmitt trigger is connected to the input terminal of the second inverter, the output terminal of the second inverter is connected to the input terminal of the debouncing filter, the output terminal of the debouncing filter is connected to the first input terminal of the fourth AND gate, the second input terminal of the fourth AND gate is connected to the third output terminal of the test mode selection module, and the output terminal of the fourth AND gate forms the output terminal of the write instruction module.

6. The circuit for adjusting chip electrical parameters using multiplexed pins according to claim 1, characterized in that, The enable module includes a fourth current source, a second pull-down NMOS transistor, and a third Schmitt trigger. The gate of the second pull-down NMOS transistor is connected to the enable terminal, the source and substrate of the second pull-down NMOS transistor are connected to ground, the drain of the second pull-down NMOS transistor is connected to the negative terminal of the fourth current source and the input terminal of the third Schmitt trigger, respectively, and the output terminal of the third Schmitt trigger is formed as the output terminal of the enable module.

7. The circuit for adjusting chip electrical parameters using multiplexed pins according to claim 4, characterized in that, The verification module may include a fifth AND gate, first to fifth AND gates, and third to tenth inverters. The input of the third inverter is connected to the Q terminal of the fourth D flip-flop, the input of the fourth inverter is connected to the Q terminal of the sixth D flip-flop, the first input of the second AND gate is connected to the Q terminal of the third D flip-flop, the second input of the second AND gate is connected to the output of the third inverter, the third input of the second AND gate is connected to the Q terminal of the fifth D flip-flop, and the fourth input of the second AND gate is connected to the output of the fourth inverter. The input of the fifth inverter is connected to the eighth D flip-flop. The Q inputs of the flip-flops are connected to the Q inputs of the 10th D flip-flops. The first input of the third AND gate is connected to the Q input of the 7th D flip-flop. The second input of the third AND gate is connected to the output of the 5th inverter. The third input of the third AND gate is connected to the Q input of the 9th D flip-flop. The fourth input of the third AND gate is connected to the output of the 6th inverter. The input of the 7th inverter is connected to the Q input of the 11th D flip-flop. The input of the 8th inverter is connected to the Q input of the 13th D flip-flop. The first input of the fourth AND gate is connected to the output of the 7th inverter. The fourth AND gate's second input is connected to the Q terminal of the twelfth D flip-flop; its third input is connected to the output of the eighth inverter; and its fourth input is connected to the Q terminal of the fourteenth D flip-flop. The input of the ninth inverter is connected to the Q terminal of the fifteenth D flip-flop; the input of the tenth inverter is connected to the Q terminal of the seventeenth D flip-flop; the first input of the fifth AND gate is connected to the output of the ninth inverter; its second input is connected to the Q terminal of the sixteenth D flip-flop; and its third input is connected to the output of the tenth inverter. The fourth input of the fifth quad AND gate is connected to the Q terminal of the eighteenth D flip-flop; the first input of the first quad AND gate is connected to the output of the second quad AND gate, the second input of the first quad AND gate is connected to the output of the third quad AND gate, the third input of the first quad AND gate is connected to the output of the fourth quad AND gate, the fourth input of the first quad AND gate is connected to the output of the fifth quad AND gate; the output of the first quad AND gate is connected to the first input of the fifth binary AND gate, the second input of the fifth binary AND gate is connected to the first output of the test mode selection module, and the output of the fifth binary AND gate forms the output of the verification module.

8. The circuit for adjusting chip electrical parameters using multiplexed pins according to claim 4, characterized in that, The primary programming module includes a first fuse unit to a sixteenth fuse unit arranged in sequence. The first input terminals of the first fuse unit to the sixteenth fuse unit are all connected to the output terminal of the write instruction module. The second input terminals of the first fuse unit to the sixteenth fuse unit are all connected to the second output terminal of the test mode selection module. The third input terminal of the first fuse unit is connected to the Q terminal of the third D flip-flop. The output terminal of the first fuse unit forms the fourth output terminal of the primary programming module. The second fuse unit to the sixteenth fuse unit correspond one-to-one with the fourth D flip-flop to the eighteenth D flip-flop. For each of the second fuse unit to the sixteenth fuse unit, the third input terminal of the fuse unit is connected to the output terminal of the previous fuse unit and the Q terminal of the corresponding D flip-flop.

9. The circuit for adjusting chip electrical parameters using multiplexed pins according to claim 8, characterized in that, Each fuse unit includes a sixth AND gate, a current NMOS transistor, a fifth current source, a fuse, an eleventh inverter, and a signal selector. The second input of the sixth AND gate serves as the first input of the fuse unit. The output of the sixth AND gate is connected to the gate of the current NMOS transistor. The source and substrate of the current NMOS transistor are connected to ground. The drain of the current NMOS transistor, the positive terminal of the fifth current source, the input of the eleventh inverter, and one end of the fuse are interconnected. The other end of the fuse is connected to the input of the step-down chip. The negative terminal of the fifth current source is connected to ground. The output of the eleventh inverter is connected to the first input of the signal selector. The second input of the signal selector and the first input of the sixth AND gate together form the third input of the fuse unit. The third input of the signal selector serves as the second input of the fuse unit. The output of the signal selector serves as the output of the fuse unit.

Images