Data management method, device and readable storage medium of memory

Abstract

The present application relates to the technical field of data management, and particularly relates to a data management method and device of a memory and a readable storage medium. The method comprises the following steps: when a micro-processing core loads an instruction from the memory, determining a target address corresponding to a target instruction loaded by the micro-processing core; loading the target instruction based on the target address and performing a verification action on the target instruction; when the target instruction passes the verification, delivering the target instruction to the micro-processing core; and when the target instruction fails to pass the verification, delivering an interrupt signal corresponding to the target instruction to the micro-processing core. The microprocessor can be prevented from executing tampered or overwritten code, and the execution quality and effectiveness of the program can be ensured. Furthermore, when debugging the program, the location where the erroneous target instruction is stored can be located. That is, when an error or exception occurs during program execution, the tampered or overwritten code can be found through the interrupt signal.

Description

Technical Field

[0001] This invention relates to the field of data management technology, and in particular to a data management method, device, and readable storage medium for a memory. Background Technology

[0002] An embedded MCU (Microcontroller Unit) is an integrated circuit chip widely used in embedded systems. MCUs integrate a microprocessor core and memory, making them suitable for various applications requiring control and processing.

[0003] In embedded MCUs, because the microprocessor core has no access restrictions on memory write and read operations and does not provide memory access monitoring functions, debugging memory overwriting issues is quite difficult. For example, if a piece of infrequently executed code is overwritten or modified, and the program only executes this infrequently executed code after a long period of time, errors or exceptions may occur during code execution, making it very difficult to locate the overwritten or modified code.

[0004] The above content is only used to help understand the technical solution of the present invention and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main objective of this invention is to provide a data management method for memory, which aims to solve the problem that it is difficult to find the overwritten or tampered code when an error or exception occurs during code execution.

[0006] To achieve the above objectives, the present invention provides a data management method for a memory, the data management method for the memory comprising the following steps:

[0007] When the microprocessor core loads instructions from memory, it determines the target address corresponding to the target instruction loaded by the microprocessor core;

[0008] Based on the target address, load the target instruction and perform a verification action on the target instruction;

[0009] When the target instruction passes the verification, the target instruction is transmitted to the microprocessor core;

[0010] When the target instruction fails the verification, the interrupt signal corresponding to the target instruction is transmitted to the microprocessor core.

[0011] Optionally, after the step of transferring the target instruction to the microprocessor core when the target instruction passes verification, the method further includes:

[0012] When the microprocessor core executes the target instruction and writes data to the memory, the data to be written by the microprocessor core is loaded.

[0013] A verification code is attached to the data to be written;

[0014] The data to be written, carrying a verification code, is written into the memory.

[0015] Optionally, before the step of loading the target instruction based on the target address and performing a verification operation on the target instruction, the method further includes:

[0016] When the microprocessor core loads instructions from the memory, it determines the code segment to which the loaded instructions belong;

[0017] Read the read permission identifier of the code segment to which the loading instruction belongs;

[0018] Based on the read permission identifier, determine whether the loading instruction has the permission to load the target instruction;

[0019] If so, execute the steps of loading the target instruction based on the target address and performing a verification action on the target instruction;

[0020] If not, send the interrupt signal corresponding to the load instruction to the microprocessor core.

[0021] Optionally, the step of loading the data to be written by the microprocessor core when writing data to the memory after the microprocessor core executes the target instruction includes:

[0022] When the microprocessor core writes data to the memory, it determines the target write address corresponding to the write instruction and the code segment to which the write instruction belongs.

[0023] Read the write permission identifier of the code segment to which the write instruction belongs;

[0024] Based on the write permission identifier, determine whether the write instruction has the permission to write data to the target write address;

[0025] If so, load the data to be written from the microprocessor core;

[0026] If not, send the interrupt signal corresponding to the write instruction to the microprocessor core.

[0027] Optionally, before the step of determining the target address corresponding to the target instruction loaded by the microprocessor core when loading instructions from memory, the method further includes:

[0028] When the program starts, the permission configuration code in the program is read;

[0029] The permission configuration code is executed to configure the registers, thereby configuring the read and write permissions for each code segment in the program.

[0030] Optionally, the step of attaching a verification code to the data to be written includes:

[0031] Generate a cyclic redundancy check code based on the data to be written for each management unit length;

[0032] At each interval of the length of the management unit, the cyclic redundancy check code is appended to the data to be written.

[0033] Optionally, the step of loading the target instruction based on the target address and performing a verification operation on the target instruction includes:

[0034] Based on the target address, load the management unit where the target instruction is located;

[0035] Read the verification code of the management unit;

[0036] The verification action is performed based on the verification code.

[0037] Optionally, the step of performing the verification action based on the verification code includes:

[0038] Call the standard verification code corresponding to the management unit;

[0039] When the verification code of the management unit matches the standard verification code, the target instruction is deemed to have passed verification.

[0040] When the verification code of the management unit does not match the standard verification code, it is determined that the target instruction has failed the verification.

[0041] In addition, to achieve the above objectives, the present invention also provides a memory data management device, the memory data management device including a memory, a processor, and a memory data management program stored on the memory and executable on the processor, wherein when the memory data management program is executed by the processor, it implements the steps of the memory data management method as described above.

[0042] In addition, to achieve the above objectives, the present invention also provides a computer-readable storage medium storing a memory data management program thereon, which, when executed by a processor, implements the steps of the memory data management method as described above.

[0043] This invention provides a data management method for memory. When a microprocessor loads instructions from memory, it loads and verifies the target instruction based on its target address. Verification of the target instruction detects whether it has been tampered with. Only if the verification passes is the target instruction passed to the microprocessor for execution; if the verification fails, an interrupt signal corresponding to the target instruction is sent to the microprocessor to interrupt program execution and output the location information of the target instruction. This aims to prevent the microprocessor from continuing to execute tampered or overwritten code, ensuring the quality and effectiveness of program execution. Furthermore, it allows for the location of the erroneous target instruction during program debugging. In other words, when an error or exception occurs during program execution, the tampered or overwritten code can be located through the interrupt signal. Attached Figure Description

[0044] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present invention and, together with the description, serve to explain the principles of the invention. To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0045] Figure 1 This is a schematic diagram of the hardware operating environment of the data management device for the memory involved in the embodiments of the present invention;

[0046] Figure 2 This is a flowchart illustrating the first embodiment of the data management method for the memory of the present invention;

[0047] Figure 3 This is a flowchart illustrating a second embodiment of the data management method for the memory of the present invention.

[0048] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0049] This application's memory data management method determines the target address corresponding to the target instruction loaded by the microprocessor core when loading instructions from memory; loads the target instruction based on the target address and performs a verification operation on the target instruction; if the target instruction passes verification, it is transmitted to the microprocessor core; if the target instruction fails verification, an interrupt signal corresponding to the target instruction is transmitted to the microprocessor core. This can prevent the microprocessor from executing tampered or overwritten code, ensuring the execution quality and effectiveness of the program. Furthermore, it allows for the location of the erroneous target instruction during program debugging. That is, when an error or exception occurs during program execution, the tampered or overwritten code can be found through the interrupt signal.

[0050] To better understand the above technical solutions, exemplary embodiments of this disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0051] As one implementation scheme, Figure 1 This is a schematic diagram of the hardware operating environment of the data management device for the memory involved in the embodiments of the present invention.

[0052] like Figure 1 As shown, the data management device for this memory may include: a processor 101, such as a central processing unit (CPU), a memory 102, and a communication bus 103. The memory 102 may be a high-speed random access memory (RAM) or a stable non-volatile memory (NVM), such as a disk drive. Optionally, the memory 102 may also be a storage device independent of the aforementioned processor 101. The communication bus 103 is used to enable communication between these components.

[0053] Those skilled in the art will understand that Figure 1 The structure shown does not constitute a limitation on the data management device of the memory and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0054] like Figure 1 As shown, the memory 102, which is a computer-readable storage medium, may include an operating system, a data storage module, a network communication module, a user interface module, and a data management program for the memory.

[0055] exist Figure 1 In the data management device of the memory shown, the processor 101 and the memory 102 can be disposed in the data management device of the memory. The data management device of the memory calls the data management program of the memory stored in the memory 102 through the processor 101 and performs the following operations:

[0056] When the microprocessor core loads instructions from memory, it determines the target address corresponding to the target instruction loaded by the microprocessor core;

[0057] Based on the target address, load the target instruction and perform a verification action on the target instruction;

[0058] When the target instruction passes the verification, the target instruction is transmitted to the microprocessor core;

[0059] When the target instruction fails the verification, the interrupt signal corresponding to the target instruction is transmitted to the microprocessor core.

[0060] In one embodiment, the processor 101 can be used to invoke a memory data management program stored in the memory 102 and perform the following operations:

[0061] When the microprocessor core executes the target instruction and writes data to the memory, the data to be written by the microprocessor core is loaded.

[0062] A verification code is attached to the data to be written;

[0063] The data to be written, carrying a verification code, is written into the memory.

[0064] In one embodiment, the processor 101 can be used to invoke a memory data management program stored in the memory 102 and perform the following operations:

[0065] When the microprocessor core loads instructions from the memory, it determines the code segment to which the loaded instructions belong;

[0066] Read the read permission identifier of the code segment to which the loading instruction belongs;

[0067] Based on the read permission identifier, determine whether the loading instruction has the permission to load the target instruction;

[0068] If so, execute the steps of loading the target instruction based on the target address and performing a verification action on the target instruction;

[0069] If not, send the interrupt signal corresponding to the load instruction to the microprocessor core.

[0070] In one embodiment, the processor 101 can be used to invoke a memory data management program stored in the memory 102 and perform the following operations:

[0071] When the microprocessor core writes data to the memory, it determines the target write address corresponding to the write instruction and the code segment to which the write instruction belongs.

[0072] Read the write permission identifier of the code segment to which the write instruction belongs;

[0073] Based on the write permission identifier, determine whether the write instruction has the permission to write data to the target write address;

[0074] If so, load the data to be written from the microprocessor core;

[0075] If not, send the interrupt signal corresponding to the write instruction to the microprocessor core.

[0076] In one embodiment, the processor 101 can be used to invoke a memory data management program stored in the memory 102 and perform the following operations:

[0077] When the program starts, the permission configuration code in the program is read;

[0078] The permission configuration code is executed to configure the registers, thereby configuring the read and write permissions for each code segment in the program.

[0079] In one embodiment, the processor 101 can be used to invoke a memory data management program stored in the memory 102 and perform the following operations:

[0080] Generate a cyclic redundancy check code based on the data to be written for each management unit length;

[0081] At each interval of the length of the management unit, the cyclic redundancy check code is appended to the data to be written.

[0082] In one embodiment, the processor 101 can be used to invoke a memory data management program stored in the memory 102 and perform the following operations:

[0083] Based on the target address, load the management unit where the target instruction is located;

[0084] Read the verification code of the management unit;

[0085] The verification action is performed based on the verification code.

[0086] In one embodiment, the processor 101 can be used to invoke a memory data management program stored in the memory 102 and perform the following operations:

[0087] Call the standard verification code corresponding to the management unit;

[0088] When the verification code of the management unit matches the standard verification code, the target instruction is deemed to have passed verification.

[0089] When the verification code of the management unit does not match the standard verification code, it is determined that the target instruction has failed the verification.

[0090] Based on the hardware architecture of the data management device of the memory described above, an embodiment of the data management method of the memory of the present invention is proposed.

[0091] Reference Figure 2 In the first embodiment, the data management method for the memory includes the following steps:

[0092] Step S100: When the microprocessor core loads an instruction from memory, determine the target address corresponding to the target instruction loaded by the microprocessor core.

[0093] In this embodiment, in the embedded MCU, when the microprocessor core loads instructions from memory, the target address corresponding to the target instruction loaded by the microprocessor core is determined based on the memory address pointed to by the instruction load instruction sent by the microprocessor core. It should be noted that the instruction load instruction is equivalent to an instruction call request, that is, requesting the memory to call the target instruction. It can be understood that the instruction load instruction is the instruction corresponding to one function module calling another function module, or one code segment calling another code segment during program execution. During program execution, the program can only continue running if the instruction is successfully called; if the call fails, the program will encounter a runtime error.

[0094] Step S200: Based on the target address, load the target instruction and perform a verification operation on the target instruction.

[0095] In this embodiment, after determining the target address corresponding to the target instruction, the target instruction is loaded into the memory based on the target address. Then, a verification operation is performed on the target instruction to determine whether the target instruction has been tampered with, or whether the code segment calling the target instruction has the authority to call the target instruction. Optionally, determining whether the target instruction has been tampered with can be done using a checksum; determining whether the code segment calling the target instruction has the authority to call the target instruction can be done using an access permission identifier.

[0096] Furthermore, it is determined whether the target instruction to be loaded has been tampered with. This can be done by first loading the management unit containing the target instruction based on the target address and reading the checksum of the management unit; then, performing the verification action based on the checksum. It should be noted that here, a management unit refers to a unit that divides the data stored in memory into sections of a certain length. For example, every 128 bytes of data constitutes a data management unit.

[0097] Each management unit is associated with a checksum. By reading the checksum, it can be determined whether the data in that management unit has been tampered with or overwritten, ensuring the integrity of the target instructions called by the microprocessor and thus preventing erroneous execution or program crashes due to data anomalies.

[0098] Optionally, the verification action is performed based on the verification code by calling the standard checksum corresponding to the management unit; when the checksum of the management unit matches the standard checksum, the target instruction is deemed to have passed verification; when the checksum of the management unit does not match the standard checksum, the target instruction is deemed to have failed verification.

[0099] As an optional implementation, CRC (Cyclic Redundancy Check) verification is used to determine whether the management unit corresponding to the target instruction has been tampered with or overwritten. Specifically, the CRC standard checksum corresponding to the management unit is called, and then an XOR operation is performed between the standard checksum and the CRC checksum of the loaded management unit to verify the management unit, i.e., to verify the target instruction. It can be understood that based on the result of the XOR operation, it can be determined whether the CRC checksum of the loaded management unit matches the standard checksum, thereby determining whether the data of the loaded management unit has been tampered with or overwritten. It should be noted that when the data of each management unit is written to memory, a CRC checksum is calculated, appended to the management unit, and then written to memory. This CRC checksum is stored as a standard checksum associated with the identifier of the management unit to verify whether the data of the management unit has been tampered with or overwritten.

[0100] By calling the standard checksum corresponding to the management unit, the correct checksum can be used for verification. If the checksum carried by the management unit matches the standard checksum (i.e., a match), it can be determined that the target instruction has not been tampered with or corrupted. A successful verification means that the integrity and correctness of the target instruction have been verified, and it can be executed correctly. If the checksum stored in the management unit does not match the standard checksum (i.e., a mismatch), it is determined that the target instruction has been tampered with or corrupted. A failed verification means that the integrity and correctness of the target instruction have been compromised, and it cannot be executed correctly.

[0101] The status of the target instruction is determined by whether the check code matches. This is done to further ensure the reliability and correctness of the loaded target instruction, prevent erroneous execution of the program, and prevent unauthorized operations.

[0102] Step S300: When the target instruction passes the verification, the target instruction is transmitted to the microprocessor core.

[0103] In this embodiment, after the target instruction is verified and passes the verification, the target instruction is passed to the microprocessor core for execution.

[0104] Furthermore, when the microprocessor core executes the target instruction and writes data to the memory, it loads the data to be written from the microprocessor core; then, it first attaches a checksum to the data to be written; and then writes the data to be written carrying the checksum into the memory.

[0105] After the microprocessor executes the target instruction, the microprocessor core may generate data that needs to be written to memory. This data includes, but is not limited to, execution results, intermediate calculation results, or other data that needs to be persisted. When writing data to memory, a checksum is appended to the data to ensure that the integrity of the data can be verified when it is read. The checksum is a verification value calculated based on the data to be written. By appending the checksum, verification can be performed after the data is written to memory, ensuring that no errors or tampering have occurred during the writing process.

[0106] The purpose of this is to prevent data tampering, corruption, or errors by adding a checksum to the data, enabling verification when the data is read from memory. This ensures the stability and reliability of the system and allows for the location of erroneous data when program errors occur. It also provides a mechanism to detect and correct potential data-related problems, thereby enhancing program reliability.

[0107] Optionally, a Cyclic Redundancy Check (CRC) code is generated based on the data to be written for each management unit length; then, the CRC code is appended to the data to be written at intervals of the management unit length. It should be noted that CRC is a checksum generated from the data to be written, used to detect errors or corruption during data transmission. A fixed-length CRC checksum can be obtained by calculating the data to be written using the CRC algorithm. Based on the management unit length, the data to be written is divided into multiple fixed-length management units, and the generated CRC checksum is appended to the corresponding data to be written between each management unit.

[0108] Because CRC checksums have low computational complexity and strong error detection capabilities, by appending a CRC checksum to the data to be written, errors or corruption that occur during transmission or storage can be detected, and these errors can be used to detect and correct them. The purpose of this is to enhance the verification of data integrity and accuracy, and to locate erroneous data.

[0109] Step S400: When the target instruction fails the verification, the interrupt signal corresponding to the target instruction is transmitted to the microprocessor core.

[0110] In this embodiment, when a target instruction to be loaded by the microprocessor fails verification, the target instruction is not passed to the microprocessor. Instead, an interrupt signal corresponding to the target instruction is passed to the microprocessor. This prevents the microprocessor from executing a tampered, overwritten, or erroneous target instruction, thus avoiding program crashes. The interrupt signal corresponding to the target instruction includes the address information of the target instruction and / or information about the code segment where the target instruction is located. This is done to improve the efficiency of locating erroneous instructions.

[0111] For example, assume the embedded MCU is an SM32 microcontroller. During program execution, suppose the microprocessor needs to invoke a timing instruction. At this time, the microprocessor core sends the load instruction corresponding to the timing instruction to the DMA (Direct Memory Access). The DMA determines the target address in memory corresponding to the timing instruction based on the load instruction. Assume the target address points to the first instruction at the first address in memory.

[0112] Assuming the management unit (MTU) is 128 bytes long and the timing instruction is 4 bytes long, the DMA loads the data of the MTU specified in the timing instruction from the first address of memory; that is, it loads all 128 bytes of data into the DMA. Then, it calls the CRC checksum corresponding to the MTU and obtains the CRC checksum from the loaded 128 bytes of data. A bitwise XOR operation is then performed between the CRC checksum and the obtained CRC checksum. If the XOR result is 1, the timing instruction is considered faulty. An interrupt signal corresponding to the timing instruction is then sent to the microprocessor. Upon receiving the interrupt signal, the microprocessor stops program execution and outputs a timing instruction call error message.

[0113] In the technical solution provided in this embodiment, when the microprocessor loads instructions from memory, it loads and verifies the target instruction based on its target address. This verification process detects whether the target instruction has been tampered with. Only when the verification passes is the target instruction passed to the microprocessor for execution; if the verification fails, an interrupt signal corresponding to the target instruction is sent to the microprocessor to interrupt program execution and output the location information of the target instruction. This is done to prevent the microprocessor from continuing to execute tampered or overwritten code, ensuring the quality and effectiveness of program execution. Furthermore, it allows for the location of the erroneous target instruction during program debugging. In other words, when an error or exception occurs during program execution, the tampered or overwritten code can be located through the interrupt signal.

[0114] Reference Figure 3 Based on the above embodiments, in the second embodiment, before the steps of loading the target instruction based on the target address and performing a verification action on the target instruction, the method further includes:

[0115] Step S500: When the microprocessor core loads instructions from the memory, determine the code segment to which the loaded instructions belong;

[0116] Step S600: Read the read permission identifier of the code segment to which the loading instruction belongs;

[0117] Step S700: Based on the read permission identifier, determine whether the loading instruction has the permission to load the target instruction;

[0118] Step S710: If yes, execute the step of loading the target instruction based on the target address and performing a verification operation on the target instruction;

[0119] Step S720: If not, send the interrupt signal corresponding to the load instruction to the microprocessor core.

[0120] In this embodiment, before performing verification on the target instruction, it is first determined whether the loading instruction to be loaded has the permission to call the target instruction. Specifically, the code segment to which the loading instruction belongs is first determined, and then the permission identifier of that code segment is read. Then, based on the permission identifier of the code segment, it is determined whether the loading instruction has the permission to load the target instruction. It can be understood that each code segment of the program is attached with a permission identifier for permission verification, which includes both read permission identifiers and write permission identifiers. When the loading instruction has the permission to load the target instruction, the steps of loading the target instruction based on the target address and performing verification on the target instruction are executed; when the loading instruction does not have the permission to load the target instruction, an interrupt signal corresponding to the loading instruction is sent to the microprocessor core to cause the processor to interrupt the program execution and output the location information of the code segment that does not have the permission to call the target instruction.

[0121] Furthermore, when the microprocessor writes data generated after executing the target instruction to the memory, it determines the target write address corresponding to the write instruction and the code segment to which the write instruction belongs. Then, it reads the write permission identifier of the code segment to which the write instruction belongs and, based on the write permission identifier, determines whether the write instruction has the permission to write data to the target write address. If yes, it loads the data to be written from the microprocessor core. If no, it sends an interrupt signal corresponding to the write instruction to the microprocessor core.

[0122] In this embodiment, each code segment has access restrictions for write operations to the memory. The same code segment can have write permissions to different memory addresses; that is, the instructions of that code segment can perform data write operations to multiple target write addresses in the memory. For the same write address, multiple code segments can have write permissions to that write address.

[0123] By determining the target write address and the code segment corresponding to the write instruction, write permissions for the write instruction are obtained, and the target location of the data to be written is determined. Here, the write permission identifier is a marker indicating the write permissions of the code segment. Based on the write permission identifier, it is determined whether the write instruction is allowed to execute. If the write instruction has write permissions for the target write address, the data to be written is loaded into the DMA. If the write instruction does not have write permissions for the target write address, an interrupt signal corresponding to the write instruction is sent to the microprocessor core, interrupting program execution and ensuring program stability. It should be noted that the interrupt signal corresponding to the write instruction includes the write instruction identifier and the target write address. Therefore, after a program interruption, during program debugging, the erroneous write instruction and the target write address can be located based on the interrupt signal.

[0124] Furthermore, through permission verification and access control, only write commands with write permissions can write data to the specified target address, thereby reducing unauthorized access and potential security threats. For unauthorized write operations, execution is aborted via an interrupt signal, improving program stability.

[0125] Furthermore, before the microprocessor loads instructions from memory, a permission configuration step is required. Specifically, at program startup, permission configuration code in the program is read; the permission configuration code is executed to configure registers, thereby configuring the read and write permissions of each code segment in the program. It should be noted that the permission configuration code here refers to instructions or configuration information used to configure the read and write permissions of each code segment in the program.

[0126] The permission configuration code configures registers to set read and write permissions for various code segments within the program. This allows for restrictions on read and write permissions for each code segment.

[0127] By configuring permissions for code segments, you can ensure that program code segments can only perform read and write operations on memory when they have the correct permissions. If a code segment in the program lacks read or write permissions, executing the corresponding instruction will trigger an interrupt or exception, thus preventing unauthorized access. The purpose of this is to improve program stability and prevent malicious code or erroneous operations from damaging the system. Furthermore, permission configuration also restricts access between different code segments, enhancing program isolation and security.

[0128] In the technical solution provided in this embodiment, the access permissions of the code segment to which the load instruction or write instruction belongs are determined, thereby determining whether the load instruction or write instruction has read permission for the target instruction or write permission for the target address. When the load instruction or write instruction does not have the corresponding access permissions, an interrupt signal corresponding to the load instruction or write instruction is sent to the microprocessor core to interrupt program execution and ensure program stability. Through permission verification and access control, unauthorized access and potential security threats can be reduced. For instructions without the corresponding permissions, program execution is terminated through an interrupt signal, protecting system stability. Furthermore, since the interrupt signal includes instruction information and location information that caused the program interruption, the efficiency of locating the instruction or data causing the program interruption during program debugging is also improved.

[0129] Furthermore, those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program includes program instructions and can be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the data management device of the memory to implement the process steps of the embodiments of the above methods.

[0130] Therefore, the present invention also provides a computer-readable storage medium storing a memory data management program, which, when executed by a processor, implements the various steps of the memory data management method described in the above embodiments.

[0131] The computer-readable storage medium can be any computer-readable storage medium capable of storing program code, such as a USB flash drive, portable hard drive, read-only memory (ROM), magnetic disk, or optical disk.

[0132] It should be noted that, since the storage medium provided in the embodiments of this application is the storage medium used to implement the methods of the embodiments of this application, those skilled in the art can understand the specific structure and variations of the storage medium based on the methods described in the embodiments of this application, and therefore will not be repeated here. All storage media used in the methods of the embodiments of this application fall within the scope of protection of this application.

[0133] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0134] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0135] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0136] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0137] It should be noted that any reference signs placed between parentheses in the claims should not be construed as limiting the claims. The word "comprising" does not exclude the presence of components or steps not listed in the claims. The word "a" or "an" preceding a component does not exclude the presence of a plurality of such components. The invention can be implemented by means of hardware comprising several different components and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, third, etc., does not indicate any order. These words can be interpreted as names.

[0138] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0139] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A data management method for a memory, characterized in that, The data management method for the memory includes the following steps: When the microprocessor core loads instructions from memory, it determines the target address corresponding to the target instruction loaded by the microprocessor core; Based on the target address, load the target instruction and perform a verification action on the target instruction; When the target instruction passes the verification, the target instruction is transmitted to the microprocessor core; When the target instruction fails the verification, the interrupt signal corresponding to the target instruction is transmitted to the microprocessor core; After the step of transmitting the target instruction to the microprocessor core when the target instruction passes verification, the method further includes: When the microprocessor core executes the target instruction and writes data to the memory, the data to be written by the microprocessor core is loaded. A verification code is attached to the data to be written; Write the data to be written, carrying the verification code, into the memory; Before the step of loading the target instruction based on the target address and performing a verification action on the target instruction, the method further includes: When the microprocessor core loads instructions from the memory, it determines the code segment to which the loaded instructions belong; Read the read permission identifier of the code segment to which the loading instruction belongs; Based on the read permission identifier, determine whether the loading instruction has the permission to load the target instruction; If so, execute the steps of loading the target instruction based on the target address and performing a verification action on the target instruction; If not, send the interrupt signal corresponding to the loading instruction to the microprocessor core; When the microprocessor core executes the target instruction and writes data to the memory, the step of loading the data to be written by the microprocessor core includes: When the microprocessor core writes data to the memory, it determines the target write address corresponding to the write instruction and the code segment to which the write instruction belongs. Read the write permission identifier of the code segment to which the write instruction belongs; Based on the write permission identifier, determine whether the write instruction has the permission to write data to the target write address; If so, load the data to be written from the microprocessor core; If not, send the interrupt signal corresponding to the write instruction to the microprocessor core.

2. The data management method for a memory as described in claim 1, characterized in that, Before the step of determining the target address corresponding to the target instruction loaded by the microprocessor core when loading instructions from memory, the method further includes: When the program starts, the permission configuration code in the program is read; The permission configuration code is executed to configure the registers, thereby configuring the read and write permissions for each code segment in the program.

3. The data management method for a memory as described in claim 1, characterized in that, The step of attaching a verification code to the data to be written includes: Generate a cyclic redundancy check code based on the data to be written for each management unit length; At each interval of the length of the management unit, the cyclic redundancy check code is appended to the data to be written.

4. The data management method for a memory as described in claim 1, characterized in that, The steps of loading the target instruction based on the target address and performing a verification action on the target instruction include: Based on the target address, load the management unit where the target instruction is located; Read the verification code of the management unit; The verification action is performed based on the verification code.

5. The data management method for a memory as described in claim 4, characterized in that, The step of performing the verification action based on the verification code includes: Call the standard verification code corresponding to the management unit; When the verification code of the management unit matches the standard verification code, the target instruction is deemed to have passed verification. When the verification code of the management unit does not match the standard verification code, it is determined that the target instruction has failed the verification.

6. A data management device for a memory, characterized in that, The data management device for the memory includes: a memory, a processor, and a memory data management program stored on the memory and executable on the processor, wherein the memory data management program is configured to implement the steps of the memory data management method as described in any one of claims 1 to 5.

7. A readable storage medium, characterized in that, The readable storage medium stores a memory data management program, which, when executed by a processor, implements the steps of the memory data management method as described in any one of claims 1 to 5.

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