A Three-Stage Pipeline BCH Decoding Method for High Bit Error Rate Memory

Abstract

This invention discloses a three-stage pipelined BCH decoding method for high bit error rate memories, belonging to the field of integrated circuit technology. This invention divides the decoder into three stages: a syndrome generation circuit, an error equation generation circuit, and a Chan's search circuit. The algebraic structure of the resulting error equation remains unchanged, while the decoding frequency of the entire decoder is increased several times over. This invention improves the decoding frequency and expands the range of systems the decoder can be applied to.

Description

Technical Field

[0001] This invention belongs to the field of BCH encoding and decoding circuit implementation technology in the field of memory and error correction coding, and specifically relates to a BCH decoding method with low latency and low resource consumption. Background Technology

[0002] Memory is often affected by random errors, such as single-event upset (SEU) and multiple-bit single-event upset (MBU). To deal with these soft errors, ECC algorithms are widely used, among which BCH code is widely used for soft error correction in memory, communication and embedded systems due to its excellent performance. MBU-resistant ECC algorithms are crucial for memory protection, taking into account the memory's resistance to single-event upsets, usually expressed as errors / bits*day. For large-capacity memory, algorithms such as BCH code are often used, but the improvement of error correction capability is accompanied by an increase in redundant bits, which affects storage space and cost. [1]

[0003] For large-capacity memories such as Nand flash, page table-level ECC error correction can provide good error correction results, but it comes with certain cost and performance considerations. In embedded products, especially MCU-level memory units, there are high requirements for the speed and parallelism of ECC encoding and decoding to ensure that the encoding and decoding process is completed within a limited clock cycle, thereby improving processor speed and pipeline utilization.

[0004] Since the introduction of Hamming codes in 1950, research on ECC algorithms has consistently focused on achieving high error correction performance, low resource consumption, and high error correction efficiency. High performance refers to low latency, high bandwidth, and multi-bit error correction; low resource consumption requires low power consumption and a small circuit area; and high error correction efficiency means correcting more data bits with fewer parity bits. For consumer embedded systems, especially for memories such as flash, SRAM, and ROM in MCUs, the requirements for low latency and low resource consumption are particularly sensitive.

[0005] For embedded memory devices that may experience multiple bit errors but have few error patterns, small storage size, critical storage content, are located close to the kernel, and require high memory access speed, the BCH parallelized encoding / decoding circuit can be considered as an ECC solution. After circuit optimization, this solution can achieve good latency and frequency performance within a controlled resource consumption range.

[0006] The BCH decoding method mainly includes three steps: generating the syndrome, generating the error equation, and solving the error equation using Chan's search. Currently, some teams have adopted a two-stage pipeline approach to optimize the BCH decoding circuit, which is beneficial for synthesizing circuits with better performance, power consumption, and size. Summary of the Invention

[0007] This invention proposes a three-stage pipelined BCH decoding method for high bit error rate memories, aiming to increase the BCH decoding frequency and reduce decoding delay. Unlike previous lookup table decoding methods and BM iteration methods, this invention is based on Peterson decoding theory. It can divide the decoder into three stages according to the specific decoding steps of a single-cycle Peterson decoder: a syndrome generation circuit, an error equation generation circuit, and a Chan search circuit. At this time, the algebraic structure of the resulting error equation remains unchanged. Due to the pipeline division, the decoding frequency of the entire decoder is increased several times.

[0008] The technical solution of the present invention is as follows:

[0009] A three-stage pipelined BCH decoding method for high bit error rate memories, characterized by the following specific steps:

[0010] 1) In the first-stage pipeline, the syndrome computation circuit receives the codeword polynomial r according to the m-th decoding cycle. m (x) Calculate the i-th syndrome S in the m-th decoding cycle. i，m (x), for a BCH code with an n-bit total codeword length, k-bit data bit length, and t-bit error correction, it is called an (n, k, t) BCH code, r m (x) and S i，m The formula for calculating (x) is as follows:

[0011]

[0012]

[0013] Where r j，m Let be the value of the j-th codeword received in the m-th decoding cycle, where a is the primitive element of the corresponding number field and can be considered a constant.

[0014] 2) Place S i，m (x) is stored in the first-stage pipeline register;

[0015] 3) In the second-stage pipeline, the m-th decoding cycle currently being performed by the system is also used as the reference value for the time dimension. The error equation generation circuit generates the equation based on the syndrome S obtained from the output of the previous pipeline. i，m-1 (x) (corresponding to the received codeword of the input system in the (m-1)th cycle), calculate the error equation δ m-1 (x), error equation δ m-1 (x) has the following form:

[0016]

[0017] Solve the error equation δ m-1 The coefficients δ of each term in (x)j，m-1 This allows you to index the location of the error, δ j，m-1 The value and S calculated in the previous step i，m-1 (x) is related, where v refers to the number of erroneous digits; the specific solution is δ. j.m-1 The formula is as follows:

[0018] S j+v，m-1 +δ 1，m-1 S j+v-1，m-1 +…+δ v-1，m-1 S j+1，m-1 +δ v，m-1 S j，m-1 =01≤j≤2t-v Equation (4)

[0019] 5) The error equation δ m-1 The coefficients of (x) are stored in the second-stage pipeline register;

[0020] 6) In the third-stage pipeline, the m-th decoding cycle currently being performed by the system is also used as the reference value for the time dimension. For the second-stage pipeline output error equation δ... m-2 (x) (corresponding to the received codeword of the input system in the (m-2)th cycle), this invention employs a Chien search circuit to solve the error equation. The Chien search circuit determines the location of the error by searching for zeros (roots of the polynomial) in a finite field. That is, by evaluating the value of each element in the finite field, it finds the element that makes the erroneous polynomial zero, thereby finding the location of the error. The specific steps include evaluating each element in the finite field and checking whether the result is zero. If the result is zero, it indicates that the element is a root of the erroneous polynomial, thus determining an error location. This process is repeated until all error locations are found.

[0021] The beneficial effects of this invention are as follows:

[0022] This invention employs a three-stage pipeline structure. Firstly, it protects the integrity of the algebraic structure, thereby ensuring the correct functioning of the decoder. Secondly, experiments have shown that the three-stage pipeline achieves a good balance between decoding cycle, decoding frequency, and circuit area. Combined with practical applications, this increases the decoding frequency and expands the range of systems the decoder can be used in. Attached Figure Description

[0023] Figure 1 A specific embodiment of the present invention is based on the overall hardware block diagram of a three-stage pipelined Peterson decoder;

[0024] Figure 2 A specific embodiment of the present invention includes a companion generation circuit;

[0025] Figure 3Specific embodiments of the present invention (44, 32) BCH decoder error equation generation circuit;

[0026] Figure 4 The verification equation sub-circuit of the Chien search circuit of the BCH decoder in specific embodiments of the present invention (44, 32);

[0027] Figure 5 The schematic diagram showing the comparison of latency and hardware resource usage of various BCH decoding methods in specific embodiments (44, 32) of the present invention. Detailed Implementation

[0028] The invention will now be illustrated by an implementation of a BCH decoder based on a Chan's search circuit for a (44, 32, 2) BCH code (n = 44, k = 32, t = 2).

[0029] The (44, 32, 2) BCH code has the following common characteristics of BCH codes:

[0030] 1. The number of data bits before encoding is k = 32, the total number of codeword bits after encoding is n = 44, and the number of check bits is nk = 12.

[0031] 2. The error correction capability of the (44, 32, 2) BCH code is 2, which can correct two random errors in a total of 44 bits. Since 26-1>44>25-1, its encoding and decoding operations occur in the Galois field GF(26). If m=6, then the length of the parity bit is mt=6x2=12.

[0032] The overall architecture of the Peterson decoder based on a three-stage pipeline is as follows: Figure 1 As shown, this invention introduces a pipeline structure between various sub-modules, which divides the critical path of the circuit without changing the algebraic structure, thereby improving the decoding frequency.

[0033] 1) In the first-stage pipeline, the syndrome computation circuit receives the codeword polynomial r according to the m-th decoding cycle. m (x) Calculate the i-th syndrome S in the m-th decoding cycle. i，m (x), for a BCH code with an n-bit total codeword length, k-bit data bit length, and t-bit error correction, it is called an (n, k, t) BCH code, r m (x) and S i，m The formula for calculating (x) is as follows:

[0034]

[0035]

[0036] Where r j，mLet be the value of the j-th codeword received in the m-th decoding cycle, where a is the primitive element of the corresponding number field and can be considered a constant.

[0037] Specifically, accompanying the first-stage pipeline is the solution process. This invention utilizes modular multiplication and modular addition operations in finite fields. For modular addition between any two elements in a finite field, "*" represents modular multiplication and "+" represents modular addition, thus constructing... Figure 2 According to the Peterson decoding principle, the syndrome generation circuit shown only requires the calculation of S in the (44, 32) BCH code. 1，m With S 3，m Then (S) 2，m S 4，m With S 1，m (equal), by Figure 2 It can be seen that these two syndromes are actually implementations of syndrome (1). The syndrome calculation circuit uses bitwise XOR to replace "+", that is, modulo addition, and then calculates the syndrome value.

[0038] 2) Place S i，m (x) is stored in the first-stage pipeline register;

[0039] 3) In the second-stage pipeline, the m-th decoding cycle currently being performed by the system is also used as the reference value for the time dimension. The error equation generation circuit generates the equation based on the syndrome S obtained from the output of the previous pipeline. i，m-1 (x) (corresponding to the received codeword of the input system in the (m-1)th cycle), calculate the error equation δ m-1 (x), error equation δ m-1 (x) has the following form:

[0040]

[0041] Solve the error equation δ m-1 The coefficients δ of each term in (x) j，m-1 This allows you to index the location of the error, δ j，m-1 The value and S calculated in the previous step i，m-1 (x) is related, where v refers to the number of erroneous digits; the specific solution is δ. j.m-1 The formula is as follows:

[0042] S j+v，m-1 +δ 1，m-1 Sj +v-1，m-1 +…+δ v-1，m-1 S j+1，m-1 +δ v，m-1 S j，m-1 =0 1≤j≤2t-v Equation (4)

[0043] Specifically, in the error equation solving part of the second-stage pipeline, based on the S output from the first-stage pipeline register...1,m-1 S 3，m-1 (Corresponding to the received codeword of the input system in the (m-1)th cycle), the modular multiplier and modular adder used in this invention construct the error equation generation circuit. According to the Peterson decoding principle, the error equation of the (44, 32) BCH code is shown in equation (4). After derivation, its coefficients are given by equation (5), where the operations are modular multiplication and modular addition. Since S1 and S3 are variables, modular multiplication is used, and the modular addition operation can be replaced by bitwise XOR. The circuit structure diagram is shown below. Figure 3 As shown.

[0044]

[0045] 4) The error equation δ m-1 The coefficients of (x) are stored in the second-stage pipeline register;

[0046] 5) In the third-stage pipeline, for the second-stage pipeline output error equation δ m-2 (x), the error equation is solved using the Chien search circuit to find the location of the error.

[0047] Specifically, in the third-stage pipeline, based on the δ output from the second-stage pipeline register... 0，m-2 δ 1，m-2 δ 2，m-2 (Corresponding to the received codeword of the input system in the (m-2)th cycle), the Chien search circuit will substitute the 44 finite field elements a0 to a-43 representing the error position into the error equation to generate 44 verification equations. The result of the verification equation is 0, which indicates that there is an error at the corresponding position. In the case of a two-bit error, the result of two verification equations will be 0.

[0048] Figure 4 The verification equation subcircuit of the Chien search circuit is presented. Its function is to solve the error equation and obtain the vector representing the error location, i.e., the error pattern. Since the verification equation subcircuit has many multiplications with the 44 finite field elements from a0 to a-43, constant modular multiplication can be used to save circuit area and reduce decoding delay.

[0049] In terms of hardware resource consumption, this invention only adds a pipeline register to the single-cycle, pipelineless Peterson decoding. Furthermore, since the circuitry used in this invention contains a large amount of bit XOR logic, the DC tool can merge common sub-expressions between different parts when fan-out is allowed. With the insertion of registers and the segmentation of complex combinational logic, DC can perform further optimizations on the combinational logic.

[0050] Figure 5The latency and hardware resource consumption of various decoding methods for (44, 32, 2) BCH codes are compared. The results show that the Peterson decoder based on a three-stage pipeline in this invention has the best timing among all schemes, with a longest path latency of only 2.20 ns at a 400 MHz clock speed and no violations. Due to its pipelined structure, the frequency improvement is significant.

[0051] References:

[0052] [1] Error Correction Coding Technology [M]. Posts & Telecom Press, 1987.

[0053] [2] A Review of ECC Error Detection and Correction Technology [C]. Wang Ning. Southeast University Anniversary Graduate Academic Conference. 2020

[0054] [3]1.Liu yang, Li jie, et alA BCH error correction scheme applied to FPGA with embedded

[0055] memoryJL.Frontiers ofInformation Technology&ElectronicEngineering2021-11):

[0056] [4]Hughes HL, Benedetto J M. Radiation Effects and Hardening of MOS

[0057] Technology:Devices and Circuits[J].IEEE Transaction on NuclearScience,2003,50(3):500-521.

[0058] [5] Zhang Jun, Wang Zhigong, Hu Qingsheng, Xiao Jie. VLSI optimization of high-speed parallel BCH(2184,2040) encoder

[0059] Design. Journal of Circuits and Systems. 2006, 11(1): 88-94.

Claims

1. A three-stage pipelined BCH decoding method for high bit error rate memories, characterized in that, The steps include: 1) In the first-stage pipeline, the syndrome computation circuit receives the codeword polynomial r according to the m-th decoding cycle. m (x) Calculate the i-th syndrome S in the m-th decoding cycle. i，m (x), for a BCH code with a total codeword length of n bits, a data bit length of k bits, and t-bit error correction, r m (x) and S i，m The formula for calculating (x) is as follows: Where r j，m Let be the value of the j-th codeword received in the m-th decoding cycle, where 'a' is the primitive element of the corresponding number field; 2) Place S i，m (x) is stored in the first-stage pipeline register; 3) In the second-stage pipeline, the error equation generation circuit generates the equation based on the syndrome S obtained from the output of the previous stage pipeline. i，m-1 (x), calculate the error equation δ m-1 (x), error equation δ m-1 (x) has the following form: Solve the error equation δ m-1 The coefficients δ of each term in (x) j，m-1 Solve for δ j.m-1 The formula is as follows: where v represents the number of erroneous bits. S j+v，m-1 +d 1，m-1 S j+v，m-1 +…+d v-1，m-1 S j+1，m-1 +d v，m-1 S j，m-1 =0 1≤j≤2t-v Equation (4) 4) The error equation δ m-1 The coefficients of (x) are stored in the second-stage pipeline register; 5) In the third-stage pipeline, for the second-stage pipeline output error equation δ m-2 (x), the error equation is solved using the Chien search circuit to find the location of the error.

2. The three-stage pipelined BCH decoding method for high bit error rate memories as described in claim 1, characterized in that, In step 1), the syndrome calculation circuit is used to construct the syndrome calculation of the (n, k, t) BCH code using a bit XOR circuit.

3. The three-stage pipelined BCH decoding method for high bit error rate memories as described in claim 1, characterized in that, In step 3), a modular multiplier and a modular adder are used to construct an error equation generation circuit.

4. The three-stage pipelined BCH decoding method for high bit error rate memories as described in claim 1, characterized in that, In step 5), the Chien search circuit determines the location of the error by searching for zeros in the finite field. That is, it evaluates each element in the finite field and checks whether the result is zero. If the result is zero, it means that the element is the root of the erroneous polynomial, thus determining an error location. This process is repeated until all error locations are found.

5. The three-stage pipelined BCH decoding method for high bit error rate memories as described in claim 4, characterized in that, Convert the error location into an error pattern.

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