Gate driving circuit and display panel

Abstract

The application discloses a kind of gate drive circuit and display panel.Gate drive circuit includes input module, control module, first output module and second output module;Input module is used to respond first clock signal and second clock signal and exports input signal;The first control end of control module is connected with input module, and the output end of control module is connected with the second control end of first output module, and control module is used to in each period of producing gate drive signal, respond the potential output first inverse voltage of first control end, and respond third clock signal and fourth clock signal and export second inverse voltage to second control end;First output module is used to be turned on or be turned off based on second inverse voltage, and export first voltage signal when being turned on;Second output module is used to be turned on or be turned off based on first inverse voltage, and export second voltage signal when being turned on.The technical scheme of the application improves the display effect of display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a gate driving circuit and a display panel. Background Technology

[0002] With the continuous development of display technology, the application range of display panels is becoming wider and wider, and people's requirements for display panels are also getting higher and higher.

[0003] However, current organic light-emitting display products have display abnormalities, and the display effect of these products needs to be improved. Summary of the Invention

[0004] This invention provides a gate driving circuit and a display panel to solve the problem of poor display effect in display products.

[0005] According to one aspect of the present invention, a gate driving circuit is provided, the gate driving circuit comprising:

[0006] An input module receives an input signal and outputs the input signal in response to a first clock signal and a second clock signal.

[0007] The system includes a control module and a first output module. The first control terminal of the control module is connected to the input module, and the output terminal of the control module is connected to the second control terminal of the first output module. The control module is configured to output a first inverted voltage in response to the potential of the first control terminal at each time period during which the gate drive signal is generated, and to output a second inverted voltage to the second control terminal in response to a third clock signal and a fourth clock signal. The first output module is configured to turn on or off based on the second inverted voltage, and to output a first voltage signal when on, so as to output the gate drive signal.

[0008] The second output module is connected to the control module and is used to turn on or off based on the first inverting voltage, and output a second voltage signal when on to output the gate drive signal.

[0009] Optionally, the control module includes: a first inverting unit, a first transmission unit, and a second inverting unit;

[0010] The control terminal of the first inverting unit is the first control terminal, the first terminal of the first inverting unit is connected to the first voltage signal, the second terminal of the first inverting unit is connected to the second voltage signal, and the first inverting unit is used to convert the voltage of the first control terminal into the first inverted voltage.

[0011] The first transmission unit is connected between the output terminal of the first inverting unit and the control terminal of the second inverting unit. The first transmission unit is used to transmit the first inverted voltage to the second inverting unit in response to the third clock signal and the fourth clock signal.

[0012] The first terminal of the second inverting unit is connected to the first voltage signal, the second terminal of the second inverting unit is connected to the second voltage signal, the output terminal of the second inverting unit is connected to the second control terminal, and the second inverting unit is used to convert the first inverted voltage into the second inverted voltage.

[0013] The third control terminal of the second output module is connected to the first transmission unit.

[0014] Optionally, the control module further includes:

[0015] The third inverting unit has its control terminal connected to the output terminal of the first inverting unit. The first terminal of the third inverting unit is connected to the first voltage signal, and the second terminal of the third inverting unit is connected to the second voltage signal. The third inverting unit is used to convert the first inverted voltage into the second inverted voltage.

[0016] The second transmission unit is connected between the output terminal of the third inverting unit and the first control terminal, and is used to transmit the second inverted voltage to the first control terminal in response to the first clock signal and the second clock signal.

[0017] Preferably, the second transmission unit is turned off when the input module is turned on, and turned on when the input module is turned off;

[0018] Preferably, the control module further includes:

[0019] The fourth inverting unit has its control terminal connected to the output terminal of the second inverting unit. The first terminal of the fourth inverting unit is connected to the first voltage signal, and the second terminal of the fourth inverting unit is connected to the second voltage signal. The fourth inverting unit is used to convert the second inverted voltage into the first inverted voltage.

[0020] The third transmission unit is connected between the output terminal of the fourth inverting unit and the control terminal of the second inverting unit, and is used to transmit the first inverted voltage to the control terminal of the second inverting unit in response to the third clock signal and the fourth clock signal.

[0021] Preferably, the third transmission unit is turned off when the first transmission unit is turned on, and turned on when the third transmission unit is turned off.

[0022] Optionally, the first inverting unit includes a first transistor and a second transistor;

[0023] The control terminal of the first transistor is the first control terminal, the first terminal of the first transistor is connected to the first voltage signal, and the second terminal of the first transistor is connected to the first transmission unit.

[0024] The control terminal of the second transistor is the first control terminal, the first terminal of the second transistor is connected to the second voltage signal, and the second terminal of the second transistor is connected to the first transmission unit;

[0025] Preferably, the first transistor is an N-type transistor and the second transistor is a P-type transistor; or, the first transistor is a P-type transistor and the second transistor is an N-type transistor.

[0026] Preferably, the first transmission unit includes a third transistor and a fourth transistor;

[0027] The control terminal of the third transistor is connected to the third clock signal, the first terminal of the third transistor is connected to the output terminal of the first inverting unit, and the second terminal of the third transistor is connected to the control terminal of the second inverting unit.

[0028] The control terminal of the fourth transistor is connected to the fourth clock signal, the first terminal of the fourth transistor is connected to the output terminal of the first inverting unit, and the second terminal of the fourth transistor is connected to the control terminal of the second inverting unit.

[0029] Preferably, the third transistor is an N-type transistor and the fourth transistor is a P-type transistor; or, the third transistor is a P-type transistor and the fourth transistor is an N-type transistor.

[0030] Preferably, the second inverting unit includes a fifth transistor and a sixth transistor;

[0031] The control electrode of the fifth transistor is connected to the first transmission unit, the first electrode of the fifth transistor is connected to the first voltage signal, and the second electrode of the fifth transistor is connected to the second control terminal.

[0032] The control electrode of the sixth transistor is connected to the first transmission unit, the first electrode of the sixth transistor is connected to the second voltage signal, and the second electrode of the sixth transistor is connected to the second control terminal.

[0033] Preferably, the fifth transistor is an N-type transistor and the sixth transistor is a P-type transistor; or, the fifth transistor is a P-type transistor and the sixth transistor is an N-type transistor.

[0034] Optionally, the gate drive circuit further includes:

[0035] The coupling module is connected to the third control terminal of the control module and the second output module respectively, and is used to couple and control the potential of the third control terminal based on the transition from the first level to the second level of the first clock signal, so as to maintain the output of the second voltage signal by the second output module.

[0036] Optionally, the coupling module includes a fourth transmission unit, a fifth transmission unit, a coupling unit, and a switching unit;

[0037] The fourth transmission unit is connected between the control module and the first end of the coupling unit. The fourth transmission unit is used to respond to the first clock signal and transmit the first inverted voltage to the first end of the coupling unit.

[0038] The control terminal of the fifth transmission unit is connected to the fourth transmission unit. The first terminal of the fifth transmission unit is connected to the first clock signal. The second terminal of the fifth transmission unit is connected to the second terminal of the coupling unit. The fifth transmission unit is used to transmit the voltage corresponding to the first clock signal to the second terminal of the coupling unit in response to the first inverted voltage.

[0039] The coupling unit is used to couple the second end of the coupling unit when the first level of the first clock signal transitions to the second level;

[0040] The control terminal of the switching unit is connected to the fourth transmission unit, the first terminal of the switching unit is connected to the first terminal of the coupling unit, and the second terminal of the switching unit is connected to the second control terminal. The switching unit is used to transmit the potential coupled from the second terminal of the coupling unit to the third control terminal.

[0041] Preferably, the voltage corresponding to the first level is the same as the first voltage signal, and the voltage corresponding to the second level is the same as the second voltage signal.

[0042] Optionally, the coupling module further includes an initialization unit;

[0043] The control terminal of the initialization unit is connected to the first control terminal, the first terminal of the initialization unit is connected to the first voltage signal, and the second terminal of the initialization unit is connected to the second terminal of the coupling unit; the initialization unit is used to respond to the potential of the first control terminal and transmit the first voltage signal to the second terminal of the coupling unit.

[0044] Optionally, the fourth transmission unit includes a seventh transistor;

[0045] The control electrode of the seventh transistor is connected to the first clock signal, the first electrode of the seventh transistor is connected to the control module, and the second electrode of the seventh transistor is connected to the first end of the coupling unit.

[0046] Preferably, the fourth transmission unit further includes an eighth transistor;

[0047] The control electrode of the eighth transistor is connected to the second voltage signal, and the eighth transistor is connected between the second electrode of the seventh transistor and the first terminal of the coupling unit;

[0048] Preferably, the fifth transmission unit includes a ninth transistor;

[0049] The control electrode of the ninth transistor is connected to the fourth transmission unit, the first electrode of the ninth transistor is connected to the first clock signal, and the second electrode of the ninth transistor is connected to the second end of the coupling unit.

[0050] Preferably, the coupling unit includes a capacitor;

[0051] The first terminal of the capacitor is the first terminal of the coupling unit, and the second terminal of the capacitor is the second terminal of the coupling unit;

[0052] Preferably, the switching unit includes a tenth transistor;

[0053] The control electrode of the tenth transistor is connected to the fourth transmission unit, the first electrode of the tenth transistor is connected to the first end of the coupling unit, and the second electrode of the tenth transistor is connected to the second control terminal.

[0054] Optionally, the gate drive circuit further includes:

[0055] A reset module, connected to the second output module and the control module, is used to respond to a reset control signal and transmit a reset signal to the second output module and the control module.

[0056] According to another aspect of the present invention, a display panel is provided, the display panel including the gate driving circuit described in any embodiment of the present invention.

[0057] The technical solution of this invention, by setting a control module, allows the first output module to turn on or off in response to the second inverted voltage output by the control module, and the second output module to turn on or off in response to the first inverted voltage output by the control module. The first and second inverted voltages are inversely related, enabling the first and second output modules to be turned on in a time-division manner, thereby outputting a first voltage signal and a second voltage signal in a time-division manner to form a gate drive signal. This avoids the first and second output modules from being turned on simultaneously, preventing ambiguity in the output level of the gate drive circuit, thus outputting an accurate gate drive signal. This facilitates accurate control of the transistors in the pixel circuit, allowing the pixel circuit to accurately output drive current and the light-emitting device to accurately emit light, thereby enabling the display product to meet display requirements and improving the display effect of the display panel. Furthermore, by setting the control module to output a first inverted voltage in response to the potential of the first control terminal at each time period of generating the gate drive signal, it is easier to maintain the potential of each connection node in the gate drive circuit, ensuring that the potential of the second control terminal can be maintained at a high or low level, without changing due to leakage current, and preventing the potential of the second control terminal from being between a high and low level. Therefore, the on / off state of the first output module can be accurately controlled, thereby outputting an accurate gate drive signal. Furthermore, there is no need to add a capacitor to maintain the potential of the second control terminal, which reduces circuit cost by avoiding the influence of leakage current on the potential of the second control terminal.

[0058] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0059] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0060] Figure 1 This is a schematic diagram of a pixel circuit.

[0061] Figure 2 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present invention;

[0062] Figure 3 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0063] Figure 4 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0064] Figure 5 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0065] Figure 6 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0066] Figure 7 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0067] Figure 8 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0068] Figure 9 This is a timing diagram of a gate driving circuit provided in an embodiment of the present invention;

[0069] Figure 10 This is a timing diagram of another gate driving circuit provided in an embodiment of the present invention;

[0070] Figure 11 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0071] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0072] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0073] The pixel unit of the display product includes interconnected pixel circuits and light-emitting devices. The pixel circuits provide driving current to the light-emitting devices, causing the light-emitting devices to emit light in response to the driving current. The pixel circuits may include 2T1C pixel circuits and their variations, or 7T1C circuits and their variations. Figure 1 This is a schematic diagram of a pixel circuit structure, such as... Figure 1 As shown, the pixel circuit includes a data writing transistor M1, a threshold compensation transistor M2, a driving transistor M3, a first initialization transistor M4, a second initialization transistor M5, a first light-emitting control transistor M6, and a second light-emitting control transistor M7; the light-emitting device includes an organic light-emitting diode (OLED). The control electrode of the data writing transistor M1 is connected to the first scan line S1, the first electrode of the data writing transistor M1 is connected to the data line Data, and the second electrode of the data writing transistor M1 is electrically connected to the first electrode of the driving transistor M3. The first electrode of the threshold compensation transistor M2 is electrically connected to the second electrode of the driving transistor M3, and the second electrode of the threshold compensation transistor M2 is electrically connected to the control electrode of the driving transistor M3. The control electrode of the threshold compensation transistor M2 is connected to the first scan line S1. The control electrode of the first initialization transistor M4 is connected to the second scan line S2, the first electrode of the first initialization transistor M4 is connected to the initialization line Vref, and the second electrode of the first initialization transistor M4 is electrically connected to the control electrode of the driving transistor M3. The control electrode of the second initialization transistor M5 is connected to the second scan line S2, the first electrode of the second initialization transistor M5 is connected to the initialization line Vref, and the second electrode of the second initialization transistor M5 is electrically connected to the anode of the OLED. The control electrode of the first light-emitting control transistor M6 is connected to the light-emitting control line EM. The first electrode of the first light-emitting control transistor M6 is connected to the first power supply VDD. The second electrode of the first light-emitting control transistor M6 is electrically connected to the first electrode of the driving transistor M3. The control electrode of the second light-emitting control transistor M7 is connected to the light-emitting control line EM. The first electrode of the second light-emitting control transistor M7 is electrically connected to the second electrode of the driving transistor M3. The second electrode of the second light-emitting control transistor M7 is electrically connected to the anode of the organic light-emitting diode (OLED). The cathode of the OLED is connected to the second power supply VSS. The storage capacitor Cst is connected between the first power supply VDD and the control electrode of the driving transistor M3. Figure 1 The diagram illustrates a scenario where the threshold compensation transistor M2, the first initialization transistor M4, the second initialization transistor M5, the first light-emitting control transistor M6, and the second light-emitting control transistor M7 are N-type transistors, while the data writing transistor M1 and the driving transistor M3 are P-type transistors. However, this is not a limitation. The transistors in the pixel circuit can also all be N-type transistors or all be P-type transistors.

[0074] The display product also includes a gate driving circuit, which outputs a gate driving signal to drive the transistors in the pixel circuit to turn on and off. The gate driving signal can be a scan driving signal corresponding to at least one of the following transistors: data writing transistor M1, threshold compensation transistor M2, driving transistor M3, first initialization transistor M4, and second initialization transistor M5; or it can be a light emission control signal corresponding to at least one of the following transistors: first light emission control transistor M6 and second light emission control transistor M7. The gate driving circuit can include two output modules, such as an active level output module and an inactive level output module. An active level is a signal that controls the transistor to turn on, and an inactive level is a signal that controls the transistor to turn off. When the control terminal of the active level output module is active, the active level output module is on and outputs an active level, which can control the transistors in the pixel circuit to turn on. When the control terminal of the inactive level output module is active, the inactive level output module is on and outputs an inactive level, which can control the transistors in the pixel circuit to turn off. However, when the leakage current of the transistor in the gate drive circuit is high, the potential of the control terminals of the effective level output module and the ineffective level output module may be low. This is insufficient to control the conduction and turn-off of the effective level output module and the ineffective level output module, causing the conduction timing of the effective level output module and the ineffective level output module to be disordered. In turn, the gate drive signal output by the gate drive circuit becomes disordered, making it impossible to accurately control the transistors in the pixel circuit. As a result, the pixel circuit cannot accurately output the drive current, and the light emission timing of the light-emitting device becomes disordered, thus affecting the display effect of the display product.

[0075] To address the aforementioned technical problems, the present invention provides a gate driving circuit. Figure 2 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present invention, for reference. Figure 2 The gate drive circuit includes an input module 110, a control module 120, a first output module 130, and a second output module 140. The input module 110 receives the input signal EIN and outputs the input signal EIN in response to the first clock signal ECK1 and the second clock signal ECK2. The first control terminal A of the control module 120 is connected to the input module 110, and the output terminal of the control module 120 is connected to the second control terminal Q of the first output module 130. The control module 120 outputs a first inverted voltage in response to the potential of the first control terminal A at each time period when the gate drive signal is generated, and outputs a second inverted voltage to the second control terminal Q in response to the third clock signal ECK3 and the fourth clock signal ECK4. The first output module 130 is turned on or off based on the second inverted voltage, and outputs a first voltage signal VG1 when turned on to output the gate drive signal.

[0076] The second output module 140 is connected to the control module 120. The second output module 140 is used to turn on or off based on the first inverted voltage, and outputs the second voltage signal VG2 when it is on to output the gate drive signal.

[0077] Wherein, the first voltage signal VG1 is a high-level signal and the second voltage signal VG2 is a low-level signal; or, the first voltage signal VG1 is a low-level signal and the second voltage signal VG2 is a high-level signal. The output terminals of the first output module 130 and the second output module 140 are both the output terminal OUT of the gate drive circuit. The first inverted voltage and the second inverted voltage are inverted; that is, when the first inverted voltage is low, the second inverted voltage is high; and when the first inverted voltage is high, the second inverted voltage is low.

[0078] Specifically, when the first clock signal ECK1 and the second clock signal ECK2 control the input module 110 to be turned on, the input module 110 transmits the input signal EIN to the first control terminal A. The control module 120 can flip (invert) the potential of the first control terminal A, converting it into a first inverted voltage for output. When the third clock signal ECK3 and the fourth clock signal ECK4 control the control module 120 to flip (invert) the first inverted voltage, that is, convert the first inverted voltage into a second inverted voltage for output, the potential of the second control terminal Q becomes the second inverted voltage. Thus, the first output module 130 is turned on or off through the second inverted voltage, and the first voltage signal VG1 is output when it is turned on. The second output module 140 is turned on or off according to the first inverted voltage, and the second voltage signal VG2 is output when it is turned on, thereby forming a gate drive signal containing both high and low levels.

[0079] Because the first and second inverted voltages are out of phase, the first output module 130 and the second output module 140 can be turned on in a time-division manner, thereby outputting the first voltage signal VG1 and the second voltage signal VG2 in a time-division manner, i.e., outputting high and low level signals in a time-division manner, thus forming a gate drive signal. This avoids the first output module 130 and the second output module 140 being turned on simultaneously, preventing the output level of the gate drive circuit OUT from being ambiguous (e.g., between high and low levels), thus outputting an accurate gate drive signal. This facilitates accurate control of the transistors in the pixel circuit, allowing the pixel circuit to accurately output drive current, and the light-emitting device to accurately emit light, thereby enabling the display product to meet display requirements and improving the display effect of the display panel.

[0080] Furthermore, by setting the control module 120 to output a first inverted voltage in response to the potential of the first control terminal A at each time period of generating the gate drive signal, it is convenient to maintain the potential of each connection node in the gate drive circuit. That is, by continuously outputting voltage to maintain the node potential, the potential of the second control terminal Q can be maintained at a high or low level, without changing due to leakage current, thus preventing the potential of the second control terminal Q from being between a high and low level, thereby maintaining the potential of the second control terminal Q. Therefore, the potential of the second control terminal Q can be effectively maintained, allowing the first output module 130 to be turned on or off more effectively, thereby outputting an accurate gate drive signal. Moreover, without the need for a capacitor to maintain the potential of the second control terminal Q, the circuit cost can be reduced while avoiding the influence of leakage current on the potential of the second control terminal Q.

[0081] The technical solution of this embodiment, by setting a control module, allows the first output module to turn on or off in response to the second inverted voltage output by the control module, and the second output module to turn on or off in response to the first inverted voltage output by the control module. The first and second inverted voltages are inversely related, allowing the first and second output modules to be turned on in a time-division manner, thereby outputting the first and second voltage signals in a time-division manner to form a gate drive signal. This avoids the first and second output modules from being turned on simultaneously, preventing ambiguity in the output level of the gate drive circuit, thus outputting an accurate gate drive signal. This facilitates accurate control of the transistors in the pixel circuit, enabling the pixel circuit to accurately output drive current and the light-emitting device to accurately emit light, thereby enabling the display product to meet display requirements and improving the display effect of the display panel. Furthermore, by setting the control module to output the first inverted voltage in response to the potential of the first control terminal at each time period of generating the gate drive signal, it is easier to maintain the potential of each connection node in the gate drive circuit, allowing the potential of the second control terminal to be maintained at a high or low level, without changing due to leakage current, and preventing the potential of the second control terminal from being between high and low levels. Therefore, the on / off state of the first output module can be accurately controlled, thereby outputting an accurate gate drive signal. Furthermore, there is no need to add a capacitor to maintain the potential of the second control terminal, which reduces circuit cost by avoiding the influence of leakage current on the potential of the second control terminal.

[0082] Based on the above technical solution, the structure of the control module will be described in detail below, but this is not intended to limit this application.

[0083] Figure 3 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention. Optionally, refer to... Figure 3 The control module 120 includes a first inverting unit 121, a first transmission unit 122, and a second inverting unit 123;

[0084] The control terminal of the first inverting unit 121 is the first control terminal A. The first terminal of the first inverting unit 121 is connected to the first voltage signal VG1, and the second terminal of the first inverting unit 121 is connected to the second voltage signal VG2. The first inverting unit 121 is used to convert the voltage of the first control terminal A into a first inverted voltage.

[0085] The first transmission unit 122 is connected between the output terminal of the first inverting unit 121 and the control terminal of the second inverting unit 123. The first transmission unit 122 is used to transmit the first inverted voltage to the second inverting unit 123 in response to the third clock signal ECK3 and the fourth clock signal ECK4.

[0086] The first terminal of the second inverting unit 123 is connected to the first voltage signal VG1, the second terminal of the second inverting unit 123 is connected to the second voltage signal VG2, the output terminal of the second inverting unit 123 is connected to the second control terminal Q, and the second inverting unit 123 is used to convert the first inverted voltage into the second inverted voltage.

[0087] The third control terminal QB of the second output module 140 is connected to the first transmission unit 122.

[0088] Specifically, the first inverting unit 121 can flip (invert) the voltage of the first control terminal A to obtain a first inverted voltage. When the third clock signal ECK3 and the fourth clock signal ECK4 control the first transmission unit 122 to be turned on, the first transmission unit 122 can transmit the first inverted voltage to the second inverting unit 123 and the second output module 140, so that the second output module 140 can be turned on or off according to the first inverted voltage. The second inverting unit 123 can flip (invert) the first inverted voltage to obtain a second inverted voltage, and the first output module 130 can be turned on or off according to the second inverted voltage. In this way, the first output module 130 and the second output module 140 can be turned on in a time-division manner, thereby outputting the first voltage signal VG1 and the second voltage signal VG2 in a time-division manner.

[0089] The first inverting unit 121 can invert the voltage of the first control terminal A. That is, regardless of whether the potential of the first control terminal A is high or low, the first inverting unit 121 always has a voltage output, so that the output terminal of the first inverting unit 121 always has a voltage input. This can maintain the potential of the output terminal of the first inverting unit 121, thereby facilitating the maintenance of the potential of the second control terminal Q and the third control terminal QB of the second output module 140. This avoids the potential of the second control terminal Q and the third control terminal QB changing due to leakage, which is beneficial for accurately controlling the conduction state of the first output module 130 and the second output module 140, thereby improving the accuracy of the output gate drive signal.

[0090] Based on the above technical solutions, Figure 4This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention. Optionally, refer to... Figure 4 The control module 120 also includes a third inverting unit 124 and a second transmission unit 125;

[0091] The control terminal of the third inverting unit 124 is connected to the output terminal of the first inverting unit 121. The first terminal of the third inverting unit 124 is connected to the first voltage signal VG1, and the second terminal of the third inverting unit 124 is connected to the second voltage signal VG2. The third inverting unit 124 is used to convert the first inverted voltage into the second inverted voltage.

[0092] The second transmission unit 125 is connected between the output terminal of the third inverting unit 124 and the first control terminal A. The second transmission unit 125 is used to transmit the second inverted voltage to the first control terminal A in response to the first clock signal ECK1 and the second clock signal ECK2. Optionally, the second transmission unit 125 is turned off when the input module 110 is turned on and turned on when the input module 110 is turned off.

[0093] Specifically, the third inverting unit 124 can flip (invert) the first inverted voltage to obtain a second inverted voltage. This second inverted voltage is the same as the potential of the first control terminal A. When the first clock signal ECK1 and the second clock signal ECK2 control the second transmission unit 125 to conduct, the second transmission unit 125 can transmit the second inverted voltage to the first control terminal A, strengthening the potential of the first control terminal A. Thus, when the input module 110 is on, it inputs voltage to the first control terminal A; when the second transmission unit 125 is on, it inputs voltage to the first control terminal A, ensuring a constant voltage input to the first control terminal A. This effectively maintains the potential of the first control terminal A without requiring an additional capacitor to maintain the potential, saving circuit costs while avoiding the impact of leakage current on the potential of the first control terminal A. Furthermore, the input module 110 and the second transmission unit 125 will not conduct simultaneously, preventing potential disturbances at the first control terminal A and improving the accuracy of the potential at the first control terminal A.

[0094] Optionally, continue to refer to Figure 4 The control module 120 also includes a fourth inverting unit 126 and a third transmission unit 127;

[0095] The control terminal of the fourth inverting unit 126 is connected to the output terminal of the second inverting unit 123. The first terminal of the fourth inverting unit 126 is connected to the first voltage signal VG1, and the second terminal of the fourth inverting unit 126 is connected to the second voltage signal VG2. The fourth inverting unit 126 is used to convert the second inverted voltage into the first inverted voltage.

[0096] The third transmission unit 127 is connected between the output terminal of the fourth inverting unit 126 and the control terminal of the second inverting unit 123. The third transmission unit 127 is used to transmit the first inverted voltage to the control terminal of the second inverting unit 123 in response to the third clock signal ECK3 and the fourth clock signal ECK4. Optionally, the third transmission unit 127 is turned off when the first transmission unit 122 is turned on, and turned on when the third transmission unit 127 is turned off.

[0097] Specifically, the fourth inverting unit 126 can flip (invert) the second inverted voltage to obtain the first inverted voltage. The voltage output by the fourth inverting unit 126 is the same as the voltage output by the first transmission unit 122. When the third clock signal ECK3 and the fourth clock signal ECK4 control the third transmission unit 127 to conduct, the third transmission unit 127 can transmit the first inverted voltage to the control terminal of the second inverting unit 123, thus strengthening the potential of the control terminal of the second inverting unit 123. In this way, when the first transmission unit 122 is on, it can input voltage to the control terminal of the second inverting unit 123; when the third transmission unit 127 is on, it can input voltage to the control terminal of the second inverting unit 123. This ensures that the control terminal of the second inverting unit 123 always has a voltage input, effectively maintaining the potential of the control terminal of the second inverting unit 123 without the need for an additional capacitor to maintain the potential. This saves circuit costs while avoiding the impact of leakage current on the potential of the control terminal of the second inverting unit 123. Furthermore, the third transmission unit 127 and the first transmission unit 122 will not be turned on simultaneously, which can avoid potential disturbance at the control terminal of the second inverting unit 123, and help improve the accuracy of the potential at the control terminal of the second inverting unit 123, thereby improving the accuracy of the control of the first output module 130.

[0098] Based on the above technical solutions, in order to ensure that the second output module 140 can better output the second voltage signal VG2, the gate drive circuit may also include a coupling module. The structure of the gate drive circuit will be specifically described below in conjunction with the structure of the coupling module, but this is not intended to limit this application.

[0099] Figure 5 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention. Optionally, refer to... Figure 5 The gate drive circuit also includes a coupling module 150, which is connected to the third control terminal QB of the control module 120 and the second output module 140 respectively. The coupling module 150 is used to couple and control the potential of the third control terminal QB based on the transition from the first level to the second level of the first clock signal ECK1, so as to maintain the output of the second voltage signal VG2 by the second output module 140.

[0100] Specifically, the second level is, for example, the same level used to control the second output module 140 to turn on. When the first clock signal ECK1 transitions from the first level to the second level, the potential at the connection point between the coupling module 150 and the third control terminal QB changes towards the second level, causing the potential of the third control terminal QB to change in the direction of the second level. When the potential of the third control terminal QB is the same level used to control the second output module 140 to turn on, the potential of the third control terminal QB will become an ultra-low level or an ultra-high level, which can control the second output module 140 to fully turn on, allowing the second output module 140 to fully output the second voltage signal VG2. This makes the level of the output gate drive signal more complete, thereby maintaining the output of the second voltage signal VG2 by the second output module 140, facilitating the output of a complete gate drive signal, and improving the accuracy of the gate drive signal output.

[0101] As a further implementation of this embodiment, based on the above technical solution, the structure of the coupling module 150 will be further described below, but this is not intended to limit the scope of this application.

[0102] Figure 6 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention. Optionally, refer to... Figure 6 The coupling module 150 includes a fourth transmission unit 151, a fifth transmission unit 152, a coupling unit 153, and a switching unit 154;

[0103] The fourth transmission unit 151 is connected between the control module 120 and the first end of the coupling unit 153. The fourth transmission unit 151 is used to transmit the first inverted voltage to the first end of the coupling unit 153 in response to the first clock signal ECK1.

[0104] The control terminal of the fifth transmission unit 152 is connected to the fourth transmission unit 151. The first terminal of the fifth transmission unit 152 is connected to the first clock signal ECK1. The second terminal of the fifth transmission unit 152 is connected to the second terminal of the coupling unit 153. The fifth transmission unit 152 is used to transmit the voltage corresponding to the first clock signal ECK1 to the second terminal of the coupling unit 153 in response to the first inverted voltage.

[0105] The coupling unit 153 is used to couple the second terminal of the first clock signal ECK1 when the first level of the first clock signal ECK1 changes to the second level.

[0106] The control terminal of the switching unit 154 is connected to the fourth transmission unit 151, the first terminal of the switching unit 154 is connected to the first terminal of the coupling unit 153, the second terminal of the switching unit 154 is connected to the second control terminal Q, and the switching unit 154 is used to transmit the potential coupled from the second terminal of the coupling unit 153 to the third control terminal QB.

[0107] Optionally, the voltage corresponding to the first level is the same as the first voltage signal VG1, and the voltage corresponding to the second level is the same as the second voltage signal VG2.

[0108] Specifically, when the first transmission unit 122 or the third transmission unit 127 is turned on, the first transmission unit 122 or the third transmission unit 127 can output a first inverted voltage. When the first clock signal ECK1 controls the fourth transmission unit 151 to be turned on, the fourth transmission unit 151 transmits the first inverted voltage to the first terminal of the coupling unit 153. When the voltage controlling the first inverted unit is the same as the voltage controlling the fifth transmission unit 152 to be turned on, the fifth transmission unit 152 transmits the first clock signal ECK1 to the second terminal of the coupling unit 153.

[0109] For example, if the first level is high and the second level is low, the second output module 140 is turned on at a low level. When the first clock signal ECK1 is high and the first inverting voltage is low, the voltage difference across the coupling unit 153 is the high level minus the low level. When the first clock signal ECK1 jumps from the first level to the second level (from high to low), the coupling unit 153 couples the low level to the first terminal of the coupling unit 153, making the first terminal of the coupling unit 153 ultra-low. The switching unit 154 transmits the ultra-low level to the third control terminal QB, thereby controlling the second output module 140 to be fully turned on.

[0110] For example, if the first level is low and the second level is high, the second output module 140 is high and turned on. When the first clock signal ECK1 is low and the first inverting voltage is high, the voltage difference across the coupling unit 153 is the high level minus the low level. When the first clock signal ECK1 jumps from the first level to the second level (from low to high), the coupling unit 153 couples the high level to the first terminal of the coupling unit 153, making the first terminal of the coupling unit 153 ultra-high. The switching unit 154 transmits the ultra-high level to the third control terminal QB, thereby controlling the second output module 140 to be fully turned on.

[0111] In this way, the coupling control of the third control terminal QB is realized, which facilitates the control of the third control terminal QB to be fully turned on, so that the second output module 140 can accurately output the second voltage signal VG2, and can maintain the output of the second voltage signal VG2 by the second output module 140, thereby improving the accuracy of the gate drive signal.

[0112] Optionally, continue to refer to Figure 6 The coupling module 150 also includes an initialization unit 155;

[0113] The control terminal of the initialization unit 155 is connected to the first control terminal A. The first terminal of the initialization unit 155 is connected to the first voltage signal VG1. The second terminal of the initialization unit 155 is connected to the second terminal of the coupling unit 153. The initialization unit 155 is used to respond to the potential of the first control terminal A and transmit the first voltage signal VG1 to the second terminal of the coupling unit 153.

[0114] Specifically, when the potential control initialization unit 155 of the first control terminal A is turned on, the initialization unit 155 transmits the first voltage signal VG1 to the second terminal of the coupling unit 153 to reset the second terminal of the coupling unit 153 and clear the residual charge of the second terminal of the coupling unit 153, so that the coupling unit 153 can perform coupling control on the third control terminal QB according to the potential jump of the first clock signal ECK1.

[0115] Optionally, continue to refer to Figure 6 The gate drive circuit also includes a reset module 160, which is connected to the second output module 140 and the control module 120. The reset module 160 is used to respond to the reset control signal RST and transmit the reset signal V1 to the second output module 140 and the control module 120.

[0116] Specifically, for example, the second voltage signal VG2 is the effective level in the gate drive signal (the level that controls the transistor in the pixel circuit to conduct), and the reset signal V1 is, for example, the first voltage signal VG1. For example, when the display panel is first powered on, the reset control signal RST controls the reset module 160 to conduct, the reset module 160 transmits the reset signal V1 to the second output module 140, the second output module 140 is turned off, and does not output the second voltage signal VG2. The control module 120 inverts the reset signal V1, causing the first output module 130 to conduct, and the first output module 130 outputs the first voltage signal VG1. In this way, the gate drive circuit is reset, and the effective level is output again according to the input signal EIN.

[0117] Based on the above technical solutions, the possible structures of each module and unit provided in the above embodiments will be further described below, but this is not intended to limit the scope of this application.

[0118] Figure 7 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention. Figure 8 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention. Optionally, refer to... Figure 7 or Figure 8 The first inverting unit 121 includes a first transistor T1 and a second transistor T2;

[0119] The control terminal of the first transistor T1 is the first control terminal A. The first terminal of the first transistor T1 is connected to the first voltage signal VG1. The second terminal of the first transistor T1 is connected to the first transmission unit 122.

[0120] The control terminal of the second transistor T2 is the first control terminal A. The first terminal of the second transistor T2 is connected to the second voltage signal VG2, and the second terminal of the second transistor T2 is connected to the first transmission unit 122.

[0121] In one implementation, alternatively, reference is made to... Figure 7 The first transistor T1 is an N-type transistor, and the second transistor T2 is a P-type transistor.

[0122] For example, the first voltage signal VG1 is at a low level, and the second voltage signal VG2 is at a high level. When the potential of the first control terminal A is high, the first transistor T1 is turned on, and the first transistor T1 outputs a first inverted voltage, which is the first voltage signal VG1. When the potential of the first control terminal A is low, the second transistor T2 is turned on, and the second transistor T2 outputs a first inverted voltage, which is the second voltage signal VG2.

[0123] In another implementation, alternatively, refer to Figure 8 The first transistor is a P-type transistor, and the second transistor is an N-type transistor.

[0124] For example, the first voltage signal VG1 is at a high level, and the second voltage signal VG2 is at a low level. When the potential of the first control terminal A is at a high level, the second transistor T2 is turned on, and the second transistor T2 outputs a first inverted voltage, which is the second voltage signal VG2. When the potential of the first control terminal A is at a low level, the first transistor T1 is turned on, and the first transistor T1 outputs a first inverted voltage, which is the first voltage signal VG1.

[0125] Thus, by setting the first inverting unit 121 to include two different types of transistors to form a complementary metal-oxide-semiconductor, the first inverting unit 121 always has a voltage output regardless of whether the potential of the first control terminal A is high or low. This facilitates maintaining the potential of the output terminal of the first inverting unit 121, thereby avoiding leakage current from affecting the potential of the output terminal of the first inverting unit 121. This also makes it easier to ensure that the potentials transmitted to the second control terminal Q of the first output module 130 and the third control terminal QB of the second output module 140 are accurate, thus improving the accuracy of the control of the first output module 130 and the second output module 140.

[0126] Optionally, refer to Figure 7 or Figure 8 The first transmission unit 122 includes a third transistor T3 and a fourth transistor T4;

[0127] The control terminal of the third transistor T3 is connected to the third clock signal ECK3. The first terminal of the third transistor T3 is connected to the output terminal of the first inverter unit 121, and the second terminal of the third transistor T3 is connected to the control terminal of the second inverter unit 123.

[0128] The control terminal of the fourth transistor T4 is connected to the fourth clock signal ECK4. The first terminal of the fourth transistor T4 is connected to the output terminal of the first inverting unit 121, and the second terminal of the fourth transistor T4 is connected to the control terminal of the second inverting unit 123. Optionally, during the same time period, the voltage corresponding to the third clock signal ECK3 and the voltage corresponding to the fourth clock signal ECK4 are inverted.

[0129] In one implementation, alternatively, reference is made to... Figure 7 The third transistor T3 is an N-type transistor, and the fourth transistor T4 is a P-type transistor.

[0130] For example, during the same period, the voltage corresponding to the third clock signal ECK3 and the voltage corresponding to the fourth clock signal ECK4 are out of phase. When the third clock signal ECK3 is high, the fourth clock signal ECK4 is low. The third transistor T3 and the fourth transistor T4 are both turned on, so that the third transistor T3 and the fourth transistor T4 can output the first inverted voltage to the second inverting unit 123 and the second output module 140.

[0131] In another implementation, alternatively, refer to Figure 8 The third transistor T3 is a P-type transistor, and the fourth transistor T4 is an N-type transistor.

[0132] For example, during the same period, the voltage corresponding to the third clock signal ECK3 and the voltage corresponding to the fourth clock signal ECK4 are out of phase. When the third clock signal ECK3 is low, the fourth clock signal ECK4 is high, and both the third transistor T3 and the fourth transistor T4 are turned on, so that the third transistor T3 and the fourth transistor T4 can output the first inverted voltage to the second inverting unit 123 and the second output module 140.

[0133] In summary, by setting the first transmission unit 122 to include two different types of transistors (one is an N-type transistor and the other is a P-type transistor), the leakage current of the P-type transistor can be reduced, the power loss can be reduced, and the first transmission unit 122 can output a smoother level, ensuring the accuracy of the output level.

[0134] Optionally, refer to Figure 7 or Figure 8 The second inverting unit 123 includes a fifth transistor T5 and a sixth transistor T6;

[0135] The control electrode of the fifth transistor T5 is connected to the first transmission unit 122, the first electrode of the fifth transistor T5 is connected to the first voltage signal VG1, and the second electrode of the fifth transistor T5 is connected to the second control terminal Q.

[0136] The control electrode of the sixth transistor T6 is connected to the first transmission unit 122, the first electrode of the sixth transistor T6 is connected to the second voltage signal VG2, and the second electrode of the sixth transistor T6 is connected to the second control terminal Q.

[0137] In one implementation, alternatively, reference is made to... Figure 7 The fifth transistor T5 is an N-type transistor, and the sixth transistor T6 is a P-type transistor.

[0138] For example, the first voltage signal VG1 is at a low level, and the second voltage signal VG2 is at a high level. After the first transmission unit 122 outputs the first inverted voltage, when the first inverted voltage is at a low level, the sixth transistor T6 is turned on, and the sixth transistor T6 outputs the second inverted voltage, which is the second voltage signal VG2. When the first inverted voltage is at a high level, the fifth transistor T5 is turned on, and the fifth transistor T5 outputs the second inverted voltage, which is the first voltage signal VG1.

[0139] like Figure 7 As shown, the working principle of the control module 120 will be explained below with reference to the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6, but this is not intended to limit the scope of this application.

[0140] When the potential of the first control terminal A is low, the second transistor T2 is turned on, outputting the first inverted voltage as the second voltage signal VG2, i.e., a high-level output. When the third clock signal ECK3 and the fourth clock signal ECK4 control the third transistor T3 and the fourth transistor T4 to turn on, the third transistor T3 and the fourth transistor T4 output the second voltage signal VG2 (high level), then the fifth transistor T5 is turned on, outputting the second inverted voltage as the first voltage signal VG1, i.e., a low-level output, making the potential of the second control terminal Q low. When the potential of the first control terminal A is high, the first transistor T1 is turned on, outputting the first inverted voltage as the first voltage signal VG1, i.e., a low-level output. When the third clock signal ECK3 and the fourth clock signal ECK4 control the third transistor T3 and the fourth transistor T4 to turn on, the third transistor T3 and the fourth transistor T4 output the first voltage signal VG1 (low level), then the sixth transistor T6 turns on and outputs the second inverted voltage, which is the second voltage signal VG2, that is, the output is high level, so that the potential of the second control terminal Q is high level.

[0141] In another implementation, alternatively, refer to Figure 8The fifth transistor T5 is a P-type transistor, and the sixth transistor T6 is an N-type transistor.

[0142] For example, the first voltage signal VG1 is at a high level, and the second voltage signal VG2 is at a low level. After the first transmission unit 122 outputs the first inverted voltage, when the first inverted voltage is at a low level, the fifth transistor T5 is turned on, and the fifth transistor T5 outputs the second inverted voltage, which is the first voltage signal VG1. When the first inverted voltage is at a high level, the sixth transistor T6 is turned on, and the sixth transistor T6 outputs the second inverted voltage, which is the second voltage signal VG2.

[0143] like Figure 8 As shown, the working principle of the control module 120 will be explained below with reference to the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6, but this is not intended to limit the scope of this application.

[0144] When the potential of the first control terminal A is low, the first transistor T1 is turned on, outputting the first inverted voltage, which is the first voltage signal VG1, i.e., a high level output. When the third clock signal ECK3 and the fourth clock signal ECK4 control the third transistor T3 and the fourth transistor T4 to turn on, the third transistor T3 and the fourth transistor T4 output the first voltage signal VG1 (high level), then the sixth transistor T6 is turned on, outputting the second inverted voltage, which is the second voltage signal VG2, i.e., a low level output, making the potential of the second control terminal Q low. When the potential of the first control terminal A is high, the second transistor T2 is turned on, outputting the first inverted voltage, which is the second voltage signal VG2, i.e., a low level output. When the third clock signal ECK3 and the fourth clock signal ECK4 control the third transistor T3 and the fourth transistor T4 to turn on, the third transistor T3 and the fourth transistor T4 output the second voltage signal VG2 (low level). Then the fifth transistor T5 turns on and outputs the second inverted voltage, which is the first voltage signal VG1, that is, the output is high level, so that the potential of the second control terminal Q is high level.

[0145] In summary, by setting the second inverting unit 123 to include two different types of transistors to form a complementary metal-oxide-semiconductor, the second inverting unit 123 always has a voltage output regardless of whether the potential output by the first transmission unit 122 is high or low. This facilitates maintaining the potential of the second control terminal Q, thereby avoiding the leakage current from affecting the potential of the second control terminal Q and improving the accuracy of controlling the first output module 130 and the second output module 140.

[0146] Optionally, refer to Figure 7 or Figure 8 The fourth transmission unit 151 includes a seventh transistor T7;

[0147] The control electrode of the seventh transistor T7 is connected to the first clock signal ECK1, the first electrode of the seventh transistor T7 is connected to the control module 120, and the second electrode of the seventh transistor T7 is connected to the first terminal of the coupling unit 153.

[0148] For example, such as Figure 7 As shown, the seventh transistor T7 is, for example, a P-type transistor. When the first clock signal ECK1 is low, the seventh transistor T7 is turned on, and the seventh transistor T7 transmits the voltage output by the first transmission unit 122 or the third transmission unit 127 to the first terminal of the coupling unit 153.

[0149] For example, such as Figure 8 As shown, the seventh transistor T7 is, for example, an N-type transistor. When the first clock signal ECK1 is high, the seventh transistor T7 is turned on, and the seventh transistor T7 transmits the voltage output by the first transmission unit 122 or the third transmission unit 127 to the first terminal of the coupling unit 153.

[0150] Optionally, refer to Figure 7 or Figure 8 The fourth transmission unit 151 also includes an eighth transistor T8;

[0151] The control electrode of the eighth transistor T8 is connected to the second voltage signal VG2, and the eighth transistor T8 is connected between the second electrode of the seventh transistor T7 and the first terminal of the coupling unit 153.

[0152] Specifically, the eighth transistor T8 is normally open, for example. By setting the eighth transistor T8, the transmission of ultra-low or ultra-high levels from the first end of the coupling unit 153 to the third transmission unit 127 and the first transmission unit 122 can be prevented, and damage to the first transmission unit 122 and the third transmission unit 127 can be prevented from being caused by ultra-low or ultra-high levels.

[0153] Optionally, refer to Figure 7 or Figure 8 The fifth transmission unit 152 includes a ninth transistor T9;

[0154] The control electrode of the ninth transistor T9 is connected to the fourth transmission unit 151, the first electrode of the ninth transistor T9 is connected to the first clock signal ECK1, and the second electrode of the ninth transistor T9 is connected to the second terminal of the coupling unit 153.

[0155] Specifically, such as Figure 7 As shown, the ninth transistor T9 is an N-type transistor. When the potential of the first terminal of the fourth transmission unit 151 transmitted to the coupling unit 153 is high, the ninth transistor T9 is turned on and transmits the first clock signal ECK1 to the second terminal of the coupling unit 153.

[0156] like Figure 8 As shown, the ninth transistor T9 is a P-type transistor. When the potential of the first terminal of the fourth transmission unit 151 transmitted to the coupling unit 153 is low, the ninth transistor T9 is turned on and transmits the first clock signal ECK1 to the second terminal of the coupling unit 153.

[0157] Optionally, refer to Figure 7 or Figure 8 The coupling unit 153 includes a capacitor C1;

[0158] The first electrode of capacitor C1 is the first terminal of coupling unit 153, and the second electrode of capacitor C1 is the second terminal of coupling unit 153.

[0159] Optionally, refer to Figure 7 or Figure 8 The switching unit 154 includes a tenth transistor T10;

[0160] The control electrode of the tenth transistor T10 is connected to the fourth transmission unit 151, the first electrode of the tenth transistor T10 is connected to the first end of the coupling unit 153, and the second electrode of the tenth transistor T10 is connected to the second control terminal Q.

[0161] Specifically, such as Figure 7 As shown, by configuring capacitor C1 and the tenth transistor T10, after the seventh transistor T7 transmits a high level to the first terminal of capacitor C1 and the ninth transistor T9 transmits a low level to the second terminal of capacitor C1, the voltage difference across capacitor C1 is the high level minus the low level. When the first clock signal ECK1 transitions from low to high, the potential at the first terminal of capacitor C1 increases. Since the voltage difference across capacitor C1 remains constant, the potential at the first terminal of capacitor C1 becomes an ultra-high level, controlling the tenth transistor T10 to conduct. Thus, the tenth transistor T10 transmits the ultra-high level to the third control terminal QB, achieving coupled control of the third control terminal QB.

[0162] like Figure 8 As shown, by configuring capacitor C1 and the tenth transistor T10, after the seventh transistor T7 transmits a low level to the first terminal of capacitor C1 and the ninth transistor T9 transmits a high level to the second terminal of capacitor C1, the voltage difference across capacitor C1 is the high level minus the low level. When the first clock signal ECK1 transitions from high to low, the potential at the first terminal of capacitor C1 decreases. Since the voltage difference across capacitor C1 remains constant, the potential at the first terminal of capacitor C1 becomes an ultra-low level, controlling the tenth transistor T10 to conduct. Thus, the tenth transistor T10 transmits the ultra-low level to the third control terminal QB, achieving coupled control of the third control terminal QB.

[0163] Optionally, refer to Figure 7 or Figure 8The initialization unit 155 includes an eleventh transistor T11, the control terminal of the eleventh transistor T11 is the control terminal of the initialization unit 155, the first terminal of the eleventh transistor T11 is the first terminal of the initialization unit 155, and the second terminal of the eleventh transistor T11 is the second terminal of the initialization unit 155.

[0164] Optionally, refer to Figure 7 or Figure 8 The third inverting unit 124 includes a twelfth transistor T12 and a thirteenth transistor T13. The control terminals of the twelfth transistor T12 and the thirteenth transistor T13 are the control terminals of the third inverting unit 124. The first terminal of the twelfth transistor T12 is connected to the first voltage signal VG1. The first terminal of the thirteenth transistor T13 is connected to the second terminal of the twelfth transistor T12. The second terminal of the thirteenth transistor T13 is connected to the second voltage signal VG2.

[0165] In one implementation, alternatively, such as Figure 7 As shown, the twelfth transistor T12 is an N-type transistor, and the thirteenth transistor T13 is a P-type transistor.

[0166] In another implementation, alternatively, such as Figure 8 As shown, the twelfth transistor T12 is a P-type transistor, and the thirteenth transistor T13 is an N-type transistor.

[0167] Optionally, refer to Figure 7 or Figure 8 The second transmission unit 125 includes a fourteenth transistor T14 and a fifteenth transistor T15. The control electrode of the fourteenth transistor T14 is connected to the second clock signal ECK2. The first electrode of the fourteenth transistor T14 is connected to the output terminal of the third inverting unit 124, and the second electrode of the fourteenth transistor T14 is connected to the first control terminal A. The control electrode of the fifteenth transistor T15 is connected to the first clock signal ECK1. The first electrode of the fifteenth transistor T15 is connected to the output terminal of the third inverting unit 124, and the second electrode of the fifteenth transistor T15 is connected to the first control terminal A.

[0168] In one implementation, alternatively, such as Figure 7 As shown, the fourteenth transistor T14 is an N-type transistor, and the fifteenth transistor T15 is a P-type transistor.

[0169] In another implementation, alternatively, such as Figure 8 As shown, the fourteenth transistor T14 is a P-type transistor, and the fifteenth transistor T15 is an N-type transistor.

[0170] Optionally, refer to Figure 7 or Figure 8The input module 110 includes a sixteenth transistor T16 and a seventeenth transistor T17; the control electrode of the sixteenth transistor T16 is connected to the first clock signal ECK1, the first electrode of the sixteenth transistor T16 is connected to the input signal EIN, and the second electrode of the sixteenth transistor T16 is connected to the first control terminal A; the control electrode of the seventeenth transistor T17 is connected to the second clock signal ECK2, the first electrode of the seventeenth transistor T17 is connected to the input signal EIN, and the second electrode of the seventeenth transistor T17 is connected to the first control terminal A.

[0171] In one implementation, alternatively, such as Figure 7 As shown, the sixteenth transistor T16 is an N-type transistor, and the seventeenth transistor T17 is a P-type transistor.

[0172] In another implementation, alternatively, such as Figure 8 As shown, the sixteenth transistor T16 is a P-type transistor, and the seventeenth transistor T17 is an N-type transistor.

[0173] Optionally, refer to Figure 7 or Figure 8 The fourth inverting unit 126 includes an eighteenth transistor T18 and a nineteenth transistor T19. The control terminals of the eighteenth transistor T18 and the nineteenth transistor T19 are connected to the second control terminal Q. The first terminal of the eighteenth transistor T18 is connected to the first voltage signal VG1. The first terminal of the nineteenth transistor T19 is connected to the second terminal of the eighteenth transistor T18. The second terminal of the nineteenth transistor T19 is connected to the second voltage signal VG2.

[0174] In one implementation, alternatively, such as Figure 7 As shown, the eighteenth transistor T18 is an N-type transistor, and the nineteenth transistor T19 is a P-type transistor.

[0175] In another implementation, alternatively, such as Figure 8 As shown, the eighteenth transistor T18 is a P-type transistor, and the nineteenth transistor T19 is an N-type transistor.

[0176] Optionally, refer to Figure 7 or Figure 8 The third transmission unit 127 includes a twentieth transistor T20 and a twenty-first transistor T21; the control terminal of the twentieth transistor T20 is connected to a fourth clock signal ECK4, the first terminal of the twentieth transistor T20 is connected to a fourth inverting unit 126, and the second terminal of the twentieth transistor T20 is connected to the control terminal of a second inverting unit 123; the control terminal of the twenty-first transistor T21 is connected to a third clock signal ECK3, the first terminal of the twenty-first transistor T21 is connected to a fourth inverting unit 126, and the second terminal of the twenty-first transistor T21 is connected to the control terminal of a second inverting unit 123.

[0177] In one implementation, alternatively, such as Figure 7 As shown, the twentieth transistor T20 is an N-type transistor, and the twenty-first transistor T21 is a P-type transistor.

[0178] In another implementation, alternatively, such as Figure 8 As shown, the twentieth transistor T20 is a P-type transistor, and the twenty-first transistor T21 is an N-type transistor.

[0179] In summary, the technical solution of this embodiment, by setting each inverting unit to include two different types of transistors, can form a complementary metal-oxide-semiconductor system, ensuring a constant level output and helping to maintain the potential of each node. Furthermore, by including two different types of transistors in each transmission unit, the leakage current of the P-type transistor can be reduced, thus lowering power loss.

[0180] Optionally, refer to Figure 7 or Figure 8 The first output module 130 includes a 22nd transistor T22, the control terminal of the 22nd transistor T22 is the second control terminal Q, the first terminal of the 22nd transistor T22 is connected to a first voltage signal, and the second terminal of the 22nd transistor T22 is the output terminal OUT of the gate drive circuit.

[0181] Optionally, refer to Figure 7 or Figure 8 The second output module 140 includes a twenty-third transistor T23. The control electrode of the twenty-third transistor T23 is connected to the first transmission unit 122. The first electrode of the twenty-third transistor T23 is connected to the second voltage signal VG2. The second electrode of the twenty-third transistor T23 is the output terminal OUT of the gate drive circuit.

[0182] Optionally, refer to Figure 7 or Figure 8 The reset module 160 includes a twenty-fourth transistor T24. The control electrode of the twenty-fourth transistor T24 is connected to the reset control signal RST, the first electrode of the twenty-fourth transistor T24 is connected to the first reset signal V1, and the second electrode of the twenty-fourth transistor T24 is connected to the second output module 140 and the control module 120.

[0183] Optionally, refer to Figure 7 or Figure 8 The gate drive circuit also includes a twenty-fifth transistor T25, the control input of the twenty-fifth transistor T25 is the second voltage signal VG2, and the twenty-fifth transistor T25 is connected between the first transmission unit 122 and the third control terminal QB of the second output module 140.

[0184] The timing diagram below illustrates the operation of the gate drive circuit, but this is not intended to limit the scope of this application.

[0185] Figure 9 This is a timing diagram of a gate driving circuit provided in an embodiment of the present invention. The following is in conjunction with... Figure 7 and Figure 9 The timing sequence of the gate drive circuit is explained. Figure 7 In the above, the first voltage signal VG1 is at a low level, and the second voltage signal VG2 is at a high level.

[0186] In the first stage t1, the input signal EIN is high, the first clock signal ECK1 is high, the second clock signal ECK2 is low, the third clock signal ECK3 is low, and the fourth clock signal ECK4 is high. The sixteenth transistor T16 and the seventeenth transistor T17 are turned on, outputting the input signal EIN to the first control terminal A. Therefore, the first control terminal A is high, the first transistor T1 is turned on, and the first inverted voltage is the first voltage signal VG1, i.e., the output is low. The third transistor T3 and the fourth transistor T4 are turned off, so the twenty-second transistor T22 and the twenty-third transistor T23 are not turned on, maintaining the output state of the previous stage.

[0187] In the second stage t2, the input signal EIN is low, the first clock signal ECK1 is low, the second clock signal ECK2 is high, the third clock signal ECK3 is high, and the fourth clock signal ECK4 is low. The sixteenth transistor T16 and the seventeenth transistor T17 are off, the first control terminal A remains high, and the first inverting voltage remains low. The thirteenth transistor T13 is on, outputting the second inverting voltage as the second voltage signal VG2, i.e., a high output. The fourteenth transistor T14 and the fifteenth transistor T15 are on, outputting a high level to the first control terminal A. This strengthens the low level of the first control terminal A, preventing its potential from changing due to leakage, thus maintaining the low level output by the first transistor T1. The third transistor T3 and the fourth transistor T4 are on, outputting a low level to the third control terminal QB and the second inverting unit 123, while the twenty-third transistor T23 is off. When the sixth transistor T6 is turned on, it outputs the second inverted voltage as the second voltage signal VG2, making the potential of the second control terminal QB high. Then, the twenty-second transistor T22 is turned on, outputting the first voltage signal VG1, and the gate drive circuit outputs the gate drive signal Vout low.

[0188] Since the potential of the first control terminal A is high, the eleventh transistor T11 is turned on, transmitting the first voltage signal VG1 to the second terminal of capacitor C1. The second terminal of capacitor C1 is then at a low level, thus initializing the second terminal of capacitor C1. Since the first clock signal ECK1 is low, the seventh transistor T7 is turned on, transmitting the low-level outputs of the third transistor T3 and the fourth transistor T4 to the first terminal of capacitor C1, thus initializing the first terminal of capacitor C1.

[0189] In the third stage t3, the input signal EIN is low, the first clock signal ECK1 is high, the second clock signal ECK2 is low, the third clock signal ECK3 is low, and the fourth clock signal ECK4 is high. The sixteenth transistor T16 and the seventeenth transistor T17 are turned on, outputting the input signal EIN to the first control terminal A, making terminal A low. The second transistor T2 is turned on, outputting the first inverted voltage as the second voltage signal VG2, i.e., a high output. The third transistor T3 and the fourth transistor T4 are not turned on. The second control terminal Q remains high. The eighteenth transistor T18 is turned on, outputting the first voltage signal VG1 as the first inverted voltage, i.e., a low output. The twentieth transistor T20 and the twenty-first transistor T21 are turned on, outputting the low level to the control terminal of the second inverting unit 123, maintaining the output of the second voltage signal VG2 from the sixth transistor T6 to the second control terminal Q, thus maintaining the high level of the second control terminal Q. If the 22nd transistor T22 remains on and outputs the first voltage signal VG1, then the gate drive circuit outputs a low gate drive signal Vout.

[0190] In this way, the potential of the second control terminal Q is maintained, preventing its change due to leakage current. This facilitates accurate control of the twenty-second transistor T22, thereby improving the accuracy of the gate drive signal and enabling accurate control of the pixel circuit. This allows the pixel circuit to output accurate drive current, improving the accuracy of the light-emitting duration and timing of the light-emitting device, ultimately enhancing the display effect of the display panel. Furthermore, no additional capacitor is needed to maintain the potential of the second control terminal Q, reducing circuit costs.

[0191] In the fourth stage t4, the input signal EIN is low, the first clock signal ECK1 is low, the second clock signal ECK2 is high, and the third clock signal ECK3 is high. The sixteenth transistor T16 and the seventeenth transistor T17 are turned off, maintaining the potential of the first control terminal A at a low level. The second transistor T2 outputs the second voltage signal VG2, i.e., a high level. Then, the twelfth transistor T12 turns on, outputting the first voltage signal VG1, i.e., a low level. The fourteenth transistor T14 and the fifteenth transistor T15 turn on, outputting a low level to the first control terminal A, thereby strengthening the potential of the first control terminal A and preventing its potential from changing due to leakage, thus maintaining the high level output of the second transistor T2. The third transistor T3 and the fourth transistor T4 turn on, outputting a high level to the second inverting unit 123 and the third control terminal QB. The fifth transistor T5 in the second inverting unit 123 is turned on, outputting the second inverted voltage, which is the first voltage signal VG1. Therefore, the potential of the second control terminal Q is low, and the twenty-second transistor T22 is turned off. Since the potential of the third control terminal QB is high, the twenty-third transistor T23 is turned on, outputting the second voltage signal VG2. Therefore, the gate drive circuit outputs the gate drive signal Vout, which is high.

[0192] Since the first clock signal ECK1 is low, the seventh transistor T7 is turned on, transmitting the high-level outputs of the third transistor T3 and the fourth transistor T4 to the first terminal of capacitor C1. This causes the ninth transistor T9 and the tenth transistor T10 to turn on. The ninth transistor T9 then transmits the first clock signal ECK1 to the second terminal of capacitor C1, making the second terminal of capacitor C1 low. The voltage difference across capacitor C1 is the high-level signal minus the low-level signal.

[0193] In the fifth stage t5, the input signal EIN is low, the first clock signal ECK1 is high, the second clock signal ECK2 is low, the third clock signal ECK3 is low, and the fourth clock signal ECK4 is high. The sixteenth transistor T16 and the seventeenth transistor T17 are turned on, outputting the input signal EIN to the first control terminal A. The potential of the first control terminal A is then low. The second transistor T2 is turned on, outputting the second voltage signal VG2 as the first inverting voltage. The third transistor T3 and the fourth transistor T4 are turned off, not outputting the first inverting voltage. The potential of the second control terminal Q remains low. The nineteenth transistor T19 is turned on, outputting the second voltage signal VG2, i.e., a high level output. The twentieth transistor T20 and the twenty-first transistor T21 transmit the high level to the control terminal of the second inverting unit 123 and the third control terminal QB, thereby maintaining the potential of the control terminal of the second inverting unit 123 and the third control terminal QB, and consequently keeping the twenty-second transistor T22 off.

[0194] The first terminal of capacitor C1 remains at a high level, and the ninth transistor T9 and the tenth transistor T10 are turned on. The ninth transistor T9 outputs the first clock signal ECK1 to the second terminal of capacitor C1, so the second terminal of capacitor C1 changes from a low level to a high level. The voltage difference across capacitor C1 remains unchanged, so the first terminal of capacitor C1 becomes ultra-high level. The tenth transistor T10 transmits the ultra-high level to the third control terminal QB, and couples and controls the third control terminal QB to make the third control terminal QB ultra-high level, thereby keeping the twenty-third transistor T23 on and outputting the second voltage signal VG2, that is, the gate drive circuit outputs the gate drive signal Vout at a high level.

[0195] Figure 10 This is a timing diagram of another gate driving circuit provided in an embodiment of the present invention. The following is in conjunction with... Figure 8 and Figure 10 The timing sequence of the gate drive circuit is explained. Figure 8 In the above, the first voltage signal VG1 is at a high level, and the second voltage signal VG2 is at a low level.

[0196] In the first stage t1', the input signal EIN is low, the first clock signal ECK1 is low, the second clock signal ECK2 is high, the third clock signal ECK3 is high, and the fourth clock signal ECK4 is low. The sixteenth transistor T16 and the seventeenth transistor T17 are turned on, outputting the input signal EIN. Therefore, the potential of the first control terminal A is low, and the first transistor T1 is turned on, outputting the first inverted voltage, the first voltage signal VG1, i.e., a high output. The fourteenth transistor T14 and the fifteenth transistor T15 are turned off, not transmitting the second inverted voltage to the first control terminal A. Since the third transistor T3 and the fourth transistor T4 are not turned on, the twenty-second transistor T22 and the twenty-third transistor T23 are not turned on, maintaining the output state of the previous stage.

[0197] In the second stage t2', the input signal EIN is high, the first clock signal ECK1 is high, the second clock signal ECK2 is low, the third clock signal ECK3 is low, and the fourth clock signal ECK4 is high. The sixteenth transistor T16 and the seventeenth transistor T17 are off, maintaining the potential of the first control terminal A at a low level. The first inverting voltage remains high, so the thirteenth transistor T13 is turned on, outputting the second inverting voltage as the second voltage signal VG2, i.e., a low output level. The fourteenth transistor T14 and the fifteenth transistor T15 are turned on, transmitting the low level to the first control terminal A. This strengthens the low level of the first control terminal A, preventing its potential from changing due to leakage, thus maintaining the high level output by the first transistor T1. The third transistor T3 and the fourth transistor T4 are turned on, outputting a high level to the second inverting unit 123 and the third control terminal QB, while the twenty-third transistor T23 is turned off. The sixth transistor T6 in the second inverting unit 123 is turned on, and the second inverted voltage is the second voltage signal VG2, that is, the output is low level to the second control terminal Q. The twenty-second transistor T22 is turned on, and the first voltage signal VG1 is output. Then the gate drive circuit outputs the gate drive signal Vout as high level.

[0198] When the first control terminal A is low, the eleventh transistor T11 is turned on, transmitting the first voltage signal VG1 to the second terminal of capacitor C1, i.e., the second terminal of capacitor C1 is high, thus initializing the second terminal of capacitor C1. Since the first clock signal ECK1 is high, the seventh transistor T7 is turned on, transmitting the high-level outputs of the third transistor T3 and the fourth transistor T4 to the first terminal of capacitor C1, thus initializing the first terminal of capacitor C1. Meanwhile, the ninth transistor T9 and the tenth transistor T10 are turned off, and will not be coupled to the third control terminal QB for control.

[0199] In the third stage t3', the input signal EIN is high, the first clock signal ECK1 is low, the second clock signal ECK2 is high, the third clock signal ECK3 is high, and the fourth clock signal ECK4 is low. The sixteenth transistor T16 and the seventeenth transistor T17 are turned on, outputting the input signal EIN to the first control terminal A. The first control terminal A is then high, and the second transistor T2 is turned on, outputting the second voltage signal VG2 as the first inverting voltage. The third transistor T3 and the fourth transistor T4 are not turned on. The control terminal of the second inverting unit 123 maintains the high level of the previous stage, and the second control terminal Q maintains the low level of the previous stage. The eighteenth transistor T18 is turned on, outputting the first voltage signal VG1, i.e., a low level output. The twentieth transistor T20 and the twenty-first transistor T21 are turned on, transmitting the low level to the control terminal of the second inverting unit 123, thereby strengthening the potential of the control terminal of the second inverting unit 123, and further strengthening the potential of the second control terminal Q. The twenty-second transistor T22 is kept on, outputting the first voltage signal VG1. Then the gate drive circuit outputs the gate drive signal Vout as a high level.

[0200] In this way, the potential of the second control terminal Q is maintained, preventing its change due to leakage current. This facilitates accurate control of the twenty-second transistor T22, thereby improving the accuracy of the gate drive signal and enabling accurate control of the pixel circuit. This allows the pixel circuit to output accurate drive current, improving the accuracy of the light-emitting duration and timing of the light-emitting device, ultimately enhancing the display effect of the display panel. Furthermore, no additional capacitor is needed to maintain the potential of the second control terminal Q, reducing circuit costs.

[0201] In the fourth stage t4', the input signal EIN is high, the first clock signal ECK1 is high, the second clock signal ECK2 is low, the third clock signal ECK3 is low, and the fourth clock signal ECK4 is high. The sixteenth transistor T16 and the seventeenth transistor T17 are turned off, the first control terminal A remains high, the second transistor T2 outputs the second voltage signal VG2 (i.e., the first inverting voltage remains low), the twelfth transistor T12 is turned on, outputting the first voltage signal VG1 (i.e., a high output), and the fourteenth transistor T14 and the fifteenth transistor T15 are turned on, transmitting the high level to the first control terminal A, strengthening the potential of the first control terminal A, and preventing the potential of the first control terminal A from changing due to leakage, thereby maintaining the low level output by the second transistor T2. The third transistor T3 and the fourth transistor T4 are turned on, transmitting a low level to the second inverting unit 123 and the third control terminal QB. The fifth transistor T5 is turned on, outputting the second inverted voltage, which is the first voltage signal VG1. Therefore, the potential of the second control terminal Q is high, and the twenty-second transistor T22 is turned off. With the third control terminal QB low, the twenty-third transistor T23 is turned on, outputting the second voltage signal VG2. Therefore, the gate drive circuit outputs the gate drive signal Vout low.

[0202] When the first clock signal ECK1 is high, the seventh transistor T7 is turned on, transmitting the low level output by the third transistor T3 and the fourth transistor T4 to the first terminal of capacitor C1. The first terminal of capacitor C1 is low, and the ninth transistor T9 is turned on, transmitting the high level of the first clock signal ECK1 to the second terminal of capacitor C1. The voltage difference across capacitor C1 is the high level minus the low level.

[0203] In the fifth stage t5', the input signal EIN is high, the first clock signal ECK1 is low, the second clock signal ECK2 is high, the third clock signal ECK3 is high, and the fourth clock signal ECK4 is low. The sixteenth transistor T16 and the seventeenth transistor T17 are turned on, transmitting the high level to the first control terminal A. The second transistor T2 outputs the second voltage signal VG2, i.e., a low level. However, the third transistor T3 and the fourth transistor T4 are turned off, and no voltage is output.

[0204] When the first terminal of capacitor C1 remains at a low level, transistors T9 and T10 are turned on. Transistor T9 transmits the first clock signal ECK1 to the second terminal of capacitor C1, meaning the second terminal of capacitor C1 changes from a high level to a low level. This causes the first terminal of capacitor C1 to become ultra-low, and transistor T10 turns on, transmitting the ultra-low level to the third control terminal QB. This keeps transistor T23 on, outputting the second voltage signal VG2, meaning the gate drive circuit outputs the gate drive signal Vout at a low level.

[0205] The present invention also provides a display panel, Figure 11 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, for reference. Figure 11 The display panel 100 includes the gate driving circuit provided in any of the above embodiments. Multiple gate driving circuits 10 are cascaded, and the input signal EIN of the nth-stage gate driving circuit 10 is provided by the output signal OUT of the (n-1)th-stage gate driving circuit 10, where n is a positive integer greater than or equal to 2. The input signal EIN of the first-stage gate driving circuit 10 can be provided by an external device. The display panel can be, for example, a display panel on a mobile phone, tablet, MP3 player, MP4 player, smartwatch, smart helmet, or other wearable device. Because the display panel of this embodiment includes the gate driving circuit provided in any of the above embodiments, the display panel of this embodiment has the same beneficial effects as the gate driving circuit provided in any of the above embodiments, and will not be described again here.

[0206] For example, such as Figure 11 As shown, the display panel 100 also includes a first clock signal line CLK1, a second clock signal line CLK2, a third clock signal line CLK3, and a fourth clock signal line CLK4. The first clock signal line CLK1 is used to provide a first clock signal ECK1 to the m-th gate drive circuit 10. The second clock signal line CLK2 is used to provide a second clock signal ECK2 to the m-th gate drive circuit 10. The third clock signal line CLK3 is used to provide a third clock signal ECK3 to the m-th gate drive circuit 10. The fourth clock signal line CLK4 is used to provide a first clock signal ECK1 to the m-th gate drive circuit 10. A fourth clock signal ECK4 is provided to the m-th gate drive circuit 10; a first clock signal line CLK1 is used to provide a third clock signal ECK3 to the (m+1)-th gate drive circuit 10; a second clock signal line CLK2 is used to provide a fourth clock signal ECK4 to the (m+1)-th gate drive circuit 10; a third clock signal line CLK3 is used to provide a first clock signal ECK1 to the (m+1)-th gate drive circuit 10; and a fourth clock signal line CLK4 is used to provide a second clock signal ECK2 to the (m+1)-th gate drive circuit 10. Here, m is a positive integer greater than or equal to 1, and m is an odd number. The second clock signal ECK2 of the second clock signal line CLK2 can be obtained by inverting the signal provided by the first clock signal line CLK1, and the fourth clock signal ECK4 of the fourth clock signal line CLK4 can be obtained by inverting the signal provided by the third clock signal line CLK3.

[0207] For example, such as Figure 11 As shown, the display panel also includes multiple pixel circuits 20 arranged in an array, such as... Figure 1The pixel circuit is shown. The output terminal OUT of each stage of the gate drive circuit is connected to a row of pixel circuits 20 to control the transistors in the pixel circuits 20, thereby controlling the light emission timing or light emission duration of the light-emitting devices corresponding to the pixel circuits 20.

[0208] It should be noted that in the above embodiments, the first electrode of each transistor can be the source or the drain, and correspondingly, the second electrode can be the drain or the source.

[0209] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A gate driving circuit, characterized in that, include: An input module receives an input signal and outputs the input signal in response to a first clock signal and a second clock signal. The system includes a control module and a first output module. The first control terminal of the control module is connected to the input module, and the output terminal of the control module is connected to the second control terminal of the first output module. The control module is configured to output a first inverted voltage in response to the potential of the first control terminal at each time period during which the gate drive signal is generated, and to output a second inverted voltage to the second control terminal in response to a third clock signal and a fourth clock signal. The first output module is configured to turn on or off based on the second inverted voltage, and to output a first voltage signal when on, so as to output the gate drive signal. The second output module is connected to the control module and is used to turn on or off based on the first inverting voltage, and output a second voltage signal when on to output the gate drive signal; The control module includes: a first inverting unit, a first transmission unit, and a second inverting unit; The control terminal of the first inverting unit is the first control terminal, the first terminal of the first inverting unit is connected to the first voltage signal, the second terminal of the first inverting unit is connected to the second voltage signal, and the first inverting unit is used to convert the voltage of the first control terminal into the first inverted voltage. The first transmission unit is connected between the output terminal of the first inverting unit and the control terminal of the second inverting unit. The first transmission unit is used to transmit the first inverted voltage to the second inverting unit in response to the third clock signal and the fourth clock signal. The first terminal of the second inverting unit is connected to the first voltage signal, the second terminal of the second inverting unit is connected to the second voltage signal, the output terminal of the second inverting unit is connected to the second control terminal, and the second inverting unit is used to convert the first inverted voltage into the second inverted voltage. The third control terminal of the second output module is connected to the first transmission unit.

2. The gate driving circuit according to claim 1, characterized in that, The control module also includes: The third inverting unit has its control terminal connected to the output terminal of the first inverting unit. The first terminal of the third inverting unit is connected to the first voltage signal, and the second terminal of the third inverting unit is connected to the second voltage signal. The third inverting unit is used to convert the first inverted voltage into the second inverted voltage. The second transmission unit is connected between the output terminal of the third inverting unit and the first control terminal, and is used to transmit the second inverted voltage to the first control terminal in response to the first clock signal and the second clock signal.

3. The gate driving circuit according to claim 2, characterized in that, The second transmission unit is turned off when the input module is turned on, and turned on when the input module is turned off.

4. The gate driving circuit according to claim 2, characterized in that, The control module also includes: The fourth inverting unit has its control terminal connected to the output terminal of the second inverting unit. The first terminal of the fourth inverting unit is connected to the first voltage signal, and the second terminal of the fourth inverting unit is connected to the second voltage signal. The fourth inverting unit is used to convert the second inverted voltage into the first inverted voltage. The third transmission unit is connected between the output terminal of the fourth inverting unit and the control terminal of the second inverting unit, and is used to transmit the first inverted voltage to the control terminal of the second inverting unit in response to the third clock signal and the fourth clock signal.

5. The gate driving circuit according to claim 4, characterized in that, The third transmission unit is turned off when the first transmission unit is turned on, and turned on when the third transmission unit is turned off.

6. The gate driving circuit according to claim 1, characterized in that, The first inverting unit includes a first transistor and a second transistor; The control terminal of the first transistor is the first control terminal, the first terminal of the first transistor is connected to the first voltage signal, and the second terminal of the first transistor is connected to the first transmission unit. The control terminal of the second transistor is the first control terminal, the first terminal of the second transistor is connected to the second voltage signal, and the second terminal of the second transistor is connected to the first transmission unit.

7. The gate driving circuit according to claim 6, characterized in that, The first transistor is an N-type transistor and the second transistor is a P-type transistor; or, the first transistor is a P-type transistor and the second transistor is an N-type transistor.

8. The gate driving circuit according to claim 1, characterized in that, The first transmission unit includes a third transistor and a fourth transistor; The control terminal of the third transistor is connected to the third clock signal, the first terminal of the third transistor is connected to the output terminal of the first inverting unit, and the second terminal of the third transistor is connected to the control terminal of the second inverting unit. The control terminal of the fourth transistor is connected to the fourth clock signal, the first terminal of the fourth transistor is connected to the output terminal of the first inverting unit, and the second terminal of the fourth transistor is connected to the control terminal of the second inverting unit.

9. The gate driving circuit according to claim 8, characterized in that, The third transistor is an N-type transistor and the fourth transistor is a P-type transistor; or, the third transistor is a P-type transistor and the fourth transistor is an N-type transistor.

10. The gate driving circuit according to claim 1, characterized in that, During the same period, the voltage corresponding to the third clock signal and the voltage corresponding to the fourth clock signal are out of phase.

11. The gate driving circuit according to claim 1, characterized in that, The second inverting unit includes a fifth transistor and a sixth transistor; The control electrode of the fifth transistor is connected to the first transmission unit, the first electrode of the fifth transistor is connected to the first voltage signal, and the second electrode of the fifth transistor is connected to the second control terminal. The control electrode of the sixth transistor is connected to the first transmission unit, the first electrode of the sixth transistor is connected to the second voltage signal, and the second electrode of the sixth transistor is connected to the second control terminal.

12. The gate driving circuit according to claim 11, characterized in that, The fifth transistor is an N-type transistor and the sixth transistor is a P-type transistor; or, the fifth transistor is a P-type transistor and the sixth transistor is an N-type transistor.

13. The gate driving circuit according to claim 1, characterized in that, Also includes: The coupling module is connected to the third control terminal of the control module and the second output module respectively, and is used to couple and control the potential of the third control terminal based on the transition from the first level to the second level of the first clock signal, so as to maintain the output of the second voltage signal by the second output module.

14. The gate driving circuit according to claim 13, characterized in that, The coupling module includes a fourth transmission unit, a fifth transmission unit, a coupling unit, and a switching unit; The fourth transmission unit is connected between the control module and the first end of the coupling unit. The fourth transmission unit is used to respond to the first clock signal and transmit the first inverted voltage to the first end of the coupling unit. The control terminal of the fifth transmission unit is connected to the fourth transmission unit. The first terminal of the fifth transmission unit is connected to the first clock signal. The second terminal of the fifth transmission unit is connected to the second terminal of the coupling unit. The fifth transmission unit is used to transmit the voltage corresponding to the first clock signal to the second terminal of the coupling unit in response to the first inverted voltage. The coupling unit is used to couple the second end of the coupling unit when the first level of the first clock signal transitions to the second level; The control terminal of the switching unit is connected to the fourth transmission unit, the first terminal of the switching unit is connected to the first terminal of the coupling unit, and the second terminal of the switching unit is connected to the second control terminal. The switching unit is used to transmit the potential coupled from the second terminal of the coupling unit to the third control terminal.

15. The gate driving circuit according to claim 14, characterized in that, The voltage corresponding to the first level is the same as the first voltage signal, and the voltage corresponding to the second level is the same as the second voltage signal.

16. The gate driving circuit according to claim 14, characterized in that, The coupling module further includes an initialization unit; The control terminal of the initialization unit is connected to the first control terminal, the first terminal of the initialization unit is connected to the first voltage signal, and the second terminal of the initialization unit is connected to the second terminal of the coupling unit; the initialization unit is used to respond to the potential of the first control terminal and transmit the first voltage signal to the second terminal of the coupling unit.

17. The gate driving circuit according to claim 14, characterized in that, The fourth transmission unit includes a seventh transistor; The control electrode of the seventh transistor is connected to the first clock signal, the first electrode of the seventh transistor is connected to the control module, and the second electrode of the seventh transistor is connected to the first end of the coupling unit.

18. The gate driving circuit according to claim 17, characterized in that, The fourth transmission unit further includes an eighth transistor; The control electrode of the eighth transistor is connected to the second voltage signal, and the eighth transistor is connected between the second electrode of the seventh transistor and the first terminal of the coupling unit.

19. The gate driving circuit according to claim 14, characterized in that, The fifth transmission unit includes a ninth transistor; The control electrode of the ninth transistor is connected to the fourth transmission unit, the first electrode of the ninth transistor is connected to the first clock signal, and the second electrode of the ninth transistor is connected to the second end of the coupling unit.

20. The gate driving circuit according to claim 14, characterized in that, The coupling unit includes a capacitor; The first terminal of the capacitor is the first end of the coupling unit, and the second terminal of the capacitor is the second end of the coupling unit.

21. The gate driving circuit according to claim 14, characterized in that, The switching unit includes a tenth transistor; The control electrode of the tenth transistor is connected to the fourth transmission unit, the first electrode of the tenth transistor is connected to the first end of the coupling unit, and the second electrode of the tenth transistor is connected to the second control terminal.

22. The gate driving circuit according to claim 1, characterized in that, Also includes: A reset module, connected to the second output module and the control module, is used to respond to a reset control signal and transmit a reset signal to the second output module and the control module.

23. A display panel, characterized in that, include: The gate drive circuit according to any one of claims 1-22.

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