Scan driving circuit and display panel

Abstract

The application discloses a scanning driving circuit and a display panel, and belongs to the technical field of display. The scanning driving circuit comprises a plurality of first shift registers, a plurality of transmission control modules and a plurality of second shift registers; the first shift register is used for shifting a signal inputted into an input end of the first shift register and outputting a stage transmission signal; wherein, an output end of a current first shift register is connected with an input end of a next first shift register; input ends of the plurality of transmission control modules are respectively connected with output ends of at least part of the first shift registers; the transmission control module is used for outputting the stage transmission signal when turned on; input ends of the plurality of second shift registers are respectively connected with output ends of the plurality of transmission control modules; and the second shift register is used for outputting a scanning signal according to a signal inputted into the input end of the second shift register. The embodiment of the application can make the display panel support the partition multi-frequency display function.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a scanning driving circuit and a display panel. Background Technology

[0002] With the development of display technology, the application scenarios of display panels are becoming increasingly diverse, and users' display needs are also becoming more varied. For users who require simultaneous display of multiple application scenarios on their terminal products, some interfaces (such as game interfaces) need to be displayed at high frequencies to ensure smooth visuals, while other interfaces can meet display requirements with low frequencies, which would reduce product power consumption. However, existing scanning drive circuits can only provide timing at the same frequency to drive pixel circuits, supporting only the full-screen switching frequency of the display panel. This cannot meet users' needs for displaying multiple scenarios on a single screen, nor can it achieve multi-frequency, zoned display within a single screen. Summary of the Invention

[0003] This invention provides a scanning drive circuit and a display panel to enable the display panel to support multi-frequency zone display function.

[0004] In a first aspect, embodiments of the present invention provide a scanning driving circuit, comprising:

[0005] Multiple first shift registers; the first shift registers are used to shift the signals input to the input of the first shift register and output the signals; wherein, the output of the first shift register of this stage is connected to the input of the first shift register of the next stage;

[0006] Multiple transmission control modules are provided, with their input terminals respectively connected to at least a portion of the output terminals of the first shift register; the transmission control modules are used to output stage transmission signals when the circuit is turned on.

[0007] Multiple second shift registers are provided, with their inputs connected to the outputs of multiple transmission control modules respectively. The second shift registers are used to output scanning signals based on the signals input to their inputs.

[0008] Optionally, the first shift register is used to shift the signal input to the first shift register and output a transmission signal according to the signals input to the first clock terminal and / or the first inverting clock terminal and the second clock terminal of the first shift register; wherein the signals input to the first clock terminal and the first inverting clock terminal are inverted signals; optionally, the first shift register includes: a first input unit, the input terminal of the first input unit is connected to the input terminal of the first shift register, the first control terminal of the first input unit is connected to the first clock terminal, and / or, the second control terminal of the first input unit is connected to the first inverting clock terminal; the first input unit is used to control whether to output the signal input to the first shift register according to the potential of the first clock terminal and / or the first inverting clock terminal; a first inverting unit, connected to the output terminal of the first input unit and connected to the first power supply signal and the second power supply signal, is used to invert the potential of the output terminal of the first input unit and output it; a first output unit, respectively connected to the output terminal of the first input unit, the output terminal of the first inverting unit, and the first... The shift register includes a second clock terminal and an output terminal of the first shift register, connected to a first power supply signal. This is used to control the output signal of the first shift register based on the potential of the output terminal of the first input unit and the output terminal of the first inverting unit. Optionally, the first shift register further includes: a second inverting unit, connected to the output terminal of the first inverting unit and connected to both the first and second power supply signals, used to invert the potential output by the first inverting unit before outputting it; a first transmission unit, connected between the control terminal of the first inverting unit and the output terminal of the second inverting unit, with the first control terminal of the first transmission unit connected to the first inverting clock terminal, and / or the second control terminal of the first transmission unit connected to the first clock terminal; the first transmission unit is used to control whether the control terminal of the first inverting unit and the output terminal of the second inverting unit are connected based on the potential of the first clock terminal and / or the first inverting clock terminal; Optionally, the on / off states of the first input unit and the first transmission unit in the same first shift register are opposite.

[0009] Optionally, the first shift register further includes: a first inverter connected between the first control terminal and the second control terminal of the first input unit, and / or a second inverter connected between the first control terminal and the second control terminal of the first transmission unit; or, the first shift register further includes: a third inverter connected between the first clock terminal and the first inverted clock terminal; optionally, at least two first shift registers share the same third inverter.

[0010] Optionally, each first shift register is connected to a corresponding transmission control module; the first shift register is used to configure the first potential pulse in the signal connected to the input terminal of the first shift register as the first potential pulse in the transmission signal, and the second shift register is used to configure the first potential pulse in the signal connected to the input terminal of the second shift register as the conduction pulse in the scan signal; optionally, the potential level of the conduction pulse is the same as that of the first potential pulse; optionally, the circuit structure of the second shift register is the same as that of the first shift register; optionally, in the first shift register and the second shift register connected to the same transmission control module, the first clock terminal of the first shift register and the second clock terminal of the second shift register are connected to the same clock signal line, and the second clock terminal of the first shift register and the first clock terminal of the second shift register are connected to the same clock signal line; the pulse width and pulse frequency of the signals connected to the first clock terminal and the second clock terminal of the first shift register are the same.

[0011] Optionally, the scan driving circuit includes multiple register groups, each register group including at least two first shift registers, and the first first shift register in each register group is connected to a transmission control module. The first shift register is used to configure a first potential pulse in the signal connected to the input terminal of the first shift register as a first potential pulse in the transmission signal. The second shift register is used to configure a first potential pulse in the signal connected to the input terminal of the second shift register as a conduction pulse in the scan signal. Optionally, the conduction pulse and the first potential pulse have different potential levels. Optionally, the second shift register further includes a third clock terminal and / or a third inverted clock terminal, and a fourth clock terminal and / or a fourth inverted clock terminal. The second shift register is used to configure the first potential pulse in the signal connected to the input terminal of the second shift register as a conduction pulse in the scan signal. The signals input to the third inverting clock terminal, and the fourth clock terminal and / or the fourth inverting clock terminal, shift the signal input to the second shift register. The signals input to the third clock terminal and the third inverting clock terminal are inverted signals. The signals input to the fourth clock terminal and the fourth inverting clock terminal are inverted signals. The pulse frequencies of the signals input to the first clock terminal and the second clock terminal of the first shift register are the same, and the pulse frequencies of the signals input to the third clock terminal and the fourth clock terminal of the second shift register are the same. Each register group includes j first shift registers, where j is an integer greater than or equal to 2. The pulse frequency of the signal input to the first clock terminal of the first shift register is j times the pulse frequency of the signal input to the third clock terminal of the second shift register. Optionally, j = 2.

[0012] Optionally, the second shift register includes: a second input unit, the input terminal of which is connected to the input terminal of the second shift register, a first control terminal of which is connected to a third clock terminal, and / or, a second control terminal of which is connected to a third inverting clock terminal; the second input unit is used to control whether to output the signal connected to the input terminal of the second shift register according to the potential of the third clock terminal and / or the third inverting clock terminal; a third inverting unit, connected to the output terminal of the second input unit and connected to a first power supply signal and a second power supply signal, used to invert the potential of the output terminal of the second input unit and output it; and a second transmission unit, the input terminal of which is connected to the output terminal of the third inverting unit. The first control terminal of the second transmission unit is connected to the fourth clock terminal, and / or the second control terminal of the second transmission unit is connected to the fourth inverting clock terminal; the second transmission unit is used to control whether to output the potential of the output terminal of the third inverting unit according to the potential of the fourth clock terminal and / or the fourth inverting clock terminal; the fourth inverting unit is connected to the output terminal of the second transmission unit and connected to the first power signal and the second power signal, and is used to invert the potential output by the second transmission unit before outputting it; the second output unit is connected to the output terminal of the second transmission unit, the output terminal of the fourth inverting unit, and the output terminal of the second shift register, and connected to the first power signal and the second power signal, and is used to control whether to output the potential of the output terminal of the second transmission unit according to the potential of the output terminal of the second transmission unit and the output terminal of the fourth inverting unit. The bit control first power signal or second power signal is output as a scan signal; optionally, the second shift register further includes: a fifth inverting unit, connected to the output terminal of the third inverting unit, and connected to the first power signal and the second power signal, used to invert the potential output by the third inverting unit and output it; a third transmission unit, connected between the control terminal of the third inverting unit and the output terminal of the fifth inverting unit, and the first control terminal of the third transmission unit is connected to the third inverting clock terminal, and / or, the second control terminal of the third transmission unit is connected to the third clock terminal; the third transmission unit is used to control whether the control terminal of the third inverting unit and the output terminal of the fifth inverting unit are connected according to the potential of the third clock terminal and / or the third inverting clock terminal; sixth An inverting unit is connected to the output terminal of the fourth inverting unit and is connected to a first power signal and a second power signal. It is used to invert the potential output by the fourth inverting unit and then output it. A fourth transmission unit is connected between the control terminal of the fourth inverting unit and the output terminal of the sixth inverting unit. The first control terminal of the fourth transmission unit is connected to the fourth inverting clock terminal, and / or, the second control terminal of the fourth transmission unit is connected to the fourth clock terminal. The fourth transmission unit is used to control whether the control terminal of the fourth inverting unit and the output terminal of the sixth inverting unit are connected according to the potential of the fourth clock terminal and / or the fourth inverting clock terminal. Optionally, the second shift register further includes: an initialization unit, a fifth transmission unit, a sixth transmission unit, a coupling unit, and a switching unit.The initialization unit's input terminal is connected to a first power signal, its control terminal is connected to the output terminal of the second input unit, and its output terminal is connected to the first terminal of the coupling unit. The initialization unit is used to turn on or off according to the potential of the output terminal of the second input unit. The fifth transmission unit is connected between the output terminal of the second transmission unit and the second terminal of the coupling unit, and is used to turn on or off according to the potential of the third clock terminal. The sixth transmission unit is connected between the third clock terminal and the first terminal of the coupling unit, and its control terminal is connected to the output terminal of the fifth transmission unit. The sixth transmission unit is used to turn on or off according to the potential of its control terminal. The control terminal and the first terminal of the switching unit are both connected to the second terminal of the coupling unit, and the second terminal of the switching unit is connected to the second output unit. The switching unit is used to turn on or off according to the potential of its control terminal. Optionally, the second input unit and the second transmission unit in the same second shift register are time-divisionally turned on. Optionally, the on / off states of the second input unit and the third transmission unit in the same second shift register are opposite. Optionally, the on / off states of the second transmission unit and the fourth transmission unit in the same second shift register are opposite.

[0013] Optionally, the second shift register further includes: a fourth inverter connected between the first control terminal and the second control terminal of the second input unit, and / or a seventh inverter connected between the first control terminal and the second control terminal of the fourth transmission unit; and the second shift register further includes: a fifth inverter connected between the first control terminal and the second control terminal of the second transmission unit, and / or a sixth inverter connected between the first control terminal and the second control terminal of the third transmission unit; or, the second shift register further includes: an eighth inverter connected between the third clock terminal and the third inverted clock terminal, and / or a ninth inverter connected between the fourth clock terminal and the fourth inverted clock terminal; optionally, at least two second shift registers share the same eighth inverter, and / or at least two second shift registers share the same ninth inverter.

[0014] Optionally, the transmission control module includes a twelfth transistor, the first terminal of which is connected to the output terminal of the first shift register connected to the transmission control module, the second terminal of which is connected to the input terminal of the second shift register connected to the transmission control module, and the gate of which is connected to the first control terminal of the transmission control module. Optionally, the transmission control module also includes a thirteenth transistor, which is connected in parallel with the twelfth transistor, and the gate of which is connected to the second control terminal of the transmission control module. The twelfth and thirteenth transistors have different channel types, and the signals input to the first and second control terminals of the transmission control module are inverted signals. Optionally, the transmission control module also includes a fourteenth transistor, the gate of which is connected to either the first or second control terminal of the transmission control module, the first terminal of which is connected to a cutoff control signal, and the second terminal of which is connected to the input terminal of the second shift register connected to the transmission control module. The conduction state of the fourteenth transistor is opposite to that of the twelfth transistor. Optionally, the transmission control module also includes a tenth inverter, connected between the first and second control terminals of the transmission control module. Optionally, some or all of the transmission control modules share the same tenth inverter.

[0015] Secondly, embodiments of the present invention also provide a display panel, including: a scan driving circuit as provided in any embodiment of the present invention, and a plurality of scan lines; the output terminal of each second shift register is connected to at least one scan line.

[0016] Optionally, the display panel further includes: a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line; the first clock terminal of the 4k-3 stage first shift register is connected to the first clock signal line, and the second clock terminal of the 4k-3 stage first shift register is connected to the second clock signal line; the first clock terminal of the 4k-2 stage first shift register is connected to the second clock signal line, and the second clock terminal of the 4k-2 stage first shift register is connected to the third clock signal line; the first clock terminal of the 4k-1 stage first shift register is connected to the third clock signal line, and the second clock terminal of the 4k-1 stage first shift register is connected to the fourth clock signal line; the first clock terminal of the 4k-1 stage first shift register is connected to the fourth clock signal line, and the second clock terminal of the 4k-1 stage first shift register is connected to the fourth clock signal line; where k is a positive integer; or, the display panel further includes: a fifth clock signal line and a sixth clock signal line; the first clock terminal of the odd-numbered stage first shift register is connected to the fifth clock signal line, and the second clock terminal of the odd-numbered stage first shift register is connected to the first clock signal line; where k is a positive integer; or, the display panel further includes: a fifth clock signal line and a sixth clock signal line; the first clock terminal of the odd-numbered stage first shift register is connected to the fifth clock signal line, and the second clock terminal of the odd-numbered stage first shift register is connected to the sixth clock signal line. The display panel includes six clock signal lines; the first clock terminal of the even-numbered first shift register is connected to the sixth clock signal line, and the second clock terminal of the even-numbered first shift register is connected to the fifth clock signal line; optionally, when the second shift register includes a third clock terminal and a fourth clock terminal, the display panel further includes a seventh clock signal line and an eighth clock signal line; the third clock terminal of the odd-numbered second shift register is connected to the seventh clock signal line, and the fourth clock terminal of the odd-numbered second shift register is connected to the eighth clock signal line; the third clock terminal of the even-numbered second shift register is connected to the eighth clock signal line, and the fourth clock terminal of the even-numbered second shift register is connected to the seventh clock signal line; optionally, there are multiple scan driving circuits, including a first scan driving circuit and a second scan driving circuit, which share multiple first shift registers; optionally, the conduction pulse of the scan signal output by one of the first scan driving circuit and the second scan driving circuit is a high-potential conduction pulse, and the conduction pulse of the scan signal output by the other is a low-potential conduction pulse.

[0017] The scanning drive circuit provided in this embodiment of the invention includes cascaded multi-stage first shift registers, multiple transmission control modules connected to at least some of the first shift registers, and multiple second shift registers connected to each transmission control module. Through the cascading of the first shift registers at each stage, the first scan input signal can be shifted and output stage by stage. In each display frame, by adjusting the on / off state of the transmission control modules, the transmission of the corresponding cascaded signal to the second shift register can be allowed / blocked, thereby controlling whether the second shift register outputs the conduction pulse of the scan signal, thus controlling the frequency of the scan signal pulse. Based on this, the scanning drive circuit allows the output of scan signals with different pulse frequencies, thereby enabling the display panel using this scanning drive circuit to support zoned multi-frequency display functionality. Furthermore, while satisfying the display effect, controlling some display zones to perform low-frequency display can effectively reduce product power consumption.

[0018] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of a scanning drive circuit provided in an embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram of the structure of a first shift register provided in an embodiment of the present invention;

[0022] Figure 3 This is a schematic diagram of another first shift register structure provided in an embodiment of the present invention;

[0023] Figure 4 This is a schematic diagram of the driving timing of a first shift register provided in an embodiment of the present invention;

[0024] Figure 5 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention;

[0025] Figure 6 This is a schematic diagram of the driving timing of a scanning driving circuit provided in an embodiment of the present invention;

[0026] Figure 7This is a schematic diagram of the driving timing of another scanning driving circuit provided in an embodiment of the present invention;

[0027] Figure 8 This is a driving timing diagram of another scanning driving circuit provided in an embodiment of the present invention;

[0028] Figure 9 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention;

[0029] Figure 10 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention;

[0030] Figure 11 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention;

[0031] Figure 12 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention;

[0032] Figure 13 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention;

[0033] Figure 14 This is a schematic diagram illustrating the timing relationship of multiple clock signals provided in an embodiment of the present invention;

[0034] Figure 15 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention;

[0035] Figure 16 This is a schematic diagram of the structure of a second shift register provided in an embodiment of the present invention;

[0036] Figure 17 This is a schematic diagram of another second shift register provided in an embodiment of the present invention.

[0037] Figure 18 This is a schematic diagram of the driving timing of a second shift register provided in an embodiment of the present invention;

[0038] Figure 19 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention;

[0039] Figure 20 This is a driving timing diagram of another scanning driving circuit provided in an embodiment of the present invention;

[0040] Figure 21 This is a driving timing diagram of another scanning driving circuit provided in an embodiment of the present invention;

[0041] Figure 22This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention;

[0042] Figure 23 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention;

[0043] Figure 24 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention;

[0044] Figure 25 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention;

[0045] Figure 26 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention;

[0046] Figure 27 This is a schematic diagram of the structure of an inverter provided in an embodiment of the present invention;

[0047] Figure 28 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0048] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0049] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0050] This invention provides a scanning driving circuit that enables a display panel using this scanning driving circuit to support vertically arbitrary partitioning of the screen, and at least some of the display partitions to be displayed at different refresh rates. Figure 1 This is a schematic diagram of a scanning drive circuit provided in an embodiment of the present invention. See also... Figure 1The scan drive circuit 100 includes: a plurality of first shift registers 10, a plurality of transmission control modules 20, and a plurality of second shift registers 30. The plurality of transmission control modules 20 are configured corresponding to at least a portion of the first shift registers 10, and the plurality of transmission control modules 20 are configured in a one-to-one correspondence with the plurality of second shift registers 30. Figure 1 The example shows a one-to-one correspondence between the transmission control module 20 and the first shift register 10, but this is not intended to limit the invention.

[0051] The first shift register 10 is used to shift the signal input to its input terminal and output a staged signal. For example, the first shift register 10 is used to shift the signal input to its input terminal based on the signals input to its first clock terminal and second clock terminal, and output a staged signal. Alternatively, the first shift register 10 is used to shift the signal input to its input terminal based on the signals input to its first inverted clock terminal and second clock terminal, and output a staged signal. Alternatively, the first shift register 10 is used to shift the signal input to its input terminal based on the signals input to its first clock terminal, first inverted clock terminal, and second clock terminal, and output a staged signal, where the signals input to the first clock terminal and the first inverted clock terminal are inverted signals; wherein the output terminal of this stage's first shift register 10 is connected to the input terminal of the next stage's first shift register 10. Specifically, the first shift register 10 is used to configure the first potential pulse in the signal (equivalent to the input signal) connected to its input terminal as the first potential pulse in the cascade signal, such that the first potential pulse in the cascade signal appears later than the first potential pulse in the input signal of the first shift register 10; the first potential pulse can be a high-potential pulse or a low-potential pulse. The signals connected to the first clock terminal and the second clock terminal have the same pulse frequency, and the first potential pulses in the signals connected to the first clock terminal and the second clock terminal appear alternately. The start time of the first potential pulse in the signal connected to the first clock terminal is, for example, half a pulse cycle apart from the start time of the first potential pulse in the signal connected to the second clock terminal. Correspondingly, the width of the first potential pulse in the cascade signal is, for example, the same as the width of the first potential pulse in the signal connected to the first clock terminal; the start time of the first potential pulse in the cascade signal is, for example, half a pulse cycle apart from the start time of the first potential pulse in the input signal of the first shift register 10. The structure of the first shift register 10 can be configured according to its specific function. Figure 1As shown, along the top-to-bottom direction, the first-stage first shift register 10 shifts the first scan input signal SIN1 to obtain the first-stage transmission signal Carry1; the second-stage first shift register 10 shifts the first-stage transmission signal Carry1 to obtain the second-stage transmission signal Carry2; the third-stage first shift register 10 shifts the second-stage transmission signal Carry2 to obtain the third-stage transmission signal Carry3, and so on. Based on the cascaded first shift registers 10, the first potential pulse in the first scan input signal SIN1 can be shifted and output step by step.

[0052] The input terminals of multiple transmission control modules 20 are respectively connected to at least a portion of the output terminals of the first shift register 10; the transmission control module 20 is used to output the cascade signal connected to its input terminal when it is turned on, and to prevent the cascade signal from being transmitted to the second shift register 30 connected to the transmission control module 20 when it is turned off.

[0053] The input terminals of multiple second shift registers 30 are respectively connected to the output terminals of multiple transmission control modules 20. The second shift registers 30 are used to output scan signals based on the signals input to their input terminals. Specifically, the second shift registers 30 are used to configure a first potential pulse in the input signal of the second shift register 30 as a conduction pulse in the scan signal, such that the conduction pulse in the scan signal appears later than the first potential pulse in the input signal of the second shift register 30; and the second shift registers 30 are used to configure input signals without a first potential pulse as scan signals without a conduction pulse (i.e., scan signals maintaining a cutoff potential). The conduction pulse is the duration of the potential used to control the conduction of the transistor connected to the scan signal. For example, when the controlled transistor is a P-type transistor, the conduction potential of the scan signal is low and the cutoff potential is high; when the controlled transistor is an N-type transistor, the conduction potential of the scan signal is high and the cutoff potential is low. The potential levels of the conduction pulse and the first potential pulse can be the same or different, and the structure of the second shift register 30 can be configured according to its specific function. like Figure 1 As shown, along the top-to-bottom direction, the first-stage second shift register 30 converts its input signal to obtain the first scan signal GOUT1; the second-stage second shift register 30 converts its input signal to obtain the second scan signal GOUT2, and so on.

[0054] For example, for the scan drive circuit 100, in any display frame, for any first-level second shift register 30, during the phase of the first potential pulse in the output stage of the first shift register 10 connected to the transmission control module 20 connected to the second shift register 30:

[0055] If the transmission control module 20 connected to the second shift register 30 is turned on, that is, the input and output terminals of the transmission control module 20 are connected, the first potential pulse of the stage transmission signal can be transmitted to the input terminal of the second shift register 30, and the second shift register 30 can convert the stage transmission signal with the first potential pulse into a scanning signal with a conduction pulse.

[0056] If the transmission control module 20 connected to the second shift register 30 is turned off, that is, the input and output terminals of the transmission control module 20 are disconnected, the first potential pulse of the transmission signal cannot be transmitted to the input terminal of the second shift register 30. Therefore, the scanning signal output by the second shift register 30 does not have a conduction pulse in the display frame and maintains the cutoff potential.

[0057] In summary, in each display frame, during the first potential pulse stage of the transmission signal, the on / off state of the transmission control module 20 can be controlled to determine whether there is a conduction pulse in the corresponding scan signal, thereby controlling the pulse frequency of the scan signal. If the transmission control module 20 remains on in all display frames, a scan signal with the same pulse frequency as the transmission signal can be obtained. If the transmission control module 20 is off in at least some display frames, a scan signal with a pulse frequency lower than that of the transmission signal can be obtained. For example, the output of each stage of the second shift register 30 is connected to at least one scan line, and one scan line is connected to at least one row of sub-pixels. Therefore, by controlling the pulse frequencies of at least two stages of scan signals to be different, at least two zones on the display panel in the column direction (i.e., the vertical direction of the screen) can be displayed at different frequencies.

[0058] For example, the scan signal is transmitted through the scan line to the gate of the transistor in the sub-pixel that is related to the data writing process. In any display frame, when the scan signal contains a turn-on pulse, the sub-pixel in the corresponding row can be controlled to refresh data; while when the scan signal maintains a cut-off potential, the sub-pixel in the corresponding row cannot refresh data. Therefore, the pulse frequency of the scan signal determines the data refresh frequency of the sub-pixel, and thus determines the refresh frequency of the display partition where the sub-pixel is located. Based on this, different frequencies of display in the column direction of the display panel can be achieved. The scan driving circuit in the prior art can only provide a scan signal of the same frequency, and the frequency of the scan signal can only be switched uniformly across the entire screen. Therefore, in order to ensure the display effect of the display partition that requires high-frequency display, only the entire screen can be controlled to display at a high frequency. Compared with the prior art, the scan driving circuit 100 provided in the embodiment of the present invention can control the display partition that does not require high-frequency display to refresh at a lower frequency as needed, thereby reducing the power consumption of the product through the multi-frequency display driving scheme of partitions.

[0059] Since there is no cascading relationship between the various levels of the second shift registers 30, whether each level of the second shift register 30 can output the conduction pulse in the scan signal is independently controlled by the transmission control module 20 connected to it. This allows the pulse frequency of each level of the scan signal to be independently controlled, enabling the position of the display partition to be arbitrarily adjusted as needed. Furthermore, since the first potential pulse of the first scan input signal SIN1 can be shifted and output stage by stage through each level of the first shift register 10, and each level of transmission signal is a high-frequency signal with the same pulse frequency as the first scan input signal SIN1, this provides the conditions for each level of the second shift register 30 to freely choose whether to output the conduction pulse of the scan signal based on the control of the transmission control module 20. This makes the adjustment range of the pulse frequency of each level of the scan signal unlimited and can be arbitrarily adjusted as needed.

[0060] The scanning drive circuit 100 provided in this embodiment of the invention includes cascaded multi-stage first shift registers 10, multiple transmission control modules 20 corresponding to at least some of the first shift registers 10, and multiple second shift registers 30 corresponding to each transmission control module 20. Through the cascading of the first shift registers 10 at each stage, the first scan input signal SIN1 can be shifted and output stage by stage. In each display frame, by adjusting the on / off state of the transmission control module 20, the corresponding cascaded signal can be allowed / blocked from being transmitted to the second shift register 30, thereby controlling whether the second shift register 30 outputs the conduction pulse of the scan signal, thus controlling the frequency of the scan signal pulse. Based on this, the scanning drive circuit 100 allows the output of scan signals with different pulse frequencies, thereby enabling the display panel using the scanning drive circuit 100 to support zoned multi-frequency display functionality. Furthermore, while satisfying the display effect, by controlling some display zones to perform low-frequency display, the power consumption of the product can be effectively reduced.

[0061] The above embodiments exemplify the modular structure of the scan drive circuit. The specific structures that each functional module in the scan drive circuit may have are described below.

[0062] Figure 2 This is a schematic diagram of the structure of a first shift register provided in an embodiment of the present invention. See also... Figure 2 In one embodiment, the first shift register 10 may optionally include a first input unit 41, a first inverting unit 42, and a first output unit 45.

[0063] The input terminal of the first input unit 41 is connected to the input terminal IN1 of the first shift register 10, the first control terminal of the first input unit 41 is connected to the first clock terminal PCK1, and / or the second control terminal of the first input unit 41 is connected to the first inverting clock terminal PCK1B.

[0064] The first inverting unit 42 is connected to the output terminal of the first input unit 41 and is connected to the first power signal and the second power signal. For example, the control terminal of the first inverting unit 42 is connected to the output terminal of the first input unit 41, the first input terminal of the first inverting unit 42 is connected to the first power terminal PVGH1 of the first shift register 10, and the second input terminal of the first inverting unit 42 is connected to the second power terminal PVGL1 of the first shift register 10.

[0065] The first output unit 45 is connected to the output terminal of the first input unit 41, the output terminal of the first inverting unit 42, the second clock terminal PCK of the first shift register 10, and the output terminal OUT1 of the first shift register 10, and is connected to the first power supply signal. For example, the first control terminal of the first output unit 45 is connected to the output terminal of the first input unit 41, the second control terminal of the first output unit 45 is connected to the output terminal of the first inverting unit 42, the first input terminal of the first output unit 45 is connected to the first power supply terminal PVGH1, the second input terminal of the first output unit 45 is connected to the second clock terminal PCK2 of the first shift register 10, and the output terminal of the first output unit 45 is connected to the output terminal OUT1 of the first shift register 10.

[0066] In this shift register 10, the first power supply terminal PVGH1 is connected to the first power supply signal, and the second power supply terminal PVGL1 is connected to the second power supply signal. The first power supply signal and the second power supply signal have different potentials, for example, the first power supply signal is at a high potential and the second power supply signal is at a low potential.

[0067] The first input unit 41 controls whether to output the signal connected to the input terminal IN1 of the first shift register 10 based on the potential of the first clock terminal PCK1 and / or the first inverting clock terminal PCK1B, which is equivalent to controlling whether the signal connected to the input terminal IN1 of the first shift register 10 is transmitted to the output terminal of the first input unit 41. The first inverting unit 42 controls the output of a first power signal or a second power signal based on the potential of its control terminal, so as to invert the potential of the output terminal of the first input unit 41 and output it. The first output unit 45 controls the first power signal or the signal connected to the second clock terminal PCK2 as the output signal of the first shift register 10 based on the potential of the output terminal of the first input unit 41 and the potential of the output terminal of the first inverting unit 42; for example, the first output unit 45 controls whether the first input terminal and the output terminal of the first output unit 45 are connected based on the potential of the output terminal of the first inverting unit 42, and controls whether the second input terminal and the output terminal of the first output unit 45 are connected based on the potential of the output terminal of the first input unit 41.

[0068] In the above "and / or" relationships, the following examples provide specific explanations for the "and" case. The circuit principle for the "or" case is similar and will not be repeated.

[0069] Figure 3 This is a schematic diagram of another first shift register provided in an embodiment of the present invention. See also... Figure 3 Furthermore, the first shift register 10 may also include a second inverting unit 43 and a first transmission unit 44.

[0070] The second inverting unit 43 is connected to the output terminal of the first inverting unit 42 and is connected to the first power signal and the second power signal. For example, the control terminal of the second inverting unit 43 is connected to the output terminal of the first inverting unit 42, the first input terminal of the second inverting unit 43 is connected to the first power terminal PVGH1, and the second input terminal of the second inverting unit 43 is connected to the second power terminal PVGL1.

[0071] The first transmission unit 44 is connected between the control terminal of the first inverting unit 42 and the output terminal of the second inverting unit 43, and the first control terminal of the first transmission unit 44 is connected to the first inverting clock terminal PCK1B, and / or the second control terminal of the first transmission unit 44 is connected to the first clock terminal PCK1.

[0072] The second inverting unit 43 controls the output of a first power signal or a second power signal based on the potential of its control terminal, thereby inverting the potential of the output terminal of the first inverting unit 42 before outputting it. The first transmission unit 44 controls whether the control terminal of the first inverting unit 42 and the output terminal of the second inverting unit 43 are connected based on the potential of the first clock terminal PCK1 and / or the first inverting clock terminal PCK1B. The first input unit 41 in the same first shift register has the opposite on / off state to the first transmission unit 44. For ease of description, the node connected to the output terminal of the first input unit 41 is referred to as node A, and the node connected to the output terminal of the first inverting unit 42 is referred to as node B.

[0073] When the first input unit 41 is turned on, the potential of the input terminal IN1 can be transmitted to node A. Then, through the inversion processing of the first inverting unit 42, the potential of node B can change synchronously with the potential of the input terminal IN1, thereby enabling the output state of the first output unit 45 to be adjusted synchronously.

[0074] When the first input unit 41 is turned off, the potential of input terminal IN1 cannot be transmitted to node A. At this time, the first transmission unit 44 is turned on, so that the first inverting unit 42 and the second inverting unit 43 are connected as two cross-coupled inverters, which can realize the potential storage function, so that the potentials of node A and node B are maintained at the potentials before the first input unit 41 was turned off. Therefore, the output state of the first output unit 45 also maintains the state before the first input unit 41 was turned off.

[0075] For example, by controlling the switching time of the on / off state of the first input unit 41 (e.g., the time when it changes from on to off) to later than the potential change time of the input signal at the input terminal IN1, the potential change (or pulse) of the input signal of the first shift register 10 can be delayed and transmitted to node A, thereby controlling the switching time of the output state of the first output unit 45 to be later than the potential change time of the input signal of the first shift register 10, and realizing the shift output function of the first shift register 10.

[0076] The working process of the first shift register 10 will be explained below in conjunction with the specific structure of the first shift register 10.

[0077] See also Figure 3 Specifically, the first input unit 41 may include a first transistor T1 connected between the input and output terminals of the first input unit 41, and the gate of the first transistor T1 is connected to the first control terminal of the first input unit 41. And / or, the first input unit 41 may include a ninth transistor T9 connected between the input and output terminals of the first input unit 41, and the gate of the ninth transistor T9 is connected to the second control terminal of the first input unit 41. The ninth transistor T9 and the first transistor T1 have different channel types; for example, the ninth transistor T9 is an N-type transistor, and the first transistor T1 is a P-type transistor. This configuration allows the ninth transistor T9 and the first transistor T1 to form a transmission gate structure, which can effectively improve the reliability of the first shift register 10. Specifically, P-type transistors allow high potentials to pass through without loss, and N-type transistors allow low potentials to pass through without loss. By setting the first input unit 41 as a transmission gate structure and connecting two signals that are opposite to each other to the two control terminals, the switching states of the two transistors can be kept consistent, and both low and high potentials can pass through without loss, effectively ensuring the potential transmission capability of the first input unit 41 and avoiding output abnormalities caused by threshold voltage loss.

[0078] It should be noted that the N-type transistors mentioned in this article can all be metal-oxide (e.g., indium gallium zinc oxide, IGZO) transistors, and the P-type transistors can all be polysilicon (LTPS) transistors, which will not be elaborated further hereafter.

[0079] The first inverting unit 42 includes a second transistor T2 and a third transistor T3. The gates of both transistors T2 and T3 are connected to the control terminal of the first inverting unit 42. The first terminal of the second transistor T2 is connected to the first power supply terminal PVGH1; the first terminal of the third transistor T3 is connected to the second power supply terminal PVGL1; and the second terminals of both transistors T2 and T3 are connected to the output terminal of the first inverting unit 42. The second transistor T2 and the third transistor T3 have different channel types; for example, the second transistor T2 is a P-type transistor, and the third transistor T3 is an N-type transistor.

[0080] The second inverting unit 43 includes a fourth transistor T4 and a fifth transistor T5. The gates of both transistors T4 and T5 are connected to the control terminal of the second inverting unit 43. The first terminal of transistor T4 is connected to the first power supply terminal PVGH1, and the first terminal of transistor T5 is connected to the second power supply terminal PVGL1. The second terminals of both transistors T4 and T5 are connected to the output terminal of the second inverting unit 43. The fourth transistor T4 and the fifth transistor T5 have different channel types; for example, transistor T4 is a P-type transistor, and transistor T5 is an N-type transistor.

[0081] The first transmission unit 44 may include a sixth transistor T6, connected between the control terminal of the first inverting unit 42 and the output terminal of the second inverting unit 43, and the gate of the sixth transistor T6 is connected to the first control terminal of the first transmission unit 44. Alternatively, the first transmission unit 44 may include a tenth transistor T10, connected between the control terminal of the first inverting unit 42 and the output terminal of the second inverting unit 43, and the gate of the tenth transistor T10 is connected to the second control terminal of the first transmission unit 44. The tenth transistor T10 and the sixth transistor T6 have different channel types; for example, the tenth transistor T10 is an N-type transistor, and the sixth transistor T6 is a P-type transistor. This configuration allows the tenth transistor T10 and the sixth transistor T6 to form a transmission gate structure, effectively improving the reliability of the first shift register 10. The first transistor T1 and the sixth transistor T6 may have the same channel type. The first transistor T1 and the tenth transistor T10 may have different channel types. The ninth transistor T9 and the sixth transistor T6 may have different channel types. The ninth transistor T9 and the tenth transistor T10 may have the same channel type.

[0082] The first output unit 45 includes a seventh transistor T7, an eighth transistor T8, and a first capacitor C1. The gate of the seventh transistor T7 is connected to the output terminal of the first inverting unit 42. The first terminal of the seventh transistor T7 is connected to the first input terminal of the first output unit 45. The second terminal of the seventh transistor T7 is connected to the output terminal of the first output unit 45. The gate of the eighth transistor T8 is connected to the control terminal of the first inverting unit 42 (or the output terminal of the first input unit 41). The first terminal of the eighth transistor T8 is connected to the second input terminal of the first output unit 45. The second terminal of the eighth transistor T8 is connected to the output terminal of the first output unit 45. The first capacitor C1 is connected between the gate and the second terminal of the eighth transistor T8. The seventh transistor T7 and the eighth transistor T8 are, for example, P-type transistors. Further, the first output unit 45 may also include an eleventh transistor T11, connected between the control terminal of the first inverting unit 42 (or the output terminal of the first input unit 41) and the gate of the eighth transistor T8; and the gate of the eleventh transistor T11 is connected to the second power supply terminal PVGL1. By setting the eleventh transistor T11, the lower potential obtained by the gate of the eighth transistor T8 due to the coupling effect of the first capacitor C1 can be avoided from the control terminal of the first inverting unit 42, so as to avoid the transistors connected to the control terminal of the first inverting unit 42 from being damaged due to excessive voltage stress.

[0083] Figure 4 This is a schematic diagram illustrating the driving timing of a first shift register according to an embodiment of the present invention. (Combined with...) Figure 3 and Figure 4 The signal connected to the input terminal IN1 of the first shift register is denoted as the scan input signal SIN, the signal connected to the first clock terminal PCK1 is denoted as the first clock signal SCK1, the signal connected to the first inverting clock terminal PCK1B is denoted as the first inverting clock signal SCK1B, and the signal connected to the second clock terminal PCK2 is denoted as the second clock signal SCK2. Taking a low-potential pulse as an example, the driving process of the first shift register 10 includes:

[0084] In the first stage TT1, both the scan input signal SIN and the first clock signal SCK1 are at low potentials, while both the first inverted clock signal SCK1B and the second clock signal SCK2 are at high potentials. The sixth transistor T6 and the tenth transistor T10 are turned off. The first transistor T1 and the ninth transistor T9 are turned on, transmitting the low potential of the scan input signal SIN to node A. This low potential continues to be transmitted through the eleventh transistor T11 to the gate of the eighth transistor T8, controlling the eighth transistor T8 to turn on. The high potential of the second clock signal SCK2 is output to the output of the first shift register through the eighth transistor T8. Simultaneously, the second transistor T2 is turned on, transmitting the high potential of the first power supply signal to node B, controlling the seventh transistor T7 to turn off. Therefore, in this stage, the stage transfer signal Carry is at a high potential. The first potential pulse of the scan input signal SIN (exemplarily a low potential pulse here) overlaps with the effective potential pulse of the first clock signal SCK1.

[0085] In the second stage, TT2, at the start, the scan input signal SIN is still low, the first clock signal SCK1 jumps to high, and the first inverted clock signal SCK1B jumps to low. The first transistor T1 and the ninth transistor T9 are turned off, preventing the scan input signal SIN from being transmitted to node A, which remains at a low level. The second transistor T2 is turned on, keeping node B at a high level. The fifth transistor T5 is turned on, transmitting the low level of the second power supply signal VGL to the output of the second inverting unit 43 through the fifth transistor T5. Simultaneously, the sixth transistor T6 and the tenth transistor T10 are turned on, connecting the control terminal of the first inverting unit 42 to the output of the second inverting unit 43, ensuring that node A remains at a low level. During this stage, the first clock signal SCK1 remains high, the first inverted clock signal SCK1B remains low, and the potential of node A is unaffected by the potential change of the scan input signal SIN. The seventh transistor T7 is turned off; the eighth transistor T8 is turned on, outputting the second clock signal SCK2 to the output of the first shift register. During this stage, the staged signal Carry has the same low-level pulse as the second clock signal SCK2.

[0086] In the third stage (TT3), the first clock signal SCK1 is low, while the scan input signal SIN, the first inverted clock signal SCK1B, and the second clock signal SCK2 are all high. The sixth transistor T6 and the tenth transistor T10 are turned off. The first transistor T1 and the ninth transistor T9 are turned on, transmitting the high potential of the scan input signal SIN to node A. This high potential continues to be transmitted through the eleventh transistor T11 to the gate of the eighth transistor T8, controlling the eighth transistor T8 to turn off. Simultaneously, the third transistor T3 is turned on, transmitting the low potential of the second power supply signal to node B, controlling the seventh transistor T7 to turn on. The high potential of the first power supply signal is output to the output of the first shift register through the seventh transistor T7. Therefore, in this stage, the stage transfer signal Carry is high.

[0087] In the fourth stage (TT4), the first clock signal SCK1 is high, and the first inverted clock signal SCK1B is low. The first input unit 41 is off, preventing the scan input signal SIN from being transmitted through it. The first transmission unit 44 is on, connecting the control terminal of the first inverting unit 42 to the output terminal of the second inverting unit 43. Node A remains high, and node B remains low. The eighth transistor T8 is off, and the seventh transistor T7 is on, allowing the high potential of the first power supply signal to be output to the output terminal of the first shift register through the seventh transistor T7. Therefore, in this stage, the staged transmission signal Carry remains high.

[0088] The subsequent stages repeat the driving process of the third stage TT3 and the fourth stage TT4 until the scan input signal SIN jumps to a low level again. If the scan input signal SIN remains at a high level and does not have a low level stage, then the driving process of the first shift register 10 does not have the first stage TT1 and the second stage TT2, but instead continuously repeats the third stage TT3 and the fourth stage TT4.

[0089] Based on the above embodiments, optionally, the conduction pulse of the scan signal and the first potential pulse in the scan input signal SIN may be the same or different. The specific structures that the scan drive circuit 100 may have under different conditions will be described by example below.

[0090] In one implementation, alternatively, such as Figure 1 As shown, the conduction pulse of the scan signal and the first potential pulse of the stage transmission signal Carry have the same potential level, for example, both are low potential pulses. Furthermore, each first shift register 10 is connected to a corresponding transmission control module 20; that is, the number of first shift registers 10, the number of transmission control modules 20, and the number of second shift registers 20 in the scan drive circuit 100 are all the same.

[0091] Based on this, the second shift register 30 can be selected from shift register circuits with the same function as the first shift register 10. Furthermore, the circuit structure of the second shift register 30 can be set to be the same (partially the same or completely the same) or similar to the circuit structure of the first shift register 10, so that the layout of the scan drive circuit 100 in the display panel is easy to design and implement.

[0092] Figure 5 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention. Figure 5 The example shows a primary transmission control module 20 and its connected first shift register 10 and second shift register 20. See also Figure 5 For example, both the first shift register 10 and the second shift register 30 can be adopted as follows: Figure 3 The difference lies in the specific way the relevant signals are provided, rather than in the structure of the other two.

[0093] Specifically, see Figure 5The first shift register 10 is connected to the scan input signal SIN, and its output is connected to the input of the transmission control module 20. In the first shift register 10: the first clock input PCK1 is connected to the first clock signal SCK1, the first inverted clock input PCK1B is connected to the first inverted clock signal SCK1B, the second clock input PCK2 is connected to the second clock signal SCK2, the first power input PVGH1 is connected to the first power signal VGH, and the second power input is connected to the second power signal VGL. The input of the second shift register 30 is connected to the output of the transmission control module 20, and the second shift register 30 outputs the scan signal GOUT. In the second shift register 30: the first clock input PCK1 is connected to the second clock signal SCK2, the first inverted clock input PCK1B is connected to the second inverted clock signal SCK2B, the second clock input PCK2 is connected to the first clock signal SCK1, the first power input PVGH1 is connected to the first power signal VGH, and the second power input is connected to the second power signal VGL. In this configuration, the second clock signal SCK2 and the second inverted clock signal SCK2B are inverted signals. The first clock signal SCK1 and the second clock signal SCK2 are clock signals with the same pulse frequency and pulse width, and their low-level pulses alternate. The effective potential pulses of the first clock signal SCK1 and the second clock signal SCK2 are staggered. The effective potential pulse of the first clock signal SCK1 can be a conduction pulse that controls the conduction of the first input unit 41 in the first shift register 10. The effective potential pulse of the first inverted clock signal SCK1B can be a conduction pulse that controls the conduction of the first transmission unit 44 in the first shift register 10. The effective potential pulse of the second clock signal SCK2 can be a conduction pulse that controls the conduction of the first input unit 41 in the second shift register 30. The effective potential pulse of the second inverted clock signal SCK2B can be a conduction pulse that controls the conduction of the first transmission unit 44 in the second shift register 30. In this way, when the transmission control module 20 is turned on, the second shift register 30 can successfully shift and output the first potential pulse of the stage transmission signal Carry; so that the time interval between the scan input signal SIN and the first potential pulse of the stage transmission signal Carry is the same as the time interval between the first potential pulse of the stage transmission signal Carry and the scan signal GOUT.

[0094] Based on this circuit structure, in the first shift register 10 and the second shift register 30 connected to the same transmission control module 20, the first clock terminal PCK1 of the first shift register 10 and the second clock terminal PCK2 of the second shift register 30 are connected to the same clock signal line, and the second clock terminal PCK2 of the first shift register 10 and the first clock terminal PCK1 of the second shift register 30 are connected to the same clock signal line. For example, the first clock terminal PCK1 of a certain stage of the first shift register 10 and the second clock terminal PCK2 of the same stage of the second shift register 30 can be connected to the same clock signal line, and the second clock terminal PCK2 of a certain stage of the first shift register 10 and the first clock terminal PCK1 of the same stage of the second shift register 30 can be connected to the same clock signal line.

[0095] See also Figure 5 Based on the above embodiments, optionally, the transmission control module 20 includes a twelfth transistor T12. The first terminal of the twelfth transistor T12 is connected to the input terminal of the transmission control module 20, that is, the first terminal of the twelfth transistor T12 is connected to the output terminal of the first shift register 10 to which the transmission control module 20 is connected. The second terminal of the twelfth transistor T12 is connected to the output terminal of the transmission control module 20, that is, the second terminal of the twelfth transistor T12 is connected to the input terminal of the second shift register 30 to which the transmission control module 20 is connected. The gate of the twelfth transistor T12 is connected to the first control terminal of the transmission control module 20 and is connected to the transmission control signal C3.

[0096] Furthermore, the transmission control module 20 may also include a thirteenth transistor T13. The first terminal of the thirteenth transistor T13 is connected to the input terminal of the transmission control module 20, and the second terminal of the thirteenth transistor T13 is connected to the output terminal of the transmission control module 20. The thirteenth transistor T13 is connected in parallel with the twelfth transistor T12. The gate of the thirteenth transistor T13 is connected to the second control terminal of the transmission control module 20, and an inverted transmission control signal C3B is input. The transmission control signal C3B and the inverted transmission control signal C3B are inverted signals. The twelfth transistor T12 and the thirteenth transistor T13 have different channel types; for example, the twelfth transistor T12 is an N-type transistor, and the thirteenth transistor T13 is a P-type transistor. This configuration allows the twelfth transistor T12 and the thirteenth transistor T13 to form a transmission gate structure, which can effectively improve the reliability of the scan drive circuit 100.

[0097] Furthermore, the transmission control module 20 may also include a fourteenth transistor T14. The gate of the fourteenth transistor T14 is connected to either the first or second control terminal of the transmission control module 20. The first terminal of the fourteenth transistor T14 is connected to a cutoff control signal, and the second terminal of the fourteenth transistor T14 is connected to the output terminal of the transmission control module 20. That is, the second terminal of the fourteenth transistor T14 is connected to the input terminal of the second shift register 30 to which the transmission control module 20 is connected. The conduction state of the fourteenth transistor T14 is opposite to that of the twelfth transistor T12. In other words, when the twelfth transistor T12 is turned off, preventing the transmission signal Carry from being transmitted backward, the fourteenth transistor T14 is turned on, continuously providing a cutoff control signal to the input terminal of the second shift register 30. This ensures that the second shift register 30 reliably and continuously outputs the cutoff potential of the scan signal GOUT, avoiding the impact on the output stability of the second shift register 30 due to the floating potential of its input terminal. The cutoff control signal is a DC signal with a potential opposite to that of the first potential pulse. For example, when the first potential pulse is low, the first power supply signal VGH can be multiplexed as a cutoff control signal (e.g., Figure 5 When the first potential pulse is at a high potential, the second power supply signal VGL can be multiplexed as a cutoff control signal.

[0098] like Figure 5 As shown, the channel types of the fourteenth transistor T14 and the twelfth transistor T12 can be different, and the gate of the fourteenth transistor T14 can be connected to the gate of the twelfth transistor T12. Alternatively, the channel types of the fourteenth transistor T14 and the twelfth transistor T12 can be the same, and the gate of the fourteenth transistor T14 can be connected to the gate of the thirteenth transistor T13.

[0099] Figure 6 This is a driving timing diagram of a scanning driving circuit provided in an embodiment of the present invention, which can be corresponding to... Figure 5 In the circuit structure, the driving timing when the input and output terminals of the transmission control module 20 are connected when the first shift register 10 outputs the first potential pulse is described. Combined with... Figure 5 and Figure 6It can be seen that the first shift register 10 shifts the first potential pulse (here, a low potential pulse) of the scan input signal SIN, and the first potential pulse in the stage transmission signal Carry corresponds to the low potential pulse in the second clock signal SCK2. During the first potential pulse stage of the stage transmission signal Carry, the transmission control signal C3 controls the twelfth transistor T12 to turn on, and the inverting transmission control signal C3B controls the thirteenth transistor T13 to turn on, so that the input and output terminals of the control transmission module 20 are connected. The second shift register 30 can receive the stage transmission signal Carry and realize the shift output of the first potential pulse of the stage transmission signal Carry, resulting in a scan signal GOUT with a conduction pulse. The conduction pulse of the scan signal GOUT corresponds to the low potential pulse in the first clock signal SCK1.

[0100] Figure 7 This is a driving timing diagram of another scanning driving circuit provided in an embodiment of the present invention, which can be corresponding to... Figure 5 In the circuit structure, the driving timing when the input and output terminals of the transmission control module 20 are disconnected when the first shift register 10 outputs the first potential pulse is considered. Figure 5 and Figure 7 During the first potential pulse phase of the transmission signal Carry, the transmission control signal C3 controls the twelfth transistor T12 to turn off, and the inverting transmission control signal C3B controls the thirteenth transistor T13 to turn off. When the input and output terminals of the transmission control module 20 are disconnected, the second shift register 30 cannot receive the transmission signal Carry. At this time, the transmission control signal C3 controls the fourteenth transistor T14 to turn on, so that the second shift register 30 stably receives the high potential of the first power supply signal VGH. Therefore, the scan signal GOUT output by the second shift register 30 maintains the cutoff potential (high potential here).

[0101] Based on the above embodiments, optionally, the scanning drive circuit 100 is connected to two transmission control signal lines, one of which is connected to the first control terminal of each transmission control module 20, and the other is connected to the second control terminal of each transmission control module 20. That is, both the transmission control signal C3 and the inverted transmission control signal C3B are global signals, capable of controlling the simultaneous on / off of all transmission control modules 20 on the screen. This configuration simplifies the wiring and control logic of the display panel and facilitates the implementation of narrow bezels.

[0102] Figure 8 This is a schematic diagram of the driving timing of another scanning driving circuit provided in an embodiment of the present invention. Figure 8The example provides an illustration of the output of six levels of scan signals, showing the first-level transmission signal Carry1 to the sixth-level transmission signal Carry6, and the first-level scan signal GOUT1 to the sixth-level scan signal GOUT6. See also... Figure 8 In the first type frame F1, the transmission control signal C3 remains high, and the inverting transmission control signal C3B remains low, ensuring that the input and output of the transmission control module 20 remain connected in the first type frame F1, resulting in conduction pulses in each level of the scan signal GOUT. In the second type frame F2, the transmission control signal C3 is low for some periods, and the inverting transmission control signal C3B is high for corresponding periods, causing the input and output of the transmission control module 20 to be disconnected during some periods in the second type frame F2. For example, in the first potential pulse stage of the third-level transmission signal Carry3 and the fourth-level transmission signal Carry4, the transmission control signal C3 is low, and the inverting transmission control signal C3B is high, resulting in no conduction pulses in the third scan signal GOUT3 and the fourth scan signal GOUT4. Figure 8 Taking the timing sequence as an example, the pulse frequencies of the third scan signal GOUT3 and the fourth scan signal GOUT4 are lower than those of other scan signals. Correspondingly, the refresh frequency of the display partitions corresponding to the third scan signal GOUT3 and the fourth scan signal GOUT4 is also lower than that of other display partitions, thus realizing multi-frequency display of the display panel. For example, the display partitions corresponding to the first scan signal GOUT1 and the second scan signal GOUT2 refresh at 120Hz, the display partitions corresponding to the third scan signal GOUT3 and the fourth scan signal GOUT4 refresh at 60Hz, and the display partitions corresponding to the fifth scan signal GOUT5 and the sixth scan signal GOUT6 refresh at 120Hz. This partitioned frequency driving is controlled by the transmission control signal C3 and the inverting transmission control signal C3B. By adjusting the pulse width or pulse position of the transmission control signal C3 and the inverting transmission control signal C3B, partitioned frequency driving can be achieved at any vertical position of the screen. For example, the partition width can be adjusted by adjusting the pulse width of the transmission control signal C3 and the inverted transmission control signal C3B, and the partition boundary position can be adjusted by adjusting the pulse position of the transmission control signal C3 and the inverted transmission control signal C3B.

[0103] Figure 9 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention. See also... Figure 9 In one embodiment, the scan drive circuit 100 may optionally be connected to four clock signal lines and two transmission control signal lines.

[0104] For example, the two transmission control signal lines are the first transmission control signal line LC3 and the second transmission control signal line LC3B, respectively; the first transmission control signal line LC3 is connected to the first control terminal PC3 of each transmission control module 20, and the second transmission control signal line LC3B is connected to the second control terminal P3CB of each transmission control module 20.

[0105] For example, the four clock signal lines are designated as the fifth clock signal line L1, the fifth inverted clock signal line L1B, the sixth clock signal line L2, and the sixth inverted clock signal line L2B. The fifth clock signal line L1 and the fifth inverted clock signal line L1B transmit clock signals that are inverted from each other, and the sixth clock signal line L2 and the sixth inverted clock signal line L2B transmit clock signals that are inverted from each other. The clock signals transmitted by the fifth clock signal line L1 and the sixth clock signal line L2 have the same pulse frequency, and low-level pulses alternate. The effective potential pulses of the clock signals transmitted by the fifth clock signal line L1 and the sixth clock signal line L2 are staggered.

[0106] For each functional module of the first level, the first clock terminal PCK1, the first inverted clock terminal PCK1B, and the second clock terminal PCK2 in the first shift register 10 of the first level are respectively connected to the fifth clock signal line L1, the fifth inverted clock signal line L1B, and the sixth clock signal line L2. Similarly, the first clock terminal PCK1, the first inverted clock terminal PCK1B, and the second clock terminal PCK2 in the second shift register 30 of the first level are respectively connected to the sixth clock signal line L2, the sixth inverted clock signal line L2B, and the fifth clock signal line L1. For each functional module of the second level, the first clock terminal PCK1, the first inverted clock terminal PCK1B, and the second clock terminal PCK2 in the first shift register 10 of the second level are respectively connected to the sixth clock signal line L2, the sixth inverted clock signal line L2B, and the fifth clock signal line L1. Likewise, the first clock terminal PCK1, the first inverted clock terminal PCK1B, and the second clock terminal PCK2 in the second shift register 30 of the second level are respectively connected to the fifth clock signal line L1, the fifth inverted clock signal line L1B, and the sixth clock signal line L2. The connection relationships between subsequent odd-numbered level functional modules and clock signal lines can refer to the first-level functional modules, and the connection relationships between subsequent even-numbered level functional modules and clock signal lines can refer to the second-level functional modules. Additionally, the input terminal of the first-level first shift register 10 can be connected to the input signal line LIN to receive the first scan input signal SIN1.

[0107] Based on the above embodiments, optionally, by adding an inverter at an appropriate position in the scanning drive circuit 100, the number of signal lines and / or the number of signal output channels and signal output ports of the driver chip can be effectively reduced, providing favorable conditions for reducing product power consumption and realizing flexible wiring of the display panel. Several of these configuration methods will be described below.

[0108] See also Figure 9 In one embodiment, optionally, an inverter 61 can be placed between the fifth clock signal line L1 and the fifth inverted clock signal line L1B to reduce the number of clock signal output terminals of the driver chip and lower the requirement for the number of output ports of the driver chip. This is equivalent to some of the first shift registers 10 in the same scan driver circuit sharing inverter 61, and other first shift registers 10 sharing inverter 62. For example, all odd-level first shift registers 10 share inverter 61, and all even-level first shift registers 10 share inverter 62. For example, the control terminal of inverter 61 can be connected to the fifth clock signal line L1, and the output terminal can be connected to the fifth inverted clock signal line L1B. Similarly, an inverter 62 can be placed between the sixth clock signal line L2 and the sixth inverted clock signal line L2B. This is equivalent to some of the second shift registers 30 in the same scan drive circuit sharing an inverter 61, while other second shift registers 10 share an inverter 62. For example, all odd-level second shift registers 30 share an inverter 62, and all even-level second shift registers 30 share an inverter 61. And / or, an inverter 63 can be placed between the first transmission control signal line LC3 and the second transmission control signal line LC3B. This is equivalent to all transmission control modules 20 in the same scan drive circuit sharing the same inverter. All of the above inverters can be placed at the bottom bezel of the display panel to reduce the area occupied by the side bezels of the display panel, which is beneficial for achieving a narrow bezel.

[0109] Figure 10 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention. See also... Figure 10 In another embodiment, optionally, an inverter 64 may be provided in the first shift register 10, connected between the first clock terminal PCK1 and the first inverted clock terminal PCK1B. For example, the control terminal of the inverter 64 is connected to the first clock terminal PCK1, and the output terminal is connected to the first inverted clock terminal PCK1B. This is equivalent to the first input unit 41 and the first transmission unit 44 in the same first shift register 10 sharing the same inverter.

[0110] The above scheme can be summarized as follows: The first shift register 10 further includes a third inverter, connected between the first clock input PCK1 and the first inverting clock input PCK1B. Optionally, at least two first shift registers 10 may share the same third inverter. Figure 9 As shown, inverter 61 is the third inverter shared by all odd-level first shift registers 10 after a portion, and inverter 62 is the third inverter shared by all even-level first shift registers 10 after a portion. Figure 10 As shown, inverter 64 is a third inverter set up separately for each of the first shift registers 1.

[0111] See also Figure 10 Similarly to the first shift register 10, an inverter 65 can be set in the same position in the second shift register 30. This is equivalent to the first input unit 41 and the first transmission unit 44 sharing the same inverter in the same second shift register 10. Figure 10 The blocks in the first shift register 10, excluding the inverter 64, are used to represent... Figure 3 The circuitry in the second shift register 30 is represented by the blocks excluding the inverter 65. Figure 3 The circuitry in the scan drive circuit 100 is described. By using inverters 64 and 65, the clock signal lines connected to each first inverted clock terminal PCK1B can be eliminated. Furthermore, by adding an inverter to each shift register, the number of clock signal lines can be reduced by half. Compared to the linewidth of the clock signal lines, the area occupied by transistors in the layout of the scan drive circuit 100 is smaller, thus this arrangement is beneficial for achieving a narrow bezel.

[0112] Figure 11 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention. See also... Figure 11 In another embodiment, optionally, each shift register may include at least one inverter. The structure of the first shift register 10 will be described below as an example; the adjustment method of the second shift register 30 is similar and will not be repeated. For example, see... Figure 11 ,exist Figure 3 Based on this, for the first shift register 10, the first inverter 46 can be connected between the first control terminal and the second control terminal of the first input unit 41, and / or the second inverter 47 can be connected between the first control terminal and the second control terminal of the first transmission unit 44. For example, the control terminal of the first inverter 46 can be connected to the first control terminal of the first input unit 41, and the output terminal of the first inverter 46 can be connected to the second control terminal of the first input unit 41; the control terminal of the second inverter 47 can be connected to the second control terminal of the first transmission unit 44, and the output terminal of the second inverter 47 can be connected to the first control terminal of the first transmission unit 44. This configuration allows the first inverted clock terminal in the shift register to function as an internal port, eliminating the need for a clock signal line connection. See also... Figure 12 There is no need to lay out each inverting clock signal line in the display panel, which also helps to achieve the effect of narrow bezel.

[0113] See also Figure 11In another embodiment, optionally, the transmission control module 20 further includes a tenth inverter 21 connected between the first control terminal and the second control terminal of the transmission control module 20, thus eliminating the need for a transmission control signal line. For example, the control terminal of the tenth inverter 21 is connected to the first control terminal PC3 of the transmission control module 20, and the output terminal of the tenth inverter 21 is connected to the second control terminal PC3B of the transmission control module 20. Then, as... Figure 12 As shown, the second transmission control signal line LC3B can be omitted, and only the first transmission control signal line LC3 needs to be set. Figure 11 The example provided illustrates a scheme where each transmission control module 20 includes a tenth inverter 21, but this is not intended to limit the invention. In other embodiments, some or all transmission control modules 20 may share the same tenth inverter. For example... Figure 9 As shown, inverter 63 can be used as the tenth inverter shared by all transmission control modules 20.

[0114] Based on the above embodiments, optionally, the display panel may further include a first power line (not shown in the figure) for providing a first power signal VGH; and a second power line (not shown in the figure) for providing a second power signal VGL. In the display panel, the input signal line LIN, each transmission control signal line, each power line, and each clock signal line can all be connected to a driver chip, and the driver chip provides corresponding signals to each signal line.

[0115] The above embodiments exemplify a scheme in which two clock signal lines are set for the first clock terminal PCK1 and the second clock terminal PCK2 of each stage of the first shift register 10 (e.g.) Figure 12 This allows for full-screen driving using fewer clock signal lines. However, the above wiring method is not intended to limit the invention. In other embodiments, optionally, four clock signal lines can be provided for the first clock terminal PCK1 and the second clock terminal PCK2 of each stage of the first shift register 10, as illustrated below.

[0116] Figure 13 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention. See also... Figure 13 In another embodiment, the display panel may optionally include: a first clock signal line LCK1, a second clock signal line LCK2, a third clock signal line LCK3, and a fourth clock signal line LCK4. See also... Figure 14The low-level pulses of the first global clock signal CLK1 transmitted by the first clock signal line LCK1, the second global clock signal CLK2 transmitted by the second clock signal line LCK2, the third global clock signal CLK3 transmitted by the third clock signal line LCK3, and the fourth global clock signal CLK4 transmitted by the fourth clock signal line LCK4 do not overlap, and their initial pulses appear sequentially. The frequencies of the first global clock signal CLK1, the second global clock signal CLK2, the third global clock signal CLK3, and the fourth global clock signal CLK4 are the same. Within one pulse period of the first global clock signal CLK1, the effective pulses of the first global clock signal CLK1, the second global clock signal CLK2, the third global clock signal CLK3, and the fourth global clock signal CLK4 (e.g., ...) Figure 14 As shown, for example, low-level pulses (with a pulse width less than or equal to one-quarter of the pulse period of the first global clock signal CLK1) appear sequentially and are staggered, i.e., they do not overlap. Specifically, the initial low-level pulses of the first global clock signal CLK1, the second global clock signal CLK2, the third global clock signal CLK3, and the fourth global clock signal CLK4 are delayed sequentially by a preset time (e.g., one-quarter of a pulse period), and the low-level pulses of adjacent global clock signals do not overlap. The low-level pulse width of the global clock signal is less than or equal to the preset time. The pulse periods of the four global clock signals are the same.

[0117] like Figure 13 As shown, the first clock input PCK1 of the 4k-3 stage first shift register 10 can be connected to the first clock signal line LCK1, and the second clock input PCK2 of the 4k-3 stage first shift register 10 can be connected to the second clock signal line LCK2; the first clock input PCK1 of the 4k-2 stage first shift register 10 can be connected to the second clock signal line LCK2, and the second clock input PCK2 of the 4k-2 stage first shift register 10 can be connected to the third clock signal line LCK3; the first clock input PCK1 of the 4k-1 stage first shift register 10 can be connected to the third clock signal line LCK3, and the second clock input PCK2 of the 4k-1 stage first shift register 10 can be connected to the fourth clock signal line LCK4; the first clock input PCK1 of the 4k stage first shift register 10 can be connected to the fourth clock signal line LCK4, and the second clock input PCK2 of the 4k stage first shift register 10 can be connected to the first clock signal line LCK1. Where k is a positive integer.

[0118] Correspondingly, when the circuit structure of the second shift register 30 is the same as or similar to that of the first shift register 10, the first clock terminal PCK1 of the 4k-3 stage second shift register 30 can be connected to the second clock signal line LCK2, and the second clock terminal PCK2 of the 4k-3 stage second shift register 30 can be connected to the first clock signal line LCK1; the first clock terminal PCK1 of the 4k-2 stage second shift register 30 can be connected to the third clock signal line LCK3, and the second clock terminal PCK2 of the 4k-2 stage second shift register 30 can be connected to the second clock signal line LCK2; the first clock terminal PCK1 of the 4k-1 stage second shift register 30 can be connected to the fourth clock signal line LCK4, and the second clock terminal PCK2 of the 4k-1 stage second shift register 30 can be connected to the third clock signal line LCK3; the first clock terminal PCK1 of the 4k stage second shift register 30 can be connected to the first clock signal line LCK1, and the second clock terminal PCK2 of the 4k stage second shift register 30 can be connected to the fourth clock signal line LCK4.

[0119] This embodiment is designed to achieve a scanning drive circuit 100 based on four clock signal lines. Compared to setting only two clock signal lines, the load on each clock signal line is reduced and the equivalent impedance of the clock signal lines is reduced, which can effectively reduce the power consumption of the product.

[0120] It should be noted that the above embodiments exemplarily illustrate the connection relationship between each clock signal line and each clock terminal, but do not mention the connection between the inverting clock terminal and the inverting clock signal line. In other embodiments, optionally, when the scan driving circuit 100 adopts other structures provided in the above embodiments, for example... Figure 9 In the structure described above, if each clock terminal also has a corresponding inverted clock terminal, then corresponding inverted clock signal lines can be set accordingly. The connection method between each inverted clock signal line and each inverted clock terminal can refer to the connection method between each clock signal line and each clock terminal. As long as the first clock terminal PCK1 and the first inverted clock terminal PCK1B in the same shift register are connected to two clock signals that are inverted from each other, it will not be elaborated here.

[0121] The above embodiments exemplify that the conduction pulse of the scan signal GOUT and the first potential pulse of the stage transmission signal Carry have the same potential, but this is not intended to limit the invention. In other embodiments, optionally, the conduction pulse of the scan signal GOUT and the first potential pulse of the stage transmission signal Carry have different potentials. The following description uses the example of the conduction pulse of the scan signal GOUT being at a high potential and the first potential pulse of the stage transmission signal Carry being at a low potential.

[0122] Figure 15This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention. See also... Figure 15 The scan drive circuit 100 includes multiple register groups 101. Each j (j is an integer greater than or equal to 2, for example, j is 2) of the first shift registers 10 forms a register group 101. The first first shift register 10 in each register group 101 is connected to a transmission control module 20. The structure and driving timing of the second shift register 30 that can be used in this architecture are described below.

[0123] Figure 16 This is a schematic diagram of the structure of a second shift register provided in an embodiment of the present invention. See also... Figure 16 In one embodiment, optionally, the second shift register 30 includes: a third clock terminal PCK3 and / or a third inverting clock terminal PCK3B, and a fourth clock terminal PCK4 and / or a fourth inverting clock terminal PCK4B. The second shift register 30 is used to shift and output the signal input to the input terminal IN2 of the second shift register 20 according to the signals input to the third clock terminal PCK3 and / or the third inverting clock terminal PCK3B, and the fourth clock terminal PCK4 and / or the fourth inverting clock terminal PCK4B, and output a scan signal from the output terminal OUT2 of the second shift register 20. In the above "AND / OR" relationship, the following examples provide specific descriptions for the "AND" case; the circuit principle for the "OR" case is similar and will not be repeated. Specifically, the signals input to the third clock terminal PCK3 and the third inverting clock terminal PCK3B are inverted signals; the signals input to the fourth clock terminal PCK4 and the fourth inverting clock terminal PCK4B are also inverted signals. For example, the signals connected to the first clock terminal PCK1 and the second clock terminal PCK2 of the first shift register 10 have the same pulse frequency and pulse width, and the first potential pulses appear alternately. The signals connected to the third clock terminal PCK3 and the fourth clock terminal PCK4 of the second shift register 30 have the same pulse frequency and pulse width, and the first potential pulses appear alternately. The pulse frequency of the signal connected to the first clock terminal PCK1 of the first shift register 10 is j times the pulse frequency of the signal connected to the corresponding third clock terminal PCK3 of the second shift register 30, for example, twice, that is, j is 2. Each first potential pulse in the signal connected to the third clock terminal PCK3 of the second shift register 30 corresponds, for example, to a portion of the first potential pulses in the signal connected to the corresponding second clock terminal PCK2 of the first shift register 10, and the pulse widths are the same.

[0124] See Figure 16 Based on the above embodiments, optionally, the second shift register 30 includes: a second input unit 51, a third inverting unit 52, a second transmission unit 53, a fourth inverting unit 54, and a second output unit 55.

[0125] The input terminal of the second input unit 51 is connected to the input terminal IN2 of the second shift register 30. The first control terminal of the second input unit 51 is connected to the third clock terminal PCK3, and / or, the second control terminal of the second input unit 51 is connected to the third inverting clock terminal PCK3B. The control terminal of the third inverting unit 52 is connected to the output terminal of the second input unit 51. The first input terminal of the third inverting unit 52 is connected to a first power supply signal, for example, the first input terminal of the third inverting unit 52 is connected to the first power supply terminal PVGH2 of the second shift register 30. The second input terminal of the third inverting unit 52 is connected to a second power supply signal, for example, the second input terminal of the third inverting unit 52 is connected to the second power supply terminal PVGL2 of the second shift register 30. The input terminal of the second transmission unit 53 is connected to the output terminal of the third inverting unit 52. The first control terminal of the second transmission unit 53 is connected to the fourth clock terminal PCK4, and / or, the second control terminal of the second transmission unit 53 is connected to the fourth inverting clock terminal PCK4B. The control terminal of the fourth inverting unit 54 is connected to the output terminal of the second transmission unit 53. The first input terminal of the fourth inverting unit 54 is connected to a first power supply signal, for example, the first input terminal of the fourth inverting unit 54 is connected to the first power supply terminal PVGH2 of the second shift register 30. The second input terminal of the fourth inverting unit 54 is connected to a second power supply signal, for example, the second input terminal of the fourth inverting unit 54 is connected to the second power supply terminal PVGL2 of the second shift register 30. The second output unit is connected to the output terminal of the second transmission unit, the output terminal of the fourth inverting unit, and the output terminal of the second shift register 30. The first control terminal of the second output unit 55 is connected to the output terminal of the fourth inverting unit 54. The second control terminal of the second output unit 55 is connected to the output terminal of the second transmission unit 53. The first input terminal of the second output unit 55 is connected to a first power supply signal, for example, the first input terminal of the second output unit 55 is connected to the first power supply terminal PVGH2 of the second shift register 30. The second input terminal of the second output unit 55 is connected to a second power supply signal, for example, the second input terminal of the second output unit 55 is connected to the second power supply terminal PVGL2 of the second shift register 30. The output terminal of the second output unit 55 is connected to the output terminal OUT2 of the second shift register 30.

[0126] The first power supply terminal PVGH2 of the second shift register 30 can be connected to a first power supply signal, and the second power supply terminal PVGL2 can be connected to a second power supply signal.

[0127] The second input unit 51 is used to control whether to output the signal connected to the input terminal IN2 of the second shift register 30 according to the potential of the third clock terminal PCK3 and / or the third inverting clock terminal PCK3B. The third inverting unit 532 is used to invert the potential of the output terminal of the second input unit 51 and output it. The second transmission unit 53 is used to control whether to output the potential of the output terminal of the third inverting unit 52 according to the potential of the fourth clock terminal PCK4 and / or the fourth inverting clock terminal PCK4B. The fourth inverting unit 54 is used to invert the potential output by the second transmission unit 53 and output it. The second output unit 55 is used to control whether to output the first power signal or the second power signal as a scan signal according to the potential of the output terminal of the second transmission unit 53 and the output terminal of the fourth inverting unit 54. For example, the second output unit 55 controls whether the first input terminal and the output terminal of the second output unit 55 are connected according to the potential of the output terminal of the fourth inverting unit 54, and controls whether the second input terminal and the output terminal of the second output unit 55 are connected according to the potential of the output terminal of the second transmission unit 53. The second input unit 51 and the second transmission unit 53 in the same second shift register can be turned on in a time-division manner.

[0128] Figure 17 This is a schematic diagram of another second shift register provided in an embodiment of the present invention. See also... Figure 17 Furthermore, the second shift register 30 may also include a fifth inverting unit 56 and a third transmission unit 57. The fifth inverting unit 56 is connected to the output terminal of the third inverting unit 52 and is connected to a first power supply signal and a second power supply signal. For example, the control terminal of the fifth inverting unit 56 is connected to the output terminal of the third inverting unit 52, the first input terminal of the fifth inverting unit 56 is connected to the first power supply signal, and the second input terminal of the fifth inverting unit 56 is connected to the second power supply signal. The fifth inverting unit 56 is used to invert the potential output by the third inverting unit 52 and then output it. The third transmission unit 57 is connected between the control terminal of the third inverting unit 52 (or the output terminal of the second input unit 51) and the output terminal of the fifth inverting unit 56. The first control terminal of the third transmission unit 57 is connected to the third inverting clock terminal PCK3B, and / or the second control terminal of the third transmission unit 57 is connected to the third clock terminal PCK3. The third transmission unit 57 is used to control whether the control terminal of the third inverting unit 52 and the output terminal of the fifth inverting unit 56 are connected based on the potential of the third clock terminal PCK3 and / or the third inverting clock terminal PCK3B. The on / off states of the third transmission unit 57 and the second input unit 51 in the same second shift register can be opposite.

[0129] The specific functions of the fifth inverting unit 56 and the third transmission unit 57 can be found in the description of the second inverting unit 43 and the first transmission unit 44 in the first shift register 10, and will not be repeated here.

[0130] See also Figure 17 Based on the above embodiments, optionally, the second shift register 30 may further include a sixth inverting unit 58 and a fourth transmission unit 59. The sixth inverting unit 58 is connected to the output terminal of the fourth inverting unit 54 and is connected to a first power signal and a second power signal, used to invert the potential output by the fourth inverting unit 54 before outputting it. The fourth transmission unit 59 is connected between the control terminal of the fourth inverting unit 54 (or the output terminal of the second transmission unit 53) and the output terminal of the sixth inverting unit 58, and the first control terminal of the fourth transmission unit 59 is connected to the fourth inverting clock terminal PCK4B, and / or the second control terminal of the fourth transmission unit 59 is connected to the fourth clock terminal PCK4. The fourth transmission unit 59 is used to control whether the control terminal of the fourth inverting unit 54 and the output terminal of the sixth inverting unit 58 are connected according to the potential of the fourth clock terminal PCK4 and / or the fourth inverting clock terminal PCK4B. The on / off states of the second transmission unit 53 and the fourth transmission unit 59 in the same second shift register may be opposite.

[0131] The specific functions of the sixth inverting unit 58 and the fourth transmission unit 59 can be found in the description of the second inverting unit 43 and the first transmission unit 44 in the first shift register 10, and will not be repeated here.

[0132] See also Figure 17 Based on the above embodiments, optionally, the second shift register 30 further includes a coupling module for coupling control of the potential of the second control terminal of the second output unit 55 based on the potential transition of the third clock terminal PCK3, so as to improve the output stability of the second shift register 30. Specifically, the coupling module may include: an initialization unit 71, a fifth transmission unit 75, a sixth transmission unit 73, a coupling unit 72, and a switching unit 74.

[0133] An initialization unit 71 has a first power signal input, a control terminal connected to the output of a second input unit 51, and an output terminal connected to the first terminal of a coupling unit 72. The initialization unit 71 is used to turn on or off based on the potential of the output of the second input unit 51. A fifth transmission unit 75 is connected between the output of the second transmission unit 53 and the second terminal of the coupling unit 72, and is used to turn on or off based on the potential of the third clock terminal PCK3. A sixth transmission unit 73 is connected between the third clock terminal PCK3 and the first terminal of the coupling unit 72, and its control terminal is connected to the output of the fifth transmission unit 75. The sixth transmission unit 73 is used to turn on or off based on the potential of its control terminal. The control terminal and the first terminal of a switching unit 74 are both connected to the second terminal of the coupling unit 72. The second terminal of the switching unit 74 is connected to the second control terminal of the second output unit 55, and the switching unit 74 is used to turn on or off based on the potential of its control terminal.

[0134] Specifically, the fifth transmission unit 75 is used to transmit the potential of the output terminal of the second transmission unit 53 to the second terminal of the coupling unit 72 in response to the signal input to the third clock terminal PCK3; the sixth transmission unit 73 is used to transmit the signal input to the third clock terminal PCK3 to the first terminal of the coupling unit 72 in response to the potential of the second terminal of the coupling unit 72; the coupling unit 72 is used to perform potential coupling on the second terminal of the coupling unit 72 when the signal input to the third clock terminal PCK3 undergoes a potential transition; the switching unit 74 is used to transmit the potential after coupling at the second terminal of the coupling unit 72 to the second control terminal of the second output unit 55.

[0135] For example, when the second control terminal of the second output unit 55 is connected to a low potential, the second input terminal and the output terminal of the second output unit 55 are connected to conduction. When the third clock terminal PCK3 is connected to a high potential and the output terminal of the second transmission unit 53 is at a low potential, the voltage difference across the coupling unit 72 is the high potential minus the low potential. When the signal connected to the third clock terminal PCK3 jumps from a high potential to a low potential, the coupling unit 72 couples the low potential to the second terminal of the coupling unit 72, making the second terminal of the coupling unit 72 an ultra-low potential. The switching unit 74 transmits this ultra-low potential to the second control terminal of the second output unit 55, thereby controlling the second input terminal and the output terminal of the second output unit 55 to conduct fully, so that the second output unit 55 can accurately output the second power signal and improve the accuracy of the scan signal GOUT.

[0136] Based on this, the initialization unit 71 is used to respond to the potential of the output terminal of the second input unit 51, transmit the first power signal to the first terminal of the coupling unit 72, reset the first terminal of the coupling unit 72, clear the residual charge of the first terminal of the coupling unit 72, so as to facilitate the subsequent coupling control of the coupling unit 72.

[0137] Based on the above embodiments, optionally, the second shift register 30 further includes a reset unit 76. The reset unit 76 is connected between the reset terminal PV1 of the second shift register 30 and the second control terminal of the second output unit 55, and the control terminal of the reset unit 76 is connected to the reset control terminal PRST of the second shift register 30. For example, the reset control terminal PRST is connected to a reset control signal, and the reset terminal PV1 can be connected to a first power signal. Specifically, when the display panel is first powered on, the reset control signal controls the reset unit 76 to conduct, and the reset unit 76 transmits the first power signal to the second control terminal of the second output unit 55, so that the second output unit 55 does not output a second power signal. Simultaneously, the fourth inverting unit 54 inverts the first power signal, making the first input terminal and output terminal of the second output unit 55 conduct, and the second output unit 55 outputs the first power signal, thereby resetting the second shift register 30.

[0138] The working process of the second shift register 30 will be explained below in conjunction with the specific structure of the second shift register 30.

[0139] See also Figure 17 Specifically, optionally, see reference. Figure 7 or Figure 8 The second input unit 51 includes a thirty-sixth transistor T36 and / or a thirty-seventh transistor T37. The gate of the thirty-sixth transistor T36 is connected to the third clock terminal PCK3, the first terminal of the thirty-sixth transistor T36 is connected to the input terminal IN2 of the second shift register 30, and the second terminal of the thirty-sixth transistor T36 is connected to the output terminal of the second input unit 51. The gate of the thirty-seventh transistor T37 is connected to the third inverting clock terminal PCK3B, the first terminal of the thirty-seventh transistor T37 is connected to the input terminal IN2 of the second shift register 30, and the second terminal of the thirty-seventh transistor T37 is connected to the output terminal of the second input unit 51. The thirty-seventh transistor T37 and the thirty-sixth transistor T36 are connected in parallel. The thirty-sixth transistor T36 and the thirty-seventh transistor T37 have different channel types; for example, the thirty-sixth transistor T36 is a P-type transistor, and the thirty-seventh transistor T37 is an N-type transistor.

[0140] The third inverting unit 52 includes a twenty-first transistor T21 and a twenty-second transistor T22. The gates of both transistors T21 and T22 are connected to the output of the second input unit 51. The first terminal of transistor T21 is connected to a first power supply signal, and the second terminals of both transistors T21 and T22 are connected to the output of the third inverting unit 52. The first terminal of transistor T22 is connected to a second power supply signal. The twenty-first transistor T21 and T22 have different channel types; for example, transistor T21 is a P-type transistor, and T22 is an N-type transistor.

[0141] The second transmission unit 53 includes a twenty-third transistor T23 and / or a twenty-fourth transistor T24. The gate of the twenty-third transistor T23 is connected to the fourth clock terminal PCK4, the first terminal of the twenty-third transistor T23 is connected to the output terminal of the third inverting unit 52, and the second terminal of the twenty-third transistor T23 is connected to the control terminal of the fourth inverting unit 54. The gate of the twenty-fourth transistor T24 is connected to the fourth inverting clock terminal PCK4B, the first terminal of the twenty-fourth transistor T24 is connected to the output terminal of the third inverting unit 52, and the second terminal of the twenty-fourth transistor T24 is connected to the control terminal of the fourth inverting unit 54. The twenty-fourth transistor T24 and the twenty-third transistor T23 are connected in parallel. The twenty-third transistor T23 and the twenty-fourth transistor T24 have different channel types; for example, the twenty-third transistor T23 is a P-type transistor, and the twenty-fourth transistor T24 is an N-type transistor. The thirty-sixth transistor T36 and the twenty-third transistor T23 may have the same channel type. The twenty-fourth transistor T24 and the thirty-seventh transistor T37 may have the same channel type. The channel types of transistor T36 (thirty-sixth transistor) and transistor T24 (twenty-fourth transistor) may be different. The channel types of transistor T24 (twenty-fourth transistor) and transistor T23 (twenty-third transistor) may also be different.

[0142] The fourth inverting unit 54 includes a twenty-fifth transistor T25 and a twenty-sixth transistor T26. The gates of both transistors T25 and T26 are connected to the output of the second transmission unit 53. The first terminal of transistor T25 is connected to a first power supply signal, and the first terminal of transistor T26 is connected to a second power supply signal. The second terminals of both transistors T25 and T26 are connected to the output of the fourth inverting unit 54. The twenty-fifth transistor T25 and T26 have different channel types; for example, transistor T25 is a P-type transistor, and T26 is an N-type transistor.

[0143] The fifth inverting unit 56 includes a thirty-second transistor T32 and a thirty-third transistor T33. The gates of the thirty-second transistor T32 and the thirty-third transistor T33 are the control terminals of the fifth inverting unit 56. The first terminal of the thirty-second transistor T32 is connected to a first power supply signal, and the first terminal of the thirty-third transistor T33 is connected to a second power supply signal. The second terminals of the thirty-second transistor T32 and the thirty-third transistor T33 are connected to the output terminals of the fifth inverting unit 56. The thirty-second transistor T32 and the thirty-third transistor T33 have different channel types; for example, the thirty-second transistor T32 is a P-type transistor, and the thirty-third transistor T33 is an N-type transistor.

[0144] The third transmission unit 57 includes a thirty-fourth transistor T34 and / or a thirty-fifth transistor T35. The gate of the thirty-fourth transistor T34 is connected to the third inverting clock terminal PCK3B, the first terminal of the thirty-fourth transistor T34 is connected to the output terminal of the fifth inverting unit 56, and the second terminal of the thirty-fourth transistor T34 is connected to the control terminal of the third inverting unit 52. The gate of the thirty-fifth transistor T35 is connected to the third clock terminal PCK3, the first terminal of the thirty-fifth transistor T35 is connected to the output terminal of the fifth inverting unit 56, and the second terminal of the thirty-fifth transistor T35 is connected to the control terminal of the third inverting unit 52. The thirty-fifth transistor T35 and the thirty-fourth transistor T34 are connected in parallel. The thirty-fourth transistor T34 and the thirty-fifth transistor T35 have different channel types; for example, the thirty-fourth transistor T34 is a P-type transistor, and the thirty-fifth transistor T35 is an N-type transistor. The thirty-fourth transistor T34 and the thirty-sixth transistor T36 may have the same channel type. The thirty-fifth transistor T35 and the thirty-seventh transistor T37 may have the same channel type. The channel types of transistors T36 (thirty-sixth) and T35 (thirty-fifth) may be different. The channel types of transistors T37 (thirty-seventh) and T34 (thirty-fourth) may also be different.

[0145] The sixth inverting unit 58 includes a thirty-eighth transistor T38 and a thirty-ninth transistor T39. The gates of both transistors T38 and T39 are connected to the control terminal of the sixth inverting unit 58. The first terminal of transistor T38 is connected to a first power supply signal, and the first terminal of transistor T39 is connected to a second power supply signal. The second terminals of both transistors T38 and T39 are connected to the output terminal of the sixth inverting unit 58. The thirty-eighth transistor T38 and the thirty-ninth transistor T39 have different channel types; for example, transistor T38 is a P-type transistor, and transistor T39 is an N-type transistor.

[0146] The fourth transmission unit 59 includes a 40th transistor T40 and / or a 41st transistor T41. The gate of the 40th transistor T40 is connected to the fourth inverting clock terminal PCK4B, the first terminal of the 40th transistor T40 is connected to the output terminal of the sixth inverting unit 58, and the second terminal of the 40th transistor T40 is connected to the control terminal of the fourth inverting unit 54. The gate of the 41st transistor T41 is connected to the fourth clock terminal PCK4, the first terminal of the 41st transistor T41 is connected to the output terminal of the sixth inverting unit 58, and the second terminal of the 41st transistor T41 is connected to the control terminal of the fourth inverting unit 54. The 41st transistor T41 is connected in parallel with the 40th transistor T40. The 40th transistor T40 and the 41st transistor T41 have different channel types; for example, the 40th transistor T40 is a P-type transistor, and the 41st transistor T41 is an N-type transistor. The 40th transistor T40 and the 23rd transistor T23 may have the same channel type. The 40th transistor T40 and the 24th transistor T24 may have different channel types. The channel type of transistor T41 (41) and transistor T24 (24) can be the same. The channel type of transistor T41 (41) and transistor T23 (23) can be different.

[0147] The second output unit 55 includes a forty-second transistor T42 and a forty-third transistor T43. The gate of the forty-second transistor T42 is connected to the first control terminal of the second output unit 55, the first terminal of the forty-second transistor T42 is connected to a first power supply signal, and the second terminal of the forty-second transistor T42 is connected to the output terminal OUT2 of the second shift register 30. The gate of the forty-third transistor T43 is connected to the second control terminal of the second output unit 55, the first terminal of the forty-third transistor T43 is connected to a second power supply signal, and the second terminal of the forty-third transistor T43 is connected to the output terminal OUT2 of the second shift register 30. The forty-second transistor T42 and the forty-third transistor T43 have the same channel type, for example, both are P-type transistors.

[0148] Furthermore, the second output unit 55 also includes a forty-fifth transistor T45, the gate of which is connected to a second power supply signal. The forty-fifth transistor T45 is connected between the output terminal of the second transmission unit 53 and the second control terminal (or the gate of the forty-third transistor T43) of the second output unit 55. The forty-fifth transistor T45 is, for example, a P-type transistor.

[0149] The fifth transmission unit 75 includes a twenty-seventh transistor T27; the gate of the twenty-seventh transistor T27 is connected to the third clock terminal PCK3, the first terminal of the twenty-seventh transistor T27 is connected to the control terminal of the fourth inverting unit 54, and the second terminal of the twenty-seventh transistor T27 is connected to the second terminal of the coupling unit 72. The twenty-seventh transistor T27 is, for example, an N-type transistor.

[0150] Furthermore, the fifth transmission unit 75 also includes a twenty-eighth transistor T28; the gate of the twenty-eighth transistor T28 is connected to a second power supply signal, and the twenty-eighth transistor T28 is connected between the second terminal of the twenty-seventh transistor T27 and the second terminal of the coupling unit 72. The twenty-eighth transistor T28 is, for example, a P-type transistor. By setting the twenty-eighth transistor T28, the ultra-low potential of the second terminal of the coupling unit 72 can be prevented from being transmitted to the fourth transmission unit 59 and the second transmission unit 53, and damage to the second transmission unit 53 and the fourth transmission unit 59 can be avoided.

[0151] The sixth transmission unit 73 includes a twenty-ninth transistor T29; the gate of the twenty-ninth transistor T29 is connected to the output terminal of the fifth transmission unit 75, the first terminal of the twenty-ninth transistor T29 is connected to the third clock terminal PCK3, and the second terminal of the twenty-ninth transistor T29 is connected to the first terminal of the coupling unit 72. The twenty-ninth transistor T29 is, for example, a P-type transistor.

[0152] The coupling unit 72 includes a second capacitor C2; the first electrode of the second capacitor C2 is the first terminal of the coupling unit 72, and the second electrode of the second capacitor C2 is the second terminal of the coupling unit 72.

[0153] Switching unit 154 includes a thirtieth transistor T30; the gate of the thirtieth transistor T30 is connected to the output terminal of the fifth transmission unit 75, the first terminal of the thirtieth transistor T30 is connected to the second terminal of the coupling unit 72, and the second terminal of the thirtieth transistor T30 is connected to the gate of the forty-third transistor T43. The thirtieth transistor T30 is, for example, a P-type transistor.

[0154] The initialization unit 71 includes a thirty-first transistor T31. The gate of the thirty-first transistor T31 is connected to the output terminal of the second input unit 51. The first terminal of the thirty-first transistor T31 is connected to a first power supply signal, and the second terminal of the thirty-first transistor T31 is connected to the first terminal of the second capacitor C2. The thirty-first transistor T31 is, for example, a P-type transistor.

[0155] The reset unit 76 includes a forty-fourth transistor T44. The gate of the forty-fourth transistor T44 is connected to the reset control terminal PRST, the first terminal of the forty-fourth transistor T44 is connected to the reset terminal PV1, and the second terminal of the forty-fourth transistor T44 is connected to the output terminal of the second transmission unit 53. The forty-fourth transistor T44 is, for example, a P-type transistor.

[0156] Figure 18 This is a schematic diagram illustrating the driving timing of a second shift register according to an embodiment of the present invention. (Combined with...) Figure 17 and Figure 18The signal connected to the input terminal IN2 of the second shift register 30 is denoted as the second input signal EIN, the signal connected to the third clock terminal PCK3 is denoted as the third clock signal ECK1, the signal connected to the third inverting clock terminal PCK3B is denoted as the third inverting clock signal ECK1B, the signal connected to the fourth clock terminal PCK4 is denoted as the fourth clock signal ECK2, and the signal connected to the fourth inverting clock terminal PCK4B is denoted as the fourth inverting clock signal ECK2B. Taking the first potential pulse as a low potential pulse and the conduction pulse as a high potential pulse as an example, the driving process of the second shift register 30 is as follows:

[0157] In the first stage t1', the second input signal EIN is low, the third clock signal ECK1 is low, the third inverted clock signal ECK1B is high, the fourth clock signal ECK2 is high, and the fourth inverted clock signal ECK2B is low. Transistors T36 and T37 are turned on, outputting the second input signal EIN. Then, transistor T21 is turned on, and the third inverting unit 52 outputs the first power supply signal, i.e., a high output. Transistors T34 and T35 are turned off. Transistors T23 and T24 are also turned off. The output potential of the second transmission unit 53 remains the same as in the previous stage. Therefore, the second output unit 55 maintains the output state of the previous period, and the scan signal GOUT is low.

[0158] In the second stage t2', the second input signal EIN is high, the third clock signal ECK1 is high, the third inverted clock signal ECK1B is low, the fourth clock signal ECK2 is low, and the fourth inverted clock signal ECK2B is high. The thirty-sixth transistor T36 and the thirty-seventh transistor T37 are turned off, the output of the second input unit 51 remains low, the third inverting unit 52 outputs a high level, and the thirty-third transistor T33 turns on, outputting a low level. The thirty-fourth transistor T34 and the thirty-fifth transistor T35 turn on, keeping the control terminal of the third inverting unit 52 low. The twenty-third transistor T23 and the twenty-fourth transistor T24 turn on, the second transmission unit 53 outputs a high level, and the forty-third transistor T43 turns off. The fourth inverting unit 54 outputs a low level, and the forty-second transistor T42 turns on, outputting the first power supply signal. During this stage, the scan signal GOUT is high.

[0159] When the control terminal of the third inverting unit 52 is at a low potential, the thirty-first transistor T31 is turned on, transmitting the first power supply signal to the first terminal of the second capacitor C2, initializing the first terminal of the second capacitor C2. Since the third clock signal ECK1 is at a high potential, the twenty-seventh transistor T27 is turned on, transmitting the high potential output by the twenty-third transistor T23 and the twenty-fourth transistor T24 to the second terminal of the second capacitor C2, initializing the second terminal of the second capacitor C2. Furthermore, the twenty-ninth transistor T29 and the thirtieth transistor T30 are turned off, and will not couple to the second control terminal of the second output unit 55.

[0160] In the third stage t3', the second input signal EIN is high, the third clock signal ECK1 is low, the third inverted clock signal ECK1B is high, the fourth clock signal ECK2 is high, and the fourth inverted clock signal ECK2B is low. Transistors T36 and T37 are turned on, outputting the second input signal EIN. Transistor T22 is turned on, and the third inverting unit 52 outputs the second power signal. Transistors T23 and T24 are turned off, not conducting. The control terminal of the fourth inverting unit 54 maintains the high potential from the previous stage, and transistor T42 remains on. The second output unit 55 outputs the first power signal. Transistor T38 is turned on, and the sixth inverting unit 58 outputs the first power signal. Transistors T40 and T41 are turned on, transmitting the high potential to the control terminal of the fourth inverting unit 54, ensuring that the control terminal of the fourth inverting unit 54 remains high. During this stage, the scan signal GOUT remains high.

[0161] In the fourth stage t4', the second input signal EIN is high, the third clock signal ECK1 is high, the third inverted clock signal ECK1B is low, the fourth clock signal ECK2 is low, and the fourth inverted clock signal ECK2B is high. Transistors T36 and T37 are off, maintaining the output of the second input unit 51 at a high level. Transistor T22 outputs the second power supply signal, transistor T32 is on, the fifth inverting unit 56 outputs the first power supply signal, and transistors T34 and T35 are on, ensuring the output of the second input unit 51 remains high. Transistors T23 and T24 are on, transmitting the low potential to the control terminal of the fourth inverting unit 54. Transistor T43 is on, the fourth inverting unit 54 outputs a high potential, and transistor T42 is off. During this stage, the scan signal GOUT is low.

[0162] At this time, the third clock signal ECK1 is at a high potential, the twenty-seventh transistor T27 is turned on, and the low potential output by the twenty-third transistor T23 and the twenty-fourth transistor T24 is transmitted to the second terminal of the second capacitor C2. The twenty-ninth transistor T29 is turned on, and the high potential of the third clock signal ECK1 is transmitted to the first terminal of the second capacitor C2. The voltage difference across the second capacitor C2 is the high potential minus the low potential.

[0163] In the fifth stage t5', the second input signal EIN is high, the third clock signal ECK1 is low, the third inverted clock signal ECK1B is high, the fourth clock signal ECK2 is high, and the fourth inverted clock signal ECK2B is low. The thirty-sixth transistor T36 and the thirty-seventh transistor T37 are turned on, the second input unit 51 outputs a high level, and the twenty-second transistor T22 outputs the second power supply signal, i.e., a low level. However, the twenty-third transistor T23 and the twenty-fourth transistor T24 are turned off, and the control terminal of the fourth inverting unit 54 maintains the low level from the previous stage.

[0164] The second terminal of the second capacitor C2 is at a low potential, and the twenty-ninth transistor T29 and the thirtieth transistor T30 are turned on. The twenty-ninth transistor T29 transmits the third clock signal ECK1 to the first terminal of the second capacitor C2, that is, the first terminal of the second capacitor C2 changes from a high potential to a low potential. Due to capacitive coupling, the second terminal of the second capacitor C2 becomes an ultra-low potential, and the thirtieth transistor T30 turns on, transmitting this ultra-low potential to the gate of the forty-third transistor T43, thereby keeping the forty-third transistor T43 on and outputting the second power supply signal, that is, the scan signal GOUT, at a low potential.

[0165] The subsequent stages repeat the driving process of the fourth stage t4' and the fifth stage t5' until the second input signal EIN jumps low again. If the second input signal EIN remains high and does not have a low-level stage, then the driving process of the second shift register 30 does not have the second stage t2' and the third stage t3', but instead continuously repeats the fourth stage t4' and the fifth stage t5', keeping the scan signal GOUT at the cutoff potential (low level in this case).

[0166] Figure 19 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention; Figure 19 The example shows a primary transmission control module 20 and its connected first shift register 10 and second shift register 30. See also Figure 19 For example, the first shift register 10 may employ as follows: Figure 3 In the structure described above, the second shift register 30 can be adopted as follows: Figure 17 The structure of the transmission control module 20 can be found in the section on... Figure 5 The explanation.

[0167] Figure 20 This is a driving timing diagram of another scanning driving circuit provided in an embodiment of the present invention, which can be corresponding to... Figure 19 In the circuit structure, the driving timing when the input and output terminals of the transmission control module 20 are connected when the first shift register 10 outputs the first potential pulse is described. Combined with... Figure 19 and Figure 20 It can be seen that the first shift register 10 shifts the first potential pulse (here, a low potential pulse) of the scan input signal SIN, and the first potential pulse in the stage transmission signal Carry corresponds to the low potential pulse in the second clock signal SCK2. During the first potential pulse stage of the stage transmission signal Carry, the transmission control signal C3 controls the twelfth transistor T12 to turn on, and the inverting transmission control signal C3B controls the thirteenth transistor T13 to turn on, so that the input and output terminals of the control transmission module 20 are connected. The second shift register 30 can receive the stage transmission signal Carry and realize the conversion of the first potential pulse of the stage transmission signal Carry to obtain the scan signal GOUT with a high potential conduction pulse.

[0168] Conversely, during the first potential pulse phase of the transmission signal Carry, the transmission control signal C3 controls the twelfth transistor T12 to turn off, and the inverting transmission control signal C3B controls the thirteenth transistor T13 to turn off. When the input and output terminals of the transmission control module 20 are disconnected, the second shift register 30 cannot receive the transmission signal Carry. At this time, the transmission control signal C3 controls the fourteenth transistor T14 to turn on, so that the second shift register 30 stably receives the high potential of the first power supply signal VGH, and the scan signal GOUT output by the second shift register 30 is maintained at the cutoff potential.

[0169] During the display process, the reset control signal RST received by the reset control terminal PRST can be maintained at a high potential, so that the forty-fourth transistor T44 remains in the off state and does not affect the normal operation of the second shift register 30 at each stage.

[0170] Figure 21 This is a schematic diagram of the driving timing of another scanning driving circuit provided in an embodiment of the present invention. Figure 21 The example provides four levels of scan signals, with corresponding data for the first-level transmission signal Carry1, the third-level transmission signal Carry3, the fifth-level transmission signal Carry5, and the seventh-level transmission signal Carry7. See also... Figure 21In the first type frame F1, the transmission control signal C3 remains at a high potential, and the inverting transmission control signal C3B remains at a low potential, ensuring that the input and output terminals of the transmission control module 20 remain connected in the first type frame F1, thus providing conduction pulses in each level of the scan signal GOUT. In the second type frame F2, the transmission control signal C3 is at a low potential for a certain period, and the inverting transmission control signal C3B is at a high potential for the corresponding period, thus disconnecting the input and output terminals of the transmission control module 20 during a certain period in the second type frame F2. For example, during the first potential pulse stage from the third-level transmission signal Carry3 to the fifth-level transmission signal Carry5, the transmission control signal C3 is at a low potential, and the inverting transmission control signal C3B is at a high potential, ensuring that there are no conduction pulses in the second scan signal GOUT2 and the third scan signal GOUT3, maintaining a cutoff potential.

[0171] Figure 22 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention; see also Figure 22 In one embodiment, optionally, the scan drive circuit 100 is connected to eight clock signal lines and two transmission control signal lines. The arrangement of the clock signal lines connected to each of the first shift registers 10 and their various variations, as well as the arrangement of the transmission control signal lines connected to each of the transmission control modules 20 and their various variations, can be found in the descriptions of the above embodiments and will not be repeated here. The following mainly describes the arrangement of the clock signal lines related to the second shift register 30.

[0172] For example, the four clock signal lines associated with the second shift register 30 are the seventh clock signal line L7, the seventh inverted clock signal line L7B, the eighth clock signal line L8, and the eighth inverted clock signal line L8B. The seventh clock signal line L7 and the seventh inverted clock signal line L7B transmit clock signals that are inverted from each other, and the eighth clock signal line L8 and the eighth inverted clock signal line L8B transmit clock signals that are inverted from each other. The clock signals transmitted by the seventh clock signal line L7 and the eighth clock signal line L8 have the same pulse frequency and pulse width, and low-level pulses appear alternately.

[0173] The third clock input PCK3, the third inverted clock input PCK3B, the fourth clock input PCK4, and the fourth inverted clock input PCK4B in the first-stage second shift register 30 are respectively connected to the seventh clock signal line L7, the seventh inverted clock signal line L7B, the eighth clock signal line L8, and the eighth inverted clock signal line L8B. Similarly, the third clock input PCK3, the third inverted clock input PCK3B, the fourth clock input PCK4, and the fourth inverted clock input PCK4B in the second-stage second shift register 30 are respectively connected to the eighth clock signal line L8, the eighth inverted clock signal line L8B, the seventh clock signal line L7, and the seventh inverted clock signal line L7B. The connection relationships between subsequent odd-numbered stage second shift registers 30 and the clock signal lines can be referenced to those of the first-stage second shift register 30, and the connection relationships between subsequent even-numbered stage second shift registers 30 and the clock signal lines can be referenced to those of the second-stage second shift register 30.

[0174] Based on the above embodiments, optionally, by adding an inverter at an appropriate position in the second shift register, the number of signal lines and / or the number of signal output channels and signal output ports of the driver chip can be effectively reduced, providing favorable conditions for reducing product power consumption and realizing flexible wiring of the display panel. Several of these configuration methods are described below.

[0175] See also Figure 22 In one embodiment, optionally, an inverter 66 can be disposed between the seventh clock signal line L7 and the seventh inverted clock signal line L7B, and / or an inverter 67 can be disposed between the eighth clock signal line L8 and the eighth inverted clock signal line L8B. All of the above inverters can be disposed at the bottom bezel of the display panel to reduce the area occupied by the side bezel of the display panel, which is beneficial for achieving a narrow bezel.

[0176] Figure 23 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention; see also Figure 10 In another embodiment, optionally, the second shift register 30 may also include two inverters; wherein, the eighth inverter 68 is connected between the third clock terminal PCK3 and the third inverting clock terminal PCK3B, which is equivalent to the second input unit 51 and the third transmission unit 57 sharing the same inverter in the same second shift register 30. The ninth inverter 69 is connected between the fourth clock terminal PCK4 and the fourth inverting clock terminal PCK4B, which is equivalent to the second transmission unit 53 and the fourth transmission unit 59 sharing the same inverter in the same second shift register 30. Figure 23 The blocks in the second shift register 30, excluding inverters 68 and 69, are used to represent this. Figure 17The circuit in the circuit. By setting inverters 68 and 69, the inverter clock signal lines connected to each third inverter clock terminal PCK3B and each fourth inverter clock terminal PCK4B can be eliminated. By adding two inverters to each second shift register 30, the number of clock signal lines can be reduced by half.

[0177] The above embodiments exemplify the separate configuration of an eighth inverter and a ninth inverter in each second shift register 30, but this is not intended to limit the invention. In other embodiments, at least two second shift registers 30 may share the same eighth inverter; for example, some or all of the second shift registers 30 may share the same eighth inverter. Figure 22 As shown, inverter 66 can serve as the eighth inverter shared by some or all of the odd-level second shift registers 30, and inverter 67 can serve as the eighth inverter shared by some or all of the even-level second shift registers 30. And / or, at least two second shift registers 30 can also be configured to share the same ninth inverter, for example, some or all of the second shift registers 30 can share the same ninth inverter. Figure 22 As shown, inverter 67 can serve as the ninth inverter shared by some or all of the odd-stage second shift registers 30, and inverter 66 can serve as the ninth inverter shared by some or all of the even-stage second shift registers 30. The eighth inverter in some or all of the odd-stage second shift registers 30 can be multiplexed as the ninth inverter in some or all of the even-stage second shift registers 30. The ninth inverter in some or all of the odd-stage second shift registers 30 can be multiplexed as the eighth inverter in some or all of the even-stage second shift registers 30.

[0178] Figure 24 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention. See also... Figure 24 In another embodiment, optionally, each second shift register 30 may be configured with: a fourth inverter 81 connected between the first and second control terminals of the second input unit 51, and / or a seventh inverter 84 connected between the first and second control terminals of the fourth transmission unit 59; and a fifth inverter 83 connected between the first and second control terminals of the second transmission unit 53, and / or a sixth inverter 82 connected between the first and second control terminals of the third transmission unit 57. Figure 24 As shown, all four inverters can be configured in the second shift register 30. This configuration allows each inverting clock input in the second shift register 30 to function as an internal port, eliminating the need for connecting inverting clock signal lines. See also... Figure 25 There is no need to lay out each inverting clock signal line in the display panel, which also helps to achieve the effect of narrow bezel.

[0179] The above embodiments exemplify a scheme in which two clock signal lines are provided for the first clock terminal PCK1 and the second clock terminal PCK2 of each stage of the first shift register 10. However, the above wiring method is not intended to limit the present invention. In other embodiments, optionally, see [link to other embodiments]. Figure 26 For the first clock input PCK1 and the second clock input PCK2 of each stage of the first shift register 10, four clock signal lines can also be set. The connection relationship between the four clock signal lines and each stage of the first shift register 10 can be found in the... Figure 13 The description will not be repeated here.

[0180] Figure 27 This is a schematic diagram of an inverter provided in an embodiment of the present invention. See also... Figure 27 All of the inverters mentioned above can adopt this structure. Specifically, the inverter may include transistors T18 and T19. The gates of transistors T18 and T19 are both connected to the control terminal NC of the inverter. The first terminal of transistor T18 is connected to a first power supply signal VGH, and the first terminal of transistor T19 is connected to a second power supply signal VGL. The second terminals of transistors T18 and T19 are both connected to the output terminal NO of the inverter. Transistors T18 and T19 have different channel types; for example, transistor T18 is a P-type transistor, and transistor T19 is an N-type transistor. Exemplarily, this inverter can be fabricated using CMOS technology.

[0181] It should be noted that in the above embodiments, specific explanations are given for the "and" case in the setting relationship where "and / or" exists. In actual applications, the scanning drive circuit can also operate normally in any "or" case, and the circuit principle is similar, so it will not be described again.

[0182] This invention also provides a display panel, including one or more scanning driving circuits provided in any embodiment of this invention, which have corresponding beneficial effects. Figure 28 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. See also: Figure 28 The display panel includes a display area AA and a non-display area NAA. A scan drive circuit 100 may be disposed in the non-display area NAA, and multiple scan lines LS extend into the display area AA to transmit scan signals to each sub-pixel (not shown) in the display area AA. Exemplarily, the output of each second shift register 3030 is connected to at least one scan line LS, and one scan line LS, for example, connects to at least one row of sub-pixels, so that the display panel supports the display of different frequencies of partitions in the column direction. Sub-pixels may include pixel circuitry and light-emitting devices.

[0183] Based on the above embodiments, optionally, the display panel further includes: a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line. The first clock terminal of the 4k-3 stage first shift register 10 is connected to the first clock signal line, and the second clock terminal of the 4k-3 stage first shift register 10 is connected to the second clock signal line; the first clock terminal of the 4k-2 stage first shift register 10 is connected to the second clock signal line, and the second clock terminal of the 4k-2 stage first shift register 10 is connected to the third clock signal line; the first clock terminal of the 4k-1 stage first shift register 10 is connected to the third clock signal line, and the second clock terminal of the 4k-1 stage first shift register 10 is connected to the fourth clock signal line; the first clock terminal of the 4k stage first shift register 10 is connected to the fourth clock signal line, and the second clock terminal of the 4k stage first shift register 10 is connected to the first clock signal line; where k is a positive integer.

[0184] Alternatively, the display panel may also include: a fifth clock signal line and a sixth clock signal line; the first clock terminal of the odd-level first shift register 10 is connected to the fifth clock signal line, and the second clock terminal of the odd-level first shift register 10 is connected to the sixth clock signal line; the first clock terminal of the even-level first shift register 10 is connected to the sixth clock signal line, and the second clock terminal of the even-level first shift register 10 is connected to the fifth clock signal line.

[0185] Based on the above embodiments, optionally, when the second shift register 30 includes a third clock terminal and a fourth clock terminal, the display panel further includes a seventh clock signal line and an eighth clock signal line; the third clock terminal of the odd-level second shift register 30 is connected to the seventh clock signal line, and the fourth clock terminal of the odd-level second shift register 30 is connected to the eighth clock signal line; the third clock terminal of the even-level second shift register 30 is connected to the eighth clock signal line, and the fourth clock terminal of the even-level second shift register 30 is connected to the seventh clock signal line.

[0186] Optionally, the display panel includes multiple scan driving circuits, including a first scan driving circuit and a second scan driving circuit. The first and second scan driving circuits share multiple first shift registers 10. The second shift register 30 in the first scan driving circuit may include some or all of the first input unit, first inverting unit, first output unit, second inverting unit, and first transmission unit, for example, with... Figure 11The structures shown are the same or similar. The second shift register 30 in the second scan drive circuit may include some or all of the following: a second input unit, a third inverting unit, a second transmission unit, a fourth inverting unit, a second output unit, a fifth inverting unit, a third transmission unit, a sixth inverting unit, a fourth transmission unit, an initialization unit, a fifth transmission unit, a sixth transmission unit, a coupling unit, and a switching unit, for example, with... Figure 19 The structures shown are the same or similar.

[0187] In the first and second scan drive circuits, one outputs a high-potential turn-on pulse for the scan signal, while the other outputs a low-potential turn-on pulse. For example, the first scan drive circuit can output a scan signal to a scan line connected to the data write transistor in the pixel circuit, and the turn-on pulse of the scan signal output by the first scan drive circuit can control the data write transistor (which can be a P-type transistor) to turn on. Similarly, the second scan drive circuit can output a scan signal to a scan line connected to the threshold compensation transistor (which can be an N-type transistor) in the pixel circuit, and the turn-on pulse of the scan signal output by the second scan drive circuit can control the threshold compensation transistor to turn on.

[0188] For example, a second shift register 30 in the first scan driving circuit can be electrically connected to one row of pixel circuits, equivalent to one-to-one operation. For example, a second shift register 30 in the second scan driving circuit can be electrically connected to at least two rows (e.g., j rows, where j is a positive integer greater than or equal to 2) of pixel circuits, equivalent to one-to-two or one-to-many operation.

[0189] It should be noted that in the various embodiments of the scanning drive circuit, specific descriptions are provided for different display panel wiring structures. These structures can be considered as the relevant structures of the display panel provided in the embodiments of the present invention, and repeated content will not be described here.

[0190] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0191] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A scanning drive circuit, characterized in that, include: Multiple first shift registers; The first shift register is used to shift the signal input to the first shift register and output the signal; wherein, the output of the first shift register in this stage is connected to the input of the first shift register in the next stage; Multiple transmission control modules are provided, with their input terminals respectively connected to at least a portion of the output terminals of the first shift register; each transmission control module is used to output the transmission signal when it is turned on. Multiple second shift registers are provided, with their inputs respectively connected to the outputs of multiple transmission control modules; the second shift registers are used to output scan signals based on the signals input to their inputs. The second shift register further includes: a third clock input and / or a third inverted clock input, and a fourth clock input and / or a fourth inverted clock input. The second shift register is used to shift and output the signal input to the second shift register according to the signals input to the third clock input and / or the third inverted clock input, and the fourth clock input and / or the fourth inverted clock input. The signals input to the third clock input and the third inverted clock input are inverted signals. The signals input to the fourth clock input and the fourth inverted clock input are inverted signals. The second shift register includes: The second input unit has its input terminal connected to the input terminal of the second shift register, its first control terminal connected to the third clock terminal, and / or its second control terminal connected to the third inverting clock terminal; the second input unit is used to control whether to output the signal connected to the input terminal of the second shift register according to the potential of the third clock terminal and / or the third inverting clock terminal. The third inverting unit is connected to the output terminal of the second input unit and is connected to the first power signal and the second power signal. It is used to invert the potential of the output terminal of the second input unit and output it. The second transmission unit has its input terminal connected to the output terminal of the third inverting unit, its first control terminal connected to the fourth clock terminal, and / or its second control terminal connected to the fourth inverting clock terminal; the second transmission unit is used to control whether to output the potential of the output terminal of the third inverting unit according to the potential of the fourth clock terminal and / or the fourth inverting clock terminal. The fourth inverting unit is connected to the output terminal of the second transmission unit and is connected to the first power signal and the second power signal. It is used to invert the potential output by the second transmission unit and then output it. The second output unit is connected to the output terminal of the second transmission unit, the output terminal of the fourth inverting unit, and the output terminal of the second shift register, respectively, and is connected to the first power signal and the second power signal. It is used to control the first power signal or the second power signal as the scan signal output according to the potential of the output terminal of the second transmission unit and the potential of the output terminal of the fourth inverting unit. The second shift register further includes: an initialization unit, a fifth transmission unit, a sixth transmission unit, a coupling unit, and a switching unit; The input terminal of the initialization unit is connected to the first power signal, the control terminal of the initialization unit is connected to the output terminal of the second input unit, the output terminal of the initialization unit is connected to the first terminal of the coupling unit, and the initialization unit is used to turn on or off according to the potential of the output terminal of the second input unit. The fifth transmission unit is connected between the output terminal of the second transmission unit and the second terminal of the coupling unit, and is used to turn on or off according to the potential of the third clock terminal; The sixth transmission unit is connected between the third clock terminal and the first terminal of the coupling unit, and the control terminal of the sixth transmission unit is connected to the output terminal of the fifth transmission unit. The sixth transmission unit is used to turn on or off according to the potential of the control terminal of the sixth transmission unit. The control terminal and the first terminal of the switching unit are both connected to the second terminal of the coupling unit. The second terminal of the switching unit is connected to the second output unit. The switching unit is used to turn on or off according to the potential of the control terminal of the switching unit.

2. The scanning drive circuit according to claim 1, characterized in that, The first shift register is used to shift the signal input to the first shift register and output a staged signal according to the signal input to the first clock terminal and / or the first inverted clock terminal and the second clock terminal of the first shift register; wherein the signals input to the first clock terminal and the first inverted clock terminal are inverted signals.

3. The scanning drive circuit according to claim 2, characterized in that, The first shift register includes: A first input unit, wherein the input terminal of the first input unit is connected to the input terminal of the first shift register, the first control terminal of the first input unit is connected to the first clock terminal, and / or, the second control terminal of the first input unit is connected to the first inverting clock terminal; the first input unit is used to control whether to output the signal connected to the input terminal of the first shift register according to the potential of the first clock terminal and / or the first inverting clock terminal. The first inverting unit is connected to the output terminal of the first input unit and is connected to a first power signal and a second power signal, and is used to invert the potential of the output terminal of the first input unit and output it. The first output unit is connected to the output terminal of the first input unit, the output terminal of the first inverting unit, the second clock terminal of the first shift register, and the output terminal of the first shift register, respectively, and is connected to the first power supply signal. It is used to control the first power supply signal or the signal connected to the second clock terminal as the output signal of the first shift register according to the potential of the output terminal of the first input unit and the potential of the output terminal of the first inverting unit.

4. The scanning drive circuit according to claim 3, characterized in that, The first shift register also includes: The second inverting unit is connected to the output terminal of the first inverting unit and is connected to the first power signal and the second power signal. It is used to invert the potential output by the first inverting unit and then output it. A first transmission unit is connected between the control terminal of the first inverting unit and the output terminal of the second inverting unit, and the first control terminal of the first transmission unit is connected to the first inverting clock terminal, and / or the second control terminal of the first transmission unit is connected to the first clock terminal; the first transmission unit is used to control whether the control terminal of the first inverting unit and the output terminal of the second inverting unit are connected according to the potential of the first clock terminal and / or the first inverting clock terminal.

5. The scanning drive circuit according to claim 4, characterized in that, The on / off states of the first input unit and the first transmission unit in the same first shift register are opposite.

6. The scanning drive circuit according to claim 4, characterized in that, The first shift register also includes: The first inverter is connected between the first control terminal and the second control terminal of the first input unit. And / or, a second inverter, connected between the first control terminal and the second control terminal of the first transmission unit; Alternatively, the first shift register may further include a third inverter connected between the first clock input and the first inverted clock input.

7. The scanning drive circuit according to claim 6, characterized in that, At least two of the first shift registers share the same third inverter.

8. The scanning drive circuit according to any one of claims 1-7, characterized in that, Each of the first shift registers is connected to one of the transmission control modules; the first shift register is used to configure the first potential pulse in the signal connected to the input terminal of the first shift register as the first potential pulse in the transmission signal, and the second shift register is used to configure the first potential pulse in the signal connected to the input terminal of the second shift register as the conduction pulse in the scan signal.

9. The scanning drive circuit according to claim 8, characterized in that, The conduction pulse has the same potential level as the first potential pulse.

10. The scanning drive circuit according to claim 8, characterized in that, The circuit structure of the second shift register is the same as that of the first shift register.

11. The scanning drive circuit according to claim 8, characterized in that, In the first shift register and the second shift register connected to the same transmission control module, the first clock terminal of the first shift register and the second clock terminal of the second shift register are connected to the same clock signal line, and the second clock terminal of the first shift register and the first clock terminal of the second shift register are connected to the same clock signal line. The pulse width and pulse frequency of the signals connected to the first clock terminal and the second clock terminal of the first shift register are the same.

12. The scanning drive circuit according to any one of claims 1-7, characterized in that, The scan driving circuit includes multiple register groups, each register group including at least two first shift registers, and the first first shift register in each register group is connected to one of the transmission control modules; the first shift register is used to configure the first potential pulse in the signal connected to the input terminal of the first shift register as the first potential pulse in the transmission signal; The second shift register is used to configure the first potential pulse in the signal connected to the input terminal of the second shift register as the conduction pulse in the scan signal.

13. The scanning drive circuit according to claim 12, characterized in that, The conduction pulse has a different potential level than the first potential pulse.

14. The scanning drive circuit according to claim 12, characterized in that, The pulse frequencies of the signals connected to the first clock terminal and the second clock terminal of the first shift register are the same, and the pulse frequencies of the signals connected to the third clock terminal and the fourth clock terminal of the second shift register are the same. Each register group includes j of the first shift registers, where j is an integer greater than or equal to 2, and the pulse frequency of the signal connected to the first clock terminal of the first shift register is j times the pulse frequency of the signal connected to the third clock terminal of the second shift register.

15. The scanning drive circuit according to claim 14, characterized in that, j=2。 16. The scanning drive circuit according to claim 1, characterized in that, The second shift register also includes: The fifth inverting unit is connected to the output terminal of the third inverting unit and is connected to the first power signal and the second power signal. It is used to invert the potential output by the third inverting unit and then output it. A third transmission unit is connected between the control terminal of the third inverting unit and the output terminal of the fifth inverting unit, and the first control terminal of the third transmission unit is connected to the third inverting clock terminal, and / or the second control terminal of the third transmission unit is connected to the third clock terminal; the third transmission unit is used to control whether the control terminal of the third inverting unit and the output terminal of the fifth inverting unit are connected according to the potential of the third clock terminal and / or the third inverting clock terminal. The sixth inverting unit is connected to the output terminal of the fourth inverting unit and is connected to the first power signal and the second power signal. It is used to invert the potential output by the fourth inverting unit and then output it. A fourth transmission unit is connected between the control terminal of the fourth inverting unit and the output terminal of the sixth inverting unit, and the first control terminal of the fourth transmission unit is connected to the fourth inverting clock terminal, and / or the second control terminal of the fourth transmission unit is connected to the fourth clock terminal; the fourth transmission unit is used to control whether the control terminal of the fourth inverting unit and the output terminal of the sixth inverting unit are connected according to the potential of the fourth clock terminal and / or the fourth inverting clock terminal.

17. The scanning drive circuit according to claim 1, characterized in that, The second input unit and the second transmission unit in the same second shift register are time-division multiplexed.

18. The scanning drive circuit according to claim 16, characterized in that, The on / off states of the second input unit and the third transmission unit in the same second shift register are opposite.

19. The scanning drive circuit according to claim 16, characterized in that, The on / off states of the second transmission unit and the fourth transmission unit in the same second shift register are opposite.

20. The scanning drive circuit according to claim 16, characterized in that, The second shift register further includes: a fourth inverter connected between the first control terminal and the second control terminal of the second input unit, and / or a seventh inverter connected between the first control terminal and the second control terminal of the fourth transmission unit; and the second shift register further includes: a fifth inverter connected between the first control terminal and the second control terminal of the second transmission unit, and / or a sixth inverter connected between the first control terminal and the second control terminal of the third transmission unit. Alternatively, the second shift register may further include: an eighth inverter connected between the third clock terminal and the third inverted clock terminal, and / or a ninth inverter connected between the fourth clock terminal and the fourth inverted clock terminal.

21. The scanning drive circuit according to claim 20, characterized in that, At least two of the second shift registers share the same eighth inverter, and / or at least two of the second shift registers share the same ninth inverter.

22. The scanning drive circuit according to claim 1, characterized in that, The transmission control module includes a twelfth transistor. The first terminal of the twelfth transistor is connected to the output terminal of the first shift register to which the transmission control module is connected. The second terminal of the twelfth transistor is connected to the input terminal of the second shift register to which the transmission control module is connected. The gate of the twelfth transistor is connected to the first control terminal of the transmission control module.

23. The scanning drive circuit according to claim 22, characterized in that, The transmission control module further includes a thirteenth transistor, which is connected in parallel with the twelfth transistor, and the gate of the thirteenth transistor is connected to the second control terminal of the transmission control module; wherein the twelfth transistor and the thirteenth transistor have different channel types, and the signals input to the first control terminal and the second control terminal of the transmission control module are inverted signals.

24. The scanning drive circuit according to claim 22, characterized in that, The transmission control module further includes a fourteenth transistor, the gate of which is connected to either the first or second control terminal of the transmission control module. The first terminal of the fourteenth transistor is connected to a cutoff control signal, and the second terminal of the fourteenth transistor is connected to the input terminal of the second shift register to which the transmission control module is connected. The conduction state of the fourteenth transistor is opposite to that of the twelfth transistor.

25. The scanning drive circuit according to claim 1, characterized in that, The transmission control module further includes a tenth inverter, connected between the first control terminal and the second control terminal of the transmission control module.

26. The scanning drive circuit according to claim 25, characterized in that, Some or all of the transmission control modules share the same tenth inverter.

27. A display panel, characterized in that, include: The scan driving circuit as described in any one of claims 1-26, and a plurality of scan lines; the output of each of the second shift registers is connected to at least one of the scan lines.

28. The display panel according to claim 27, characterized in that, Also includes: First clock signal line, second clock signal line, third clock signal line, and fourth clock signal line; The first clock terminal of the first shift register of the 4k-3 stage is connected to the first clock signal line, and the second clock terminal of the first shift register of the 4k-3 stage is connected to the second clock signal line; The first clock terminal of the first shift register of the 4k-2 stage is connected to the second clock signal line, and the second clock terminal of the first shift register of the 4k-2 stage is connected to the third clock signal line; The first clock terminal of the first shift register of the 4k-1 stage is connected to the third clock signal line, and the second clock terminal of the first shift register of the 4k-1 stage is connected to the fourth clock signal line. The first clock terminal of the 4k-stage first shift register is connected to the fourth clock signal line, and the second clock terminal of the 4k-stage first shift register is connected to the first clock signal line. Where k is a positive integer; or, The display panel also includes: a fifth clock signal line and a sixth clock signal line; The first clock terminal of the odd-stage first shift register is connected to the fifth clock signal line, and the second clock terminal of the odd-stage first shift register is connected to the sixth clock signal line; The first clock terminal of the even-stage first shift register is connected to the sixth clock signal line, and the second clock terminal of the even-stage first shift register is connected to the fifth clock signal line.

29. The display panel according to claim 27, characterized in that, When the second shift register includes a third clock terminal and a fourth clock terminal, the display panel further includes a seventh clock signal line and an eighth clock signal line; The third clock terminal of the odd-stage second shift register is connected to the seventh clock signal line, and the fourth clock terminal of the odd-stage second shift register is connected to the eighth clock signal line. The third clock terminal of the even-numbered stage second shift register is connected to the eighth clock signal line, and the fourth clock terminal of the even-numbered stage second shift register is connected to the seventh clock signal line.

30. The display panel according to claim 27, characterized in that, The scan driving circuit is a plurality of circuits, including a first scan driving circuit and a second scan driving circuit, wherein the first scan driving circuit and the second scan driving circuit share the plurality of first shift registers.

31. The display panel according to claim 30, characterized in that, The scanning signal turn-on pulse output by one of the first scanning driving circuit and the second scanning driving circuit is a high-potential turn-on pulse, while the scanning signal turn-on pulse output by the other is a low-potential turn-on pulse.

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