Display panel, driving method and display device

Abstract

Embodiments of the present application provide a display panel, a driving method and a display device, and relate to the field of display panels. In the display panel, n effective pixel rows are electrically connected with n reset control signal lines; the display panel works in a first target mode or a second target mode; in the first target mode, in a picture display period, at a first time and a second time when a reset signal is provided for a light emitting device, there are m reset control signal lines in the n reset control signal lines, and only the reset control signal provided by the m reset control signal lines is at an enable level; in the second target mode, target reset control signal lines in the n reset control signal lines at the first time and the second time in the picture display period are different; target signals corresponding to the first time and the second time are different, and the target signals are used to adjust the light emitting brightness of the light emitting device. According to the embodiments of the present application, the brightness uniformity can be better achieved.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a display panel, driving method and display device. Background Technology

[0002] With the rapid development of display technology, new types of display panels, such as Organic Light Emitting Diode (OLED) and Micro Light Emitting Diode (micro LED), are emerging in large numbers, and full-screen displays have become the development trend of mobile display devices such as mobile phones. However, the inventors of this application have discovered that current display panels are prone to uneven brightness in some scenarios, resulting in poor display performance. Summary of the Invention

[0003] This application provides a display panel, a driving method, and a display device that can better achieve brightness uniformity, thereby effectively improving the display effect of the display panel.

[0004] In a first aspect, embodiments of this application provide a display panel, the display panel comprising:

[0005] There are n valid pixel rows, arranged along a first direction; each valid pixel row includes multiple sub-pixels arranged along a second direction; each sub-pixel in each valid pixel row includes a pixel circuit and a light-emitting device; the pixel circuit includes a reset module, which is used to provide a reset signal to the light-emitting device under the control of a reset control signal;

[0006] There are n reset control signal lines, each of which is electrically connected to the control terminal of the reset module in one of the n effective pixel rows. Each reset control signal line is used to provide a reset control signal to the reset module in the corresponding effective pixel row.

[0007] The display panel operates in either the first target mode or the second target mode;

[0008] In the first type of target mode, within one screen display cycle, at the first and second moments when providing reset signals to the light-emitting device, only m of the n reset control signal lines provide reset control signals at the enable level; m is a positive integer less than n.

[0009] In the second type of target mode, there are a first time and a second time in the screen display cycle. The number of target reset control signal lines in the n reset control signal lines in the first time is different from the number of target reset control signal lines in the n reset control signal lines in the second time. The target reset control signal line is a reset control signal line with the reset control signal at the enable level. The target signal corresponding to the first time is different from the target signal corresponding to the second time. The target signal is used to adjust the light emission brightness of the light-emitting device.

[0010] According to the implementation of the first aspect of this application, in order to more reasonably achieve the following at the first and second moments of the screen display cycle, the number of reset control signal lines with enable level provided by the above n reset control signal lines is consistent, that is, the connected load remains unchanged, including: a screen display cycle of the display panel includes an effective display period and a vertical blanking period; in the first type of target mode, the reset control signal on the same reset control signal line has k enable pulses within the screen display cycle, or the reset control signal on the same reset control signal line has k enable pulses after the data writing stage within a refresh frame; k is determined based on the duration of the effective display period and the duration of the vertical blanking period, and k is a positive integer.

[0011] According to the implementation of the first aspect of this application, k is determined based on the ratio of the duration of the effective display period to the duration of the vertical blanking period.

[0012] According to the implementation of the first aspect of this application, k is determined based on the ratio of the duration of the effective display period corresponding to the maximum refresh rate of the display panel to the duration of the vertical blanking period.

[0013] According to an embodiment of the first aspect of this application, the ratio of the duration of the effective display period to the duration of the vertical blanking period is q / v, where q and v are integers, and k is equal to the sum of q and v.

[0014] According to the first aspect of the present application, the pulse duration of each of the k enable pulses is the same and is a first duration; the interval between any two adjacent enable pulses in the k enable pulses is the same and is a second duration.

[0015] According to the implementation of the first aspect of this application, the sum of the first duration and the second duration is equal to the duration of the vertical blanking period.

[0016] According to the implementation of the first aspect of this application, k equals (t1 / t2)+1, where t1 is the product of the total number of rows of pixel circuits in the display area of ​​the display panel and the row scanning time, and t2 is the duration of the vertical blanking period; the row scanning time is the time for the reset control signal to scan the corresponding row of pixel circuits, or the row scanning time is the minimum time interval between the start times of the enable pulses of the reset control signals corresponding to two adjacent rows of pixel circuits.

[0017] According to an embodiment of the first aspect of this application, the pixel circuit includes a driving module and a bias adjustment module; the driving module is used to drive the light-emitting device to emit light; the bias adjustment module is used to provide a bias adjustment signal to a first end or a second end of the driving module under the control of a first scan signal.

[0018] According to an embodiment of the first aspect of this application, the reset control signal is different from the first scan signal, or the reset control signal is multiplexed as the first scan signal.

[0019] According to the first aspect of this application, the method includes: in the second type of target mode, the number of enable pulses of the reset control signal on the same reset control signal line during the screen display cycle is greater than or equal to 2, and the target signal at the first moment is different from the target signal at the second moment.

[0020] According to the first aspect of this application, the display panel operates in a first target mode, a second target mode, or a third target mode; in the third target mode, the reset control signal on the same reset control signal line has one and only one enable pulse within the screen display cycle.

[0021] According to an embodiment of the first aspect of this application, the pixel circuit includes a driving module and a bias adjustment module; the driving module is used to drive the light-emitting device to emit light; the bias adjustment module is used to provide a bias adjustment signal to a first or second terminal of the driving module under the control of a first scan signal; wherein, the number of enable pulses of the first scan signal corresponding to the same pixel circuit within the screen display cycle is greater than or equal to 2.

[0022] According to an embodiment of the first aspect of this application, in the second type of target mode, the target signal includes a reset signal.

[0023] According to an embodiment of the first aspect of this application, at a first time, the number of target reset control signal lines among the n reset control signal lines is the number of first signal lines; at a second time, the number of target reset control signal lines among the n reset control signal lines is the number of second signal lines; the number of first signal lines is less than the number of second signal lines; the voltage value of the reset signal at the first time is Vref21; the voltage value of the reset signal at the second time is Vref22; wherein, the absolute value of Vref21 is less than the absolute value of Vref22.

[0024] According to the implementation of the first aspect of this application, Vref21 and Vref22 are negative numbers, and Vref21 > Vref22.

[0025] According to an embodiment of the first aspect of this application, the difference between Vref21 and Vref22 is determined based on the number of first signal lines and the number of second signal lines.

[0026] According to an embodiment of the first aspect of this application, the difference between Vref21 and Vref22 is determined based on the difference between the number of first signal lines and the number of second signal lines.

[0027] According to an embodiment of the first aspect of this application, the voltage value of the reset signal at the first moment is adjusted so that Vref21 > Vref22.

[0028] According to an embodiment of the first aspect of this application, the pixel circuit includes a driving module and a bias adjustment module; the driving module is used to drive the light-emitting device to emit light; the bias adjustment module is used to provide a bias adjustment signal to a first end or a second end of the driving module under the control of a first scan signal; the target signal includes the bias adjustment signal.

[0029] According to an embodiment of the first aspect of this application, if the reset control signal is multiplexed as a first scan signal, the voltage value of the bias adjustment signal at the first moment is different from the voltage value of the bias adjustment signal at the second moment.

[0030] According to an embodiment of the first aspect of this application, the reset control signal is different from the first scan signal; the first effective pixel row includes: the effective pixel row corresponding to the target reset control signal line among the n reset control signal lines at the first time; the second effective pixel row includes: the effective pixel row corresponding to the target reset control signal line among the n reset control signal lines at the second time; the voltage value of the bias adjustment signal corresponding to the first effective pixel row is different from the voltage value of the bias adjustment signal corresponding to the second effective pixel row.

[0031] According to an embodiment of the first aspect of this application, the pixel circuit further includes an initialization module; the initialization module is used to provide an initialization signal to the control terminal of the driving module under the control of the second scanning signal; the target signal includes the initialization signal.

[0032] According to an embodiment of the first aspect of this application, the method includes: when the target brightness parameter of the target image is less than a preset threshold, the display panel operates in a first type of target mode or a second type of target mode; wherein, the target image is the image displayed by the display panel during the current image display cycle.

[0033] According to an embodiment of the first aspect of this application, the target brightness parameter is the average brightness value of the target image.

[0034] According to an embodiment of the first aspect of this application, the target brightness parameter is the average grayscale value of the target image.

[0035] According to the implementation of the first aspect of this application, the first moment is located during the vertical blanking period, and the second moment is located during the effective display period;

[0036] According to the implementation of the first aspect of this application, the first moment is located at any moment during the vertical blanking period, and the second moment is located at any moment during the effective display period.

[0037] Based on the same inventive concept, in a second aspect, embodiments of this application provide a driving method applied to a display panel provided in any of the foregoing embodiments of the first aspect of this application, the driving method comprising:

[0038] The control display panel can operate in either the first type of target mode or the second type of target mode;

[0039] In the first type of target mode, during the screen display cycle, at the first and second moments when providing reset signals to the light-emitting device, only m of the n reset control signal lines provide reset control signals at the enable level; m is a positive integer less than n.

[0040] In the second type of target mode, there are a first time and a second time in the screen display cycle. The number of target reset control signal lines in the n reset control signal lines in the first time is different from the number of target reset control signal lines in the n reset control signal lines in the second time. The target reset control signal line is a reset control signal line with the reset control signal at the enable level. The target signal corresponding to the first time is different from the target signal corresponding to the second time. The target signal is used to adjust the light emission brightness of the light-emitting device.

[0041] Based on the same inventive concept, in a third aspect, embodiments of this application provide a display panel, the display panel comprising:

[0042] There are n valid pixel rows, arranged along a first direction; each valid pixel row includes multiple sub-pixels arranged along a second direction; each sub-pixel in each valid pixel row includes a pixel circuit and a light-emitting device; the pixel circuit includes a functional module, which is used to provide a preset signal to the pixel circuit under the control of the scan control signal;

[0043] There are n scan control signal lines, and each of the n scan control signal lines is electrically connected to the control terminal of the functional module in the n effective pixel row. Each scan control signal line is used to provide a scan control signal to the functional module in the corresponding effective pixel row.

[0044] The display panel operates in either the first target mode or the second target mode;

[0045] In the first type of target mode, within one screen display cycle, at the first and second moments when providing preset signals to the pixel circuit, only m of the n scan control signal lines provide scan control signals at the enable level; m is a positive integer less than n.

[0046] In the second type of target mode, there are a first time and a second time in the screen display cycle. The number of target scan control signal lines in the n scan control signal lines at the first time is different from the number of target scan control signal lines in the n scan control signal lines at the second time. The target scan control signal line is a scan control signal line with the provided scan control signal at the enable level. The target signal corresponding to the first time is different from the target signal corresponding to the second time. The target signal is used to adjust the light emission brightness of the light-emitting device.

[0047] Based on the same inventive concept, in a fourth aspect, embodiments of this application provide a display device, which includes a display panel as provided in the embodiments of the first aspect of this application.

[0048] As described above, the display panel, driving method, and display device provided in this application embodiment propose a first type of operating mode and a second type of operating mode for the display panel. In the first type of operating mode, within a screen display cycle, at the first and second moments when a reset signal is provided to the light-emitting devices, the number of effective pixel rows undergoing anode initialization of the light-emitting devices in the display panel remains constant. This ensures that the load connected to the reset signal line in the display panel remains constant, thereby preventing changes in the reset signal voltage value due to load variations. This helps avoid uneven display caused by inconsistent initialization levels of the light-emitting devices in the effective pixel rows of the display panel. In the second type of operating mode, there are a first moment and a second moment in the screen display cycle. The number of effective pixel rows undergoing anode initialization of the light-emitting devices at the first moment differs from that at the second moment, meaning the load connected to the reset signal line in the display panel changes. In this case, by adjusting the target signal used to adjust the brightness at the first and second moments, the change in the reset signal voltage value caused by load variations can be indirectly compensated, thus also improving the problem of uneven display on the display panel. Overall, operating the display panel in either the first or second working mode helps to improve the problem of uneven display, thereby enhancing the display effect and improving the market competitiveness of the display panel. Attached Figure Description

[0049] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 This is a schematic diagram illustrating the anode reset state of a light-emitting device according to an embodiment of this application;

[0051] Figure 2 This is a schematic diagram of another anode reset situation of the light-emitting device provided in the embodiment of this application;

[0052] Figure 3 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0053] Figure 4 This is a schematic diagram of a pixel circuit provided in an embodiment of this application;

[0054] Figure 5 This is a schematic diagram illustrating another anode reset situation of a light-emitting device provided in an embodiment of this application;

[0055] Figure 6 This is a schematic diagram illustrating another anode reset situation of a light-emitting device provided in an embodiment of this application;

[0056] Figure 7 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this application;

[0057] Figure 8 This is a schematic diagram illustrating another anode reset situation of a light-emitting device provided in an embodiment of this application;

[0058] Figure 9 This is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0059] Figure 10 This is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0060] Figure 11 This is a schematic diagram of another display panel structure provided in an embodiment of this application;

[0061] Figure 12 This is a flowchart illustrating a driving method provided in an embodiment of this application;

[0062] Figure 13 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0063] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0064] It should be noted that the transistors in the embodiments of this application can be either N-type or P-type transistors. For N-type transistors, the on-state level is high and the off-state level is low. That is, when the gate of an N-type transistor is high, its first and second terminals are connected; when the gate of an N-type transistor is low, its first and second terminals are off. For P-type transistors, the on-state level is low and the off-state level is high. That is, when the control terminal of a P-type transistor is low, its first and second terminals are connected; when the control terminal of a P-type transistor is high, its first and second terminals are off. In specific implementations, the gate of each transistor is used as its control terminal. Furthermore, depending on the signal and type of the gate of each transistor, its first terminal can be used as the source and its second terminal as the drain, or vice versa. No distinction is made here. Additionally, the on-state and off-state levels in the embodiments of this invention are general terms. The on-state level refers to any level that enables the transistor to conduct, and the off-state level refers to any level that enables the transistor to turn off / become off.

[0065] Before describing the technical solutions provided in the embodiments of this application, in order to facilitate understanding of the embodiments of this application, this application first specifically explains the problems existing in the related technologies:

[0066] As mentioned above, the inventors of this application have discovered that the related technologies have problems such as uneven display of the display panel and even screen splitting, which is not conducive to improving the competitiveness of the display panel market.

[0067] In order to solve the problems of uneven display or even screen splitting in display panels, the inventors of this application first studied and analyzed the root causes of the above-mentioned technical problems.

[0068] In the field of display panel technology, a display cycle of a display panel includes an effective display period and a vertical blanking period. The vertical blanking period typically occurs between display frames and is used for preparing and transmitting screen data. The effective display period and the vertical blanking period can be defined by the external interface signal TE of the display panel. The TE signal is a non-display trigger signal; a high level of the TE signal corresponds to the vertical blanking period, and a low level corresponds to the effective display period.

[0069] The display panel includes an effective display area and a blank area. The effective display area includes multiple actual rows of pixels, while the blank area includes multiple virtual rows of pixels. More specifically, the aforementioned vertical blanking period can be distributed between the last row of pixels in the effective display area writing data from the previous frame to the first row writing data from the next frame. Specifically, the multiple virtual rows of pixels do not exist on the display panel; they are merely hypothetical for ease of understanding. The number of virtual rows of pixels is equal to the number of pixel rows that the scan signal used to control data writing can scan within a preset duration, which is the same as the duration of the vertical blanking period at the maximum refresh rate.

[0070] The specific research and analysis process for the aforementioned technical problems is as follows: The inventors of this application discovered that display panels typically include pixel circuits. Driving these pixel circuits enables the light-emitting devices in the display panel to emit light, thus the operating characteristics of the pixel circuits are closely related to the display performance of the display panel. Taking the 8T1C pixel circuit as an example, in the actual application of the 8T1C pixel circuit, the reset control signal for initializing the anode of the light-emitting device is usually a high-frequency signal. Display panels driven by this pixel circuit are prone to screen splitting.

[0071] Specifically, within a single display cycle, the reset control signal provided by the same reset control signal line EL includes multiple pulses. For example, within a single display cycle, the reset control signal provided by the same reset control signal line EL includes three pulses. The pulse width is related to the scan time of the pixel row. Here, the pulse width of the reset control signal provided by the reset control signal line EL can correspond to multiple rows (e.g., the pulse width can correspond to the scan time of 20 rows of pixel circuits). Figure 1 As shown, pulses a, b, and c in the reset control signal (corresponding to the enable level positions) are all in the Vactive area (corresponding to the effective display area of ​​the display panel). This is equivalent to three pixel circuits in the first zone 01 within the Vactive area (i.e., the effective display area of ​​the display panel) resetting and initializing the anodes of the light-emitting elements. For example, at this time, the load in the display area is the load corresponding to the 60-row pixel circuit. Figure 2As shown, the reset control signal pulses a, b, and c move downwards. One pulse of the reset control signal (such as pulse a) will enter the Vblank area (i.e., the blank area of ​​the display panel). At this time, the effective display area (i.e.,...) Figure 3 In the Vactive area, only two pixel circuits in the second zone 02 are initialized for the anode reset of the light-emitting element. For example, the load in the display area at this time corresponds to the load of 40 rows of pixel circuits. This results in a situation where, at one time during a display cycle, pixel circuits in two areas of the display panel are being initialized, while at another time, pixel circuits in three areas are being initialized. This leads to a difference in the number of rows of scanning circuits and pixel circuits providing reset signals to the anode of the light-emitting element in different time periods, resulting in a difference in the load in the display area. Consequently, when the reset control signal provided by the same reset control signal line EL includes three enable levels within a display cycle, it may cause... Figure 3 The image shows a three-part screen display exhibiting uneven brightness. Specifically, when a pulse from the reset control signal enters the Vblank area, the display panel begins the vertical blanking phase.

[0072] To address the aforementioned technical problems, embodiments of this application provide a display panel, a driving method, and a display device, which can solve the problem of uneven brightness display and screen splitting in related technologies.

[0073] It should be noted that the embodiments provided in this application are not intended to limit the scope of this application.

[0074] The technical concept of this application embodiment lies in the following: Through further research, the inventors have discovered that the reason for the split-screen phenomenon in the above example is that when the number of effective pixel rows enabled by the reset control signal decreases, the number of sub-pixels undergoing anode initialization of the light-emitting devices within the effective display area of ​​the display panel decreases accordingly. As a result, the number of light-emitting devices electrically connected to the reset signal line used to provide reset signals to the anodes of the light-emitting devices decreases, leading to a reduction in the load on the reset signal line. Consequently, the reset signal voltage value provided by the reset signal line changes under the influence of the connected load, resulting in a change in the degree of anode initialization of the light-emitting devices in the effective pixel rows under this situation, thus causing the split-screen phenomenon of the display panel.

[0075] Based on this, this application considers providing two operating modes for the display panel to solve the display splitting problem. Specifically, in the first operating mode, during the first and second moments of the screen display cycle, the number of effective pixel rows undergoing anode initialization of the light-emitting devices in the display panel remains constant. This ensures that the load connected to the reset signal line in the display panel remains constant, thereby preventing the reset signal voltage value from changing due to load variations. This helps avoid display unevenness caused by inconsistent initialization levels of the light-emitting devices in the effective pixel rows of the display panel. In the second operating mode, there are a first and a second moment in the screen display cycle. The number of effective pixel rows undergoing anode initialization of the light-emitting devices differs between the first and second moments, meaning the load connected to the reset signal line in the display panel changes. In this case, by adjusting the target signal used to adjust the brightness during the first and second moments, the change in the reset signal voltage value caused by load variations can be indirectly compensated, thus also improving the display unevenness problem.

[0076] The display panel provided in the embodiments of this application will be described first below.

[0077] Figure 3 A schematic diagram of a display panel 100 provided in an embodiment of this application is shown. The display panel 100 can be AMOLED, OLED, or other types. Those skilled in the art should understand that in other implementations of this application, the display panel 100 can also be a micro-light-emitting diode display panel 100, a quantum dot display panel 100, etc.

[0078] like Figure 3 As shown in the illustration, a display panel 100 provided in this application embodiment includes n effective pixel rows 20 and n reset control signal lines EL. Specifically, the n effective pixel rows 20 are arranged along a first direction Y. Each effective pixel row 20 includes a plurality of sub-pixels 21 arranged along a second direction X.

[0079] The aforementioned n reset control signal lines EL are electrically connected to the control terminals of the reset modules 107 in the n effective pixel rows 20, and any reset control signal line EL is used to provide a reset control signal to the corresponding reset module 107 in the effective pixel row 20.

[0080] Please refer to the following: Figure 4 , Figure 4 This is a schematic diagram of a pixel circuit provided in an embodiment of this application. Figure 4As shown, a sub-pixel 21 in any valid pixel row 20 may specifically include a pixel circuit 10 and a light-emitting device D. The pixel circuit 10 may specifically include a reset module 107, which is connected to the light-emitting device D. The reset module 107 can be used to provide a reset signal to the light-emitting device D under the control of a reset control signal.

[0081] For example, one end of the reset module 107 can be connected to the first reset signal terminal Vrefn2, which can be used to provide a reset signal. The other end of the reset module 107 can be electrically connected to the anode of the light-emitting device D. The reset module 107 can be turned on or off under the control of the reset control signal line EL. When the reset control signal provided by the reset control signal line EL is at the enable level, the reset module 107 is turned on, transmitting the reset signal provided by the first reset signal terminal Vrefn2 to the anode of the light-emitting device to reset the anode of the light-emitting device D.

[0082] As an example, the reset module 107 may include a seventh transistor T7, the gate of which can receive a reset control signal provided by the reset control signal line EL. The first terminal of the seventh transistor T7 can be connected to the first reset signal terminal Vrefn2 (whose reset signal is output by the reset signal line), and the second terminal of the seventh transistor T7 is electrically connected to the anode of the light-emitting device D. The reset control signal provided by the reset control signal line is a pulse signal, and the high or low level (enable level and disable level) of the pulse signal controls the seventh transistor T7 to be turned on or off.

[0083] One display cycle of the aforementioned display panel 100 includes an effective display period and a vertical blanking period.

[0084] In actual display operation, the aforementioned display panel 100 operates in either the first target mode or the second target mode. The first or second target mode can be pre-programmed, and the specific setting method is not limited here.

[0085] In the first type of target mode described above, within one frame display cycle, at the first and second moments when a reset signal is provided to the light-emitting device D, only m of the n reset control signal lines EL provide reset control signals at the enable level. m is a positive integer less than n.

[0086] Optionally, the first moment mentioned above is located during the vertical blanking period, and the second moment mentioned above is located during the effective display period.

[0087] Optionally, the first moment can be located at any moment during the vertical blanking period, and the second moment can be located at any moment during the effective display period.

[0088] In the second type of target mode, there are a first time and a second time in the screen display cycle. The number of target reset control signal lines in the n reset control signal lines EL at the first time is different from the number of target reset control signal lines in the n reset control signal lines EL at the second time.

[0089] The aforementioned target reset control signal line is a reset control signal line with an enable level provided by the reset control signal. The target signal corresponding to the first moment is different from the target signal corresponding to the second moment; the target signal is used to adjust the brightness of the light-emitting device D.

[0090] In this application, the target signal corresponding to the first time moment is different from the target signal corresponding to the second time moment. This can be directly expressed as the voltage value of the reset signal provided by the driver chip at the first time moment being different from the voltage value of the reset signal at the second time moment.

[0091] Alternatively, in some other feasible embodiments, the data voltage received by the effective pixel row undergoing anode reset at the first moment during the data writing phase may be a first data voltage, and the data voltage received by the effective pixel row undergoing anode reset at the second moment during the data writing phase may be a second data voltage, wherein the first data voltage is different from the second data voltage.

[0092] It should be noted that, considering the diversity of methods for adjusting the brightness of light-emitting devices in related technologies, this application does not impose specific limitations on this.

[0093] As can be seen from the above description, the display panel 100 provided in this application embodiment proposes a first type of working mode and a second type of working mode for the display panel 100, so as to fully guarantee the display effect of the display panel 100.

[0094] Specifically, in the first type of working mode, at the first and second moments of the screen display cycle, the number of effective pixel rows 20 in the display panel 100 that are undergoing anode initialization of the light-emitting devices remains unchanged, thereby ensuring that the load connected to the reset signal line in the display panel 100 remains unchanged, thus ensuring that the reset signal voltage value will not be affected by load changes, which helps to avoid the display unevenness problem caused by the different initialization degree of the light-emitting devices in the effective pixel rows 20 of the display panel 100.

[0095] In the second type of operating mode, there are a first moment and a second moment in the display cycle. The number of effective pixel rows 20 undergoing anode initialization of the light-emitting device in the first moment differs from that in the second moment, meaning the load connected to the reset signal line in the display panel 100 changes. In this situation, by adjusting the target signal used to adjust the brightness in the first and second moments, the change in the reset signal voltage caused by the load change can be indirectly compensated, thereby improving the uneven display of the display panel 100.

[0096] Overall, whether the display panel 100 operates in the first or second working mode, it helps to improve the problem of uneven display of the display panel 100, thereby improving the display effect of the display panel 100 and enhancing the market competitiveness of the display panel 100.

[0097] Please see below. Figure 5 , Figure 5 This is a timing diagram of a display panel provided in an embodiment of this application. For example... Figure 5 As shown, according to some embodiments of this application, optionally, in order to more reasonably achieve the first and second moments of the screen display cycle, the number of reset control signal lines with enable levels provided by the above n reset control signal lines EL is consistent, that is, the load connected to the first reset signal terminal Vrefn2 remains unchanged, and one screen display cycle of the display panel includes an effective display period and a vertical blanking period; in the first type of target mode, the reset control signal on the same reset control signal line has k enable pulses within the screen display cycle, or, the reset control signal on the same reset control signal line has k enable pulses after the data writing phase within a refresh frame. k is determined based on the duration of the effective display period and the duration of the vertical blanking period, and k is a positive integer.

[0098] In some specific implementations, k is determined based on the ratio of the effective display period duration to the vertical blanking period.

[0099] In some more specific implementations, k is determined based on the ratio of the duration of the effective display period to the duration of the vertical blanking period corresponding to the maximum refresh rate of the display panel 100.

[0100] Optionally, the ratio of the duration of the effective display period to the duration of the vertical blanking period is q / v, where q and v are integers, and k is equal to the sum of q and v.

[0101] Optionally, continue as follows Figure 5 As shown, the pulse duration of each of the above k enable pulses is the same and is the first duration T1.

[0102] The interval between any two adjacent enable pulses in the k enable pulses is the same and is the second duration T2.

[0103] Optionally, the sum of the first duration and the second duration can be equal to the duration of the vertical blanking period.

[0104] Optionally, k equals (t1 / t2)+1, where t1 is the product of the total number of rows of pixel circuits in the display area of ​​the display panel and the row scanning time, and t2 is the duration of the vertical blanking period; the row scanning time is the time for the reset control signal to scan the corresponding row of pixel circuits, or the row scanning time is the minimum time interval between the start times of the enable pulses of the reset control signals corresponding to two adjacent rows of pixel circuits.

[0105] For example, Figure 5 Taking a ratio of 3:1 between the effective display period and the vertical blanking period as an example, the reset control signal can have 4 enable pulses (a, b, c, d) in one screen display cycle. This ensures that, regardless of whether it's the first time t1 or the second time t2, the reset control signal provided by the n reset control signal lines EL(t1) or EL(t2) is always at an enable level, equal to 3 times the pulse width (3 pulses in scanning).

[0106] Taking an enable pulse width of 28H as an example, where H is the time required for the scan signal to scan one row of pixels, the number of effective pixel rows that are always maintained at three times the pulse width in the n reset control signal lines EL, i.e., 28*3=84 effective pixel rows are in the anode reset stage, i.e., m=84.

[0107] Please see below. Figure 6 , Figure 6 This is a schematic diagram illustrating another anode reset state of a light-emitting device provided in an embodiment of this application. For example... Figure 6 As shown, according to some embodiments of this application, optionally, Figure 6 Taking a ratio of 5:1 between the effective display period and the vertical blanking period as an example, the reset control signal can have 6 enable pulses (a, b, c, d, e, f) in one screen display cycle. This ensures that, regardless of whether it's the first time t1 or the second time t2, the provided reset control signal line EL(t1) or EL(t2) always maintains a reset control signal level of 5 times the pulse width (5 pulses in scan), and Mura is invisible in this mode.

[0108] Please see below. Figure 7 , Figure 7 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this application. For example... Figure 7As shown, according to some embodiments of this application, optionally, the pixel circuit 10 includes a driving module 101 and a bias adjustment module 108. The driving module 101 is used to drive the light-emitting device D to emit light. The bias adjustment module 108 is used to provide a bias adjustment signal to a first or second terminal of the driving module 101 under the control of a first scan signal.

[0109] For example, the control terminal of the bias adjustment module 108 is electrically connected to the first scan signal line SP2. The bias adjustment module 108 can be turned on or off under the control of the first scan signal provided by the first scan signal line SP2. One end of the bias adjustment module 108 can be connected to the bias adjustment signal terminal Vrefp, which can be used to provide the aforementioned bias adjustment signal. The other end of the bias adjustment module 108 can be electrically connected to the first or second terminal of the drive module 101. When the first scan signal provided by the first scan signal line SP2 is at an enable level, the bias adjustment module 108 is turned on, transmitting the aforementioned bias adjustment signal provided by the bias adjustment signal terminal Vrefp to the first or second terminal of the drive module 101 to adjust the bias state of the drive module 101.

[0110] As an example, the drive module 101 may include a first transistor T1, and the bias adjustment module 108 may specifically include an eighth transistor T8. The gate of the eighth transistor T8 may receive a first scan signal provided by a first scan signal line SP2. The first terminal of the eighth transistor T8 may be connected to the bias adjustment signal terminal Vrefp, and the second terminal of the eighth transistor T8 may be electrically connected to either the first or second terminal of the first transistor T1. The first scan signal provided by the first scan signal line SP2 is a pulse signal, and the high or low level (enable level and non-enable level) of the pulse signal controls the eighth transistor T8 to be turned on or off.

[0111] Optionally, the reset control signal is different from the first scan signal, or the reset control signal is multiplexed as the first scan signal. When the reset control signal is multiplexed as the first scan signal, reasonable multiplexing of signals in the display panel can be achieved.

[0112] According to some embodiments of this application, optionally, the reset control signal is different from the first scan signal, and the first scan signal corresponding to the same pixel circuit has w enable pulses within the screen display cycle, where w is an integer greater than k.

[0113] According to some embodiments of this application, optionally, the screen display cycle includes refresh frames and hold frames. Within a refresh frame, the number of enable pulses of the first scan signal corresponding to the same pixel circuit is greater than the number of enable pulses of the reset control signal corresponding to the same pixel circuit.

[0114] Within a single frame, the number of enable pulses for the first scan signal corresponding to the same pixel circuit is greater than the number of enable pulses for the reset control signal corresponding to the same pixel circuit.

[0115] According to some embodiments of this application, optionally, in the second type of target mode, the number of enable pulses of the reset control signal on the same reset control signal line within the screen display cycle is greater than or equal to 2, and the target signal at the first moment is different from the target signal at the second moment.

[0116] Please see below. Figure 8 , Figure 8 This is a schematic diagram illustrating another anode reset state of a light-emitting device provided in an embodiment of this application. For example... Figure 8 As shown, according to some embodiments of this application, optionally, the display panel 100 operates in a first target mode, a second target mode, or a third target mode; in the third target mode, the reset control signal on the same reset control signal line has one and only one enable pulse 'a' within the screen display cycle. Thus, in the third target mode, the split-screen phenomenon can be avoided by using a low-frequency reset control signal. Specifically, when the reset control signal has one and only one enable pulse within the screen display cycle, even if the load changes due to the existence of the vertical blanking period, only the bottom effective pixel row of the display panel is slightly affected out of n effective pixel rows, and the brightness change caused by this effect is negligible.

[0117] According to some embodiments of this application, optionally, when the reset control signal has one and only one enable pulse within the screen display cycle, in order to fully improve the uniformity of display brightness, the pixel circuit 10 includes a driving module 101 and a bias adjustment module 108. The driving module 101 is used to drive the light-emitting device D to emit light; the bias adjustment module 108 is used to provide a bias adjustment signal to the first or second terminal of the driving module 101 under the control of the first scan signal. Wherein, the number of enable pulses of the first scan signal corresponding to the same pixel circuit within the screen display cycle is greater than or equal to 2. Thus, by setting a high-frequency first scan signal to fully guarantee the bias adjustment of the driving module 101, it is beneficial to improve the problem of uneven display on the display panel, thereby improving the display effect of the display panel.

[0118] According to some embodiments of this application, optionally, in the second type of target mode, in order to more reasonably and efficiently compensate for the change in the reset signal voltage value caused by load changes, thereby improving the problem of uneven display on the display panel, the above-mentioned target signal may specifically include a reset signal.

[0119] More specifically, at the first time point, the number of target reset control signal lines EL among the n reset control signal lines EL is the number of first signal lines, and at the second time point, the number of target reset control signal lines EL among the n reset control signal lines EL is the number of second signal lines. The number of first signal lines is less than the number of second signal lines.

[0120] The voltage value of the reset signal at the first moment is Vref21, and the voltage value of the reset signal at the second moment is Vref22. The absolute value of Vref21 is less than the absolute value of Vref22. For example, Vref21 and Vref22 are negative, with Vref21 > Vref22.

[0121] It should be added that, in conjunction with the previous embodiment, the aforementioned reset signal is specifically the voltage value input to the first reset signal terminal Vrefn2. When the reset module 107 is turned on, this first reset signal terminal Vrefn2 transmits this reset signal to the anode of the light-emitting device D to realize the reset operation of the anode of the light-emitting device D.

[0122] According to some embodiments of this application, optionally, the difference between Vref21 and Vref22 is determined based on the number of first signal lines and the number of second signal lines.

[0123] Furthermore, the difference between Vref21 and Vref22 is determined based on the difference between the number of the first signal lines and the number of the second signal lines.

[0124] According to some embodiments of this application, optionally, the voltage value of the reset signal at the first moment can be adjusted so that Vref21 > Vref22.

[0125] For example, if the number of first signal lines is 56 and the number of second signal lines is 84, the display panel 100 has 84 rows of effective pixel rows in the anode reset phase under normal conditions (before scanning line by line to the Vblank area). After scanning line by line to the Vblank area, the number of light-emitting devices in the remaining 56 rows of effective pixel rows gradually decreases from 84 to the anode reset phase. At this time, the reset signal at the first moment (the moment when the remaining 56 rows of effective pixel rows are in the anode reset phase) can be adjusted.

[0126] For example, under normal circumstances (including the second moment), the voltage value of the reset signal provided by the driver chip is -0.9V. However, in the first moment, due to the reduction of the connected load by 28 rows, the voltage value of this reset signal changes to -1.0V due to the load change. In this case, the voltage value of the reset signal provided by the driver signal in the first moment can be adjusted from -0.9V to -0.8V. Thus, when the reset signal voltage value changes due to load changes, it will be adjusted from -0.8V to -0.9V, ensuring that even if the load changes in the first and second moments, the final voltage value of the reset signal is consistent. This effectively ensures the consistency of the anode reset degree and avoids the uneven brightness display splitting problem caused by inconsistent anode reset degrees.

[0127] According to some embodiments of this application, optionally, the pixel circuit 10 includes a driving module 101 and a bias adjustment module 108; the driving module 101 is used to drive the light-emitting device D to emit light; the bias adjustment module 108 is used to provide a bias adjustment signal to a first end or a second end of the driving module 101 under the control of a first scan signal; the target signal includes the bias adjustment signal.

[0128] According to some embodiments of this application, optionally, if the reset control signal is multiplexed as the first scan signal, the voltage value of the bias adjustment signal at the first moment is different from the voltage value of the bias adjustment signal at the second moment. Its adjustment principle is similar to that of the aforementioned reset signal, and will not be elaborated upon here.

[0129] For example, in this embodiment, by utilizing the difference between the voltage value of the bias adjustment signal at the first moment and the voltage value of the bias adjustment signal at the second moment, the 56 rows of effective pixels in the anode reset phase at the first moment and the 84 rows of effective pixels in the anode reset phase at the second moment are subjected to different degrees of bias state adjustment, so that the brightness of the 56 rows of effective pixels in the first moment and the 84 rows of effective pixels in the second moment is consistent when emitting light.

[0130] According to some embodiments of this application, optionally, the reset control signal is different from the first scan signal; the first effective pixel row 20 includes: the effective pixel row 20 corresponding to the target reset control signal line EL among the n reset control signal lines EL at the first time. The second effective pixel row 20 includes: the effective pixel row 20 corresponding to the target reset control signal line EL among the n reset control signal lines EL at the second time. The voltage value of the bias adjustment signal corresponding to the first effective pixel row 20 is different from the voltage value of the bias adjustment signal corresponding to the second effective pixel row 20.

[0131] It should be added here that, in conjunction with the previous embodiment, the aforementioned bias adjustment signal is specifically the voltage value input to the aforementioned bias adjustment signal terminal Vrefp. When the bias reset module 108 is turned on, this bias adjustment signal Vrefp is transmitted to the first or second terminal of the drive module 101 through the turned-on bias reset module 108 to adjust the bias state of the drive module 101.

[0132] Please see below. Figure 9 , Figure 9 This is a schematic diagram of another pixel circuit provided in an embodiment of this application. For example... Figure 9 As shown, according to some embodiments of this application, optionally, the pixel circuit 10 further includes an initialization module 104. The initialization module 104 is used to provide an initialization signal to the control terminal of the driving module 101 under the control of the second scan signal. The target signal includes the initialization signal.

[0133] For example, one end of the initialization module 104 can be connected to the second reset signal terminal Vrefn1, which can be used to provide the aforementioned initialization signal. The initialization module 104 can be turned on or off under the control of the second scan signal line SN1. When the second scan signal provided by the second scan signal line SN1 is at the enable level, the initialization module 104 is turned on, providing the initialization signal provided by the second reset signal terminal Vrefn1 to the control terminal of the drive module 101.

[0134] As an example, the drive module 101 includes a first transistor T1, and the initialization module 104 may include a fourth transistor T4. The gate of the fourth transistor T4 can receive a second scan signal provided by a second scan signal line SN1. The first terminal of the fourth transistor T4 can be connected to a second reset signal terminal Vrefn1, and the second terminal of the fourth transistor T4 is electrically connected to the first terminal of the first transistor T1. The second scan signal provided by the second scan signal line SN1 is a pulse signal, and the high or low level (enable level and non-enable level) of the pulse signal controls the fourth transistor T4 to be turned on or off.

[0135] It should be noted that, in addition to the transistors listed above, the pixel circuit 10 of this application may also include other transistors, which together constitute various types of pixel circuits 10, such as... Figure 10 The schematic diagram of another pixel circuit provided in the embodiment of this application is shown, etc., and this application does not make any specific limitations on it.

[0136] It should be understood that, taking into account Figure 10 The pixel circuit shown is widely used in the field of display technology; therefore, this embodiment focuses on... Figure 10 The pixel circuits and their operating processes shown will not be described in detail. Furthermore, Figure 11This is a schematic diagram of another display panel structure provided in an embodiment of this application. Figure 11 and Figure 10 The difference is: Figure 11 The first terminal of the eighth transistor T8 is electrically connected to the second terminal of the first transistor T1 so as to adjust the bias state of the second terminal of the first transistor T1.

[0137] According to some embodiments of this application, optionally, considering that uneven display and split-screen phenomena on the display panel are more easily detected by the human eye in low grayscale and low brightness situations, this application can make targeted settings for the specific scenarios of the aforementioned first type of target mode or second type of target mode. Based on this, when the target brightness parameter of the target image is less than a preset threshold, the display panel 100 operates in the first type of target mode or the second type of target mode. The target image is the image displayed by the display panel 100 within the current image display cycle.

[0138] According to some embodiments of this application, optionally, the target brightness parameter can be the average brightness value of the target image. In other feasible embodiments, optionally, the target brightness parameter can be the average grayscale value of the target image.

[0139] Based on the display panel 100 provided in the above embodiments, this application also provides a driving method. The driving method of this application can be applied to the display panel 100 provided in any of the foregoing embodiments.

[0140] Figure 12 This is a flowchart illustrating a driving method provided in an embodiment of this application. Figure 12 As shown, a driving method according to an embodiment of this application may include the following steps:

[0141] S1201, The control display panel 100 operates in either the first type of target mode or the second type of target mode.

[0142] In the first type of target mode, within one screen display cycle, at the first and second moments when providing reset signals to the light-emitting device, only m of the n reset control signal lines provide reset control signals at the enable level; m is a positive integer less than n.

[0143] In the second type of target mode, there are a first time and a second time in the screen display cycle. The number of target reset control signal lines in the n reset control signal lines in the first time is different from the number of target reset control signal lines in the n reset control signal lines in the second time. The target reset control signal line EL is a reset control signal line with the reset control signal at the enable level. The target signal corresponding to the first time is different from the target signal corresponding to the second time. The target signal is used to adjust the brightness of the light-emitting device.

[0144] As described above, the driving method provided in this application improves the display panel's uneven display problem by controlling the display panel to operate in a first or second working mode. Specifically, in the first working mode, at the first and second moments of the screen display cycle, the number of effective pixel rows undergoing anode initialization of the light-emitting devices in the display panel remains constant. This ensures that the load connected to the reset signal line in the display panel remains constant, thereby preventing the reset signal voltage value from changing due to load variations. This helps avoid the uneven display problem caused by inconsistent initialization levels of the light-emitting devices in the effective pixel rows of the display panel.

[0145] In the second type of operating mode, there are a first moment and a second moment in the display cycle. The number of effective pixel rows undergoing anode initialization of the light-emitting device in the first moment differs from that in the second moment, meaning the load connected to the reset signal line in the display panel changes. In this case, by adjusting the target signal used to adjust the light emission brightness in the first and second moments, the change in the reset signal voltage value caused by the load change can be indirectly compensated, thereby improving the problem of uneven display on the display panel.

[0146] Overall, the driving method provided in this embodiment can improve the problem of uneven display of the display panel by controlling the display panel to work in the first type of working mode or the second type of working mode, which is conducive to improving the display effect of the display panel and thus effectively improving the market competitiveness of the display panel.

[0147] It should be noted that, considering that the specific implementation process of S1201 has been described in detail above, it will not be repeated here for the sake of brevity. Furthermore, the driving method provided in this application embodiment has the beneficial effects of the display panel provided in this application embodiment; for details, please refer to the specific descriptions of the display panel in the above embodiments, which will not be repeated here.

[0148] Based on the display panel provided in the above embodiments, this application also provides a display panel. The display panel includes: n effective pixel rows arranged along a first direction; each effective pixel row includes a plurality of sub-pixels arranged along a second direction; each sub-pixel in each effective pixel row includes a pixel circuit and a light-emitting device; the pixel circuit includes a functional module, which is used to provide a preset signal to the pixel circuit under the control of a scan control signal.

[0149] There are n scan control signal lines, each electrically connected to the control terminal of a functional module in one of the n effective pixel rows. Each scan control signal line is used to provide a scan control signal to the functional module in the corresponding effective pixel row.

[0150] The display panel operates in either the first target mode or the second target mode. In the first target mode, within one screen display cycle, at the first and second moments when providing preset signals to the pixel circuits, only m out of the n scan control signal lines provide scan control signals at the enable level; m is a positive integer less than n.

[0151] In the second type of target mode, there are a first time and a second time in the screen display cycle. The number of target scan control signal lines in the n scan control signal lines at the first time is different from the number of target scan control signal lines in the n scan control signal lines at the second time. The target scan control signal line is a scan control signal line with the provided scan control signal at the enable level. The target signal corresponding to the first time is different from the target signal corresponding to the second time. The target signal is used to adjust the light emission brightness of the light-emitting device.

[0152] It should be added that, in this embodiment, the above-mentioned functional module may include, but is not limited to, the reset module in the foregoing embodiments, and the above-mentioned scan control signal line may include, but is not limited to, the reset control signal line in the foregoing embodiments. This application does not impose strict limitations on this.

[0153] Based on the display panel provided in the above embodiments, this application also provides a display device, including the display panel provided in this application. Please refer to... Figure 13 , Figure 13 This is a schematic diagram of a display device provided in an embodiment of this application. Figure 13 The provided display device 1000 includes the display panel 100 provided in any of the above embodiments of this application. Figure 13The embodiments use a mobile phone as an example to describe the display device 1000. It is understood that the display device provided in the embodiments of this application can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices. This application does not impose specific limitations on these. The display device provided in the embodiments of this application has the beneficial effects of the display panel 100 provided in the embodiments of this application. For details, please refer to the specific descriptions of the display panel 100 in the above embodiments. These descriptions will not be repeated here.

[0154] It should be understood that the specific circuit structures and cross-sectional structures of the display panels provided in the accompanying drawings of the embodiments of this application are merely examples and are not intended to limit this application. Furthermore, the above embodiments provided in this application can be combined with each other unless there is contradiction.

[0155] It should be clarified that the various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. According to the embodiments described above, these embodiments do not exhaustively describe all details, nor do they limit this application to only the specific embodiments described. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to make good use of this application and modifications based on it. This application is limited only by the claims and their full scope and equivalents.

[0156] Those skilled in the art will understand that the above embodiments are exemplary and not restrictive. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Based on a study of the drawings, specification, and claims, those skilled in the art should be able to understand and implement other variations of the disclosed embodiments. In the claims, the term "comprising" does not exclude other structures; the quantity refers to "one" but does not exclude multiple; the terms "first" and "second" are used to identify names and not to indicate any particular order. Any reference numerals in the claims should not be construed as limiting the scope of protection. The appearance of certain technical features in different dependent claims does not mean that these technical features cannot be combined to achieve beneficial effects.

Claims

1. A display panel, characterized in that, The display panel includes: There are n effective pixel rows, which are arranged along a first direction; each effective pixel row includes a plurality of sub-pixels arranged along a second direction; each sub-pixel in each effective pixel row includes a pixel circuit and a light-emitting device; the pixel circuit includes a reset module, which is used to provide a reset signal to the light-emitting device under the control of a reset control signal; n reset control signal lines, each of which is electrically connected to the control terminal of a reset module in one of the n effective pixel rows. Each of the n reset control signal lines is used to provide a reset control signal to the corresponding reset module in the effective pixel row. The display panel operates in either the first type of target mode or the second type of target mode; In the first type of target mode, within one screen display cycle, at the first and second moments when a reset signal is provided to the light-emitting device, there are exactly m reset control signal lines among the n reset control signal lines that provide the reset control signal at the enable level; m is a positive integer less than n; In the second type of target mode, there are a first moment and a second moment in the screen display cycle. The number of target reset control signal lines in the n reset control signal lines at the first moment is different from the number of target reset control signal lines in the n reset control signal lines at the second moment. The target reset control signal line is a reset control signal line where the provided reset control signal is at the enable level. The target signal corresponding to the first moment is different from the target signal corresponding to the second moment. The target signal is used to adjust the light emission brightness of the light-emitting device. A display cycle of the display panel includes an effective display period and a vertical blanking period. In the first type of target mode, the reset control signal on the same reset control signal line has k enable pulses within the display cycle, or the reset control signal on the same reset control signal line has k enable pulses after the data writing phase within a refresh frame. k is determined based on the duration of the effective display period and the duration of the vertical blanking period, and k is a positive integer. k is determined based on the ratio of the duration of the effective display period to the duration of the vertical blanking period. The pulse duration of each of the k enable pulses is consistent and is a first duration. The interval duration between any two adjacent enable pulses in the k enable pulses is consistent and is a second duration. The sum of the first duration and the second duration is equal to the duration of the vertical blanking period.

2. The display panel according to claim 1, characterized in that, k is determined based on the ratio of the duration of the effective display period to the duration of the vertical blanking period corresponding to the maximum refresh rate of the display panel.

3. The display panel according to claim 1, characterized in that, The ratio of the duration of the effective display period to the duration of the vertical blanking period is q / v, where q and v are integers, and k is equal to the sum of q and v.

4. The display panel according to claim 1, characterized in that, k equals (t1 / t2) + 1, where t1 is the product of the total number of rows of pixel circuits in the display area of ​​the display panel and the row scanning time, and t2 is the duration of the vertical blanking period; the row scanning time is the time it takes for the reset control signal to scan one row of the pixel circuits, or the row scanning time is the minimum time interval between the start times of the enable pulses of the reset control signals corresponding to two adjacent rows of the pixel circuits.

5. The display panel according to claim 1, characterized in that, The pixel circuit includes a driving module and a bias adjustment module; The driving module is used to drive the light-emitting device to emit light; the bias adjustment module is used to provide a bias adjustment signal to the first or second end of the driving module under the control of the first scan signal.

6. The display panel according to claim 5, characterized in that, The reset control signal is different from the first scan signal, or the reset control signal is multiplexed as the first scan signal.

7. The display panel according to claim 1, characterized in that, include: In the second type of target mode, the number of enable pulses of the reset control signal on the same reset control signal line within the screen display cycle is greater than or equal to 2, and the target signal at the first moment is different from the target signal at the second moment.

8. The display panel according to claim 1, characterized in that, include: The display panel operates in the first target mode, the second target mode, or the third target mode; in the third target mode, the reset control signal on the same reset control signal line has one and only one enable pulse within the screen display cycle.

9. The display panel according to claim 7, characterized in that, include: The pixel circuit includes a driving module and a bias adjustment module; The driving module is used to drive the light-emitting device to emit light; The bias adjustment module is used to provide a bias adjustment signal to the first or second end of the driving module under the control of the first scan signal; wherein, the number of enable pulses of the first scan signal corresponding to the same pixel circuit in the screen display cycle is greater than or equal to 2.

10. The display panel according to claim 1, characterized in that, In the second type of target mode, the target signal includes the reset signal.

11. The display panel according to claim 1, characterized in that, At the first moment, the number of target reset control signal lines among the n reset control signal lines is the number of first signal lines; at the second moment, the number of target reset control signal lines among the n reset control signal lines is the number of second signal lines; the number of first signal lines is less than the number of second signal lines. The voltage value of the reset signal at the first moment is Vref21; the voltage value of the reset signal at the second moment is Vref22; wherein the absolute value of Vref21 is less than the absolute value of Vref22.

12. The display panel according to claim 11, characterized in that, Vref21 and Vref22 are negative numbers, and Vref21 > Vref22.

13. The display panel according to claim 11, characterized in that, The difference between Vref21 and Vref22 is determined based on the number of the first signal lines and the number of the second signal lines.

14. The display panel according to claim 13, characterized in that, The difference between Vref21 and Vref22 is determined based on the difference between the number of the first signal lines and the number of the second signal lines.

15. The display panel according to claim 11, characterized in that, By adjusting the voltage value of the reset signal at the first moment, Vref21 > Vref22.

16. The display panel according to claim 1, characterized in that, The pixel circuit includes a driving module and a bias adjustment module; The driving module is used to drive the light-emitting device to emit light; the bias adjustment module is used to provide a bias adjustment signal to the first or second end of the driving module under the control of the first scan signal; the target signal includes the bias adjustment signal.

17. The display panel according to claim 16, characterized in that, If the reset control signal is multiplexed as the first scan signal, the voltage value of the bias adjustment signal at the first moment is different from the voltage value of the bias adjustment signal at the second moment.

18. The display panel according to claim 16, characterized in that, The reset control signal is different from the first scan signal; The first effective pixel row includes: the effective pixel row corresponding to the target reset control signal line among the n reset control signal lines at the first time moment; The second effective pixel row includes: the effective pixel row corresponding to the target reset control signal line among the n reset control signal lines at the second time moment; The voltage value of the bias adjustment signal corresponding to the first effective pixel row is different from the voltage value of the bias adjustment signal corresponding to the second effective pixel row.

19. The display panel according to claim 16, characterized in that, The pixel circuit further includes an initialization module; the initialization module is used to provide an initialization signal to the control terminal of the driving module under the control of the second scan signal; the target signal includes the initialization signal.

20. The display panel according to claim 1, characterized in that, include: When the target brightness parameter of the target image is less than a preset threshold, the display panel operates in the first type of target mode or the second type of target mode; wherein, the target image is the image displayed by the display panel within the current image display cycle.

21. The display panel according to claim 20, characterized in that, The target brightness parameter is the average brightness value of the target image.

22. The display panel according to claim 20, characterized in that, The target brightness parameter is the average grayscale value of the target image.

23. The display panel according to claim 1, characterized in that, The first moment is during the vertical blanking period, and the second moment is during the effective display period.

24. The display panel according to claim 23, characterized in that, The first moment is located at any moment during the vertical blanking period, and the second moment is located at any moment during the effective display period.

25. A driving method, characterized in that, Applied to a display panel as described in any one of claims 1-24, the driving method includes: Control the display panel to operate in either the first target mode or the second target mode; In the first type of target mode, within one screen display cycle, at the first and second moments when providing reset signals to the light-emitting device, there are exactly m reset control signal lines among the n reset control signal lines that provide reset control signals at the enable level; m is a positive integer less than n; In the second type of target mode, the display cycle includes a first moment and a second moment. The number of target reset control signal lines in the n reset control signal lines at the first moment is different from the number of target reset control signal lines in the n reset control signal lines at the second moment. The target reset control signal line is a reset control signal line where the provided reset control signal is at the enable level. The target signal corresponding to the first moment is different from the target signal at the second moment. The target signal is used to adjust the brightness of the light-emitting device. A display cycle of the display panel includes an effective display period and a vertical blanking period. In the first type of target mode, the reset control signal on the same reset control signal line has k enable pulses within the display cycle, or the reset control signal on the same reset control signal line has k enable pulses after the data writing phase within a refresh frame. k is determined based on the duration of the effective display period and the duration of the vertical blanking period, and k is a positive integer. k is determined based on the ratio of the duration of the effective display period to the duration of the vertical blanking period. The pulse duration of each of the k enable pulses is consistent and is a first duration. The interval duration between any two adjacent enable pulses in the k enable pulses is consistent and is a second duration. The sum of the first duration and the second duration is equal to the duration of the vertical blanking period.

26. A display panel, characterized in that, The display panel includes: There are n effective pixel rows, which are arranged along a first direction; each effective pixel row includes a plurality of sub-pixels arranged along a second direction; each sub-pixel in each effective pixel row includes a pixel circuit and a light-emitting device; the pixel circuit includes a functional module, which is used to provide a preset signal to the pixel circuit under the control of a scan control signal; n scan control signal lines, wherein the n scan control signal lines are electrically connected to the control terminals of the functional modules in the n effective pixel rows, and each of the scan control signal lines is used to provide a scan control signal to the corresponding functional module in the effective pixel row; The display panel operates in either the first type of target mode or the second type of target mode; In the first type of target mode, within one screen display cycle, at the first and second moments when providing preset signals to the pixel circuit, there are exactly m scan control signal lines among the n scan control signal lines that provide scan control signals at the enable level; m is a positive integer less than n; In the second type of target mode, there are a first moment and a second moment in the screen display cycle. The number of target scan control signal lines in the n scan control signal lines at the first moment is different from the number of target scan control signal lines in the n scan control signal lines at the second moment. The target scan control signal line is a scan control signal line where the provided scan control signal is at the enable level. The target signal corresponding to the first moment is different from the target signal corresponding to the second moment. The target signal is used to adjust the light emission brightness of the light-emitting device. A display cycle of the display panel includes an effective display period and a vertical blanking period. In the first type of target mode, the scan control signal on the same scan control signal line has k enable pulses within the display cycle, or the scan control signal on the same scan control signal line has k enable pulses after the data writing phase within a refresh frame. k is determined based on the duration of the effective display period and the duration of the vertical blanking period, and k is a positive integer. k is determined based on the ratio of the duration of the effective display period to the duration of the vertical blanking period. The pulse duration of each of the k enable pulses is consistent and is a first duration. The interval duration between any two adjacent enable pulses in the k enable pulses is consistent and is a second duration. The sum of the first duration and the second duration is equal to the duration of the vertical blanking period.

27. A display device, characterized in that, The display device includes a display panel as described in any one of claims 1-24.

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