Chip stacking structure and manufacturing method thereof

Abstract

The present disclosure provides a chip stack structure and a manufacturing method thereof. The chip stack structure comprises a first semiconductor chip, a second semiconductor chip, a signal transmission structure connecting the first semiconductor chip and the second semiconductor chip, and a first control circuit and a first selection circuit disposed on the first semiconductor chip. The signal transmission structure comprises a first transmission structure and a second transmission structure. The first control circuit comprises a first programming device configured to store state information of the first transmission structure. The first control circuit is coupled to a control end of the first selection circuit. Two output ends of the first selection circuit are respectively coupled to the first transmission structure and the second transmission structure. The first selection circuit is configured to transmit a signal to one of the first transmission structure and the second transmission structure according to the state information stored by the first programming device. The state information of the first transmission structure can be read at the moment of power-on of the chip stack structure, and the information transmission path is shortened.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a chip stacking structure and its fabrication method. Background Technology

[0002] Because HBM (High Bandwidth Memory) is formed by stacking multiple semiconductor chips, the signal path array that penetrates these chips needs to be tested after HBM production. When a signal path is in a poor conduction state, its position in the signal path array needs to be recorded and the signal conduction path adjusted.

[0003] To record defects in signal paths, a common practice is to place an integrated fuse array on the bottommost interface chip in the HBM thickness direction. Each fuse in the integrated fuse array corresponds to a signal path in the signal path array, recording the location of signal paths in a faulty conduction state. By reading the integrated fuse array, the position of the signal path in the signal path array can be determined and repaired. However, this setup results in a large area occupied by the logic circuitry of the integrated fuse array, making timing control difficult, operation complex, and information transmission paths long. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a chip stacking structure and a method for fabricating the same.

[0006] According to a first aspect of the present disclosure, a chip stacking structure is provided, comprising:

[0007] A first semiconductor chip, a second semiconductor chip, a signal transmission structure connecting the first semiconductor chip and the second semiconductor chip, a first control circuit and a first selection circuit disposed on the first semiconductor chip;

[0008] The signal transmission structure includes a first transmission structure and a second transmission structure, both of which include through-silicon vias disposed in the second semiconductor chip.

[0009] The first control circuit includes a first programming device, which is a one-time programmable device. The first programming device is configured to store the state information of the first transmission structure. The first control circuit is coupled to the control terminal of the first selection circuit.

[0010] The two output terminals of the first selection circuit are respectively coupled to the first transmission structure and the second transmission structure. The first selection circuit is configured to transmit a signal to one of the first transmission structure and the second transmission structure according to the state information stored in the first programming device.

[0011] According to some embodiments of this disclosure, the chip stacking structure further includes: a second control circuit and a second selection circuit disposed on the second semiconductor chip;

[0012] The second control circuit includes a second programming device, which is a one-time programmable device. The second programming device is configured to store the state information of the first transmission structure. The second control circuit is coupled to the control terminal of the second selection circuit.

[0013] The two input terminals of the second selection circuit are respectively coupled to the first transmission structure and the second transmission structure. The second selection circuit is configured to output the signal on one of the first transmission structure and the second transmission structure according to the state information stored in the second programming device.

[0014] According to some embodiments of this disclosure, the chip stacking structure further includes: a third transmission structure connecting the first semiconductor chip and the second semiconductor chip, and a second selection circuit disposed on the second semiconductor chip;

[0015] The third transmission structure is configured to couple the first control circuit to the control terminal of the second selection circuit;

[0016] The two output terminals of the second selection circuit are respectively coupled to the first transmission structure and the second transmission structure. The second selection circuit is configured to output the signal on one of the first transmission structure and the second transmission structure according to the state information stored in the first programming device.

[0017] According to some embodiments of this disclosure, the status information of the first transmission structure includes one of a first status information and a second status information, wherein the first status information indicates that the first transmission structure is valid and not occupied, and the second status information indicates that the first transmission structure is invalid or occupied.

[0018] According to some embodiments of this disclosure, the one-time programmable device includes one of a fuse device and an antifuse device.

[0019] According to some embodiments of this disclosure, the first control circuit further includes a status information transmission sub-circuit and an induction amplification sub-circuit;

[0020] The status information transmission sub-circuit is coupled to the first programming device, and the status information transmission sub-circuit is configured to transmit the status information stored in the first programming device to the inductive amplification sub-circuit.

[0021] The sensing amplification subcircuit is coupled to the state information transmission subcircuit. The sensing amplification subcircuit is configured to sense the state information and output the control signal corresponding to the state information to the first selection circuit.

[0022] According to some embodiments of this disclosure, the first control circuit further includes a programming control sub-circuit, which is coupled to the status information transmission sub-circuit and configured to jointly control the programming operation of the first programming device with the status information transmission sub-circuit.

[0023] According to some embodiments of this disclosure, the status information transmission sub-circuit includes a first transistor; a first terminal of the first transistor is coupled to a second terminal of the first programming device, the second terminal of the first transistor is coupled to a first node, and a first terminal of the first programming device is coupled to a read / write signal terminal, the read / write signal terminal being configured to provide a read signal or a programming signal.

[0024] According to some embodiments of this disclosure, the inductive amplifier subcircuit includes a second transistor, a third transistor, and a latch;

[0025] The first terminal of the second transistor is coupled to the first node, and the second terminal of the second transistor is coupled to the second node.

[0026] The first terminal of the third transistor is coupled to the first power supply terminal, and the second terminal of the third transistor is coupled to the second node.

[0027] The input terminal of the latch is coupled to the second node, and the output terminal of the latch serves as the output terminal of the first control circuit.

[0028] According to some embodiments of this disclosure, the programmable control subcircuit includes a fourth transistor; a first terminal of the fourth transistor is coupled to the first node, and a second terminal of the fourth transistor is coupled to a second power supply terminal.

[0029] According to some embodiments of this disclosure, the voltage of the read signal is zero voltage.

[0030] According to some embodiments of this disclosure, the structure of the second control circuit is the same as that of the first control circuit.

[0031] According to some embodiments of the present disclosure, the first transmission structure further includes a first contact pad disposed on the first semiconductor chip and a second contact pad disposed on the second semiconductor chip, wherein the first contact pad and the second contact pad are electrically connected.

[0032] The second transmission structure further includes a third contact pad disposed on the first semiconductor chip and a fourth contact pad disposed on the second semiconductor chip, wherein the third contact pad and the fourth contact pad are electrically connected.

[0033] The two output terminals of the first selection circuit are coupled to the first contact pad and the third contact pad, respectively, and the two input terminals of the second selection circuit are coupled to the second contact pad and the fourth contact pad, respectively.

[0034] According to some embodiments of this disclosure, the third transmission structure includes a through-silicon via (TSV) disposed on the second semiconductor chip, wherein the planar dimension of the TSV in the third transmission structure is larger than the planar dimension of the TSV in either the first transmission structure or the second transmission structure.

[0035] According to some embodiments of this disclosure, the third transmission structure further includes a fifth contact pad disposed on the first semiconductor chip and a sixth contact pad disposed on the second semiconductor chip; the first control circuit is coupled to the fifth contact pad, and the control terminal of the second selection circuit is coupled to the sixth contact pad.

[0036] According to a second aspect of the present disclosure, a method for fabricating a chip stacking structure is provided, comprising:

[0037] A first semiconductor chip is provided, the first semiconductor chip including a first control circuit and a first selection circuit;

[0038] A second semiconductor chip is provided, the second semiconductor chip including a through-silicon via;

[0039] The second semiconductor chip is bonded to the first semiconductor chip to form a signal transmission structure;

[0040] The signal transmission structure includes a first transmission structure and a second transmission structure, both of which include through-silicon vias disposed in the second semiconductor chip.

[0041] The first control circuit includes a first programming device, which is a one-time programmable device. The first programming device is configured to store the state information of the first transmission structure. The first control circuit is coupled to the control terminal of the first selection circuit.

[0042] The two output terminals of the first selection circuit are respectively coupled to the first transmission structure and the second transmission structure. The first selection circuit is configured to transmit a signal to one of the first transmission structure and the second transmission structure according to the state information stored in the first programming device.

[0043] In the chip stacking structure and manufacturing method provided in this disclosure, by setting a first control circuit and a first selection circuit corresponding to each first transmission structure position on the first semiconductor chip, the area ratio on the first semiconductor chip is reduced. At the same time, the first selection circuit can read the status information of the first transmission structure stored in the first control circuit at the moment of power-on during the initialization process of the chip stacking structure, which shortens the information transmission path, reduces the complexity of the repair operation, eliminates complex logic control and does not require time-division transmission, simplifies wiring resources and reduces area cost.

[0044] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0045] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0046] Figure 1 This is a schematic diagram of a chip stacking structure illustrated in an exemplary embodiment of this disclosure.

[0047] Figure 2 This is a schematic diagram of a first control circuit illustrated in an exemplary embodiment of the present disclosure.

[0048] Figure 3 This is a schematic diagram of a chip stacking structure illustrated in an exemplary embodiment of this disclosure.

[0049] Figure 4 This is a schematic diagram of a chip stacking structure illustrated in an exemplary embodiment of this disclosure.

[0050] Figure 5 This is a schematic diagram of a chip stacking structure illustrated in an exemplary embodiment of this disclosure.

[0051] Figure 6 This is a schematic diagram of a chip stacking structure illustrated in an exemplary embodiment of this disclosure.

[0052] Figure 7 This is a schematic diagram of a chip stacking structure illustrated in an exemplary embodiment of this disclosure.

[0053] Figure 8 This is a flowchart illustrating a method for fabricating a chip stacking structure according to an exemplary embodiment of this disclosure.

[0054] Reference numerals: 100, Chip stack structure; 10, First semiconductor chip; 20, Second semiconductor chip; 21, First chip; 22, Second chip; 30a, First signal transmission structure; 30b, Second signal transmission structure; 31, First transmission structure; 311, First contact pad; 312, Second contact pad; 313, First solder section; 32, Second transmission structure; 321, Third contact pad; 322, Fourth contact pad; 323, Second solder section; 33, Through-Silicon Via (TSV); 33a, First TSV; 33b, Second TSV; 34, Fourth transmission structure; 35, Fifth transmission structure; 40, First control circuit; 41, First programming device; 42, [unclear text - possibly a typo, should be something like "state"]. 421, First transistor; 43, Inductive amplifier sub-circuit; 431, Second transistor; 432, Third transistor; 433, Latch; 433a, First device; 433b, Second device; 44, Programming control sub-circuit; 441, Fourth transistor; 45, First node; 46, Read / write signal terminal; 47, Second node; 48, First power supply terminal; 49, Second power supply terminal; 50, First selection circuit; 60, Second control circuit; 70, Second selection circuit; 70', Second selection circuit; 80a, Third transmission structure; 80b, Sixth transmission structure; 81, Fifth contact pad; 82, Sixth contact pad; 83, Third solder section. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0056] After HBM production is completed, the signal path array penetrating multiple semiconductor chips needs to be tested. When a signal path is in a poor conducting state, its position in the signal path array needs to be recorded. To record signal path defects, currently, an integrated fuse array is typically placed on the bottommost interface chip in the HBM thickness direction. Each fuse in the integrated fuse array corresponds to each signal path in the signal path array, so that the position of the signal path in a poor conducting state is recorded in the integrated fuse array.

[0057] However, the logic circuits of the integrated fuse array occupy a large area, and when reading the integrated fuse array to determine the position of the signal path in the signal path array, it is necessary to traverse each fuse in the integrated fuse array one by one, resulting in a long information transmission path; in addition, multiple control circuits such as clock generation circuits and control circuits need to be set up, making the operation more complicated.

[0058] In view of the above, this disclosure provides a chip stacking structure, including: a first semiconductor chip, a second semiconductor chip, a signal transmission structure connecting the first semiconductor chip and the second semiconductor chip, a first control circuit and a first selection circuit disposed on the first semiconductor chip; wherein, the signal transmission structure includes a first transmission structure and a second transmission structure, both of which include through-silicon vias disposed in the second semiconductor chip; the first control circuit includes a first programming device, which is a one-time programmable device, configured to store state information of the first transmission structure, and the first control circuit is coupled to the control terminal of the first selection circuit; the two output terminals of the first selection circuit are respectively coupled to the first transmission structure and the second transmission structure, and the first selection circuit is configured to transmit a signal to one of the first transmission structure and the second transmission structure according to the state information stored in the first programming device. By setting a first control circuit and a first selection circuit corresponding to each first transmission structure position on the first semiconductor chip, the area ratio on the first semiconductor chip is reduced. At the same time, the first selection circuit can read the status information of the first transmission structure stored in the first control circuit at the moment the chip stack structure is powered on, which shortens the information transmission path, reduces the complexity of the repair operation, eliminates complex logic control and does not require time-division transmission, simplifies wiring resources and reduces area cost.

[0059] In an exemplary embodiment of this disclosure, such as Figure 1As shown, a chip stacking structure 100 is provided, which can be applied to structures such as HBM memory formed by stacking multiple semiconductor chips. The chip stacking structure 100 includes a first semiconductor chip 10, a second semiconductor chip 20, a signal transmission structure connecting the first semiconductor chip 10 and the second semiconductor chip 20, a first control circuit 40 disposed on the first semiconductor chip 10, and a first selection circuit 50. The signal transmission structure includes a first transmission structure 31 and a second transmission structure 32, both of which include a first through-silicon via 33a disposed in the second semiconductor chip 20. The first control circuit 40 includes a first programming device 41, which is a one-time programmable device configured to store the state information of the first transmission structure 31. The first control circuit 40 is coupled to the control terminal of the first selection circuit 50. The two output terminals of the first selection circuit 50 are respectively coupled to the first transmission structure 31 and the second transmission structure 32, and the first selection circuit 50 is configured to transmit a signal to one of the first transmission structure 31 and the second transmission structure 32 according to the state information stored in the first programming device 41.

[0060] In the exemplary embodiments of this disclosure, the first semiconductor chip 10 and the second semiconductor chip 20 can be any chips that can be stacked together to achieve the corresponding functions. (See reference...) Figure 1 The first semiconductor chip 10 can be a control chip connecting the second semiconductor chip 20 and the substrate, such as a base die or a logic die. The first semiconductor chip 10 contains a large number of circuits for implementing various control logics, such as numerous digital circuits like AND gates, NAND gates, NOT gates, XOR gates, and other analog circuits. Through the first semiconductor chip 10, one or more second semiconductor chips 20 stacked on top of it can be controlled. The second semiconductor chip 20 can be the body of an unpackaged small integrated circuit made of semiconductor material, called a bare die, which is a chip that has not been packaged after the wafer has been cut and tested. Each second semiconductor chip 20 integrates its own memory core containing an array of memory cells.

[0061] The signal transmission structure may include a first signal transmission structure 30a connecting a first semiconductor chip 10 and a second semiconductor chip 20. The first semiconductor chip 10 controls the second semiconductor chip 20 through the first signal transmission structure 30a and performs functions such as communication circuitry, data storage, and data retrieval. The first signal transmission structure 30a may, for example, include a first transmission structure 31 and a second transmission structure 32, which are identical in structure and arranged adjacent to each other. One of the first transmission structures 31 and 32 may be a backup transmission structure. For example, the second transmission structure 32 may be a backup transmission structure for the first transmission structure 31, used for signal transmission when the first transmission structure 31 fails (e.g., is defective) or is occupied. It is understood that the first transmission structure 31 may also be a backup transmission structure in other first signal transmission structures 30a.

[0062] Both the first transmission structure 31 and the second transmission structure 32 may include a first through-silicon via 33a (TSV) disposed in the second semiconductor chip 20. The first through-silicon via 33a may be formed on the second semiconductor chip 20 by first forming a via through the second semiconductor chip 20 using laser drilling, wet etching or dry etching, etc., then depositing or coating an insulating material on the sidewall of the via, and filling the via with a conductive material. The conductive material may be, for example, copper, tungsten, polysilicon, etc. The conductive material in the via forms the first through-silicon via 33a.

[0063] In some possible implementations, refer to Figure 1 As shown, the first transmission structure 31 further includes a first contact pad 311 disposed on the first semiconductor chip 10 and a second contact pad 312 disposed on the second semiconductor chip 20, the first contact pad 311 and the second contact pad 312 being electrically connected; the second transmission structure 32 further includes a third contact pad 321 disposed on the first semiconductor chip 10 and a fourth contact pad 322 disposed on the second semiconductor chip 20, the third contact pad 321 and the fourth contact pad 322 being electrically connected.

[0064] The first contact pad 311 and the third contact pad 321 are pads, solder joints, bumps, or exposed circuit layers on the contact surface of the first semiconductor chip 10 opposite to the second semiconductor chip 20, respectively. The second contact pad 312 and the fourth contact pad 322 are pads, solder joints, bumps, or exposed circuit layers on the contact surface of the second semiconductor chip 20 opposite to the first semiconductor chip 10, respectively. The first contact pad 311 and the second contact pad 312 are positioned correspondingly and electrically connected to each other, for example, through a first solder part 313, which may be a solder ball, a conductive via, or a bump. The second contact pad 312 is connected to the first through-silicon via 33a in the first transmission structure 31, so that the signal can be transmitted from the first semiconductor chip 10 to the second semiconductor chip 20 in sequence through the first contact pad 311, the first solder part 313, the second contact pad 312, and the first through-silicon via 33a (i.e., the first transmission structure 31).

[0065] It is understood that the third contact pad 321 and the fourth contact pad 322 are positioned correspondingly and electrically connected to each other, for example, through a second solder section 323, which may be a solder ball, a conductive via, or a bump. The fourth contact pad 322 is connected to the first through-silicon via 33a in the second transmission structure 32, so that the signal can be transmitted from the first semiconductor chip 10 to the second semiconductor chip 20 in sequence through the third contact pad 321, the second solder section 323, the fourth contact pad 322, and the first through-silicon via 33a (i.e., the second transmission structure 32).

[0066] For example, a first control circuit 40 and a first selection circuit 50 are provided on the first semiconductor chip 10. The first control circuit 40 is used to store the status information of the first transmission structure 31. The status information of the first transmission structure 31 can be determined by testing during the manufacturing and testing phase. For example, a test logic circuit is connected to the chip stack structure 100, and a functional scan of the first signal transmission structure 30a in the chip stack structure 100 is performed by a test signal to determine the status information of the first signal transmission structure 30a. Taking the first transmission structure 31 as an example, the status information of the first transmission structure 31 includes one of a first status information and a second status information. For example, when the first transmission structure 31 is in an active state and is not occupied by other signal transmission paths (i.e., the first transmission structure 31 is used as a backup transmission structure in other first signal transmission structures 30a, but is not enabled), the first control circuit 40 stores the status information of the first transmission structure 31 as the first status information. When the first transmission structure 31 is in a faulty state, for example, when the first through-silicon via 33a is in a faulty conduction state or the connection of the pad or solder ball connecting the upper and lower first through-silicon vias 33a is in a faulty conduction state, or when the first transmission structure 31 is occupied (i.e., the first transmission structure 31 is used as a backup transmission structure in other first signal transmission structures 30a and is enabled), the first control circuit 40 stores the status information of the first transmission structure 31 as the second status information.

[0067] refer to Figure 2 As shown, the first control circuit 40 includes a first programming device 41. For example, the first programming device 41 can store the state information of the first transmission structure 31. The first programming device 41 is a one-time programmable device, that is, after the first programming device 41 stores the state information of the first transmission structure 31, the state information of the first transmission structure 31 remains valid and cannot be changed or reprogrammed, but it can be read multiple times. The first programming device 41 can be, for example, a fuse or an anti-fuse. The fuse includes a polysilicon gate or a metal gate. When the fuse is not programmed, the fuse is connected to the polysilicon gate or the metal gate; when the fuse is programmed, the fuse is melted away from the polysilicon gate or the metal gate. The anti-fuse includes two layers of electrodes and an anti-fuse dielectric layer between the two layers of electrodes. When the anti-fuse is not programmed, the two layers of electrodes are not connected to each other; when the anti-fuse is programmed, the anti-fuse dielectric is broken down under the action of a strong electric field to form a conductive path, thereby connecting the two layers of electrodes. In some embodiments, the first programming device 41 is an antifuse device, which has high security and reliability, can be read a large number of times, and has low power consumption.

[0068] For example, when the state information of the first transmission structure 31 is the first state information, that is, the first transmission structure 31 is in an effective state and is not occupied by the signal transmission path of other transmission structures (that is, the first transmission structure 31 serves as a backup transmission structure in other first signal transmission structures 30a, but is not activated), the first programming device 41 does not perform programming. When the first programming device 41 is a fuse device, that is, the fuse is connected to the polysilicon gate or the metal gate; when the first programming device 41 is an antifuse device, the two layers of electrodes are not connected to each other. When the state information of the first transmission structure 31 is the second state information, that is, the first transmission structure 31 is disabled, or is occupied by the signal transmission path (that is, the first transmission structure 31 serves as a backup transmission structure in other first signal transmission structures 30a and is activated), the first programming device 41 performs programming. When the first programming device 41 is a fuse device, that is, the fuse is melted by the polysilicon gate or the metal gate; when the first programming device 41 is an antifuse device, the antifuse medium forms a conductive path under the action of a strong electric field, so that the two layers of electrodes are connected to each other. The first state information or the second state information of the first transmission structure 31 is stored by utilizing the difference in the connection state before and after programming the first programming device 41.

[0069] Coupling refers to the organic connection formed between multiple corresponding ports of two objects, which can be a physical connection or electromagnetic coupling. The first selection circuit 50 can be a circuit that determines the signal path based on the different state information stored in the first control circuit 40 coupled to it. The first selection circuit 50 can be, for example, a data distributor (Demultiplexer, DeMUX), configured with a single input and multiple outputs. Through the data distributor, it can determine which output path the signal will take. Exemplarily, by setting the control terminal of the first selection circuit 50, different logic signals received from the first control circuit 40 characterize different state information of the first transmission structure 31, thereby causing the first selection circuit 50 to select either the first transmission structure 31 or the second transmission structure 32 to transmit the signal. In this embodiment, the signal can be a control signal or a data signal. Since the control terminals of the first control circuit 40 and the first selection circuit 50 are coupled, and the two output terminals of the first selection circuit 50 are respectively coupled to the first transmission structure 31 and the second transmission structure 32, the control terminal of the first selection circuit 50 can read the logic state output by the first programming device 41 in the first control circuit 40, and the control signal can be output through the output terminal connected to the first transmission structure 31 or the output terminal connected to the second transmission structure 32. For example, when a read signal is applied to the first control circuit 40, if the first control circuit 40 outputs a low level, the state information representing the first transmission structure 31 is the first state information, and the first selection circuit 50 transmits the signal to the first transmission structure 31; if the first control circuit 40 outputs a high level, the state information representing the first transmission structure 31 is the second state information, and the first selection circuit 50 transmits the signal to the second transmission structure 32.

[0070] In some possible implementations, the two outputs of the first selection circuit 50 are coupled to the first contact pad 311 and the third contact pad 321, respectively. Since the first selection circuit 50 is located inside the first semiconductor chip 10, and the first contact pad 311 and the third contact pad 321 are located on the first semiconductor chip 10, coupling the two outputs of the first selection circuit 50 to the first contact pad 311 and the third contact pad 321, respectively, allows the first selection circuit 50 to transmit signals to the first transmission structure 31 or the second transmission structure 32 through the first contact pad 311 or the third contact pad 321 according to the state information of the first transmission structure 31 stored in the first control circuit 40.

[0071] For example, both the first control circuit 40 and the first selection circuit 50 are disposed on the first semiconductor chip 10 and are located between the first transmission structure 31 and the second transmission structure 32, as shown in the reference. Figure 1As shown, a first control circuit 40 and a first selection circuit 50 are provided between adjacent first transmission structures 31 and second transmission structures 32, and the output terminals of the first selection circuit 50 are coupled to the corresponding first transmission structures 31 and second transmission structures 32. By making full use of the area between the first transmission structures 31 and second transmission structures 32, the area ratio of the repair circuit composed of the first control circuit 40 and the first selection circuit 50 on the first semiconductor chip 10 is reduced, thereby reducing chip cost. At the same time, when the chip stack structure 100 is powered on during the initialization process, the first selection circuit 50 can read the state information of the first transmission structure 31 stored in the first control circuit 40, shorten the transmission path of the state information of the first transmission structure 31, reduce the complexity of the repair operation, eliminate complex logic control and do not require time-division transmission, simplify wiring resources and reduce area cost.

[0072] In some possible implementations, a plurality of second semiconductor chips 20 may be disposed in the chip stack structure 100, and the plurality of second semiconductor chips 20 may be stacked on top of the first semiconductor chip 10 to form the chip stack structure 100. For example... Figure 3 As shown, Figure 3 It includes a first semiconductor chip 10 and a plurality of second semiconductor chips 20, which are stacked on top of the first semiconductor chip 10. For two adjacent second semiconductor chips 20, the chip closer to the first semiconductor chip 10 can be the first chip 21, and the chip farther away from the first semiconductor chip 10 can be the second chip 22.

[0073] The signal transmission structure also includes a second signal transmission structure 30b that connects any two adjacent second semiconductor chips 20. For example, the second signal transmission structure 30b is used to connect the first chip 21 and the second chip 22. The second signal transmission structure 30b has the same structure as the first signal transmission structure 30a, and their positions correspond to each other. (Refer to...) Figure 3 The second signal transmission structure 30b includes a fourth transmission structure 34 and a fifth transmission structure 35. The fourth transmission structure 34 corresponds to the position of the first transmission structure 31, and the fifth transmission structure 35 corresponds to the position of the second transmission structure 32. This allows the signal to be further transmitted to the fourth transmission structure 34 when it is transmitted to the first transmission structure 31, or to the fifth transmission structure 35 when it is transmitted to the second transmission structure 32. This enables the first semiconductor chip 10 to control other second semiconductor chips 20 located away from the first semiconductor chip 10.

[0074] In some possible implementations, refer to Figure 4As shown, the chip stack structure 100 also includes a second control circuit 60 and a second selection circuit 70 disposed on the second semiconductor chip 20; the second control circuit 60 includes a second programming device, which is a one-time programmable device, and is configured to store the state information of the first transmission structure 31. The second control circuit 60 is coupled to the control terminal of the second selection circuit 70; the two input terminals of the second selection circuit 70 are respectively coupled to the first transmission structure 31 and the second transmission structure 32, and the second selection circuit 70 is configured to output a signal on one of the first transmission structure 31 and the second transmission structure 32 according to the state information stored in the second programming device.

[0075] In this embodiment, since the chip stack structure 100 is provided with multiple second semiconductor chips 20, during the use of the chip stack structure 100, the second control circuit 60 and the second selection circuit 70 are used to select whether the signal needs to be transmitted to the next second semiconductor chip 20 that is far away from the first semiconductor chip 10. That is, in some cases, the signal only needs to be transmitted from the first semiconductor chip 10 to the adjacent second semiconductor chip 20. In this case, it is only necessary to activate the first control circuit 40 and the first selection circuit 50 on the first semiconductor chip 10 to transmit the signal to the first transmission structure 31 or the second transmission structure 32 that connects the first semiconductor chip 10 and the second semiconductor chip 20. In other cases, when a signal needs to be transmitted from the first semiconductor chip 10 to a second semiconductor chip 20 that is far away from the first semiconductor chip 20, the first control circuit 40 and the first selection circuit 50 on the first semiconductor chip 10, as well as the second control circuit 60 and the second selection circuit 70 on the second semiconductor chip 20, need to be activated simultaneously to output a signal connected to the first transmission structure 31 or the second transmission structure 32 of the first semiconductor chip 10 and the second semiconductor chip 20, and transmit the signal to the first transmission structure 31 or the second transmission structure 32 that connects two adjacent second semiconductor chips 20.

[0076] The configuration of the second control circuit 60 is similar to that of the first control circuit 40. The second control circuit 60 includes a second programming device, similar to the first programming device 41. The second programming device is a one-time programmable device, such as a fuse or an anti-fuse. The second programming device is configured to store the state information of the first transmission structure 31. The second control circuit 60 is coupled to the control terminal of the second selection circuit 70. The second selection circuit 70 can be, for example, a multiplexer (MUX). The MUX has multiple inputs and a single output, allowing the selection of which input signal can be output. Exemplarily, by setting the control terminal of the second selection circuit 70, different logic signals received from the second control circuit 60 represent different state information of the first transmission structure 31, thereby enabling the second selection circuit 70 to select signals connected to the first transmission structure 31 or the second transmission structure 32 of the first semiconductor chip 10 and the second semiconductor chip 20 for further transmission. Since the control terminal of the second control circuit 60 is coupled to the control terminal of the second selection circuit 70, and the two input terminals of the second selection circuit 70 are coupled to the first transmission structure 31 and the second transmission structure 32 respectively, the control terminal of the second selection circuit 70 can control the signal output on the first transmission structure 31 or the signal output on the second transmission structure 32 by reading the logic state output by the second programming device in the second control circuit 60.

[0077] For example, a read signal is applied to the second control circuit 60. When the second control circuit 60 outputs a low level, the state information representing the first transmission structure 31 is the first state information, that is, the first transmission structure 31 is valid and not occupied. At this time, the first transmission structure 31 transmits the signal that should originally be transmitted by the first transmission structure 31, and the second transmission structure 32 transmits the signal that should originally be transmitted by the second transmission structure 32. The second selection circuit 70 outputs the signal on the first transmission structure 31 according to the state information of the first transmission structure 31. When the second control circuit 60 outputs a high level, the state information representing the first transmission structure 31 is the second state information, that is, the first transmission structure 31 is invalid or occupied. When the first transmission structure 31 fails, the signal that should have been transmitted by the first transmission structure 31 is transmitted by the second transmission structure 32, and the first transmission structure 31 does not transmit signals. Therefore, the second selection circuit 70 selects to output the signal on the second transmission structure 32. When the first transmission structure 31 is occupied, that is, when the first transmission structure 31 is used as a backup transmission structure for other first signal transmission structures 30a and is enabled, the first transmission structure 31 transmits other signals, and the signal that should have been transmitted by the first transmission structure 31 is transmitted by the second transmission structure 32. Therefore, the second selection circuit 70 selects to output the signal on the second transmission structure 32.

[0078] In some possible implementations, the two input terminals of the second selection circuit 70 are coupled to the second contact pad 312 and the fourth contact pad 322, respectively. Since the second selection circuit 70 is located inside the second semiconductor chip 20, and the second contact pad 312 and the fourth contact pad 322 are located on the second semiconductor chip 20, coupling the two input terminals of the second selection circuit 70 to the second contact pad 312 and the fourth contact pad 32, respectively, allows the signal transmitted on the first transmission structure 31 or the second transmission structure 32 to be transmitted to the second selection circuit 70. Furthermore, the second selection circuit 70 can select to output the signal transmitted on the first transmission structure 31 or the second transmission structure 32 based on the state information of the first transmission structure 31 stored in the second control circuit 60.

[0079] For example, both the second control circuit 60 and the second selection circuit 70 are disposed on the second semiconductor chip 20 and are located between the first transmission structure 31 and the second transmission structure 32, as shown in the reference. Figure 4 As shown, in the second semiconductor chip 20, a second control circuit 60 and a second selection circuit 70 are provided between adjacent first transmission structures 31 and second transmission structures 32. The input terminals of the second selection circuit 70 are coupled to the corresponding first transmission structures 31 and second transmission structures 32. This allows the second selection circuit 70 to read the state information of the first transmission structure 31 stored in the second control circuit 60 at the moment of power-on during the initialization process of the chip stack structure 100, thereby shortening the transmission path of the state information of the first transmission structure 31 and reducing the complexity of the repair operation.

[0080] In some possible implementations, a plurality of second semiconductor chips 20 may be disposed in the chip stack structure 100, and the plurality of second semiconductor chips 20 may be stacked on top of the first semiconductor chip 10 to form the chip stack structure 100. For example... Figure 5 As shown, Figure 5 The system includes a first semiconductor chip 10 and multiple second semiconductor chips 20, which are stacked on top of the first semiconductor chip 10. Each of the multiple second semiconductor chips 20 is equipped with a second control circuit 60 and a second selection circuit 70. For two adjacent second semiconductor chips 20, the chip closer to the first semiconductor chip 10 can be the first chip 21, and the chip farther from the first semiconductor chip 10 can be the second chip 22. The second control circuit 60 in the second chip 22 is coupled to the control terminal of the second selection circuit 70 in the second chip 22, and the input terminal of the second selection circuit 70 in the second chip 22 is coupled to the fourth transmission structure 34 and the fifth transmission structure 35, respectively.

[0081] For example, a read signal can be applied to the second control circuit 60 in the second chip 22. When the signal output by the second control circuit 60 indicates that the state information of the first transmission structure 31 is the first state information, that is, the first transmission structure 31 is not occupied and is valid, the first transmission structure 31 transmits the signal that should have been transmitted by the first transmission structure 31 and further transmits it to the fourth transmission structure 34, and the second transmission structure 32 transmits the signal that should have been transmitted by the second transmission structure 32 and further transmits it to the fifth transmission structure 35. The second selection circuit 70 in the second chip 22 selects to output the signal on the fourth transmission structure 34 corresponding to the position of the first transmission structure 31 according to the state information of the first transmission structure 31.

[0082] When the signal output by the second control circuit 60 in the second chip 22 represents the second state information of the first transmission structure 31, i.e., the first transmission structure 31 is faulty or occupied, the second selection circuit 70 in the second chip 22 selects to output the signal on the fifth transmission structure 35 corresponding to the position of the second transmission structure 32. In some embodiments, when the first transmission structure 31 is faulty, the signal that should have been transmitted by the first transmission structure 31 is transmitted by the second transmission structure 32 and further transmitted to the fifth transmission structure 35. The first transmission structure 31 does not transmit a signal, therefore the fourth transmission structure 34 also does not transmit a signal. Therefore, the second selection circuit 70 in the second chip 22 selects to output the signal on the fifth transmission structure 35. In other embodiments, when the first transmission structure 31 is occupied, i.e., the first transmission structure 31 is used as a backup transmission structure for other first signal transmission structures 30a and is enabled, the first transmission structure 31 transmits other signals, and the fourth transmission structure 34 is also used as a backup transmission structure for other second signal transmission structures 30b and is also enabled, and the fourth transmission structure 34 also transmits other signals. The signal that should have been transmitted by the first transmission structure 31 is transmitted by the second transmission structure 32, which then transmits the signal to the fifth transmission structure 35. Therefore, the second selection circuit 70 in the second chip 22 selects to output the signal on the fifth transmission structure 35.

[0083] By setting a second control circuit 60 and a second selection circuit 70 in multiple second semiconductor chips 20, the first semiconductor chip 10 can control other second semiconductor chips 20 that are far away from the first semiconductor chip 10, and quickly and accurately select the signal transmission path according to the state information of the stored first transmission structure 31.

[0084] In some possible implementations, refer to Figure 6As shown, the chip stack structure 100 further includes: a third transmission structure 80a connecting the first semiconductor chip 10 and the second semiconductor chip 20, and a second selection circuit 70' disposed on the second semiconductor chip 20; the third transmission structure 80a is configured to couple the first control circuit 40 to the control terminal of the second selection circuit 70'; the two input terminals of the second selection circuit 70' are respectively coupled to the first transmission structure 31 and the second transmission structure 32, and the second selection circuit 70' is configured to output a signal on one of the first transmission structure 31 and the second transmission structure 32 according to the state information stored in the first programming device 41.

[0085] In this embodiment, the third transmission structure 80a is used to connect the first semiconductor chip 10 and the second semiconductor chip 20. Specifically, the third transmission structure 80a couples the first control circuit 40 to the control terminal of the second selection circuit 70'. The structure and implementation of the second selection circuit 70' can be the same as those in the above embodiment. The two input terminals of the second selection circuit 70' are coupled to the first transmission structure 31 and the second transmission structure 32, respectively. The third transmission structure 80a is used to transmit the state information of the first transmission structure 31 stored in the first programming device 41 in the first control circuit 40 to the control terminal of the second selection circuit 70, so that the second selection circuit 70' can select to output the signal of the first transmission structure 31 or the signal of the second transmission structure 32 according to the state information of the first transmission structure 31 stored in the first programming device 41 in the first control circuit 40.

[0086] For example, refer to Figure 6 As shown, the third transmission structure 80a includes a second through-silicon via 33b disposed on the second semiconductor chip 20. The planar dimension of the second through-silicon via 33b of the third transmission structure 80a is larger than the planar dimension of the first through-silicon via 33a of either the first transmission structure 31 or the second transmission structure 32.

[0087] The second through-silicon via 33b in the third transmission structure 80a is formed in the same way as the first through-silicon via 33a in the first transmission structure 31 and the second transmission structure 32. Since the third transmission structure 80a is used to transmit the state information of the first transmission structure 31 stored in the first control circuit 40, the planar dimension of the second through-silicon via 33b is set to be larger than the planar dimension of the first through-silicon via 33a of either the first transmission structure 31 or the second transmission structure 32. This enhances the structural reliability of the third transmission structure 80a and ensures that the state information stored in the first control circuit 40 can be stably transmitted to the second selection circuit 70'.

[0088] By setting the control terminal of the second selection circuit 70', the different logic signals received by the control terminal from the first control circuit 40 represent different state information of the first transmission structure 31. This allows the second selection circuit 70' to select either the signal on the first transmission structure 31 or the signal on the second transmission structure 32 connected to the first semiconductor chip 10 and the second semiconductor chip 20 for further transmission. Since the control terminal of the first control circuit 40 is coupled to the control terminal of the second selection circuit 70', and the two input terminals of the second selection circuit 70' are coupled to the first transmission structure 31 and the second transmission structure 32 respectively, the control terminal of the second selection circuit 70' can control the signal output on the first transmission structure 31 or the signal output on the second transmission structure 32 by reading the logic state output by the first programming device 41 in the first control circuit 40.

[0089] In some possible implementations, refer to Figure 6 The third transmission structure 80a also includes a fifth contact pad 81 disposed on the first semiconductor chip 10 and a sixth contact pad 82 disposed on the second semiconductor chip 20; the first control circuit 40 is coupled to the fifth contact pad 81, and the control terminal of the second selection circuit 70' is coupled to the sixth contact pad 82.

[0090] The fifth contact pad 81 and the sixth contact pad 82 in the third transmission structure 80a are similar to the first contact pad 311 and the second contact pad 312 in the first transmission structure 31, and the third contact pad 321 and the fourth contact pad 322 in the second transmission structure 32, and will not be described in detail here. The fifth contact pad 81 and the sixth contact pad 82 are electrically connected, for example, through the third solder section 83. The first control circuit 40 is coupled to the fifth contact pad 81, so that the state information of the first transmission structure 31 stored in the first control circuit 40 can be transmitted to the fifth contact pad 81, and then to the sixth contact pad 82 via the third solder section 83. The control terminal of the second selection circuit 70' is coupled to the sixth contact pad 82, so that the second selection circuit 70' can select to output the signal transmitted on the first transmission structure 31 or the second transmission structure 32 according to the state information of the first transmission structure 31 stored in the first control circuit 40.

[0091] In some possible implementations, a plurality of second semiconductor chips 20 may be disposed in the chip stack structure 100, such as Figure 7 As shown, Figure 7It includes a first semiconductor chip 10 and multiple second semiconductor chips 20. The multiple second semiconductor chips 20 are stacked on the first semiconductor chip 10. Any two adjacent second semiconductor chips 20 are also connected through a sixth transmission structure 80b. The sixth transmission structure 80b has the same structure as the third transmission structure 80a and their positions correspond to each other, so that when the state information of the first transmission structure 31 stored in the first control circuit 40 is transmitted to the third transmission structure 80a, the state information of the first transmission structure 31 can be further transmitted to the sixth transmission structure 80b.

[0092] Each of the multiple second semiconductor chips 20 is provided with a second selection circuit 70'. For two adjacent second semiconductor chips 20, the chip closer to the first semiconductor chip 10 can be the first chip 21, and the chip farther away from the first semiconductor chip 10 can be the second chip 22. The control terminal of the second selection circuit 70' in the second chip 22 is coupled to the first control circuit 40 through the sixth transmission structure 80b, and the input terminal of the second selection circuit 70' in the second chip 22 is coupled to the fourth transmission structure 34 and the fifth transmission structure 35, respectively. Since the sixth transmission structure 80b is connected to the third transmission structure 80a, the state information of the first transmission structure 31 stored in the first control circuit 40 can be transmitted to the sixth transmission structure 80b through the third transmission structure 80a. The control terminal of the second selection circuit 70' in the second chip 22 is coupled to the sixth transmission structure 80b, so that the second selection circuit 70' in the second chip 22 can select to output the signal on the fourth transmission structure 34 corresponding to the position of the first transmission structure 31, or select to output the signal on the fifth transmission structure 35 corresponding to the position of the second transmission structure 32, based on the state information of the first transmission structure 31 transmitted by the sixth transmission structure 80b.

[0093] By setting a third transmission structure 80a connecting the first semiconductor chip 10 and the second semiconductor chip 20, a sixth transmission structure 80b connecting two adjacent second semiconductor chips 20, and a second selection circuit 70' in multiple second semiconductor chips 20, the state information of the first transmission structure 31 stored in the first control circuit 40 can be stably transmitted through the third transmission structure 80a and the sixth transmission structure 80b with larger planar dimensions. This enables the first semiconductor chip 10 to control other second semiconductor chips 20 that are far away from the first semiconductor chip 10, and to quickly and accurately select the signal transmission path according to the state information of the stored first transmission structure 31.

[0094] In one exemplary embodiment, reference Figure 2As shown, the first control circuit 40 further includes a status information transmission sub-circuit 42 and a sensing amplifier sub-circuit 43; the status information transmission sub-circuit 42 is coupled to the first programming device 41, and the status information transmission sub-circuit 42 is configured to transmit the status information stored in the first programming device 41 to the sensing amplifier sub-circuit 43; the sensing amplifier sub-circuit 43 is coupled to the status information transmission sub-circuit 42, and the sensing amplifier sub-circuit 43 is configured to sense the status information and output the control signal corresponding to the status information to the first selection circuit 50.

[0095] In this embodiment, combined with Figure 1 and Figure 2 The status information transmission sub-circuit 42 can be, for example, a circuit transmission line or a flexible circuit. When it is necessary to read the status information stored in the first programming device 41, the first and second terminals of the status information transmission sub-circuit 42 are coupled to the first programming device 41 and the inductive amplifier sub-circuit 43, respectively, so that the status information of the first transmission structure 31 stored in the first programming device 41 can be transmitted to the status information transmission sub-circuit 42 and then to the inductive amplifier sub-circuit 43. An inductive amplifier can be provided in the inductive amplifier sub-circuit 43. When the status information of the first transmission structure 31 is transmitted to the inductive amplifier sub-circuit 43, for example, a read signal is applied to the first programming device 41. When the status information transmission sub-circuit 42 outputs a low level, it indicates that the status information of the first transmission structure 31 is the second status information. The inductive amplifier sub-circuit 43 can sense the status information and output the control signal corresponding to the status information to the first selection circuit 50. For example, the inductive amplifier sub-circuit 43 reverses the phase of the low-level signal and outputs a high-level signal; the high-level signal corresponding to the status information of the first transmission structure 31 is output to the first selection circuit 50. For example, the control terminal of the first selection circuit 50 can be pre-configured so that a low-level signal corresponds to the first state information of the first transmission structure 31, and a high-level signal corresponds to the second state information of the first transmission structure 31. When the control terminal of the first selection circuit 50 receives a high-level signal, it controls the output terminal of the first selection circuit 50 to transmit the signal that should have been transmitted from the first transmission structure 31 to the second transmission structure 32, that is, to enable the second transmission structure 32 as a backup signal transmission structure for the first transmission structure 31.

[0096] For example, a first terminal of the first programming device 41 is coupled to a read / write signal terminal 46, which is configured to provide a read signal to read the state information of the first transmission structure 31 from the first programming device 41. The first terminal of the state information transmission sub-circuit 42 is coupled to the first programming device 41, for example, the first terminal of the first transistor 421 of the state information transmission sub-circuit 42 is coupled to the second terminal of the first programming device 41. The first transistor 421 can be a diode, transistor, thyristor, MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), etc., and the first transistor 421 can be, for example, an NMOS or a PMOS.

[0097] The second terminal of the status information transmission sub-circuit 42 is coupled to the inductive amplifier sub-circuit 43, for example, through the first node 45. The second terminal of the first transistor 421 is coupled to the first node 45, and the first terminal of the second transistor 431 of the inductive amplifier sub-circuit 43 is coupled to the first node 45. The second terminal of the second transistor 431 is coupled to the second node 47. The second transistor 431 is used to control the coupling or disconnection of the inductive amplifier sub-circuit 43 and the status information transmission sub-circuit 42. For example, when reading the first programming device 41, the second transistor 431 is in the on state; when programming or performing other operations on the first programming device 41, the second transistor 431 is in the off state. The second transistor 431 may be the same as or different from the first transistor 421.

[0098] The inductive amplifier sub-circuit 43 also includes a third transistor 432. The first terminal of the third transistor 432 is coupled to a first power supply terminal 48, which provides a high voltage to the inductive amplifier sub-circuit 43 (described in detail later). The second transistor 431 is used to determine whether to provide a high voltage to the inductive amplifier sub-circuit 43 when it receives different state information from the first transmission structure 31, so as to ensure that the control signal output by the inductive amplifier sub-circuit 43 is more accurate. The inductive amplifier sub-circuit 43 also includes a latch 433. The input terminal of the latch 433 is coupled to a second node 47. The latch 433 performs inductive amplification based on the state information of the first transmission structure 31 received by the second node 47. The output terminal of the latch 433 serves as the output terminal of the first control circuit 40, that is, the latch 433 outputs the control signal corresponding to the state information and outputs it to the control terminal of the first selection circuit 50.

[0099] The following describes in detail the process of reading the status information of the first transmission structure 31 stored in the first programming device 41. In this embodiment, the first programming device 41 is exemplarily an antifuse device.

[0100] Before reading from the first programming device 41, a low-level voltage can be used to precharge the latch 433, for example, by providing a low-level voltage to the first device 433a, so that the low-level voltage signal is transmitted through the second node 47 in the inductive amplifier sub-circuit 43. When the second transistor 431 and the first transistor 421 are NMOS, a high voltage is provided to the gates of the second transistor 431 and the first transistor 421, so that the second transistor 431 and the first transistor 421 are turned on, and a read signal is input to the read / write signal terminal 46. The voltage of the read signal can be, for example, a zero voltage of 0V, which is applied to the first terminal of the first programming device 41.

[0101] When the state information of the first transmission structure 31 stored in the first programming device 41 is the second state information, the first programming device 41 is programmed. The two electrodes in the first programming device 41 are interconnected. Since the first device 433a is pre-charged with a low-level voltage, the low-level voltage is discharged through the first programming device 41, and the second terminal of the first programming device 41 outputs a low-level signal. This low-level signal is then transmitted sequentially through the first transistor 421, the first node 45, the second transistor 431, and the second node 47 to the latch 433, so that the input terminal of the latch 433 receives the low-level signal. The second device 433b can be configured as an inverter, so that the output terminal of the latch 433 outputs a high-level signal, that is, the output terminal of the first control circuit 40 outputs a high-level signal. When the output terminal of the first control circuit 40 outputs a high-level signal, it indicates that the state information of the first transmission structure 31 stored in the first programming device 41 is the second state information. The first selection circuit 50 transmits the signal to the second transmission structure 32 according to the received high-level signal.

[0102] When the state information of the first transmission structure 31 stored in the first programming device 41 is the first state information, the first programming device 41 does not perform programming, and the two layers of electrodes in the first programming device 41 are not connected to each other. At this time, the third transistor 432 is in the conducting state, and the first power supply terminal 48 provides a high-level voltage to the second node 47 through the third transistor 432. The first power supply terminal 48 can be, for example, a VDD power supply or a VCC power supply, so that the input terminal of the latch 433 receives a high-level signal. The second device 433b can be configured as an inverter, so that the output terminal of the latch 433 outputs a low-level signal, that is, the output terminal of the first control circuit 40 outputs a low-level signal. When the output terminal of the first control circuit 40 outputs a low-level signal, it indicates that the state information of the first transmission structure 31 stored in the first programming device 41 is the first state information, and the first selection circuit 50 transmits the signal to the first transmission structure 31 according to the received low-level signal.

[0103] In some possible implementations, refer to Figure 2As shown, the first control circuit 40 also includes a programming control sub-circuit 44, which is coupled to the status information transmission sub-circuit 42. The programming control sub-circuit 44 is configured to work with the status information transmission sub-circuit 42 to control the programming operation of the first programming device 41.

[0104] Combination Figure 1 and Figure 2 When it is necessary to store the state information of the first transmission structure 31, the first and second ends of the state information transmission sub-circuit 42 are coupled to the first programming device 41 and the programming control sub-circuit 44, respectively, to control the programming operation of the first programming device 41. For example, the first end of the first programming device 41 is coupled to the read / write signal end 46, which is also configured to provide a programming signal to store the state information of the first transmission structure 31 on the first programming device 41. The first end of the state information transmission sub-circuit 42 is coupled to the first programming device 41, for example, by coupling the first end of the first transistor 421 of the state information transmission sub-circuit 42 to the second end of the first programming device 41. The second end of the state information transmission sub-circuit 42 is coupled to the programming control sub-circuit 44, for example, through a first node 45, by coupling the second end of the first transistor 421 to the first node 45, and connecting the first end of the fourth transistor 441 of the programming control sub-circuit 44 to the first node 45. The second terminal of the fourth transistor 441 is coupled to the second power supply terminal 49, which is used to provide a low-level voltage to the programming control sub-circuit 44. The second power supply terminal 49 may be, for example, the VSS power supply terminal.

[0105] The storage process of the first programming device 41 storing the state information of the first transmission structure 31 will be described in detail below. In this embodiment, the first programming device 41 is exemplarily an antifuse device.

[0106] When the test determines that the status information of the first transmission structure 31 is valid and not occupied, the first programming device 41 does not need to be programmed. When the test determines that the status information of the first transmission structure 31 is invalid or occupied, that is, the status information of the first transmission structure 31 is the second status information, the read / write signal terminal 46 provides a programming signal of a strong electric field voltage, such as a high voltage of 6V or above. The strong electric field voltage acts on the first terminal of the first programming device 41, controlling the first transistor 421 and the fourth transistor 441 to be in the conducting state, so that the antifuse dielectric is broken down under the action of the strong electric field and then a conductive path is formed. The two layers of electrodes in the first programming device 41 are connected to each other, and the strong electric field voltage is transmitted to the second power supply terminal 49 through the first transistor 421 and the fourth transistor 441, thus completing the storage of the second status information of the first transmission structure 31.

[0107] In some possible implementations, the structure of the second control circuit 60 is the same as or similar to that of the first control circuit 40. That is, the configuration of the second control circuit 60 is the same as that of the first control circuit 40; when the first programming device 41 is a fuse, the second programming device is also a fuse; when the first programming device 41 is an anti-fuse, the second programming device is also an anti-fuse. Furthermore, the second control circuit 60 also includes corresponding programming circuits, status transmission circuits, induction amplification circuits, etc., to simplify the programming and repair operations.

[0108] In some other possible implementations, the second control circuit 60 may be omitted. For example, as... Figure 6 and Figure 7 As shown, when using the aforementioned third transmission structure 80a, the control signal output by the first control circuit 40 can be transmitted to the control terminal of the second selection circuit 70 via the third transmission structure 80a. Alternatively, a portion of the circuit structure of the second control circuit 60 can be omitted, while retaining another portion; that is, the second control circuit 60 can share some circuit structures with the first control circuit 40. For example, in one example, the second control circuit 60 may only include a latch (refer to latch 433), and the second node 47 of the first control circuit 40 can be coupled to the latch of the second control circuit 60 via the third transmission structure 80a.

[0109] In one exemplary embodiment, a method for fabricating a chip stacking structure is provided. This method is used to fabricate the chip stacking structure described in the above embodiment, such as... Figure 8 As shown, the fabrication method of the chip stacking structure includes the following steps:

[0110] Step S100: Provide a first semiconductor chip, the first semiconductor chip including a first control circuit and a first selection circuit;

[0111] Step S200: Provide a second semiconductor chip, the second semiconductor chip including a through-silicon via (TSV);

[0112] Step S300: Bond the second semiconductor chip to the first semiconductor chip to form a signal transmission structure;

[0113] The signal transmission structure includes a first transmission structure and a second transmission structure, both of which include through-silicon vias (TSVs) disposed in a second semiconductor chip. The first control circuit includes a first programming device, which is a one-time programmable device configured to store the state information of the first transmission structure. The first control circuit is coupled to the control terminal of a first selection circuit. The two output terminals of the first selection circuit are respectively coupled to the first transmission structure and the second transmission structure. The first selection circuit is configured to transmit a signal to one of the first transmission structure and the second transmission structure according to the state information stored in the first programming device.

[0114] In step S100, the first semiconductor chip is, for example, a substrate chip or a logic chip, and is used to control the second semiconductor chip. The first semiconductor chip includes a first control circuit and a first selection circuit. The first control circuit includes a first programming device, which is a one-time programmable device. The first programming device is configured to store the state information of the first transmission structure. The storage process of the state information of the first transmission structure is similar to that described in the above embodiments and will not be repeated here. Once the first programming device is programmed, the state information of the first transmission structure will be continuously stored in the first programming device. The control terminals of the first control circuit and the first selection circuit are coupled, and multiple first control circuits and first selection circuits are arranged in an array on the first semiconductor chip.

[0115] In step S200, the second semiconductor chip may be stacked along the thickness direction of the first semiconductor chip and disposed above the first semiconductor chip. The second semiconductor chip may be an unpackaged bare die, and a through-silicon via (TSV) may be provided in the second semiconductor chip. The TSV may be formed by first forming a through-hole in the second semiconductor chip using techniques such as laser drilling, wet etching, or dry etching, then depositing or coating an insulating material on the sidewall of the TSV, and filling the TSV with a conductive material, such as copper, tungsten, or polysilicon. The conductive material in the TSV forms the TSV.

[0116] In step S300, contact pads are formed on the second semiconductor chip, for example, by chemical vapor deposition. The positions of the contact pads are set to correspond to the positions of multiple through-silicon vias (TSVs), allowing signals to be transmitted through the contact pads on the second semiconductor chip to the TSVs. Contact pads are also formed on the first semiconductor chip, with their positions corresponding to those on the second semiconductor chip. For example, a solder joint can be provided between the contact pads on the first and second semiconductor chips, connecting them. Alternatively, the contact pads on the first and second semiconductor chips can be directly connected, bonding the second semiconductor chip to the first. The contact pads, solder joint, and TSVs together form a first signal transmission structure, allowing the first semiconductor chip to transmit signals to the second semiconductor chip or control the second semiconductor chip via the first signal transmission structure. For example, adjacent second semiconductor chips can also be bonded to form a second signal transmission structure, allowing the first semiconductor chip to transmit signals to a second semiconductor chip located away from it.

[0117] The first signal transmission structure includes a first transmission structure and a second transmission structure, wherein either the first or second transmission structure is a backup transmission structure. For example, the second transmission structure can be a backup transmission structure of the first transmission structure. When the first signal transmission structure is defective or fails, the second transmission structure is used for signal transmission. The two outputs of the first selection circuit are coupled to the first and second transmission structures respectively. The first selection circuit can transmit the signal to one of the first and second transmission structures based on the status information of the first signal transmission structure stored in the first programming device. For example, when the status information of the first signal transmission structure indicates that the first signal transmission structure is valid and not occupied, the first selection circuit transmits the signal to the first transmission structure, i.e., it selects the original first transmission structure for signal transmission. When the status information of the first signal transmission structure indicates that the first signal transmission structure is defective or occupied, the first selection circuit transmits the signal to the second transmission structure, i.e., it activates the backup transmission structure to transmit the signal that should have been transmitted by the first signal transmission structure.

[0118] In the chip stacking structure fabrication method provided in this embodiment, by setting multiple first control circuits and first selection circuits arranged in an array in the first semiconductor chip, the area around the first signal output structure is fully utilized, reducing the area ratio of the repair circuit composed of the first control circuit and the first selection circuit on the first semiconductor chip, thereby reducing chip cost; at the same time, at the moment of power-on during the initialization phase of chip use, the first selection circuit can read the state information of the first transmission structure stored in the first control circuit, shortening the transmission path of the state information of the first transmission structure and reducing the time of the initialization process, thereby reducing the complexity of the repair operation.

[0119] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0120] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure.

[0121] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0122] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0123] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0124] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0125] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A chip stacking structure, characterized in that, include: A first semiconductor chip, a second semiconductor chip, a signal transmission structure connecting the first semiconductor chip and the second semiconductor chip, a first control circuit and a first selection circuit disposed on the first semiconductor chip; The signal transmission structure includes a first transmission structure and a second transmission structure, both of which include through-silicon vias disposed in the second semiconductor chip. The first control circuit includes a first programming device, which is a one-time programmable device. The first programming device is configured to store the state information of the first transmission structure. The first control circuit is coupled to the control terminal of the first selection circuit. The two output terminals of the first selection circuit are respectively coupled to the first transmission structure and the second transmission structure. The first selection circuit is configured to transmit a signal to one of the first transmission structure and the second transmission structure according to the state information stored in the first programming device. The first control circuit also includes a status information transmission sub-circuit and an induction amplifier sub-circuit; The status information transmission sub-circuit is coupled to the first programming device, and the status information transmission sub-circuit is configured to transmit the status information stored in the first programming device to the inductive amplification sub-circuit. The sensing amplification subcircuit is coupled to the state information transmission subcircuit. The sensing amplification subcircuit is configured to sense the state information and output the control signal corresponding to the state information to the first selection circuit.

2. The chip stacking structure according to claim 1, characterized in that, The chip stacking structure further includes: a second control circuit and a second selection circuit disposed on the second semiconductor chip; The second control circuit includes a second programming device, which is a one-time programmable device. The second programming device is configured to store the state information of the first transmission structure. The second control circuit is coupled to the control terminal of the second selection circuit. The two input terminals of the second selection circuit are respectively coupled to the first transmission structure and the second transmission structure. The second selection circuit is configured to output the signal on one of the first transmission structure and the second transmission structure according to the state information stored in the second programming device.

3. The chip stacking structure according to claim 1, characterized in that, The chip stacking structure further includes: a third transmission structure connecting the first semiconductor chip and the second semiconductor chip, and a second selection circuit disposed on the second semiconductor chip; The third transmission structure is configured to couple the first control circuit to the control terminal of the second selection circuit; The two input terminals of the second selection circuit are respectively coupled to the first transmission structure and the second transmission structure. The second selection circuit is configured to output the signal on one of the first transmission structure and the second transmission structure according to the state information stored in the first programming device.

4. The chip stacking structure according to any one of claims 1-3, characterized in that, The status information of the first transmission structure includes one of a first status information and a second status information, wherein the first status information indicates that the first transmission structure is valid and not occupied, and the second status information indicates that the first transmission structure is invalid or occupied.

5. The chip stacking structure according to any one of claims 1-3, characterized in that, The one-time programmable device includes one of a fuse device and an antifuse device.

6. The chip stacking structure according to any one of claims 1-3, characterized in that, The first control circuit further includes a programming control sub-circuit, which is coupled to the status information transmission sub-circuit and is configured to jointly control the programming operation of the first programming device with the status information transmission sub-circuit.

7. The chip stacking structure according to claim 6, characterized in that, The status information transmission sub-circuit includes a first transistor; a first terminal of the first transistor is coupled to a second terminal of the first programming device, the second terminal of the first transistor is coupled to a first node, and a first terminal of the first programming device is coupled to a read / write signal terminal, which is configured to provide a read signal or a programming signal.

8. The chip stacking structure according to claim 7, characterized in that, The inductive amplifier sub-circuit includes a second transistor, a third transistor, and a latch; The first terminal of the second transistor is coupled to the first node, and the second terminal of the second transistor is coupled to the second node. The first terminal of the third transistor is coupled to the first power supply terminal, and the second terminal of the third transistor is coupled to the second node. The input terminal of the latch is coupled to the second node, and the output terminal of the latch serves as the output terminal of the first control circuit.

9. The chip stacking structure according to claim 7, characterized in that, The programming control sub-circuit includes a fourth transistor; the first terminal of the fourth transistor is coupled to the first node, and the second terminal of the fourth transistor is coupled to a second power supply terminal.

10. The chip stacking structure according to claim 7, characterized in that, The voltage of the read signal is zero.

11. The chip stacking structure according to claim 2, characterized in that, The structure of the second control circuit is the same as that of the first control circuit.

12. The chip stacking structure according to claim 2 or 3, characterized in that, The first transmission structure further includes a first contact pad disposed on the first semiconductor chip and a second contact pad disposed on the second semiconductor chip, wherein the first contact pad and the second contact pad are electrically connected. The second transmission structure further includes a third contact pad disposed on the first semiconductor chip and a fourth contact pad disposed on the second semiconductor chip, wherein the third contact pad and the fourth contact pad are electrically connected. The two output terminals of the first selection circuit are coupled to the first contact pad and the third contact pad, respectively, and the two input terminals of the second selection circuit are coupled to the second contact pad and the fourth contact pad, respectively.

13. The chip stacking structure according to claim 3, characterized in that, The third transmission structure includes a through-silicon via (TSV) disposed on the second semiconductor chip, wherein the planar dimension of the TSV in the third transmission structure is larger than the planar dimension of the TSV in either the first transmission structure or the second transmission structure.

14. The chip stacking structure according to claim 13, characterized in that, The third transmission structure further includes a fifth contact pad disposed on the first semiconductor chip and a sixth contact pad disposed on the second semiconductor chip; the first control circuit is coupled to the fifth contact pad, and the control terminal of the second selection circuit is coupled to the sixth contact pad.

15. A method for fabricating a chip stacking structure, characterized in that, include: A first semiconductor chip is provided, the first semiconductor chip including a first control circuit and a first selection circuit; A second semiconductor chip is provided, the second semiconductor chip including a through-silicon via; The second semiconductor chip is bonded to the first semiconductor chip to form a signal transmission structure; The signal transmission structure includes a first transmission structure and a second transmission structure, both of which include through-silicon vias disposed in the second semiconductor chip. The first control circuit includes a first programming device, which is a one-time programmable device. The first programming device is configured to store the state information of the first transmission structure. The first control circuit is coupled to the control terminal of the first selection circuit. The two output terminals of the first selection circuit are respectively coupled to the first transmission structure and the second transmission structure. The first selection circuit is configured to transmit a signal to one of the first transmission structure and the second transmission structure according to the state information stored in the first programming device. The first control circuit also includes a status information transmission sub-circuit and an induction amplifier sub-circuit; The status information transmission sub-circuit is coupled to the first programming device, and the status information transmission sub-circuit is configured to transmit the status information stored in the first programming device to the inductive amplification sub-circuit. The sensing amplification subcircuit is coupled to the state information transmission subcircuit. The sensing amplification subcircuit is configured to sense the state information and output the control signal corresponding to the state information to the first selection circuit.

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