A method for optimizing LDPC T1 codes for spaceborne ASIC chip development
By optimizing the RAM call logic in the spaceborne ASIC chip and replacing the 512b RAM cell with a 64b RAM, the problem of wasted LDPC T1 code encoding resources was solved, achieving low-power and high-reliability LDPC T1 code encoding, which is suitable for spaceborne ASIC chips.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIAN INSTITUE OF SPACE RADIO TECH
- Filing Date
- 2023-12-25
- Publication Date
- 2026-07-17
Smart Images
Figure CN117856865B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to an LDPC T1 code encoding resource optimization method suitable for spaceborne ASIC chip development, belonging to the field of satellite data processing and transmission technology. Background Technology
[0002] In satellite terminal equipment, channel coding is an indispensable and extremely important component of the entire system. Among them, low-density parity-check (LDPC) coding technology has a coding gain that is very close to the theoretical limit. Furthermore, the coding gain of LDPC T1 code is as high as 9dB or more in 8psk. LDPC T1 code coding technology can effectively solve the problem of limited satellite downlink transmission power.
[0003] Currently, the main technical implementation of LDPC T1 code encoding is FPGA-based. Data caching and parity calculation for LDPC T1 code encoding often use RAM, which means that the data to be encoded is cached sequentially into multiple RAMs. Then, based on the read and write addresses calculated from the parity matrix, read and write operations are performed on the data in the multiple RAMs. Finally, the encoded parity bits are obtained by performing relevant operations on the read data.
[0004] Hardware implementations of LDPC T1 codes often require hundreds or even thousands of RAM units; however, as Figure 2 As shown, traditional FPGA-based LDPC implementations repeatedly call 512b RAM cells from the 65nm IP library. Although the actual cache size required each time is much smaller than 512b, each call still utilizes a 512b RAM cell. This implementation severely wastes RAM hardware resources and significantly increases system power consumption. The traditional implementation uses 8-bit input data and 1-bit output data for each RAM cell. A write operation is performed on one RAM cell per clock cycle, while the read enable is disabled. After the write operation, the read enable is enabled, and several read operations are performed based on the read address information generated by the RAM read / write control module. This method of reading and writing RAM cells is logically simple but over-utilizes RAM resources, resulting in severe resource waste, increased chip area, and increased difficulty in back-end layout and routing, as well as low-power design. It also increases the number of single-event faults (SIF) on the ASIC chip, thus increasing the risk of SIF on the spaceborne ASIC chip.
[0005] Spaceborne systems often have extremely stringent requirements for device power consumption and radiation resistance, making traditional LDPC T1 hardware implementations unsuitable for spaceborne applications. Therefore, it is necessary to optimize the relevant logic of the LDPC hardware implementation to achieve low power consumption and high reliability. Summary of the Invention
[0006] The technical problem solved by this invention is to overcome the shortcomings of the prior art and provide an LDPC T1 code encoding resource optimization method suitable for spaceborne ASIC chip development.
[0007] The technical solution of this invention is:
[0008] This invention discloses an LDPC T1 code encoding resource optimization system suitable for spaceborne ASIC chip development, comprising: a data receiving module, a RAM read / write control module, a RAM module, a RAM recall module, and a framing module; wherein,
[0009] The data receiving module splits the input data to be encoded into bytes and then passes it to the RAM call module.
[0010] The read address signal of the RAM read / write control module is connected to the RAM call module, and the write address and read / write enable signals of the RAM read / write control module are connected to the RAM module.
[0011] The output data signal and read address signal of the RAM call module are connected to the RAM module and are responsible for writing the output data of the data receiving module into different RAM modules bit by bit according to the read address;
[0012] The RAM module is used to store the data to be encoded after it has been processed by the data receiving module;
[0013] The framing module formats the data read from RAM and then outputs it.
[0014] Furthermore, in the above resource optimization system, the RAM module is composed of internal registers of the ASIC chip, and the capacity of the RAM module is LENGTH; LENGTH≥64bit.
[0015] Furthermore, in the above resource optimization system, the RAM read / write control module generates read address rd_addr, write address wr_addr, read enable rd_en, and write enable wr_en signals for the RAM module based on the LDPC T1 code rate, code length, or specified information sequence. When writing data to the RAM module, read operations on the RAM module are prohibited.
[0016] Furthermore, in the above resource optimization system, the read address of the RAM module is rd_addr = [(i + M * j) * 9 + 9], where i is i = 0, 1...M-1, j is 0, 2...7; M ≥ 25.
[0017] Furthermore, in the above resource optimization system, the RAM calling module calls the RAM module of the LENGTH bit according to the current state, and the input and output data bit widths are both 1 bit; the RAM module is written according to the write address signal wr_addr generated by the RAM read and write control module, and the RAM module read data rd_data[i+M*j] has a bit width of M*8 bits; M≥25.
[0018] This invention discloses an LDPC T1 code encoding resource optimization method suitable for spaceborne ASIC chip development, comprising:
[0019] Step 1: The data receiving module splits the input data to be encoded into bytes and outputs it to the RAM call module. The RAM read / write control module generates the read / write address and read / write enable signal for the RAM module according to the LDPC T1 code encoding requirements.
[0020] Step 2: The RAM calling module writes the input data datin1 bit by bit into M*8 different RAMs, with each group of 8 bits writing M times in total, and repeats this process; M≥25;
[0021] Step 3: When reading data, the M*9-bit address information of the read address is judged, and different RAMs are selected sequentially for reading operations, for a total of M reads; the framing module formats the read data according to the read address and outputs the calculated data with an M*8-bit width.
[0022] Furthermore, in the above resource optimization method, the RAM calling module writes the input data datin1 into M*8 different RAMs bit by bit. Specifically, the RAM calling module writes the input data datin1[0] into RAM[0+M*i], datin[1] into RAM[1+M*i], and so on, datin1[7] into RAM[7+M*i]; where i=0,1...M-1, M≥25.
[0023] Furthermore, in the above resource optimization method, the framing module formats the read data according to the read address and outputs calculated data with a width of M*8 bits, specifically as follows:
[0024] The framing module sorts the read data from RAM[i+M*j] according to the read address information, where M≥25;
[0025] If rd_addr[(0+M*j)*9+2:(0+M*j)*9] = "000", then assign the value of rd_data[i+M*j] to data[0+M*j].
[0026] If rd_addr[(1+M*j)*9+2:(1+M*j)*9] = "001", then assign the value of rd_data[i+M*j] to data[1+M*j].
[0027] Similarly, when rd_addr[(7+M*j)*9+2:(7+M*j)*9] = "000", the value of rd_data[i+M*j] is assigned to data[7+M*j]; where i = 0, 1...M-1; j = 0, 1...7, and M ≥ 25.
[0028] The advantages of this invention compared to existing technical solutions are as follows:
[0029] (1) This invention discloses a method for optimizing LDPC T1 code encoding resources based on a relay terminal onboard ASIC chip. By optimizing the calling logic, the RAM resources used by the LDPC T1 code are reduced from the original 200x512b to 200x64b. This method significantly reduces RAM resource utilization and greatly reduces chip power consumption.
[0030] (2) This invention discloses a method for optimizing the encoding resources of LDPC T1 code based on the relay terminal spaceborne ASIC chip. The original IP in the 65nm library is replaced by building RAM through registers, thus avoiding the waste of the entire board resources caused by directly calling RAM.
[0031] (3) This invention discloses an optimization method for LDPC T1 code encoding resources based on a relay terminal onboard ASIC chip. The optimization algorithm is easy to implement on the ASIC and will not increase other soft core or hard core resources, which is beneficial to reducing the area of the ASIC chip.
[0032] (4) Under the 65nm ten-layer metal silicon gate CMOS process, the data throughput of this invention can reach 1.5Gbps at 187.5M clock. Compared with conventional algorithms, the area of the on-board ASIC chip is reduced by 23%, the power consumption is reduced by about 300mw, the difficulty of single-particle target and back-end layout and wiring is reduced, thereby increasing the anti-single-particle performance of the ASIC chip. Attached Figure Description
[0033] Figure 1 This is a block diagram of the method of the present invention;
[0034] Figure 2 It is the traditional scheme of LDPC T1 code encoding. Detailed Implementation
[0035] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0036] like Figure 1 As shown, this invention discloses an LDPC T1 code encoding resource optimization system suitable for spaceborne ASIC chip development, comprising: a data receiving module, a RAM read / write control module, a RAM module, a RAM recall module, and a framing module; wherein,
[0037] The data receiving module splits the input data to be encoded into bytes and then passes it to the RAM call module.
[0038] The read address signal of the RAM read / write control module is connected to the RAM call module, and the write address and read / write enable signals of the RAM read / write control module are connected to the RAM module.
[0039] The output data signal and read address signal of the RAM call module are connected to the RAM module and are responsible for writing the output data of the data receiving module into different RAM modules bit by bit according to the read address;
[0040] The RAM module is used to store the data to be encoded after it has been processed by the data receiving module;
[0041] The framing module formats the data read from RAM and then outputs it.
[0042] Preferably, the RAM module consists of internal registers of the ASIC chip, and the capacity of the RAM module is LENGTH; LENGTH ≥ 64 bits.
[0043] Preferably, the RAM read / write control module generates read address rd_addr, write address wr_addr, read enable rd_en, and write enable wr_en signals for the RAM module based on the LDPC T1 code rate, code length, or specified information sequence. When writing data to the RAM module, read operations of the RAM module are prohibited.
[0044] Preferably, the read address of the RAM module is rd_addr = [(i+M*j)*9+9], where i is i = 0, 1...M-1, j is 0, 2...7, and M ≥ 25.
[0045] Preferably, the RAM calling module calls the RAM module of the LENGTH bit according to the current state, and the input and output data bit widths are both 1 bit; the RAM module is written according to the write address signal wr_addr generated by the RAM read and write control module, and the RAM module read data rd_data[i+M*j] has a bit width of M*8 bits; M≥25.
[0046] This invention discloses an LDPC T1 code encoding resource optimization method suitable for spaceborne ASIC chip development, comprising:
[0047] Step 1: The data receiving module splits the input data to be encoded into bytes and outputs it to the RAM call module. The RAM read / write control module generates the read / write address and read / write enable signal for the RAM module according to the LDPC T1 code encoding requirements.
[0048] Step 2: The RAM calling module writes the input data datin1 bit by bit into M*8 different RAMs, with each group of 8 bits writing M times in total, and repeats this process; M≥25;
[0049] Step 3: When reading data, the M*9-bit address information of the read address is judged, and different RAMs are selected sequentially for reading operations, for a total of M reads; the framing module formats the read data according to the read address and outputs the calculated data with an M*8-bit width.
[0050] Preferably, the RAM calling module writes the input data datin1 into M*8 different RAMs bit by bit. Specifically, the RAM calling module writes the input data datin1[0] into RAM[0+M*i], datin[1] into RAM[1+M*i], and so on, datin1[7] into RAM[7+M*i]; where i=0,1...M-1, M≥25.
[0051] Preferably, the framing module formats the read data according to the read address and outputs calculated data with a width of M*8 bits, specifically:
[0052] The framing module sorts the read data from RAM[i+M*j] according to the read address information, where M≥25;
[0053] If rd_addr[(0+M*j)*9+2:(0+M*j)*9] = "000", then assign the value of rd_data[i+M*j] to data[0+M*j].
[0054] If rd_addr[(1+M*j)*9+2:(1+M*j)*9] = "001", then assign the value of rd_data[i+M*j] to data[1+M*j].
[0055] Similarly, when rd_addr[(7+M*j)*9+2:(7+M*j)*9] = "000", the value of rd_data[i+M*j] is assigned to data[7+M*j]; where i = 0, 1...M-1; j = 0, 1...7, and M ≥ 25.
[0056] Example
[0057] The basic principle of this invention is that, compared with the traditional FPGA implementation, the spaceborne ASIC technology approach allows for customization of the minimum capacity of the basic memory RAM cell. Specifically, it replaces the original 512b basic memory RAM cell IP in the 65nm library with a 64b RAM built using registers. Furthermore, it optimizes the logical calling relationship of the 64b memory RAM cell and implements a low-power design, thereby reducing the hardware resource overhead of the hundreds or even thousands of memory RAM cells used multiple times in the hardware implementation of LDPC T1 code. This reduces system power consumption. While ensuring the encoding function, it reduces the resource area of the spaceborne ASIC chip, lowers the difficulty of the ASIC chip back-end layout and routing design, and reduces the single-event flip risk of the spaceborne ASIC chip.
[0058] Furthermore, such as Figure 1 An LDPC T1 code encoding resource optimization system for a relay terminal onboard ASIC chip includes: a RAM read / write control module, a RAM call module, a framing module, and a data receiving module. The RAM is used to store the data to be encoded after processing by the receiving module. The RAM read / write control module generates read / write addresses and read / write enable signals for the RAM based on the required code rate (or code length, specified information sequence combination) of the LDPC T1 code, such as (15360, 7680), (15360, 10240), or (15360, 12800). The RAM call module calls the instantiated RAM according to the current state; the RAM size is 64 bits, and the input and output data bit widths are both 1 bit. The framing module formats the data output from the RAM.
[0059] like Figure 1 In this embodiment, the LDPC T1 code encoding resource optimization method based on the relay terminal's onboard ASIC chip includes: reasonably splitting the byte data processed by the data receiving module, writing it bit by bit into 200 different RAMs, grouping them into sets of 8, writing them 25 times in a loop; when reading data, judging the 1800-bit wide address information of the read address, sequentially selecting different RAMs for reading operations, reading 25 times in total; the framing module formats the read data according to the read address, and finally outputs 200-bit wide calculated data. Further, the specific implementation method is as follows:
[0060] The RAM read / write control module receives the data to be encoded after processing by the receiving module according to the coding rate requirements of each LDPC T1 code. Through continuous internal counting and in combination with the T1 code rate, it dynamically generates the RAM write address signal, write enable signal, read address signal, and read enable signal.
[0061] The RAM read / write control module generates an 1800-bit wide read address signal, denoted as rd_addr[(i+25*j)*9+9], and a 6-bit wide write address signal. When writing data to the RAM, read operations are disabled. i = 0, 1...24; j = 0, 2...7.
[0062] The RAM access module calls a 64-bit RAM. It directly writes to the RAM based on the write address signal generated by the RAM read / write control module. The write data width is 8 bits, denoted as datin[k]. Subsequent algorithms require a read data width of 200 bits, denoted as data[i+25*j]. Therefore, it calls eight 64-bit RAMs a total of 25 times, denoted as RAM[i+25*j]. The RAM read address is rd_addr_r[(i+25*j]*6+6)], and the RAM read data is rd_data[i+25*j]. Where i = 0, 1...24; j = 0, 1...7; k = 0, 1...7.
[0063] The RAM calling module writes the input data datin[0] into RAM[0+25*i], datin[1] into the second RAM[1+25*i], and so on, with datin[7] into the eighth RAM[7+25*i]; where i = 0, 1...24.
[0064] When rd_addr[(i+25*j)*9+2:(i+25*j)*9] = "000", the RAM calling module assigns the value of rd_addr[(i+25*j)*9+8:(i+25*j)*9] to the RAM read address rd_addr_r[(0+25*j]*6+5):(0+25*j]*6)]; when rd_addr[(i+25*j)*9+2:(i+25*j)*9] = "001", the RAM calling module assigns the value of rd_addr[(i+25*j)*9+8:(i+25*j]*9+2 ... The value of rd_addr[(1+25*j)*9+2:(1+25*j)*6)] is assigned to the RAM read address rd_addr_r[(1+25*j)*9+2:(i+25*j)*9]; and so on. When rd_addr[(i+25*j)*9+2:(i+25*j)*9] = "111", the RAM calling module assigns the value of rd_addr[(i+25*j)*9+8:(i+25*j)*9] to the RAM read address rd_addr_r[(7+25*j)*6+5:(7+25*j)*6)], i = 0,1...24; j = 0,1...7.
[0065] The framing module sorts the read data from RAM[i+25*j] according to the read address information. When rd_addr[(0+25*j)*9+2:(0+25*j)*9] = "000", the value of rd_data[i+25*j] is assigned to data[0+25*j]; when rd_addr[(1+25*j)*9+2:(1+25*j)*9] = "001", the value of rd_data[i+25*j] is assigned to data[1+25*j]; and so on. When rd_addr[(7+25*j)*9+2:(7+25*j)*9] = "000", the value of rd_data[i+25*j] is assigned to data[7+25*j]; where i = 0, 1...24; j = 0, 1...7.
[0066] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.
[0067] The contents not described in detail in this specification are common knowledge to those skilled in the art.
Claims
1. An LDPC T1 code encoding resource optimization system suitable for spaceborne ASIC chip development, characterized in that, include: The system comprises a data receiving module, a RAM read / write control module, a RAM module, a RAM recall module, and a framing module; among which, The data receiving module splits the input data to be encoded into bytes and then passes it to the RAM call module. The read address signal of the RAM read / write control module is connected to the RAM call module, and the write address and read / write enable signals of the RAM read / write control module are connected to the RAM module. The output data signal and read address signal of the RAM call module are connected to the RAM module and are responsible for writing the output data of the data receiving module into the RAM bit by bit according to the read address. In 8 different RAMs, 8 are grouped together and written M times in a cycle; M=25. The RAM module is used to store the data to be encoded after it has been processed by the data receiving module; When reading data, by adjusting the M value at the read address. The 9-bit address information is used for judgment, and different RAMs are selected sequentially for reading operations, for a total of M reads; The framing module formats the data read from RAM and then outputs it. The RAM module consists of internal registers of the ASIC chip, and the capacity of the RAM module is LENGTH; LENGTH = 64 bits; The read address of the RAM module is rd_addr = [(i+M j) [9+9], where i is i=0,1...M-1, and j is 0,1...7; The RAM calling module calls the RAM module of the LENGTH bit according to the current state, with both input and output data having a bit width of 1 bit; it performs write operations on the RAM module according to the write address signal wr_addr generated by the RAM read / write control module, and reads data rd_data[i+M] from the RAM module. j] Bit width is M 8 digits.
2. The LDPC T1 code encoding resource optimization system for spaceborne ASIC chip development according to claim 1, characterized in that: The RAM read / write control module generates read address rd_addr, write address wr_addr, read enable rd_en, and write enable wr_en signals for the RAM module based on the LDPC T1 code rate, code length, or a specified information sequence. When writing data to the RAM module, read operations on the RAM module are prohibited.
3. A method for optimizing LDPC T1 code encoding resources suitable for spaceborne ASIC chip development, characterized in that, include: The data receiving module splits the input data to be encoded into bytes and outputs it to the RAM call module. The RAM read / write control module generates read / write addresses and enable signals for the RAM module according to the LDPC T1 code encoding requirements. The RAM module then reads the data rd_data[i+M]. j] Bit width is M 8 bits; The RAM call module writes the input data datin1 to M bit by bit. In 8 different RAMs, 8 are grouped together and written M times in a cycle; M=25. When reading data, by adjusting the M value at the read address. The system uses a 9-bit address to determine which RAMs to read from, performing M reads in total. The framing module then formats the read data according to the address and outputs M... Calculated data with an 8-bit width; The RAM call module writes the input data datin1 into M bit by bit. In 8 different RAMs, specifically: the RAM calling module writes the input data datin1[0] into RAM[0+M i], datin1[1] writes the RAM[1+M]th RAM[1+M] i], and so on, datin1[7] is written into RAM[7+M i]; where i=0,1...M-1; The framing module formats the read data according to the read address rd_addr and outputs M. The calculation data for an 8-bit width is as follows: The framing module reads the RAM[i+M] based on the address information. Sort the data read from j]. If rd_addr[(0+M)] j) 9+2: (0+M) j) When 9] = "000", rd_data[i+M The value of j] is assigned to data[0+M j]; If rd_addr[(1+M j) 9+2: (1+M) j) When 9] = "001", rd_data[i+M The value of j] is assigned to data[1+M j]; And so on, when rd_addr[(7+M)] j) 9+2: (7+M) j) When 9] = "000", rd_data[i+M The value of j] is assigned to data[7+M j];where i=0,1...M-1;j=0,1...7.