A sealing method based on titanium-silicon ohmic contact

Abstract

The application provides a sealing method based on titanium-silicon ohmic contact, comprising the following steps: S1, preparing a separated titanium adhesion layer (10) and a passivation protection layer (11) thereon on an intermediate silicon layer (1), and performing high-temperature alloying treatment; S2, preparing a silicon lead layer (8) on the intermediate silicon layer (1); the silicon lead layer (8) and the titanium adhesion layer (10) form ohmic contact; S3, aligning a vertical through hole of a cover layer (13) and the passivation protection layer (11) on the intermediate silicon layer (1), and performing eutectic bonding sealing packaging; S4, removing the passivation protection layer (11) above the titanium adhesion layer (10) through dry etching, depositing an aluminum film on the upper surface of the cover layer (13), and forming an aluminum electrode pad (18) on the cover layer (13) through photolithography and wet etching; the aluminum electrode pad (18) is conductive with the silicon lead layer (8). The high-temperature alloying ohmic contact of titanium is separated from the aluminum electrode pad deposition process, and the process quality is improved.

Description

Technical Field

[0001] This invention belongs to the field of MEMS device packaging technology, specifically relating to a sealing method based on titanium-silicon ohmic contacts. Background Technology

[0002] In the field of MEMS process technology, there is a problem of deteriorated packaging reliability when silicon wafers are prepared for dry etching to create silicon microstructures and hermetically sealed to lead out conductive signals, and then subjected to high-temperature alloying ohmic contact process after the electrode pads are deposited.

[0003] like Figure 1 After grinding, thinning, and double-sided polishing, the intermediate silicon layer 1 is bonded to the silicon device layer 2 of the Silicon on Insulator (SOI) wafer. Before bonding, the silicon device layer 2 is etched to form a silicon conduction band layer 3 for electrical signal output and anchor points 4 for mechanical support. The SOI wafer also includes a silicon support layer 6, an intermediate insulating layer 5 for isolating the device layer 2 and the silicon support layer 6, and a bottom insulating layer 7. Since after the formation of this silicon-silicon bonded wafer, a DRIE (Deep Reactive Ion Etching) dry etching process is required to fabricate movable silicon microstructures and silicon lead layers fixed on the silicon conduction band layer 3 on the intermediate silicon layer 1. At the same time, a cover plate layer 13 containing vertical vias 14 is required to connect the silicon lead layers on the intermediate silicon layer 1 to the outside environment. Therefore, establishing a reliable high-temperature alloyed ohmic contact method is crucial.

[0004] For the intermediate silicon layer 1 to be etched with silicon microstructure, there are currently two main methods for high-temperature alloying ohmic contacts: (i) depositing an aluminum film at the bottom of the vertical through-hole of the cover plate after eutectic bonding and annealing at high temperature, thereby forming a silicon-aluminum alloy ohmic contact at the silicon-aluminum interface; (ii) sputtering a titanium adhesive layer at the bottom of the vertical through-hole of the cover plate after eutectic bonding, depositing an aluminum electrode pad on it, and forming an ohmic contact after high-temperature annealing.

[0005] Method (I) has the following main disadvantages: Since the aluminum electrode pads are prepared only after the cover plate layer with vertical through holes is eutectic bonded and sealed with the intermediate silicon layer 1, and the high-temperature alloying temperature of aluminum exceeds the melting point of the gold-silicon binary system, there is a risk of gold-silicon eutectic liquid overflow during the high-temperature alloying process. This may cause crosstalk between the electrodes that should be isolated, and may also damage the original good bonding quality, which will have an adverse effect on the sealing performance of the device. Method (II) needs to solve the following problems: (1) After the cover plate layer with vertical through holes is eutectic bonded with the intermediate silicon layer 1, in order to ensure good device sealing performance, the high-temperature alloying process should be avoided at a temperature higher than the melting point of the gold-silicon binary system. When alloying is carried out at a temperature lower than the melting point of the gold-silicon binary system, it is difficult to form titanium silicide with good conductivity, that is, it is difficult to form good ohmic contact. (2) When carrying out the high-temperature alloying process of titanium, the exposed titanium surface is easy to oxidize and lose its activity, thereby affecting the conductivity between the silicon lead layer on the intermediate silicon layer 1 and the outside world. Summary of the Invention

[0006] This invention provides a sealing method based on titanium-silicon ohmic contacts, which separates the high-temperature alloyed titanium ohmic contacts from the aluminum electrode pad deposition process, thereby improving process quality.

[0007] This invention provides a sealing method based on titanium-silicon ohmic contact, comprising:

[0008] S1. A titanium layer is sputtered on the upper surface of the intermediate silicon layer 1, and an insulating layer is deposited on the titanium layer. A separate titanium adhesion layer 10 and a passivation protection layer 11 thereon are prepared on the intermediate silicon layer 1 by photolithography and wet etching. The titanium adhesion layer 10 is located above the silicon conduction layer 3 and is subjected to high-temperature alloying treatment. An ohmic contact is formed between the intermediate silicon layer 1 and the titanium adhesion layer 10.

[0009] S2. Photolithography and DRIE dry etching are performed on the intermediate silicon layer 1 to prepare a silicon lead layer 8 on the intermediate silicon layer 1. The silicon lead layer 8 is located above the silicon conduction layer 3 and below the titanium adhesion layer 10, and an ohmic contact is formed between the silicon lead layer 8 and the titanium adhesion layer 10.

[0010] S3. Align the vertical through-hole 14 of the cover plate layer 13 with the passivation protection layer 11 on the intermediate silicon layer 1, and perform eutectic bonding and sealing encapsulation.

[0011] S4. The passivation protective layer 11 above the titanium adhesion layer 10 is removed by dry etching. An aluminum film is deposited on the upper surface of the cover plate layer 13. An aluminum electrode pad 18 is formed on the cover plate layer 13 by photolithography and wet etching. The aluminum electrode pad 18 is connected to the silicon lead layer 8.

[0012] Optionally, the number of aluminum electrode pads 18 is the same as the number of titanium adhesive layers 10.

[0013] Optionally, the number of titanium adhesive layers 10 is the same as the number of silicon conductive layers 3.

[0014] Optionally, high-temperature alloying treatment may be performed, including:

[0015] High-temperature alloying treatment at 650℃ for one hour.

[0016] Optionally, the titanium layer thickness is 100 nm.

[0017] Optionally, the insulation layer thickness is 80nm.

[0018] Optionally, the insulating layer is silicon nitride.

[0019] Optionally, the aluminum film thickness is 3μm.

[0020] This invention provides a sealing method based on titanium-silicon ohmic contacts. Addressing the characteristics of silicon wafers with vertical vias and the sealing encapsulation process, this invention leverages the separability of the high-temperature alloying ohmic contacts of titanium and the deposition process of aluminum electrode pads. First, a titanium adhesion layer is prepared on the surface of the silicon lead layer to be etched in the intermediate silicon layer 1. A passivation protective layer is deposited on the titanium adhesion layer, followed by a high-temperature alloying process to ensure good ohmic contact between titanium and silicon. After eutectic bonding between the silicon wafer with vertical vias and the intermediate silicon layer 1, the passivation protective layer is dry-etched, and aluminum electrode pads are deposited on the alloyed titanium layer, achieving conductivity between the silicon lead layer on the intermediate silicon layer 1 and the outside environment. This invention not only avoids the damage to the gold-silicon eutectic bonding surface quality caused by high-temperature alloying after sealing encapsulation, but also protects the surface activity of titanium through the ingenious design of the passivation protective layer deposited on the titanium adhesion layer. This overcomes many limitations in extracting reliable electrical signals through electrode vias, greatly improving process quality. Attached Figure Description

[0021] Figure 1 A schematic diagram of a silicon-silicon bonded wafer to be etched and hermetically sealed.

[0022] Figure 2 A schematic diagram of titanium-silicon high-temperature alloyed ohmic contacts and etching out silicon microstructures;

[0023] Figure 3 This is a schematic diagram showing the completed hermetically sealed encapsulation and aluminum electrode pad fabrication.

[0024] Explanation of reference numerals in the attached figures:

[0025] 1-Intermediate silicon layer, 2-Silicon device layer, 3-Silicon conductor layer, 4-Anchor point, 5-Intermediate insulating layer, 6-Silicon support layer, 7-Bottom insulating layer, 8-Silicon lead layer, 9-Modible silicon structure, 10-Titanium adhesion layer, 11-Passivation protection layer, 12-Eutectic bonding interface, 13-Cap plate layer, 14-Vertical via, 15-Getter deposition chamber, 16-Getter layer, 17-Inverted trapezoidal slot structure, 18-Aluminum electrode pad. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] The features and illustrative embodiments of various aspects of the present invention will now be described in detail. Numerous specific details are set forth in the following detailed description to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without requiring some of these specific details. The following description of embodiments is merely intended to provide a better understanding of the invention by illustrating examples of the invention. The invention is by no means limited to any specific setups and methods set forth below, but covers any improvements, substitutions, and modifications to structures, methods, and devices without departing from the spirit of the invention. Well-known structures and techniques are not shown in the drawings and the following description to avoid unnecessarily obscuring the invention.

[0028] It should be noted that, unless otherwise specified, the embodiments of the present invention and the features thereof can be combined with each other, and the various embodiments can be referenced and cited in each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0029] This invention provides a sealing method based on titanium-silicon ohmic contact, such as... Figure 2-3 As shown, the sealing method based on titanium-silicon ohmic contact provided by the present invention can be applied to MEMS structures such as silicon micro accelerometers and silicon micro gyroscopes.

[0030] The MEMS device structure includes: an intermediate silicon layer 1 and an SOI wafer;

[0031] The SOI wafer includes: a silicon device layer 2, a silicon conductor layer 3, an anchor point 4, an intermediate insulating layer 5, a silicon support layer 6, and a bottom insulating layer 7.

[0032] Silicon device layer 2 on the lower surface of the SOI wafer with silicon-silicon bonding, intermediate silicon layer 1 on the upper surface of the silicon-silicon bonding, and gold-silicon bonding sealing cover layer 13.

[0033] The silicon conductor layer 3 in the silicon device layer 2 of the lower surface SOI wafer of silicon-silicon bonding is correspondingly bonded to the silicon lead layer 8 in the middle silicon layer 1 of the upper surface of silicon-silicon bonding. A titanium adhesive layer 10 is deposited on the upper end of each silicon lead layer 8, and an ohmic contact is formed by high-temperature annealing. A passivation protection layer 11 is covered on the upper end of the titanium adhesive layer. A vertical via 14 and a getter deposition chamber 15 are formed on one side of the cover plate layer 13 by dry etching. The vertical via 14 and the getter deposition chamber 15 are arranged on the left and right sides of the cover plate layer. The other side of the cover plate layer 13 opposite to the vertical via 14 is formed by anisotropic wet etching to create an inverted trapezoidal slot structure 17. After the passivation protection layer 11 at the bottom of the vertical via 14 is removed by dry etching, the silicon lead layer 8 is correspondingly connected to the aluminum electrode pad 18 on the upper surface of the cover plate layer 13 through the aluminum in the vertical via 14. The anchor point 4 in the silicon device layer 2 of the SOI wafer, which is used for mechanical support, is bonded to the silicon island in the intermediate silicon layer 1 that is not used as a silicon lead. Above the movable silicon structure 9 on the intermediate silicon layer 1 is the getter deposition chamber 15 of the cover layer 13, and the bottom of the getter deposition chamber 15 is deposited with a getter layer 16.

[0034] This invention provides a sealing method based on titanium-silicon ohmic contact, wherein titanium is sputtered onto the surface of the silicon lead layer 8 of the intermediate silicon layer 1 and alloyed at high temperature, and then the intermediate silicon layer 1 and the cover plate layer with vertical through holes are eutectic bonded and sealed, and then aluminum electrode pads are deposited on the alloyed titanium at the bottom of the vertical through holes.

[0035] As an improvement to this technical solution, a passivation protective layer is deposited on the sputtered titanium to ensure that the activity of titanium is not lost during high-temperature alloying. After sealing and encapsulation, the passivation protective layer needs to be etched before depositing aluminum electrode pads.

[0036] The high-temperature alloying ohmic contact method provided by this invention is for applications such as... Figure 1 The intermediate silicon layer 1 shown is fabricated on the silicon device layer 2 of the SOI wafer via silicon-silicon bonding. After mechanical thinning and chemical mechanical polishing (CMP), the thickness of the intermediate silicon layer 1 is 100 μm. The SOI wafer includes a silicon conduction layer 3, anchor points 4, an intermediate insulating layer 5, a silicon support layer 6, and a bottom insulating layer 7.

[0037] like Figure 2 The microstructure processing and high-temperature alloying of the intermediate silicon layer 1 consist of two steps:

[0038] The first step is to sputter a titanium layer with a thickness of 100 nm on the surface of the intermediate silicon layer 1, and then deposit an insulating layer with a thickness of 80 nm on the titanium layer. Separate titanium adhesion layer 10 and passivation protection layer 11 are prepared on the intermediate silicon layer 1 by photolithography and wet etching for the extraction of multiple separate electrical signals. Then, the layers are subjected to high-temperature alloying treatment at 650°C for one hour.

[0039] The second step involves photolithography and DRIE dry etching on the intermediate silicon layer 1, which was prepared in the first step with titanium adhesion layer 10 and passivation protection layer 11, to obtain silicon lead layer 8 and movable silicon structure 9. At this point, the silicon lead layer 8 on the intermediate silicon layer 1, supported by silicon conduction layer 3, forms an ohmic contact with the titanium adhesion layer 10 after a high-temperature alloying process. This contact can then be achieved by leading the silicon lead layer 8 out through vertical vias, enabling conductivity between the silicon lead layer 8 and the outside world. After the high-temperature alloying process, the surface of the titanium adhesion layer 10 remains active due to the protection of the passivation protection layer 11, ensuring good electrical conductivity when subsequently bonded to other metals.

[0040] like Figure 3 In order to perform eutectic bonding and sealing of the intermediate silicon layer 1 with the movable silicon structure 9, the cover layer 13 to be bonded needs to be prepared first:

[0041] First, a vertical through-hole 14 with a depth of 150 μm and a diameter of 120 μm and a getter deposition chamber 15 are fabricated on one side of a double-sided polished silicon wafer using DRIE.

[0042] Second, an inverted trapezoidal groove structure with a height of 150 μm was prepared on the other side of the double-sided polished silicon wafer by back-aligned exposure and KOH anisotropic etching.

[0043] Third, after forming a surface insulating layer on the double-sided polished silicon wafer through a high-temperature oxidation diffusion process, a chromium layer and a gold layer are deposited sequentially on one side of the vertical through-hole 14, and the gold bonding surface is defined by wet etching of the chromium layer and the gold layer.

[0044] Finally, a getter layer 16 is deposited in the getter deposition chamber 15 to obtain a capping layer 13 that can be used for eutectic bonding.

[0045] By aligning the vertical through-hole 14 on the gold bonding surface of the cover plate layer 13 with the passivation protection layer 11 of the intermediate silicon layer 1, and then performing eutectic bonding and sealing at a temperature slightly higher than the gold-silicon eutectic point, the getter layer 16 is activated during bonding, thus forming a eutectic bonding interface 12 with good sealing performance.

[0046] The passivation protective layer 11 above the titanium adhesion layer 10 is removed by dry etching, and an aluminum film is deposited on the upper surface of the cover layer 13. The final aluminum electrode pad 18 is obtained by photolithography and wet etching. Since the surface of the titanium adhesion layer 10 remains active before the passivation protective layer 11 is etched away, an electrical connection is formed between the silicon lead layer 8 and the outside world through the titanium adhesion layer 10 and the aluminum electrode pad 18 after the final aluminum electrode pad 18 is formed.

[0047] Therefore, the method of preparing the titanium adhesion layer 10 and the aluminum electrode pads 18 in steps in this invention solves two major problems in forming ohmic contacts through high-temperature alloying after eutectic bonding and sealing: First, by setting the high-temperature alloying process of titanium silicon before gold silicon eutectic bonding and sealing, the influence of the high-temperature alloying process on the reliability of eutectic bonding after sealing and sealing is avoided; Second, by depositing a passivation protective layer 11 on the titanium adhesion layer 10, the surface activity of titanium is not affected after high-temperature alloying. After eutectic bonding and sealing and sealing, the passivation protective layer is etched and aluminum electrode pads are deposited on the titanium adhesion layer 10, thus providing a process basis for forming electrical conductivity with the outside world. The application of this process achieves the following objectives: after eutectic bonding and sealing and sealing the intermediate silicon layer with movable silicon structure and the cover plate layer with vertical through holes, the contradiction between achieving good ohmic contact and reliable eutectic bonding simultaneously is solved, avoiding problems such as decreased hermeticity of the package and crosstalk between isolated electrodes, greatly improving the process quality.

Claims

1. A sealing method based on titanium-silicon ohmic contact, characterized in that, include: S1. A titanium layer is sputtered on the upper surface of the intermediate silicon layer (1), and an insulating layer is deposited on the titanium layer. A separate titanium adhesion layer (10) and a passivation protection layer (11) thereon are prepared on the intermediate silicon layer (1) by photolithography and wet etching. The titanium adhesion layer (10) is located above the silicon conduction band layer (3) and is subjected to high temperature alloying treatment. An ohmic contact is formed between the intermediate silicon layer (1) and the titanium adhesion layer (10). S2. Photolithography and DRIE dry etching are performed on the intermediate silicon layer (1) to prepare a silicon lead layer (8) on the intermediate silicon layer (1). The silicon lead layer (8) is located above the silicon conduction layer (3) and below the titanium adhesion layer (10). An ohmic contact is formed between the silicon lead layer (8) and the titanium adhesion layer (10). S3. Align the vertical through-hole (14) of the cover plate layer (13) and the passivation protection layer (11) on the intermediate silicon layer (1) and perform eutectic bonding sealing encapsulation. S4. The passivation protection layer (11) above the titanium adhesion layer (10) is removed by dry etching. An aluminum film is deposited on the upper surface of the cover plate layer (13). An aluminum electrode pad (18) is formed on the cover plate layer (13) by photolithography and wet etching. The aluminum electrode pad (18) is connected to the silicon lead layer (8).

2. The sealing method based on titanium-silicon ohmic contact according to claim 1, characterized in that, The number of aluminum electrode pads (18) is the same as the number of titanium adhesive layers (10).

3. The sealing method based on titanium-silicon ohmic contact according to claim 1, characterized in that, The number of titanium adhesive layers (10) is the same as the number of silicon conductive layers (3).

4. The sealing method based on titanium-silicon ohmic contact according to claim 1, characterized in that, High-temperature alloying treatment is performed, including: High-temperature alloying treatment at 650℃ for one hour.

5. The sealing method based on titanium-silicon ohmic contact according to claim 1, characterized in that, The titanium layer is 100 nm thick.

6. The sealing method based on titanium-silicon ohmic contact according to claim 1, characterized in that, The insulation layer is 80nm thick.

7. The sealing method based on titanium-silicon ohmic contact according to claim 1, characterized in that, The insulating layer is silicon nitride.

8. The sealing method based on titanium-silicon ohmic contact according to claim 1, characterized in that, The aluminum film thickness is 3μm.

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