Adaptive working condition high-speed electromagnetic valve driving circuit and method

Abstract

The application provides a self-adaptive working condition high-speed electromagnetic valve driving circuit and method, which comprises a first D flip-flop, a second D flip-flop, an OR gate circuit, an AND gate circuit, a self-oscillation circuit, a first voltage comparison circuit, a second voltage comparison circuit, a current differential circuit, a high-side driver, a high-side switch and a current sensor. The application generates a current driving waveform satisfying a high-speed electromagnetic valve through an operational amplifier, a voltage comparator, a conventional logic gate circuit and separated components such as a resistor-capacitor and a field effect transistor, does not need to boost the driving voltage, has a simple principle, does not need a complex hardware and MCU processor, is easy to use and has a low hardware cost.

Description

Technical Field

[0001] This invention relates to the field of high-speed solenoid valve control technology, specifically to a high-speed solenoid valve drive circuit and method that adapts to different operating conditions. Background Technology

[0002] As the core control element of digital flow technology, the high-speed solenoid valve operates only in the fully open or fully closed state under electromagnetic excitation. It has the advantages of no structural dead zone, no leakage, and strong anti-pollution ability, and has been successfully applied in key technology fields such as aero-engine fuel systems and braking systems.

[0003] Traditional high-speed solenoid valves typically employ conventional PWM control, which opens the valve by applying a positive voltage and closes it by applying zero voltage. This inevitably leads to excessive coil current and increased energy consumption during the fully open phase. Furthermore, when zero voltage is applied, the high-speed solenoid valve's inherent inductive characteristics and mechanical inertia prevent the drive current from being released quickly enough to effectively close the valve, resulting in insufficient response speed and limiting its ability to operate fully open and closed at high frequencies. To ensure rapid opening of the solenoid valve while reducing energy consumption and to compensate for the shortcomings of conventional PWM control, existing technologies have proposed a Peak & Hold current-driven method for high-speed solenoid valves. However, this method currently has some shortcomings or limitations, as detailed below:

[0004] (1) For example, patent CN 110206651B discloses a peak / hold current driving circuit. This driving circuit uses a boost topology to enable high voltage excitation during the high-speed solenoid valve opening phase and low voltage excitation during the fully open holding phase. The drawback is that the high voltage excitation time depends on the experimental data measured in advance. For different operating conditions, it is necessary to conduct tests in advance, which is cumbersome. (2) The high-speed solenoid valve control system and method disclosed in patent CN 113898778B, which adapts to changes in operating conditions and control parameters, uses the sampling information of current and current derivative as a real-time feedback signal to determine whether the valve core is fully open, and can accurately identify the fully open feature point under different operating conditions. The drawback is that the control system is complex, requires high-speed AD to collect the drive current, and requires software to process the collected values. Summary of the Invention

[0005] In view of this, an embodiment is provided in this specification.

[0006] This specification provides the following technical solution in its embodiments: a high-speed solenoid valve drive circuit for adaptive operating conditions, comprising: a first D flip-flop, a second D flip-flop, an OR gate circuit, an AND gate circuit, a self-oscillating circuit, a first voltage comparator circuit, a second voltage comparator circuit, a current differentiating circuit, a high-side driver, a high-side switch, and a current sensor; wherein, the software control signal is simultaneously connected to the first input terminal of the AND gate circuit, the data input terminal of the first D flip-flop, the data input terminal of the second D flip-flop, and the reset input terminal; the clock input terminal of the first D flip-flop is connected to the self-oscillating circuit, the positive logic output terminal of the first D flip-flop is connected to the first input terminal of the OR gate circuit, the reset input terminal of the first D flip-flop is connected to the output terminal of the first voltage comparator circuit, and the second D flip-flop logic... The negative output terminal is connected to the second input terminal of the OR gate circuit; the clock input terminal of the second D flip-flop is connected to the output terminal of the second voltage comparator circuit; the output terminal of the OR gate circuit is connected to the second input terminal of the AND gate circuit; the output terminal of the AND gate circuit is connected to the input terminal of the high-side driver; the output terminal of the high-side driver is connected to the gate of the high-side switch; the source of the high-side switch is connected to the positive terminal of the high-speed solenoid valve; the drain of the high-side switch is connected to the power supply; the current sensor is connected in series between the negative terminal of the high-speed solenoid valve and ground; the output terminal of the current sensor is simultaneously connected to the inverting input terminal of the first voltage comparator circuit and the non-inverting input terminal of the second voltage comparator circuit; the non-inverting input terminal of the first voltage comparator circuit is connected to the first voltage reference; and the inverting input terminal of the second voltage comparator circuit is connected to the second voltage reference.

[0007] Compared with the prior art, the beneficial effects that at least one technical solution adopted in the embodiments of this specification can achieve include at least: 1. This invention generates the Peak & Hold current drive waveform for high-speed solenoid valves using only operational amplifiers, voltage comparators, conventional logic gate circuits, and discrete components such as resistors, capacitors, and field-effect transistors. It does not require boosting the drive voltage, has a simple principle, and does not require complex hardware or MCU processors. It is easy to use and has low hardware costs.

[0008] 2. This invention achieves online identification of the fully open feature point of the valve core by using the derivative information of the driving current of the high-speed solenoid valve. This overcomes the problem that the opening response time is sensitive to pressure changes, reduces the hardware cost of high-precision, high-end displacement sensors and the cumbersome data processing in the early experimental stage, makes the switching time of the drive circuit between the opening excitation stage and the small current maintenance stage more accurate, reduces the energy consumption caused by the switching time lag, and widens the controllable duty cycle range of the valve core. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a functional principle block diagram of a high-speed solenoid valve drive circuit with adaptive operating conditions according to an embodiment of the present invention. Figure 2 This is a graph showing the relationship between current and valve core displacement when the high-speed solenoid valve is driven by a conventional Peak & Hold in an embodiment of the present invention. Figure 3 This is a diagram showing the relationship between the high-speed solenoid valve control signal and the driving voltage and driving current in an embodiment of the present invention. Figure 4 This is a hardware schematic diagram of the current differentiating circuit in an embodiment of the present invention. Detailed Implementation

[0011] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0012] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0013] like Figures 1 to 4 As shown, this embodiment of the invention provides a high-speed solenoid valve drive circuit for adaptive operating conditions, including a first D flip-flop N1, a second D flip-flop N2, an OR gate circuit N3, an AND gate circuit N4, a self-oscillating circuit, a first voltage comparator circuit U1, a second voltage comparator circuit U2, a current differentiator circuit, a high-side driver, a high-side switch Q1, and a current sensor.

[0014] The software control signal SOF_CTL is simultaneously connected to the first input terminal of AND gate N4, the data input terminal of the first D flip-flop N1, the data input terminal of the second D flip-flop N2, and the reset input terminal.

[0015] The clock input of the first D flip-flop N1 is connected to the self-oscillating circuit. The positive logic output of the first D flip-flop N1 is connected to the first input of the OR gate circuit N3. The reset input of the first D flip-flop N1 is connected to the output of the first voltage comparator circuit U1. The negative logic output of the second D flip-flop N2 is connected to the second input of the OR gate circuit N3. The clock input of the second D flip-flop N2 is connected to the output of the second voltage comparator circuit U2.

[0016] The output of OR gate N3 is connected to the second input of AND gate N4. The output of AND gate N4 is connected to the input of the high-side driver. The output of the high-side driver is connected to the gate of high-side switch Q1. The source of high-side switch Q1 is connected to the positive terminal of the high-speed solenoid valve. The drain of high-side switch Q1 is connected to the power supply VDD. The current sensor is connected in series between the negative terminal of the high-speed solenoid valve and ground. The output of the current sensor is simultaneously connected to the inverting input of the first voltage comparator circuit U1 and the non-inverting input of the second voltage comparator circuit U2. The non-inverting input of the first voltage comparator circuit U1 is connected to the voltage reference VREF1. The inverting input of the second voltage comparator circuit U2 is connected to the voltage reference VREF.

[0017] Among them, the software control signal SOF_CTL is a high-low level switch signal (which can be a 40Hz PWM signal) with variable output duty cycle and frequency according to the software settings, used to control the high-speed solenoid valve; the high-side driver controls the on / off state of the high-side switch Q1 according to the high or low level of the input signal; the current differentiating circuit differentiates and filters the drive current detected by the current sensor to monitor the current derivative information; and the self-oscillating circuit is used to obtain a clock signal with a period of f.

[0018] The voltage value of the voltage reference VREF at the inverting input terminal of the second voltage comparator circuit U2 is less than 0, so as to ensure that the second voltage comparator circuit U2 outputs a high level before applying excitation to the high-speed solenoid valve.

[0019] It should be noted that when the rising edge of the software control signal SOF_CTL arrives, the drive current of the high-speed solenoid valve increases exponentially. When the drive current reaches a certain current value Is, the armature of the high-speed solenoid valve begins to move, causing the coil inductance to increase and the drive current to begin to decrease. When the high-speed solenoid valve is fully open, the coil inductance reaches its maximum value and remains unchanged, and the drive current changes from decreasing to increasing. Therefore, the characteristic point of the high-speed solenoid valve being fully open can be identified by the change in the sign of the derivative of the current. When the drive current of the high-speed solenoid valve first decreases and then increases after it is opened, the output voltage of the current differentiating circuit changes from negative to positive. Then, the second voltage comparison circuit U2 will output a rising edge, and the logic negative output terminal of the second D flip-flop changes from high level to low level, causing the drive circuit to enter the small current holding stage.

[0020] Preferably, the controlled high-speed solenoid valve is a single-electromagnet, single-coil solenoid valve, and the inlet hydraulic pressure always acts in the closing direction of the valve core. The current value I during the low-current holding phase of the drive circuit... OVER The gain G of the current sensor and the reference voltage VREF1 are determined by the following formula: I OVER = VREF1 / G.

[0021] The high-speed solenoid valve is divided into an opening excitation stage, a low current maintenance stage, and a closing excitation stage in sequence within a switching cycle. During the opening excitation stage, the high-speed solenoid valve uses the sign change information of the current derivative as a feedback signal to indicate whether the valve core is fully open. This allows for precise control of the solenoid valve opening time and automatic adaptation to different inlet hydraulic pressures and other operating conditions.

[0022] This invention also provides a high-speed solenoid valve driving method for adaptive operating conditions. The low-current maintenance phase specifically includes: Step S1: When the logic negative output terminal of the second D flip-flop changes from high level to low level, the driving circuit enters the low current holding stage; when the driving current I of the high-speed solenoid valve is greater than the holding current threshold I... OVER When the voltage comparison circuit U1 outputs a low level, the logic positive output signal of the first D flip-flop N1 becomes low, the OR gate circuit N3 outputs a low level, the AND gate circuit N4 outputs a low level, and the high-side driver turns off the high-side switch Q1. Step S2: When the driving current I of the high-speed solenoid valve is less than the holding current threshold I OVER When the first voltage comparison circuit U1 outputs a high level, when the real-time self-oscillation circuit outputs a rising edge again, the logic positive output signal of the first D flip-flop N1 becomes high level, the OR gate N3 outputs a high level, the AND gate N4 outputs a high level, and the high-side driver will turn on the high-side switch Q1. Step S3: Before the software control signal SOF_CTL changes from high to low, the circuit switches between steps S1 and S2 sequentially to maintain the high-speed solenoid valve drive current I at I... OVER The drive circuit operates in a low-current sustaining state.

[0023] The specific method for cyclically controlling a high-speed solenoid valve during a continuous switching cycle is as follows: Step S1: Before the rising edge of the software control signal SOF_CTL arrives, the second D flip-flop outputs a high level, and then the OR gate N3 outputs a high level; in addition, the high-speed solenoid valve drive current remains unchanged at 0, the current differentiating circuit outputs 0, and then the second voltage comparison circuit outputs a high level. Step S2: When the rising edge of the software control signal SOF_CTL arrives, since there is no rising edge signal at the clock input of the second D flip-flop, the logic negative output high level of the second D flip-flop remains unchanged, and thus the AND gate circuit N4 outputs a high level; Step S3: The high-side driver controls the high-side switch Q1 to conduct and apply DC excitation to the high-speed solenoid valve. The driving current of the high-speed solenoid valve increases exponentially. The current differentiating circuit outputs a positive voltage, and the second voltage comparator circuit U2 outputs a high level. Step S4: When the driving current of the high-speed solenoid valve reaches a certain current value Is, the armature of the high-speed solenoid valve begins to move, causing the coil inductance to increase and the driving current to decrease. Then, the second voltage comparison circuit U2 will output a falling edge, and the logic negative output voltage of the second D flip-flop will remain at a high level. Step S5: When the high-speed solenoid valve enters the fully open state, the coil inductance reaches its maximum value and remains unchanged, and the driving current changes from decreasing to increasing; then the second voltage comparison circuit U2 will output a rising edge, the logic negative output voltage of the second D flip-flop becomes low level, and the output of the OR gate circuit N3 is determined by the logic positive output voltage of the first D flip-flop, then the high-speed solenoid valve enters the low current holding stage. Step S6: Before the falling edge of the software control signal SOF_CTL arrives, regardless of the trend of the drive current change, the logic negative output voltage of the second D flip-flop remains at a low level. Step S7: When the falling edge of the software control signal SOF_CTL arrives, the logic negative output voltage of the second D flip-flop becomes high, the output of the AND gate circuit N4 becomes low, the high-side driver cuts off the high-side switch Q1, and maintains this state until the end of the current cycle.

[0024] The present invention will be further described below with reference to the accompanying drawings and embodiments. The high-speed solenoid valve of a certain type of engine fuel control system has an engagement time and a release time of no more than 6ms, a holding current of 0.55A~0.75A, and a PWM control cycle of 40Hz.

[0025] like Figure 1 As shown, this embodiment provides a high-speed solenoid valve drive circuit for adaptive operating conditions, which mainly includes a first D flip-flop N1, a second D flip-flop N2, an OR gate circuit N3, an AND gate circuit N4, a self-oscillating circuit, a first voltage comparator circuit U1, a second voltage comparator circuit U2, a current differentiator circuit, a high-side driver, a high-side switch Q1, and a current sensor.

[0026] The software control signal SOF_CTL is simultaneously connected to the first input terminal of AND gate N4, the data input terminal of the first D flip-flop N1, the data input terminal of the second D flip-flop N2, and the reset input terminal. The clock input of the first D flip-flop N1 is connected to the self-oscillating circuit. The positive logic output of the first D flip-flop N1 is connected to the first input of the OR gate N3. The reset input of the first D flip-flop N1 is connected to the output of the first voltage comparator circuit U1. The negative logic output of the second D flip-flop N2 is connected to the second input of the OR gate N3. The clock input of the second D flip-flop N2 is connected to the output of the second voltage comparator circuit U2. The output of the OR gate N3 is connected to the second input of the AND gate N4. The output of the AND gate N4 is connected to the input of the high-side driver. The output of the high-side driver is connected to the gate of the high-side switch Q1. The source of the high-side switch Q1 is connected to the positive terminal of the high-speed solenoid valve. The drain of the high-side switch Q1 is connected to the power supply VDD. The current sensor is connected in series between the negative terminal of the high-speed solenoid valve and ground. The output of the current sensor is simultaneously connected to the inverting input of the first voltage comparator circuit U1 and the non-inverting input of the second voltage comparator circuit U2. The non-inverting input of the first voltage comparator circuit U1 is connected to the voltage reference VREF1. The inverting input of the second voltage comparator circuit U2 is connected to the voltage reference VREF. The voltage reference VREF has a value of -0.1V, which ensures that the second voltage comparator circuit U2 outputs a high level before applying excitation to the high-speed solenoid valve. During the initial driving phase of the solenoid valve, no rising edge will appear at the output of the second voltage comparator circuit U2. Since VREF has a voltage value of 5V and the current sensor gain G is 8, the current value IOVER during the small current holding phase is 5 / 8 = 0.625A.

[0027] The software control signal SOF_CTL is a PWM signal with a variable output duty cycle and a frequency of 40Hz, set according to the software, used to control the high-speed solenoid valve; the high-side driver controls the on / off state of the high-side switch Q1 according to the high or low level of the input signal; the current differentiating circuit differentiates and filters the drive current detected by the current sensor to monitor the current derivative information; the self-oscillating circuit is used to obtain a clock signal with a period of 5KHz.

[0028] Furthermore, the controlled high-speed solenoid valve is a solenoid valve with a single electromagnet and a single coil structure, and the inlet hydraulic pressure always acts on the valve core in the closing direction.

[0029] like Figure 2As shown, when the rising edge of the software control signal SOF_CTL arrives, the drive current of the high-speed solenoid valve increases exponentially. When the drive current reaches a certain current value Is, the armature of the high-speed solenoid valve begins to move, causing the coil inductance to increase and the drive current to begin to decrease until the high-speed solenoid valve is fully open. At this time, the coil inductance reaches its maximum value and remains unchanged, and the drive current changes from decreasing to increasing. Therefore, the characteristic point of the high-speed solenoid valve being fully open can be identified by the change in the sign of the derivative of the drive current. When the drive current after the high-speed solenoid valve is opened first decreases and then increases, the output voltage of the current differentiator circuit changes from negative to positive. Then, the second voltage comparison circuit U2 will output a rising edge, and the logic negative output terminal of the second D flip-flop changes from high level to low level. The output voltage of the OR gate N3 is determined by the logic positive output terminal of the first D flip-flop, so that the drive circuit enters the small current holding stage.

[0030] like Figure 4 The diagram shows the hardware schematic of the current differentiator circuit. In this circuit, R1=R2=10KΩ, C1=C2=1nF, which satisfies the condition that the frequency of the current sensor output signal is much smaller than f. H =1 / (2π 10KΩ 10nF) = 15.9KHz.

[0031] Furthermore, after entering the low-current holding stage, the high-speed solenoid valve drive circuit operates as follows: Step S1: When the logic negative output of the second D flip-flop changes from high level to low level, the drive circuit enters the small current holding stage; when the high-speed solenoid valve drive current I is greater than the holding current threshold of 0.625A, the first voltage comparator circuit U1 outputs a low level; then the logic positive output signal of the first D flip-flop N1 becomes low level, the OR gate circuit N3 outputs a low level, the AND gate circuit N4 outputs a low level, and the high-side driver turns off the high-side switch Q1; Step S2: When the drive current I of the high-speed solenoid valve is less than the holding current threshold of 0.625A, the first voltage comparison circuit U1 outputs a high level; when the real-time self-oscillation circuit outputs a rising edge again, the logic positive output signal of the first D flip-flop N1 becomes high level, the OR gate N3 outputs a high level, the AND gate N4 outputs a high level, and the high-side driver will turn on the high-side switch Q1. Step S3: Before the software control signal SOF_CTL changes from high level to low level, the circuit switches between steps S1 and S2 in sequence to maintain the high-speed solenoid valve drive current I at about 0.625A, and the drive circuit works in a low current maintenance state.

[0032] like Figure 3As shown, the high-speed solenoid valve, within one switching cycle, is divided into an opening excitation phase, a low-current maintenance phase, and a closing excitation phase in sequence. During the opening excitation phase, the change in the sign of the current derivative serves as a feedback signal to determine whether the valve core is fully open. This allows for precise control of the high-speed solenoid valve's opening time and automatic adaptation to different inlet hydraulic pressures and other operating conditions. The specific method for cyclic control of the high-speed solenoid valve within a continuous switching cycle is as follows: Step S1: Before the rising edge of the software control signal SOF_CTL arrives, the second D flip-flop outputs a high level, which in turn causes the OR gate N3 to output a high level; in addition, the high-speed solenoid valve drive current remains unchanged at 0, the current differentiating circuit outputs 0, and the second voltage comparator circuit outputs a high level. Step S2: When the rising edge of the software control signal SOF_CTL arrives, since there is no rising edge signal at the clock input of the second D flip-flop, the logic negative output high level of the second D flip-flop remains unchanged, and thus the AND gate circuit N4 outputs a high level. Step S3: The high-side driver controls the high-side switch Q1 to conduct and apply DC excitation to the high-speed solenoid valve. The high-speed solenoid valve drive current increases exponentially, the current differentiating circuit outputs a positive voltage, and the second voltage comparator circuit U2 outputs a high level. Step S4: When the drive current of the high-speed solenoid valve reaches a certain current value Is, the armature of the high-speed solenoid valve begins to move, which causes the coil inductance to increase and the drive current to decrease. Then the second voltage comparison circuit U2 will output a falling edge, and the logic negative output voltage of the second D flip-flop will remain at a high level. Step S5: When the high-speed solenoid valve enters the fully open state, the coil inductance reaches its maximum value and remains unchanged, and the drive current changes from decreasing to increasing; then the second voltage comparison circuit U2 will output a rising edge, the logic negative output voltage of the second D flip-flop becomes low level, and the output of the OR gate circuit N3 is determined by the logic positive output voltage of the first D flip-flop, then the high-speed solenoid valve enters the low current holding stage. Step S6: Before the falling edge of the software control signal SOF_CTL arrives, regardless of the trend of the drive current change, the logic negative output voltage of the second D flip-flop remains at a low level. Step S7: When the falling edge of the software control signal SOF_CTL arrives, the logic negative output voltage of the second D flip-flop becomes high, the output of the AND gate circuit N4 becomes low, the high-side driver cuts off the high-side switch Q1, and maintains this state until the end of the current cycle.

[0033] In practical applications, this invention has been used in a full authority digital electronic controller for a certain type of engine. After testing and verification in the fuel control system and in actual operation, it has been shown to achieve precise control of the high-speed solenoid valve, and the system operates stably and reliably.

[0034] The above description is merely a specific embodiment of the present invention and should not be construed as limiting the scope of the invention. Therefore, any substitution of equivalent components or equivalent changes and modifications made within the scope of protection of this patent should still fall within the scope of this patent. Furthermore, the technical features, technical features and technical solutions, and technical solutions in this invention can be freely combined and used.

Claims

1. A high-speed solenoid valve drive circuit with adaptive operating conditions, characterized in that, include: The circuit comprises a first D flip-flop, a second D flip-flop, an OR gate, an AND gate, a self-oscillating circuit, a first voltage comparator circuit, a second voltage comparator circuit, a current differentiator circuit, a high-side driver, a high-side switch, and a current sensor; among which... The software control signal is simultaneously connected to the first input terminal of the AND gate circuit, the data input terminal of the first D flip-flop, the data input terminal of the second D flip-flop, and the reset input terminal; The clock input terminal of the first D flip-flop is connected to the self-oscillating circuit, the positive logic output terminal of the first D flip-flop is connected to the first input terminal of the OR gate circuit, the reset input terminal of the first D flip-flop is connected to the output terminal of the first voltage comparator circuit, the negative logic output terminal of the second D flip-flop is connected to the second input terminal of the OR gate circuit, and the clock input terminal of the second D flip-flop is connected to the output terminal of the second voltage comparator circuit. The output terminal of the OR gate is connected to the second input terminal of the AND gate, and the output terminal of the AND gate is connected to the input terminal of the high-side driver. The output terminal of the high-side driver is connected to the gate of the high-side switch, the source of the high-side switch is connected to the positive terminal of the high-speed solenoid valve, and the drain of the high-side switch is connected to the power supply. The current sensor is connected in series between the negative terminal of the high-speed solenoid valve and ground. The output terminal of the current sensor is simultaneously connected to the inverting input terminal of the first voltage comparator circuit and the non-inverting input terminal of the second voltage comparator circuit. The non-inverting input terminal of the first voltage comparator circuit is connected to the first voltage reference, and the inverting input terminal of the second voltage comparator circuit is connected to the second voltage reference.

2. The high-speed solenoid valve drive circuit for adaptive operating conditions according to claim 1, characterized in that, The voltage value of the second voltage reference at the inverting input terminal of the second voltage comparator circuit is less than 0, and the second voltage comparator circuit outputs a high level before the high-speed solenoid valve applies excitation.

3. The high-speed solenoid valve drive circuit for adaptive operating conditions according to claim 1, characterized in that, The high-speed solenoid valve is a solenoid valve with a single electromagnet or a single coil structure, and the inlet hydraulic pressure always acts on the valve core of the high-speed solenoid valve in the closing direction.

4. A high-speed solenoid valve driving method for adaptive operating conditions, implemented using the high-speed solenoid valve driving circuit for adaptive operating conditions as described in any one of claims 1 to 3, characterized in that, Within one switching cycle, the high-speed solenoid valve's adaptive high-speed solenoid valve driving method includes: sequentially performing an opening excitation phase, a low-current maintenance phase, and a closing excitation phase; during the opening excitation phase, the high-speed solenoid valve uses the sign change information of the current derivative as a feedback signal to indicate whether the valve core is fully open, in order to obtain the solenoid valve opening time and automatically adapt to the corresponding inlet liquid pressure.

5. The high-speed solenoid valve driving method for adaptive operating conditions according to claim 4, characterized in that, The low-current maintenance phase specifically includes: When the logic negative output of the second D flip-flop changes from high to low, the high-speed solenoid valve drive circuit of the adaptive operating condition enters the low-current maintenance stage; when the high-speed solenoid valve drive current I is greater than the holding current threshold I... OVER When the first voltage comparison circuit outputs a low level, the positive output signal of the first D flip-flop becomes low, the OR gate outputs a low level, the AND gate outputs a low level, and the high-side driver turns off the high-side switch. When the drive current I of the high-speed solenoid valve is less than the holding current threshold I OVER When the first voltage comparison circuit outputs a high level, when the real-time self-oscillation circuit outputs a rising edge again, the first D flip-flop logic positive output signal becomes high level, the OR gate outputs a high level, the AND gate outputs a high level, and the high-side driver will turn on the high-side switch. Before the software control signal changes from high to low, the adaptive high-speed solenoid valve drive circuit switches between the above steps to maintain the high-speed solenoid valve drive current I at I0. OVER Within the set range, the high-speed solenoid valve drive circuit for the adaptive operating condition is operated in a low-current maintenance state.

6. The high-speed solenoid valve driving method for adaptive operating conditions according to claim 5, characterized in that, Current threshold I OVER The specific formula is: I OVER = VREF1 / G, where G is the gain of the current sensor and VREF1 is the reference voltage.

7. The high-speed solenoid valve driving method for adaptive operating conditions according to claim 4, characterized in that, During a continuous switching cycle, the high-speed solenoid valve driving method for adaptive operating conditions includes: Step S1: Before the rising edge of the software control signal arrives, the second D flip-flop outputs a high level, and then the OR gate outputs a high level; the high-speed solenoid valve drive current remains unchanged at 0, the current differentiating circuit outputs 0, and then the second voltage comparison circuit outputs a high level. Step S2: When the rising edge of the software control signal arrives, since there is no rising edge signal at the clock input of the second D flip-flop, the logic negative output high level of the second D flip-flop remains unchanged, and thus the AND gate circuit outputs a high level; Step S3: The high-side driver controls the high-side switch to turn on and apply DC excitation to the high-speed solenoid valve. The driving current of the high-speed solenoid valve increases exponentially. The current differentiating circuit outputs a positive voltage, and the second voltage comparator circuit outputs a high level. Step S4: When the driving current of the high-speed solenoid valve reaches the set current value Is, the armature of the high-speed solenoid valve begins to move, causing the coil inductance to increase and the driving current to decrease. Then the second voltage comparison circuit will output a falling edge, and the logic negative output voltage of the second D flip-flop will remain at a high level. Step S5: When the high-speed solenoid valve enters the fully open state, the coil inductance reaches its maximum value and remains unchanged, and the driving current changes from decreasing to increasing; then the second voltage comparison circuit will output a rising edge, the logic negative output voltage of the second D flip-flop becomes low level, and the output of the OR gate circuit is determined by the logic positive output voltage of the first D flip-flop, then the high-speed solenoid valve enters the low current holding stage. Step S6: Before the falling edge of the software control signal arrives, the logic negative output voltage of the second D flip-flop remains at a low level. Step S7: When the falling edge of the software control signal arrives, the logic negative output voltage of the second D flip-flop becomes high, the output of the AND gate becomes low, the high-side driver cuts off the high-side switch, and maintains this state until the end of the current cycle.

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