Realization method of multi-scattering point target echo simulation based on heterogeneous platform

Abstract

The application provides a multi-scattering point target echo simulation implementation method based on a heterogeneous platform, a general storage playback type complex radar signal real-time simulation system is constructed by combining software and hardware through a heterogeneous multi-core platform based on CPU, ARM processor, FPGA, high-speed A / D and high-speed D / A, and the system is integrated into one. In the system, a multi-channel parallel processing method is used in the FPGA, the control and execution tasks of each scattering point are allocated to different processing units for processing, so that each processing unit can independently control one scattering point and simultaneously process the tasks of multiple scattering points, the working frequency of the FPGA can be equivalently improved, and more efficient task processing is realized. In each processing unit, a new solution is proposed for the problem of the interval between any two scattering points, so that the minimum distance between any two scattering points is 0.25m. The system has the characteristics of easy implementation, real-time generation and high precision, and has practical value for complex radar echo signal synthesis.

Description

Technical Field

[0001] This invention relates to the field of radar signal simulation, specifically to a system and method for simulating the echo of a multi-scattering target based on a heterogeneous multi-core platform of CPU, ARM processor, FPGA, high-speed A / D, and high-speed D / A. Background Technology

[0002] Multi-scattering point target echo simulation systems can simulate the electromagnetic environment of real-world operation in a laboratory setting, playing an irreplaceable role in radar equipment testing, teaching, and practical training. With the continuous development of electronic technology, higher demands are placed on the modular design, versatility, real-time performance, and scalability of simulators. While software simulation offers unique advantages such as low cost and high flexibility, it suffers from poor real-time performance. Hardware simulation often employs radio frequency signal storage and playback technology, offering good real-time performance but lacking versatility and unable to meet the requirements of complex and ever-changing environmental settings. Therefore, using a new heterogeneous multi-core platform combining software and hardware to implement a simple multi-scattering point target echo simulation system has significant practical implications. Summary of the Invention

[0003] The purpose of this invention is to propose a method for simulating the echo of multi-scattering target based on a heterogeneous platform. Using an FPGA module as the core as the computing unit for simulating complex radar signals, a general-purpose storage and playback type real-time simulation system for complex radar signals is constructed to achieve real-time and high-precision simulation of multi-scattering target echo signals.

[0004] To achieve the above objectives, the present invention adopts the following technical solution:

[0005] A method for simulating multi-scattering point target echoes based on a heterogeneous platform, characterized in that...

[0006] The implementation method employs the following multi-scattering point target echo simulation system based on a heterogeneous platform. The system includes a CPU module, an FPGA module, a radio frequency module, a high-speed A / D module, a high-speed D / A module, and a DDR module, wherein:

[0007] After receiving control parameters from the FPGA module, RF module, high-speed A / D module, and high-speed D / A module through the PC-side QT-developed host computer software user interface, the CPU module sends the control parameters down in real time through the PCIE high-speed interface. The FPGA module receives and parses the control parameters in real time and forwards them to the RF module, high-speed A / D module, and high-speed D / A module.

[0008] The receiving channel of the RF module generates a corresponding local oscillator signal according to the control parameters. This signal is mixed with the input signal and then low-pass filtered. The high-speed A / D module acquires the low-frequency signal and transmits it to the FPGA module in real time for energy detection. If the signal-to-noise ratio requirement is met, the signal is considered valid and written to the DDR memory. The transmitting channel of the RF module generates a corresponding local oscillator signal according to the control parameters. The FPGA module reads the stored data from the DDR module according to the control parameters and transmits it to the high-speed D / A module to generate an intermediate frequency signal. The local oscillator signal is mixed with the intermediate frequency signal to convert it into a high-frequency signal for forwarding.

[0009] Furthermore, the four parallel input FPGA signals a_i, b_i, c_i, and d_i are squared to obtain four new parallel signals a, b, c, and d. Each signal has a data buffer with a depth of 128, labeled from 0 to 127, used to temporarily store the input data. The data is retrieved from the buffer except for the data at address 127 in the first channel, and input data a; the data is retrieved from the buffer except for the data at address 127 in the first and second channels, and input data a and b; the data is retrieved from the buffer except for the data at address 127 in the first and second channels, and input data a and b. All data except for the third channel address 127, and input data a, b, c are taken from the buffer except for the data in the first, second, third, and fourth channels excluding address 127, and input data a, b, c, d. These are summed to obtain four parallel sequences a_sum, b_sum, c_sum, and d_sum. If the values ​​of a_sum, b_sum, c_sum, and d_sum all meet the signal-to-noise ratio requirements, a valid data signal is generated and written to the DDR memory.

[0010] Furthermore, the process of transmitting data from the DDR memory to the high-speed D / A module to generate the intermediate frequency signal involves two delays. The first delay is determined by the minimum initial distance and the minimum distance after movement of the multiple scattering points, which determines the time when the data is read from the DDR data read buffer memory. The second delay is determined by the dynamic distance of each of the multiple scattering points, which determines the delay time of the data in the multiple scattering point synthesis module. The delay unit consists of multiple registers.

[0011] The formulas for calculating the dynamic distance at different scattering points are as follows:

[0012] r(i)=r0(i)+v0(i)*t+0.5*a(i)*t 2 (1)

[0013] Where: i = 0, 1, 2, ..., M-1, M is the maximum number of scattering points, r0(i), v0(i), a(i) represent the difference between the initial distance and the minimum initial distance, the initial velocity, and the acceleration of different scattering points, respectively, where * represents multiplication. FPGA multi-channel parallel real-time calculation of the distance between multiple scattering points is performed. Formula (1) is discretized to obtain the following formula:

[0014] r(n+1)=r0+v0*(n / f clk )+0.5*a*(n / f clk ) 2 (2)

[0015] Where: f clk Here, n is the FPGA operating clock, and n is the pulse count value. This simplifies the process of squaring natural numbers within the FPGA; the formula is:

[0016] v(n)=r(n+1)-r(n)=v0 / f clk +0.5*a*(1 / f clk ) 2 *(2*n+1)

[0017] =a*(1 / f clk ) 2 *n+v0 / f clk +0.5*a*(1 / f clk ) 2 (3) In the FPGA, double accumulation is required. First, the accumulation is performed to calculate a*(1 / f clk ) 2 *n, and then sum them up according to formula (3) to calculate the distance value, where:

[0018] k2=a*(1 / f clk ) 2

[0019] k1 = v0 / f clk +0.5*a*(1 / f clk ) 2

[0020] k0=r0 (4)

[0021] f in FPGA clk Perform quantization processing and calculate the values ​​of k2, k1, and k0;

[0022] Furthermore, by changing the FPGA operating clock and the number of parallel paths, different minimum distance units can be achieved between any two scattering points under this architecture. When the FPGA operating clock is 300MHz and four paths are parallel, the minimum distance between any two scattering points can be 0.25m. The FPGA operates at 300MHz. The delay distance of one clock cycle is 1 / 300MHz * 3e8m / s = 1m. The DDR data read buffer stores four parallel output data channels a, b, c, and d, which are buffered to obtain a_d, b_d, c_d, and d_d. Taking the data from channels b_d, c_d, d_d, and a results in data delayed by 1 / 4 of a 300MHz clock cycle, making the minimum distance between any two scattering points 0.25m. Simultaneously, taking the data from channels c_d, d_d, a, and b results in data delayed by 1 / 2 of a 300MHz clock cycle, making the minimum distance between any two scattering points 0.5m. Taking the data from channels d_d, a, b, and c results in data delayed by 3 / 4 of a 300MHz clock cycle, making the minimum distance between any two scattering points 0.75m.

[0023] Furthermore, by increasing the depth of the data buffer, the interval between any two scattering points can be increased, where the interval is an integer multiple of the minimum distance unit. The minimum dynamic distance of the multiple scattering points is selected as the reference scattering point. The interval between any two scattering points is implemented in FPGA multi-channel parallel processing. The number of parallel channels is one less than the number of multiple scattering points. Each channel processes the interval between one scattering point and the reference scattering point. Each channel directly outputs data from the DDR data read buffer, outputs data with a minimum distance interval of 0.25m between two scattering points, outputs data with a minimum distance interval of 0.5m between two scattering points, and outputs data with a minimum distance interval of 0.75m between two scattering points. The four types of data temporarily stored in different clock cycles are selected for each channel, which makes the interval between any two scattering points an integer multiple of the minimum distance unit. Appropriate gain control parameters are selected to simulate the reflection, refraction, and scattering effects of multiple scattering points. Finally, the output data of multiple scattering points are superimposed. If there is data overflow, saturation processing is performed.

[0024] This invention addresses multi-scattering point echoes by leveraging the parallel computing advantages of FPGAs to design a suitable architecture. By changing the FPGA's operating clock and the number of parallel paths, different minimum distance units can be achieved between any two scattering points within this architecture. Specifically, with an FPGA operating clock of 300MHz and four parallel paths, a minimum distance of 0.25m between any two scattering points can be achieved. The specific advantages of this invention are as follows:

[0025] (1) This invention utilizes a heterogeneous multi-core hardware and software design to fully leverage the characteristics and advantages of different types of processors, thereby achieving more efficient computing and data processing capabilities and enabling real-time, high-precision simulation of multi-scattering point target echo signals.

[0026] (2) Design an architecture based on FPGA parallel computing. By changing the FPGA running clock and the number of parallel paths, different minimum distance units can be achieved between any two scattering points under this architecture. At the same time, by increasing the depth of the data buffer, the interval between any two scattering points can be increased, where the interval is an integer multiple of the minimum distance unit, so as to optimize the system performance and provide an effective method for realizing the echo signal of multi-scattering point target. Attached Figure Description

[0027] Figure 1 This is a flowchart illustrating the implementation of the present invention;

[0028] Figure 2 This is a diagram of the energy detection implementation architecture of the present invention;

[0029] Figure 3 This is a diagram illustrating the architecture of the data output with two delays according to the present invention.

[0030] Figure 4 This is a block diagram illustrating the distance calculation implementation of the present invention;

[0031] Figure 5 This is a block diagram of the architecture for implementing the minimum distance unit between multiple scattering point targets in this invention;

[0032] Figure 6 This is a block diagram of the multi-scattering point target echo signal implementation architecture of the present invention;

[0033] Figure 7 The simulation results are those of the target echo signal realization of the multi-scattering point of the present invention; Detailed Implementation

[0034] To enable people to intuitively and vividly understand each technical feature and overall technical solution of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0035] Reference Figure 1This invention relates to a method for simulating echoes of multi-scattering point targets based on a heterogeneous platform. The method employs a multi-scattering point target echo simulation system based on a heterogeneous platform. The system includes a CPU module, an FPGA module, a radio frequency (RF) module, a high-speed A / D module, a high-speed D / A module, and a DDR module. The CPU module is connected to the FPGA module via a PCIe interface. The FPGA module is also connected to the RF module, the high-speed A / D module, the high-speed D / A module, and the DDR module. The RF module is also connected to the high-speed A / D module and the high-speed D / A module.

[0036] After receiving control parameters from the FPGA module, RF module, high-speed A / D module, and high-speed D / A module through the PC-side QT-developed host computer software user interface, the CPU module sends the control parameters down in real time through the PCIE high-speed interface. The FPGA module receives and parses the control parameters in real time and forwards them to the RF module, high-speed A / D module, and high-speed D / A module.

[0037] The receiving channel of the RF module generates a corresponding local oscillator signal according to the control parameters. This signal is mixed with the input signal and then low-pass filtered. The high-speed A / D module acquires the low-frequency signal and transmits it to the FPGA module in real time for energy detection. If the signal-to-noise ratio requirement is met, the signal is considered valid and written to the DDR memory. The transmitting channel of the RF module generates a corresponding local oscillator signal according to the control parameters. The FPGA module reads the stored data from the DDR module according to the control parameters and transmits it to the high-speed D / A module to generate an intermediate frequency signal. The local oscillator signal is mixed with the intermediate frequency signal to convert it into a high-frequency signal for forwarding.

[0038] Reference Figure 1 The present invention provides a method for simulating the echo of a multi-scattering target based on a heterogeneous platform, the implementation steps of which are as follows:

[0039] (I) Energy Detection Implementation

[0040] The sum of 512 consecutive data points (a_i, b_i, c_i, d_i) from four parallel input FPGA signals is calculated and updated in real time. Each subsequent pair of 512 data points differs only in a single data point to reflect the latest sum value after each update. If all four consecutive sum values ​​(a_sum, b_sum, c_sum, d_sum) meet the signal-to-noise ratio requirement, a valid data signal is generated and written to the DDR memory. The overall implementation flowchart is as follows. Figure 2 As shown.

[0041] (II) Data output with two delays and distance calculation implementation

[0042] The first delay is determined by the minimum initial distance and the minimum distance after movement of the multiple scattering points, thus determining the time when data is read from the DDR data read buffer. The second delay is determined by the dynamic distance of each of the multiple scattering points, thus determining the delay duration of the data in the multiple scattering point synthesis module. The delay unit consists of multiple levels of registers. The overall implementation flowchart is as follows: Figure 3 As shown; the dynamic distance calculation for different scattering points is shown in Formula 3. In the FPGA, double accumulation is required. First, the accumulation calculation a*(1 / f) is performed. clk ) 2 *n, and then sum them up according to formula (3) to calculate the distance value, where:

[0043] k2=a*(1 / f clk ) 2

[0044] k1 = v0 / f clk +0.5*a*(1 / f clk ) 2

[0045] k0=r0 (4)

[0046] f in FPGA clk The quantization process involves calculating the values ​​of k2, k1, and k0. The overall flowchart for this process is shown below. Figure 4 As shown, where z -1 This represents a delay of one clock cycle.

[0047] (III) Achieving Minimum Distance Unit for Multi-Scattering Point Target Spacing

[0048] The FPGA operates at a clock speed of 300MHz. The delay distance of one clock cycle is 1 / 300MHz * 3e8m / s = 1m. The DDR data read buffer stores four parallel output data channels a, b, c, and d, which are buffered to obtain a_d, b_d, c_d, and d_d. Using b_d, c_d, d_d, and a results in data delayed by 1 / 4 of a 300MHz clock cycle, making the minimum distance between any two scattering points 0.25m. Using c_d, d_d, a, and b results in data delayed by 1 / 2 of a 300MHz clock cycle, making the minimum distance between any two scattering points 0.5m. Using d_d, a, b, and c results in data delayed by 3 / 4 of a 300MHz clock cycle, making the minimum distance between any two scattering points 0.75m. Changing the FPGA operating clock and the number of parallel channels allows for different minimum distances between any two scattering points within this architecture. The overall implementation framework is as follows: Figure 5 As shown.

[0049] (iv) Realization of echo signals from multi-scattering point targets

[0050] The implementation of echo signals from multi-scattering point targets with a spacing of 0.25-16m between two scattering points is described, and the architecture is as follows. Figure 6 As shown.

[0051] The delay distance is 1m per clock cycle. Therefore, to achieve a distance cell requirement of 0.25-16m, each delay module needs four inputs: one with zero delay, one with a delay of 0.25m, one with a delay of 0.5m, and one with a delay of 0.75m. The 0.25m, 0.5m, and 0.75m delay inputs are selected based on the interval between the scattering point and the reference scattering point, ultimately resulting in two inputs. One input is temporarily labeled D_ai over multiple clock cycles, and the other is temporarily labeled D_bi over multiple clock cycles.

[0052] The required interval of 0.25-16m between two scattering points is achieved by buffering up to 15 registers across two input channels. For a 1m interval, D_a0 is used as the output delay module; for a 2.25m interval, a 0.25m delay input is buffered, and D_b1 is used as the output delay module; for a 15.75m interval, a 0.75m delay input is buffered, and D_b14 is used as the output delay module. Appropriate gain control parameters are selected to simulate the reflection, refraction, and scattering effects of multiple scattering points. Finally, the output data from multiple scattering points are superimposed, and saturation processing is applied to handle any data overflow.

[0053] The echo signal of a target with multiple scattering points can be processed in parallel in an FPGA. Each path implements the same process as the echo signal of a target with two scattering points. By increasing the depth of the data buffer, the interval between any two scattering points can be increased.

[0054] right Figure 5 , Figure 6 The design employs simulation modeling and analysis, generating a linear frequency modulated signal with a data sampling rate of 1.2 GSPS and a bandwidth of 600 MHz. The radar's range resolution is then calculated as C / 2B = 3e8 / (2*6e8) = 0.25 m, where C is the speed of light and B is the signal bandwidth. The target spacing between the two scattering points is set to 2.25 m. Figure 5 , Figure 6 The design implements the corresponding echo signal generation, performs matched filtering on the echo signal and a linear frequency modulated signal to obtain a pulse-compressed signal. The signal peak is then located, and the position of this peak corresponds to the target's distance information. Simulation results are as follows... Figure 7 As shown, the peak values ​​of the two signals are 1005 and 1014, respectively, which means the interval is 0.25m*9=2.25m, consistent with the target interval setting of the two scattering points.

[0055] The above description is merely a specific example of the present invention. Those skilled in the art, after understanding the computational principle of the present invention, can reproduce it on an FPGA. Furthermore, without departing from the concept of this application, various modifications and improvements can be made, all of which fall within the scope of protection of this application. Therefore, the scope of protection of this patent application should be determined by the appended claims.

Claims

1. A method for simulating echoes from multi-scattering point targets based on a heterogeneous platform, characterized in that, The implementation method employs the following multi-scattering point target echo simulation system based on a heterogeneous platform. The system includes a CPU module, an FPGA module, a radio frequency module, a high-speed A / D module, a high-speed D / A module, and a DDR module, wherein: After receiving control parameters from the FPGA module, RF module, high-speed A / D module, and high-speed D / A module through the PC-side QT-developed host computer software user interface, the CPU module sends the control parameters down in real time through the PCIE high-speed interface. The FPGA module receives and parses the control parameters in real time and forwards them to the RF module, high-speed A / D module, and high-speed D / A module. The receiving channel of the RF module generates a corresponding local oscillator signal according to the control parameters. This signal is mixed with the input signal and then low-pass filtered. The high-speed A / D module acquires the low-frequency signal and transmits it to the FPGA module in real time for energy detection. If the signal-to-noise ratio requirement is met, the signal is considered valid and written to the DDR memory. The transmitting channel of the RF module generates a corresponding local oscillator signal according to the control parameters. The FPGA module reads the stored data from the DDR module according to the control parameters and transmits it to the high-speed D / A module to generate an intermediate frequency signal. The local oscillator signal is mixed with the intermediate frequency signal to convert it into a high-frequency signal for forwarding. The process of transferring data from the DDR memory to the high-speed D / A module to generate the intermediate frequency signal involves two logically controllable delays. The first delay is determined by the initial minimum distance and the subsequent minimum distance of the multiple scattering points, thus determining the time when the data is read from the DDR data read buffer. The second delay is determined by the dynamic distance of each of the multiple scattering points, thus determining the delay duration of the data in the multiple scattering point synthesis module. The delay unit consists of multiple levels of registers. The formula for calculating the dynamic distance of different scattering points is as follows: (1) Where: i = 0, 1, 2, ..., M-1, M is the maximum number of scattering points. , , The initial distance and minimum initial distance, initial velocity, and acceleration of different scattering points are represented by *, where * represents multiplication. FPGA performs multi-channel parallel real-time calculation of the distance between multiple scattering points. Formula (1) is discretized to obtain the following formula: (2) in: Here, n is the FPGA operating clock, and n is the pulse count value. This simplifies the process of squaring natural numbers within the FPGA. The formula is: (3) In FPGA, two accumulations are required. First, the accumulation calculation is performed to obtain... Then, the distance value is calculated by summing the results using formula (3), where: (4) In FPGA Perform quantization and calculation , , value.

2. The method for simulating multi-scattering point target echoes based on a heterogeneous platform according to claim 1, characterized in that, Four parallel input FPGA signals a_i, b_i, c_i, and d_i are squared to obtain four new parallel signals a_i, b_i, c_i, and d_i. Each signal has a data buffer with a depth of 128, labeled from 0 to 127, used to temporarily store the input data. The system retrieves all data from the buffer except for the data at address 127 in the first channel, along with input data a, b, and c_i. The system also retrieves all data from the buffer except for the data at address 127 in the first and second channels, along with input data a and b. All data except for the third channel address 127, and input data a, b, c, are taken from the buffer except for the data in the first, second, third, and fourth channels excluding the data in the first channel address 127, and input data a, b, c, d. These are summed to obtain four parallel sequences a_sum, b_sum, c_sum, and d_sum. If the values ​​of a_sum, b_sum, c_sum, and d_sum all meet the signal-to-noise ratio requirements, a valid data signal is generated and written to the DDR memory.

3. The method for simulating multi-scattering point target echoes based on a heterogeneous platform according to claim 1, characterized in that, By changing the FPGA operating clock and the number of parallel paths, different minimum distance units can be achieved between any two scattering points within the FPGA architecture. With an FPGA operating clock of 300MHz and four parallel paths, the minimum distance between any two scattering points can be 0.25m. The FPGA operating clock is 300MHz, and the delay distance per clock cycle is 1 / 300MHz. 3e8m / s = 1m. The DDR data read buffer memory outputs four parallel data streams a, b, c, and d, which are buffered to obtain a_d, b_d, c_d, and d_d. Taking the four data streams b_d, c_d, d_d, and a results in data delayed by 1 / 4 of a 300MHz clock cycle, making the minimum distance between any two scattering points 0.25m. Simultaneously, taking the four data streams c_d, d_d, a, and b results in data delayed by 1 / 2 of a 300MHz clock cycle, making the minimum distance between any two scattering points 0.5m. Taking the four data streams d_d, a, b, and c results in data delayed by 3 / 4 of a 300MHz clock cycle, making the minimum distance between any two scattering points 0.75m.

4. The method for simulating multi-scattering point target echoes based on a heterogeneous platform according to claim 1, characterized in that, By increasing the depth of the data buffer, the interval between any two scattering points can be increased, where the interval is an integer multiple of the minimum distance unit. The minimum dynamic distance of the multiple scattering points is selected as the reference scattering point. The interval between any two scattering points is implemented in FPGA multi-channel parallel processing. The number of parallel channels is one less than the number of multiple scattering points. Each channel processes the interval between one scattering point and the reference scattering point. Each channel directly outputs data from the DDR data read buffer, outputs data with a minimum distance unit of 0.25m between two scattering points, outputs data with a minimum distance interval of 0.5m between two scattering points, and outputs data with a minimum distance interval of 0.75m between two scattering points. The four types of data temporarily stored in different clock cycles are selected for each channel, which makes the interval between any two scattering points an integer multiple of the minimum distance unit. Appropriate gain control parameters are selected to simulate the reflection, refraction, and scattering effects of multiple scattering points. Finally, the output data of multiple scattering points are superimposed. If there is data overflow, saturation processing is performed.

Images