Data writing method, device, system, electronic equipment and storage medium

Abstract

The application provides a data writing method, device, system, electronic equipment and storage medium. The method is applied to a slave machine, and the slave machine at least comprises a cache space and a storage medium. The method comprises the following steps: after a first thread receives a write instruction of to-be-written data of a host machine, first monitoring a state of the cache space; if the cache space is in an empty state or a non-empty non-full state, triggering the host machine to send the to-be-written data, so as to receive and cache the to-be-written data through the cache space as to-be-written cache data; after the receiving and caching are completed, stopping data receiving and generating instruction execution information of the write instruction to return to the host machine, so as to trigger the host machine to send a next write instruction of a next to-be-written data; and second monitoring the state of the cache space through a second thread; and if the cache space is in a full state or a non-empty non-full state, writing the to-be-written cache data of the cache space into the storage medium. The method realizes parallel work of data sending and data writing, can fully utilize transmission bandwidth and improve a writing rate.

Description

Technical Field

[0001] This application relates to the field of computer technology, specifically to a data writing method, apparatus, system, electronic device, and storage medium. Background Technology

[0002] In USB (Universal Serial Bus) transmission, the MSC (Mass Storage Class) is a type of mobile storage device responsible for transferring large amounts of data, such as USB flash drives, external hard drives, and optical discs. The MSC typically uses the SCSI (Small Computer System Interface) transmission protocol command set and the BOT (Bulk-Only Transport) transmission protocol. When the host needs to write data to the MSC, it sends a command to the MSC requesting the data to be written and transmits the data to the MSC. The MSC receives the data and writes it to the storage medium. Once the previous data reception and writing is complete, the MSC returns a command execution status, and only then can the host initiate the next data transfer.

[0003] Since writing data to the storage medium by the MSC takes a relatively long time, using the above-mentioned serial working method for data writing can easily cause the host to be in a waiting state, which not only affects the data writing rate, but also wastes the USB transmission bandwidth. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, this application provides a data writing method, apparatus, system, electronic device and storage medium to solve the technical problem that data writing via serial operation easily causes the host to be in a waiting state, which not only affects the data writing rate, but also wastes USB transmission bandwidth.

[0005] This application provides a data writing method applied to a slave device, the slave device including at least a cache space and a storage medium. The method includes: after receiving a write instruction for data to be written from a host via a first thread, performing a first monitoring of the state of the cache space, the state of the cache space including an empty state, a full state, or a non-empty and non-full state; if the cache space is in an empty state or a non-empty and non-full state, triggering the host to send the data to be written, so as to receive and cache the data to be written through the cache space as cached data to be written; after receiving and caching the data to be written, stopping data reception and generating instruction execution information for the write instruction, returning the instruction execution information to the host, so as to trigger the host to send a next write instruction for the next data to be written; and performing a second monitoring of the state of the cache space via a second thread, if the cache space is in a full state or a non-empty and non-full state, writing the cached data to be written in the cache space to the storage medium.

[0006] In one embodiment of this application, before performing a first monitoring and / or a second monitoring of the state of the cache space, the method includes: pre-dividing the cache space to obtain at least three cache areas; configuring a corresponding index value for each cache area in sequence, wherein the index value of the first cache area is determined as the starting index value, and the index value corresponding to the last cache area is determined as the ending index value, wherein the starting index value is less than the ending index value.

[0007] In one embodiment of this application, the state of the cache space is monitored in a first and / or second manner, including: real-time acquisition of the head index and tail index of the cache queue in the cache space, wherein the cache queue is formed based on all cached data to be written in the cache space, the head index represents the index value of the cache area where the head of the cache queue is located, and the tail index represents the index value of the cache area where the tail of the cache queue is located; if the tail index is equal to the head index, the cache space is determined to be empty; if the tail index is not equal to the head index and is less than the end index value, the value of the tail index plus one is determined; if the value of the tail index plus one is equal to the head index, the cache space is determined to be full; if the value of the tail index plus one is not equal to the head index, the cache space is determined to be neither empty nor full; if the tail index is not equal to the head index and is equal to the end index value, the starting index value is compared with the head index; if the starting index value is equal to the head index, the cache space is determined to be full; if the starting index value is not equal to the head index, the cache space is determined to be neither empty nor full.

[0008] In one embodiment of this application, receiving and caching the data to be written through the cache space includes: after receiving the data to be written sent by the host, caching the received data to be written to the cache area pointed to by the tail index according to the tail index; after caching the received data to be written to the cache area pointed to by the tail index, updating the tail index; wherein, the step of updating the tail index includes comparing the tail index with the end index value; if the tail index is less than the end index value, incrementing the tail index by one; if the tail index is equal to the end index value, setting the tail index to the start index value.

[0009] In one embodiment of this application, writing the cached data to be written to the storage medium from the cache space includes: reading the cached data to be written from the cache area pointed to by the head index according to the head index and writing it to the storage medium; after writing the read cached data to be written to the storage medium, releasing the cache area pointed to by the head index and updating the head index; wherein, the step of updating the head index includes comparing the head index with the end index value; if the head index is less than the end index value, incrementing the head index by one; if the head index is equal to the end index value, setting the head index to the start index value.

[0010] In one embodiment of this application, after performing a first monitoring of the state of the cache space, the method further includes: if the cache space is full, triggering the host to wait to send the data to be written, and continuously performing a first monitoring of the state of the cache space; when the cache space is detected to be updated from full to empty or neither empty nor full, triggering the host to send the data to be written, so as to receive and cache the data to be written through the cache space as cached data to be written.

[0011] In one embodiment of this application, after the second thread performs a second monitoring of the state of the cache space, the method further includes: if the cache space is in an empty state, then continuously performing a second monitoring of the state of the cache space; when the cache space is detected to be updated from an empty state to a full state or a non-empty and non-full state, writing the cached data to be written to the storage medium.

[0012] In one embodiment of this application, a data writing device is also provided. The device is applied to a slave device, which includes at least a cache space and a storage medium. The device includes: a first monitoring module, configured to monitor the state of the cache space after receiving a write instruction for data to be written from a master device. The state of the cache space includes an empty state, a full state, or a non-empty and non-full state; a receiving module, configured to trigger the master device to send the data to be written if the cache space is in an empty state or a non-empty and non-full state, so as to receive and cache the data to be written through the cache space as cached data to be written; and a feedback module, configured to... After receiving and caching the data to be written, data reception is stopped and instruction execution information for the write instruction is generated. The instruction execution information is returned to the host to trigger the host to send the next write instruction for the next data to be written. The second monitoring module is used to perform a second monitoring of the state of the cache space. The writing module is used to write the cached data to be written to the storage medium if the cache space is in a full state or a non-empty and non-full state. The first monitoring module, the receiving module, and the feedback module are executed by the first thread, and the second monitoring module and the writing module are executed by the second thread.

[0013] In one embodiment of this application, a data writing system is also provided. The system includes a host and a slave device, the slave device including at least a cache space and a storage medium. The host is used to acquire a set of data to be written, split the set of data to be written into multiple sets of data to be written, and assign a write instruction to each set of data to be written. The host sends a write instruction for a set of data to be written to the slave device and monitors the data receiving enable / disable state of the slave device. If the slave device is in the data receiving enable state, the host sends the data to be written to the slave device. After receiving the instruction execution information of the write instruction from the slave device, the host sends the next write instruction for the next set of data to be written to the slave device and monitors the data receiving enable / disable state of the slave device. If the slave device is in the data receiving enable state, the host sends the next set of data to be written to the slave device, until all data to be written is written. After the data to be written has been sent, the slave device, upon receiving the write instruction via a first thread, performs a first monitoring of the state of the cache space, which includes an empty state, a full state, or a non-empty / non-full state. If the cache space is empty or non-empty / non-full, data reception is initiated, triggering the host to send the data to be written, so that the data to be written can be received and cached through the cache space as cached data to be written. After receiving and caching the data to be written, data reception is stopped and the instruction execution information is generated and returned to the host, triggering the host to send the next write instruction. The slave device performs a second monitoring of the state of the cache space via a second thread. If the cache space is full or non-empty / non-full, the cached data to be written is written to the storage medium.

[0014] In one embodiment of this application, an electronic device is also provided, the electronic device comprising: one or more processors; and a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the electronic device implements the data writing method as described above.

[0015] In one embodiment of this application, a computer-readable storage medium is also provided, on which a computer program is stored, which, when executed by a computer's processor, causes the computer to perform the data writing method described above.

[0016] The beneficial effects of this invention are as follows: This invention provides a data writing method, apparatus, system, electronic device, and storage medium. The data writing method receives write commands from the host via a first thread. When the buffer space is empty or neither empty nor full, it receives and buffers the data to be written. After receiving and buffering is complete, it stops receiving data and generates instruction execution information for the write command, returning it to the host to trigger the host to send the next write command for the next data to be written. When the buffer space is full or neither empty nor full, a second thread writes the buffered data to be written to the storage medium. By having the slave device immediately return instruction execution information after receiving the data to be written from the host and write the data to the storage medium, the host, upon receiving the instruction execution information, can initiate the transmission of the next data to be written. This allows the current data to be written to the storage medium and the next data to be written to be transmitted in parallel, thus achieving parallel operation of host data transmission and slave data writing. This fully utilizes the USB transmission bandwidth and improves the data writing rate.

[0017] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a data stream model for a bulk transfer protocol.

[0019] Figure 2 This is a timing diagram for serial operation of a master-slave machine that writes data via a bulk transfer protocol.

[0020] Figure 3 This is a schematic diagram illustrating the implementation environment of a data writing method according to an exemplary embodiment of this application;

[0021] Figure 4 This is a flowchart illustrating a data writing method in an exemplary embodiment of this application;

[0022] Figure 5 This is a timing diagram illustrating the parallel operation of the master and slave machines during data writing, as shown in a specific embodiment of this application.

[0023] Figure 6 This is a schematic diagram of a circular buffer shown in a specific embodiment of this application;

[0024] Figure 7 This is a flowchart illustrating the first thread of a specific embodiment of this application;

[0025] Figure 8 This is a flowchart illustrating the workflow of the second thread according to a specific embodiment of this application;

[0026] Figure 9This is a timing diagram illustrating the parallel operation of the master and slave machines during data writing, as shown in another specific embodiment of this application;

[0027] Figure 10 This is a block diagram illustrating a data writing device in an exemplary embodiment of this application;

[0028] Figure 11 This is a block diagram illustrating a data writing system in an exemplary embodiment of this application;

[0029] Figure 12 This is a schematic diagram illustrating the structure of an electronic device as shown in an exemplary embodiment of this application. Detailed Implementation

[0030] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0031] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0032] It should be noted that in this application, terms such as "first" and "second" are merely for distinguishing similar objects, and do not limit the order or sequence of similar objects. The variations of "including" and "having" indicate that the scope covered by the subject of the word is not exclusive, except for the examples shown by the word.

[0033] It is understood that the various numerical designations, step numbers, and other identifiers recorded in this application are for descriptive convenience and are not intended to limit the scope of this application. The size of the identifiers in this application does not imply the order of execution; the execution order of each process should be determined by its function and internal logic.

[0034] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the present application. However, it will be apparent to those skilled in the art that embodiments of the present application may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the present application.

[0035] Please see Figure 1 , Figure 1 This is a schematic diagram of a data stream model for a bulk transfer protocol. For example... Figure 1 As shown, the data flow of the bulk transfer protocol includes a command phase, a data phase, and a status phase. For the data writing process, in the command phase, the host issues a Command Block Wrapper (CBW) data packet requesting data to be written. In the data phase, the host sends data to the slave device via an OUT (output) transaction, where an OUT transaction refers to the process of the host sending data to a peripheral device. In the status phase, after the slave device finishes receiving the data, it writes the data to the storage medium and then sends a Command Status Wrapper (CSW) data packet to notify the host of the command execution status. These three phases represent a serial operation mode. Please refer to [link to relevant documentation]. Figure 2 , Figure 2 This is a timing diagram for a master-slave serial operation that writes data using a bulk transfer protocol. (Example:) Figure 2 As shown, the master sends a write command and transmits data via an OUT transaction. After the data transmission is complete, the slave begins writing the data to the storage medium. At this point, the master is in an idle, waiting state. After the data writing is complete, the slave sends a CSW data packet. The master must receive the CSW data packet to confirm the write command execution status before initiating the next transmission, i.e., sending the next write command and transmitting the next data via an OUT transaction. During the data phase, the slave needs to write data to the storage medium, such as an SD (Secure Digital) card or SPI (Serial Peripheral Interface) Flash memory. Since writing data to the storage medium is time-consuming, the master is in a waiting state, which affects the data write rate, causing a significant reduction in the data write speed and wasting USB transmission bandwidth.

[0036] To address these issues, embodiments of this application provide a data writing method, a data writing device, a data writing system, an electronic device, a computer-readable storage medium, and a computer program product, which will be described in detail below.

[0037] Please see Figure 3 , Figure 3 This is a schematic diagram illustrating the implementation environment of a data writing method according to an exemplary embodiment of this application.

[0038] like Figure 3As shown, the implementation environment may include a host 310 and a slave 320. The slave 320 includes at least a cache space and a storage medium. The host 310 may be a computer, microprocessor, microcontroller, smart TV, etc., while the slave 320 may be a USB flash drive, external hard drive, or other MSC devices, or devices with built-in large-capacity storage space or MSC, such as computers, microprocessors, microcontrollers, tablets, mobile phones, smart TVs, smartwatches, etc. No restrictions are placed here. When the host 310 has a set of data to be written, it splits the set into multiple data sets and assigns a write instruction to each data set. The write instruction for each data set is sent to the slave 320, enabling the slave 320 to receive and write the data, thus achieving data writing.

[0039] Schematic, after receiving a write instruction for data to be written from the host 310 via the first thread, the slave device 320 performs a first monitoring of the cache space status, which includes an empty state, a full state, or a non-empty / non-full state. If the cache space is in an empty state or a non-empty / non-full state, the host 310 is triggered to send the data to be written, so that the data to be written can be received and cached in the cache space as a cached data to be written. After receiving and caching the data to be written, the slave device stops receiving data and generates instruction execution information for the write instruction, and returns the instruction execution information to the host 310 to trigger the host 310 to send the next write instruction for the next data to be written. The slave device 320 performs a second monitoring of the cache space status via the second thread. If the cache space is in a full state or a non-empty / non-full state, the cached data to be written is written to the storage medium. As can be seen, the technical solution of this application embodiment enables the slave device to immediately return instruction execution information after receiving the data to be written sent by the master device, and write the data to be written to the storage medium. After receiving the instruction execution information, the master device can start the transmission of the next data to be written, so that the current data to be written to the storage medium and the next data to be written can be transmitted in parallel. This achieves the parallel operation of the master device sending data and the slave device writing data, which can make full use of the USB transmission bandwidth and improve the data writing rate.

[0040] It should be noted that the data writing method provided in this application embodiment is generally executed by the slave device 320, and correspondingly, the data writing device is generally set in the slave device 320.

[0041] Please see Figure 4 , Figure 4 This is a flowchart illustrating a data writing method in an exemplary embodiment of this application. This data writing method can be applied to... Figure 3The implementation environment shown is specifically executed by slave device 320 within that implementation environment. It should be understood that this data writing method can also be applied to other exemplary implementation environments and specifically executed by devices in other implementation environments. This embodiment does not limit the implementation environment to which this data writing method is applicable.

[0042] like Figure 4 As shown, in an exemplary embodiment, the data writing method is applied to a slave device, which includes at least a cache space and a storage medium. The data writing method includes at least steps S410 to S440, which are described in detail below:

[0043] Step S410: After receiving a write instruction for data to be written from the host via the first thread, the status of the cache space is monitored for the first time.

[0044] In one embodiment of this application, the first thread of the slave device is mainly responsible for USB communication with the host, receiving data to be written and caching it in the cache space. When the host has a set of data to be written, it splits the set into multiple data sets and assigns a write instruction to each data set. The slave device sends a write instruction for one data set to be written to the slave device and starts an OUT transaction, waiting for the slave device to receive the write instruction and enable the OUT transaction. After the slave device enables the OUT transaction, the host starts sending the data to be written. The slave device can passively receive the write instructions sent by the host through the first thread, or it can actively listen for the write instructions through the first thread. After receiving the write instruction sent by the host, the first thread performs a first monitoring of the state of the cache space. The state of the cache space includes an empty state, a full state, or a non-empty and non-full state. An empty state indicates that the cache space is empty and there is no cached data, which can be written but not read. A full state indicates that the cache space is full and can be read but not written. A non-empty and non-full state indicates that there is data in the cache space but the cache space is not full, which can be both written and read. For illustrative purposes, the first monitoring can be real-time or periodic, and the cache space can be a double buffer or a circular buffer; there are no restrictions here.

[0045] In step S420, if the cache space is empty or neither empty nor full, the host is triggered to send data to be written, so as to receive and cache the data to be written through the cache space as cached data to be written.

[0046] In one embodiment of this application, if the slave device detects through the first thread that the cache space is empty or neither empty nor full, it indicates that the cache space is not full and data can be written. The slave device can then enable OUT transaction data reception through the first thread to trigger the master device to send the data to be written through OUT transaction data. Subsequently, the slave device caches the data to be written received in real time into the cache space through the first thread, and uses the cached data to be written in the cache space as cached data to be written.

[0047] It should be understood that if the data to be written in the current cache is the first data to be written in this data writing process, then the number of data to be written in the current cache space is one. If the data to be written in the current cache is the data to be written after the first data to be written in this data writing process, then the number of data to be written in the current cache space may be one or more.

[0048] In one embodiment of this application, after the first monitoring of the state of the cache space, the method further includes: if the cache space is full, triggering the host to wait to send data to be written, and continuously monitoring the state of the cache space; when the cache space is detected to be updated from full to empty or neither empty nor full, triggering the host to send data to be written, so as to receive and cache the data to be written through the cache space as cache data to be written.

[0049] In this embodiment, when the first thread detects that the cache space is full, it indicates that the cache space is full and data cannot be written at this time. At this time, the slave device does not enable OUT transaction data reception, and the master device's OUT transaction data transmission will be automatically delayed. By continuously monitoring the status of the cache space, changes in the cache space can be detected in a timely manner so that data to be written can be cached promptly. When the cache space changes from full to empty or neither empty nor full, it indicates that all or part of the cache space has been released, and data can be written now. The master device can be immediately triggered to send the data to be written so that it can receive and cache the data to be written through the cache space, further improving caching efficiency.

[0050] It should be noted that the conditions that must be met for a USB OUT transaction transfer include:

[0051] 1. The host initiates OUT transaction data transmission;

[0052] 2. Enable slave device to receive OUT transaction data.

[0053] Therefore, the OUT transaction initiated by the master will only truly begin transmitting the data to be written after the master initiates OUT transaction data transmission and the slave enables OUT transaction data reception. After the slave finishes receiving the data to be written from the OUT transaction, it will automatically disable OUT transaction data reception. To receive new data to be written, the slave needs to re-enable OUT transaction data reception. Thus, by controlling the transmission rhythm of the master through the slave, it is possible to effectively avoid situations where the master and slave are out of sync, resulting in overflow or loss of data to be written.

[0054] Step S430: After receiving and caching the data to be written, stop receiving data and generate instruction execution information for the write instruction. Return the instruction execution information to the host to trigger the host to send the next write instruction for the next data to be written.

[0055] In one embodiment of this application, after the slave device has finished receiving and caching the current data to be written, it can disable the OUT transaction data reception through the first thread to stop data reception and generate a CSW data packet of the write instruction, i.e., instruction execution information, to return to the host to notify the host of the instruction execution status. After receiving the instruction execution status, the host can immediately generate the next write instruction for the next data to be written and send it to the slave device to perform the transmission of the next data to be written.

[0056] It's important to note that after the master receives the slave's CSW data packet, it assumes the slave has finished processing the data to be written and can initiate the next instruction transmission. However, in reality, when the slave replies with the CSW data packet, the data in the write buffer is not yet fully written to the storage medium. If the master issues other non-write instructions, such as read instructions, the slave will buffer these instructions but will not process them. Only after the slave has written all the data in the write buffer to the storage medium and the buffer space is empty will it process the other buffered non-write instructions. This avoids the possibility of data errors caused by executing other non-write instructions before the write operation is complete, ensuring the correctness of all instruction execution and data integrity.

[0057] Step S440: The second thread performs a second monitoring of the cache space status. If the cache space is full or neither empty nor full, the cached data to be written is written to the storage medium.

[0058] In one embodiment of this application, the second thread of the slave device is mainly responsible for writing the data to be written to the storage medium, that is, retrieving the data to be written from the cache space as cache data to be written and writing it to the storage medium. First, the slave device performs a second detection on the status of the cache space through the second thread. If the cache space is detected to be full or neither empty nor full, it indicates that the cache space is not empty, that is, the cache space currently has readable cache data to be written. Then, the second thread reads the cache data to be written from the cache space and writes it to the storage medium. Illustratively, the second detection can be real-time or periodic, and the storage medium can be the slave device's SD card, SPI Flash, disk, optical disk, solid-state drive, etc., without limitation.

[0059] In one embodiment of this application, after the second thread performs a second monitoring of the state of the cache space, the method further includes: if the cache space is in an empty state, then continuously perform a second monitoring of the state of the cache space; when the cache space is detected to be updated from an empty state to a full state or a non-empty and non-full state, write the cached data to be written to the storage medium.

[0060] In this embodiment, when the second thread detects that the cache space is empty, it indicates that the cache space is empty, meaning there is currently no cached data to be read and written. By continuously monitoring the state of the cache space, changes in the cache space can be detected in a timely manner, allowing for the timely reading of cached data to be written. When the cache space changes from empty to full or neither empty nor full, it indicates that there is currently cached data to be written that can be read and written immediately. This allows the cache space to be released in a timely manner to write new data to be written, further improving the utilization rate of the cache space.

[0061] For MSC devices, such as USB flash drives, when the host writes a large file, it breaks it down into multiple write commands. When the USB flash drive acts as a slave, working in parallel with the first and second threads, the data transmission and writing can be transformed from a serial to a parallel operation. Furthermore, since one of the data transmission or writing operations operates at full bandwidth, the write efficiency is significantly improved. Assuming the slave's write time to the storage medium is the same as the USB data transfer time, the solution in this embodiment can increase the file write speed of the MSC device by approximately 100%.

[0062] As an illustration, the slave device can use an RTOS (Real-Time Operating System) to implement the parallel operation of the first and second threads described above.

[0063] Please see Figure 5 , Figure 5This is a timing diagram illustrating the parallel operation of the master and slave machines during data writing, as shown in a specific embodiment of this application. Figure 5 As shown, when the master has multiple data items to be written, it sends a write command to the slave. Upon receiving the write command via its first thread, the slave enables OUT transaction data reception, triggering the master to send the data to be written via an OUT transaction. After receiving the data through its cache, the slave immediately returns a CSW data packet. Simultaneously, the slave reads the received data from the cache and writes it to the storage medium via its second thread. Upon receiving the CSW data packet, the master can immediately initiate the next data transmission or transfer, enabling parallel operation of master data transmission and slave data writing. This effectively shortens the data transmission time and improves data writing efficiency, especially in scenarios with large amounts of data to be written, where the improvement in data writing efficiency is even more significant.

[0064] In one embodiment of this application, before performing the first and / or second monitoring of the state of the cache space, the method includes: pre-dividing the cache space to obtain at least three cache areas; configuring corresponding index values ​​for each cache area in sequence, wherein the index value of the first cache area is determined as the starting index value, the index value corresponding to the last cache area is determined as the ending index value, and the starting index value is less than the ending index value.

[0065] For example, to facilitate monitoring of the cache space status, a FIFO (First In First Out) method can be used to cache the data to be written. The slave device can prepare a Ring Buffer in advance to cache the data to be written sent by the master device. The depth of the Ring Buffer needs to be greater than or equal to 3. Based on this, the slave device's Ring Buffer is pre-divided into at least three buffers, and each buffer is configured with a corresponding index value in sequence. The starting index value is less than the ending index value, and the index difference between adjacent buffers is 1 (except for the first and last buffers). For example, the index value of the first buffer is 0, the index value of the second buffer is 1, the index value of the third buffer is 2, and so on, increasing sequentially. Of course, the starting index value can also be other values, which is not restricted here.

[0066] In one embodiment of this application, the state of the cache space is monitored in a first and / or second manner, including: real-time acquisition of the head index and tail index of the cache queue in the cache space, the cache queue being formed based on all cached data to be written in the cache space, the head index representing the index value of the cache area where the head of the cache queue is located, and the tail index representing the index value of the cache area where the tail of the cache queue is located; if the tail index is equal to the head index, the cache space is determined to be empty; if the tail index is not equal to the head index and is less than the end index value, the value of the tail index plus one is determined, and if the value of the tail index plus one is equal to the head index, the cache space is determined to be full, and if the value of the tail index plus one is not equal to the head index, the cache space is determined to be neither empty nor full; if the tail index is not equal to the head index and is equal to the end index value, the starting index value is compared with the head index, and if the starting index value is equal to the head index, the cache space is determined to be full, and if the starting index value is not equal to the head index, the cache space is determined to be neither empty nor full.

[0067] In this embodiment, when caching data to be written using a FIFO (First-In, First-Out) approach, all cached data to be written in the cache space forms a cache queue according to the cache order. Data to be written to the cache space is added to the cache queue, and data to be written to the cache space is read from the cache space and leaves the cache queue. The Rear index of the cached data is used to indicate which buffer the data to be written sent by the host is stored in, and the Front index is used to indicate which buffer the data to be written is read from to be written to the storage medium. The Rear index is updated as data is written to the cache space, and the Front index is updated as data is read from the cache space. Therefore, the Front and Rear indices can be obtained in real time, and the state of the cache space can be determined based on the real-time obtained Front and Rear indices. If the Rear index is equal to the Front index, the cache space is determined to be empty, that is, the cache space is in an empty state. If the tail index is not equal to the head index, further determine if the tail index has reached the last buffer. If the tail index is less than the end index, it means the tail index has not yet reached the last buffer. After writing data, the tail index will be incremented by one. Therefore, we can calculate the value of the tail index after incrementing it. If the value of the tail index after incrementing it is equal to the head index, the buffer space is determined to be full. Otherwise, the buffer space is determined to be neither empty nor full. If the tail index is equal to the end index, it means the tail index has reached the last buffer. After writing data, the tail index will be updated to the start index. Therefore, we can directly compare the start index with the head index. If the start index is equal to the head index, the buffer space is determined to be full. Otherwise, the buffer space is determined to be neither empty nor full.

[0068] Please see Figure 6 , Figure 6This is a schematic diagram of a circular buffer shown in a specific embodiment of this application. Figure 6 As shown, the Ring Buffer has a depth of 3, meaning it is divided into three buffers: BUF0, BUF1, and BUF2. BUF is an abbreviation for Buffer, and 0, 1, and 2 are the indices of each buffer. Rear is the tail of the buffer queue, and Front is the head. When the Front index equals the Rear index, the Ring Buffer is empty. When the Rear index plus 1 (which, if the result is greater than or equal to the Ring Buffer's depth, or greater than the end index, is set to 0) equals the Front index, the Ring Buffer is full.

[0069] In one embodiment of this application, receiving and caching data to be written through a cache space includes: after receiving the data to be written sent by the host, caching the received data to be written to the cache area pointed to by the tail index according to the tail index; after caching the received data to be written to the cache area pointed to by the tail index, updating the tail index; wherein, the step of updating the tail index includes comparing the tail index with the end index value; if the tail index is less than the end index value, incrementing the tail index by one; if the tail index is equal to the end index value, setting the tail index to the start index value.

[0070] For example, such as Figure 6 As shown, the Rear index is used to indicate which buffer the data to be written sent by the host is stored in. After the data to be written is stored in the buffer, the Rear index is incremented by 1. When the incremented value is greater than or equal to the depth of the Ring Buffer, or when the incremented value is greater than the end index value, the Rear index is set to 0.

[0071] By caching the received data to be written to the cache area pointed to by the tail index, and updating the tail index after the data to be written is completed, the data to be written is cached in order. This can effectively avoid the disorder of data writing order and prevent the data to be written later from overwriting the data to be written earlier that has not yet been read, so as to avoid data loss and ensure the order and integrity of the data to be written.

[0072] In one embodiment of this application, writing cached data to be written to a storage medium includes: reading cached data to be written from the cache area pointed to by the head index and writing it to the storage medium according to the head index; after writing the read cached data to be written to the storage medium, releasing the cache area pointed to by the head index and updating the head index; wherein, the step of updating the head index includes comparing the head index with the end index value; if the head index is less than the end index value, incrementing the head index by one; if the head index is equal to the end index value, setting the head index to the start index value.

[0073] For example, such as Figure 6 As shown, the Front index is used to indicate which buffer the slave device reads the data to be written from and writes it to the storage medium. After the data to be written from the buffer is read and written to the storage medium is completed, the Front index is incremented by 1. When the incremented value is greater than or equal to the depth of the Ring Buffer, or when the incremented value is greater than the end index value, the Front index is set to 0.

[0074] By reading the cached data to be written from the cache area pointed to by the head index, and after writing the read cached data to the storage medium, releasing the cache area pointed to by the head index and updating the head index, the cached data to be written is read in order. This not only effectively avoids data reading disorder and ensures that the cached data to be written is written to the storage medium in an orderly manner, but also enables the cyclical use of cache space. When new data to be written arrives, the released cache area can be reused, improving the utilization rate of cache space.

[0075] Please see Figure 7 , Figure 7 This is a flowchart illustrating the first thread of a specific embodiment of this application.

[0076] like Figure 7 As shown, the workflow of the first thread is as follows:

[0077] 1. After receiving the host CBW write command, the first thread will first check whether the Ring Buffer is full;

[0078] 2. If the Ring Buffer is not full, i.e., it is empty or neither empty nor full, it indicates that the Ring Buffer has space to buffer the data to be written sent by the host. At this time, OUT transaction data reception is enabled, triggering the host to start an OUT transaction to transmit data. After the transmission is completed, CSW data is sent. After the host receives the CSW data, it can start the next write operation.

[0079] 3. If the Ring Buffer is full, it means there is no space to buffer the data to be written from the host. The second thread needs to retrieve the buffered data and write it to storage before releasing the buffer. After the second thread releases the buffer, the Ring Buffer changes from full to partially full, and the first thread continues execution. This enables OUT transaction data reception, triggering the host to start an OUT transaction to transmit data. After the transmission is complete, CSW data is sent. Upon receiving the CSW data, the host can initiate the next write operation.

[0080] Please see Figure 8 , Figure 8 This is a flowchart illustrating the workflow of the second thread in a specific embodiment of this application.

[0081] like Figure 8 As shown, the workflow of the second thread is as follows:

[0082] 1. The second thread only checks if the Ring Buffer is empty;

[0083] 2. If the Ring Buffer is not empty, that is, the Ring Buffer is in a full state or a state that is neither empty nor full, it indicates that there is cached data to be written in the Ring Buffer. At this time, the cached data to be written in the Buffer is read out and written to the storage medium, and the Buffer is released after reading and writing are completed.

[0084] 3. If the Ring Buffer is empty, it means that there is no cached data to be written in the Ring Buffer or the data to be written has not been cached yet. It is necessary to wait for the data to be written to be cached into the Ring Buffer and cached completely.

[0085] As can be seen, for the slave device, the first thread is equivalent to the data "producer," and the second thread is equivalent to the data "consumer," working together in parallel. This collaborative parallel operation mode allows the writing of data to the storage medium and the USB data transfer to be written to the data to be written to occur in parallel, thereby improving the overall efficiency of the write operation.

[0086] like Figure 5 The master-slave parallel operation timing shown indicates that when the slave writes the data to be written to the storage medium in a time less than the transmission time of the OUT transaction data, the second thread "consumes" data faster than the first thread "produces" data, and the RingBuffer will never be full.

[0087] In one specific embodiment of this application, using Figure 6 The circular buffer shown is an example:

[0088] 1. In the initial state, the front index and rear index of the Ring Buffer are both 0, and the Ring Buffer is empty.

[0089] 2. When the first thread of the slave device receives the CBW write command, it determines that the Ring Buffer is not full, enables OUT transaction data reception, and BUF0 receives the data to be written from the master. After receiving and buffering the data, the Rear index is set to 1, and a CSW data packet is sent back. During this period, the second thread determines that the Ring Buffer is not empty and begins to retrieve the data to be written from the buffer of BUF0 and write it to the storage medium. After this step is completed, the Rear index is 1, and the Front index is 0.

[0090] 3. When the first thread of the slave device receives the CBW write command again, it determines that the Ring Buffer is not full, enables OUT transaction data reception, and BUF1 receives the data to be written from the master. After receiving and buffering the data, the Rear index is set to 2, and a CSW data packet is sent back. During this period, the second thread has retrieved the data to be written from BUF0 and written it to the storage medium, setting the Front index to 1. At this time, the second thread again determines that the Ring Buffer is not empty and begins to retrieve the data to be written from BUF1 and write it to the storage medium. After this step is completed, the Rear index is 2, and the Front index is 1.

[0091] 4. When the first thread of the slave device receives the CBW write command again, it determines that the Ring Buffer is not full, enables OUT transaction data reception, and BUF2 receives the data to be written from the master. After receiving and buffering the data, the Rear index is set to 0, and a CSW data packet is sent back. During this period, the second thread has retrieved the data to be written from BUF1 and written it to the storage medium, setting the Front index to 2. At this time, the second thread determines that the Ring Buffer is not empty and begins to retrieve the data to be written from BUF2 and write it to the storage medium. After this step is completed, the Rear index is 0, and the Front index is 2.

[0092] 5. Continue performing the above steps. (Combined with...) Figure 5 As shown, USB transmission operates at full bandwidth, eliminating the waiting time for the slave device to write the cached data to the storage medium after the host sends the data to be written. Therefore, the data transfer efficiency of write operations is very high.

[0093] If the time it takes for the slave device to write the data to be written to the storage medium is greater than or equal to the transmission time of the OUT transaction data, then the second thread "consumes" data slower than the first thread "produces" data, and the Ring Buffer may become full after a period of time. Please refer to [link / reference]. Figure 9 , Figure 9 This is a timing diagram illustrating the parallel operation of the master and slave machines during data writing, as shown in another specific embodiment of this application. Figure 9 As shown, when the Ring Buffer is full, there is no space in the Ring Buffer to receive the data to be written sent by the host OUT transaction. The slave will not enable OUT transaction data reception, and the host's OUT transaction transmission of the data to be written will be automatically delayed until the second thread retrieves the data to be written from the Ring Buffer and writes it to the storage medium. Only then will the first thread enable OUT transaction data reception so that the host's OUT transaction can transmit the data to be written.

[0094] In another specific embodiment of this application, with Figure 6 The circular buffer shown is an example:

[0095] 1. In the initial state, the front index and rear index of the Ring Buffer are both 0, and the Ring Buffer is empty.

[0096] 2. When the first thread of the slave device receives the CBW write command, it determines that the Ring Buffer is not full, enables OUT transaction data reception, and BUF0 receives the data to be written from the master. After receiving and buffering the data, the Rear index is set to 1, and a CSW data packet is sent back. During this period, the second thread determines that the Ring Buffer is not empty and begins to retrieve the data to be written from the buffer of BUF0 and write it to the storage medium. After this step is completed, the Rear index is 1, and the Front index is 0.

[0097] 3. When the first thread of the slave device receives the CBW write command again, it determines that the Ring Buffer is not full, enables OUT transaction data reception, and BUF1 receives the data to be written from the master. After receiving and buffering the data, the Rear index is set to 2, and a CSW data packet is sent back. During this period, the second thread has not yet finished retrieving the data to be written from the buffer in BUF0 and writing it to the storage medium, and continues writing to BUF0. After this step is completed, the Rear index is 2, the Front index is 0, and the Ring Buffer is full.

[0098] 4. When the slave's first thread receives the CBW write command again, it determines that the Ring Buffer is full and disables OUT transaction data reception. The data to be written by the master will be automatically delayed. After the second thread has retrieved the data to be written from the BUF0 buffer and written it to the storage medium, it releases BUF0, sets the Front index to 1, and begins retrieving the data to be written from the BUF1 buffer and writing it to the storage medium. At this time, the first thread determines that the Ring Buffer is not full and enables OUT transaction data reception. The master's OUT transaction will begin transmitting the data to be written. BUF2 will receive the data to be written from the master, and after receiving and buffering it, the Rear index will be set to 0, and a CSW data packet will be sent back. After this step, the Rear index is 0, the Front index is 1, and the Ring Buffer is full.

[0099] 5. When the slave's first thread receives the CBW write command again, it determines that the Ring Buffer is full and disables OUT transaction data reception. The data to be written by the master will be automatically delayed. After the second thread has retrieved the data to be written from the BUF1 buffer and written it to the storage medium, it releases BUF1, sets the Front index to 2, and begins retrieving the data to be written from the BUF2 buffer and writing it to the storage medium. At this time, the first thread determines that the Ring Buffer is not full and enables OUT transaction data reception. The master's OUT transaction will begin transmitting the data to be written. BUF0 will receive the data to be written from the master, and after receiving and buffering it, the Rear index will be set to 1, and a CSW data packet will be replied. After this step, the Rear index is 1, the Front index is 2, and the Ring Buffer is full.

[0100] 6. Continue performing the above steps. (Combined with...) Figure 9 As shown, when the write storage medium is operating at full bandwidth, USB data transfer and writing to the storage medium still work in parallel, and its maximum speed is determined by the speed of the write storage medium.

[0101] As can be seen, the specific embodiments of this application enable parallel operation of writing to the storage medium and USB data transmission. Regardless of whether the writing time to the storage medium and the USB data transmission time are equal, the write operation can operate in the most efficient state, that is, the USB data transmission bandwidth or the writing storage medium bandwidth is fully utilized. Compared with the serial operation of USB data transmission and writing to the storage medium, the write operation efficiency is significantly improved.

[0102] In one embodiment of this application, a data transmission method is also provided. The method is applied to a host and includes: the host acquiring a set of data to be written, splitting the set of data to be written into multiple data to be written, and assigning a write instruction to each data to be written; sending a write instruction for a data to be written to a slave device, and monitoring the data reception enable / disable state of the slave device; if the slave device is in the data reception enable state, sending the data to be written to the slave device so that the slave device writes the data to be written to the storage medium; after receiving the instruction execution information of the write instruction from the slave device, sending the next write instruction for the next data to be written to the slave device, and monitoring the data reception enable / disable state of the slave device; if the slave device is in the data reception enable state, sending the next data to be written to the slave device, until all data to be written is sent, wherein the instruction execution information is generated by the slave device after receiving and caching the data to be written. This embodiment controls the slave device to immediately return instruction execution information after receiving the data to be written from the master device. This allows the master device to start the transmission of the next data to be written after receiving the instruction execution information, so that the current data to be written to the storage medium and the next data to be written can be transmitted in parallel. This achieves parallel operation of the master device sending data and the slave device writing data, which can make full use of the USB transmission bandwidth and improve the data writing rate.

[0103] Please see Figure 10 , Figure 10 This is a block diagram illustrating a data writing apparatus according to an exemplary embodiment of this application. The apparatus can be applied to… Figure 3 The implementation environment shown is specifically configured in slave device 320. This device can also be applied to other exemplary implementation environments and specifically configured in other devices. This embodiment does not limit the implementation environment to which the device is applicable.

[0104] like Figure 10As shown, this exemplary data writing device is applied to a slave device, wherein the slave device includes at least a cache space and a storage medium. The device includes: a first monitoring module 1010, configured to perform a first monitoring of the state of the cache space after receiving a write instruction for data to be written sent by the master, the state of the cache space including an empty state, a full state, or a non-empty and non-full state; a receiving module 1020, configured to trigger the master to send the data to be written if the cache space is in an empty state or a non-empty and non-full state, so as to receive and cache the data to be written through the cache space as a cached data to be written; and a feedback module 1030, configured to, upon receiving and caching the data to be written... After writing data, data reception is stopped and instruction execution information for the write instruction is generated. The instruction execution information is returned to the host to trigger the host to send the next write instruction for the next data to be written. The second monitoring module 1040 is configured to perform a second monitoring of the status of the cache space. The write module 1050 is configured to write the cached data to be written to the storage medium if the cache space is in a full state or a state that is neither empty nor full. The first monitoring module 1010, the receiving module 1020 and the feedback module 1030 are executed by the first thread, and the second monitoring module 1040 and the write module 1050 are executed by the second thread.

[0105] It should be noted that the apparatus and method provided in the above embodiments belong to the same concept, and the specific ways in which each module and unit performs operations have been described in detail in the method embodiments, and will not be repeated here. In practical applications, the apparatus provided in the above embodiments can be assigned to different functional modules as needed, that is, the internal structure of the apparatus can be divided into different functional modules to complete all or part of the functions described above, and this is not a limitation.

[0106] Please see Figure 11 , Figure 11 This is a block diagram illustrating a data writing system as shown in an exemplary embodiment of this application. The system can be applied to... Figure 3 The implementation environment shown can also be applied to other exemplary implementation environments. This embodiment does not limit the implementation environment to which the device is applicable.

[0107] like Figure 11 As shown, the exemplary data writing system includes a host 1110 and a slave 1120, wherein the slave includes at least a cache space 1121 and a storage medium 1122;

[0108] The host 1110 is used to acquire the set of data to be written, split the set of data to be written into multiple data to be written, and assign a write instruction to each data to be written; it sends the write instruction of one data to be written to the slave 1120 and monitors the data receiving start / stop status of the slave 1120. If the slave 1120 is in the data receiving start / stop state, the data to be written is sent to the slave 1120; after receiving the instruction execution information of the write instruction from the slave 1120, it sends the next write instruction of the next data to be written to the slave 1120 and monitors the data receiving start / stop status of the slave 1120. If the slave 1120 is in the data receiving start / stop state, the next data to be written is sent to the slave 1120, until all data to be written has been sent.

[0109] After receiving a write instruction via the first thread, slave device 1120 performs a first monitoring of the state of cache space 1121, which includes an empty state, a full state, or a non-empty / non-full state. If cache space 1121 is in an empty state or a non-empty / non-full state, data reception is initiated, triggering host 1110 to send data to be written, which is then received and cached in cache space 1121 as cached data to be written. After receiving and caching the data to be written, data reception is stopped and instruction execution information is generated and returned to host 1110 to trigger host 1110 to send the next write instruction. The second thread performs a second monitoring of the state of cache space 1121. If cache space 1121 is in a full state or a non-empty / non-full state, the cached data to be written in cache space 1121 is written to storage medium 1122.

[0110] This embodiment also provides an electronic device, including: one or more processors; and a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the electronic device enables the data writing method provided in the above embodiments.

[0111] Please see Figure 12 , Figure 12 This is a schematic diagram illustrating the structure of an electronic device according to an exemplary embodiment of this application. It should be noted that... Figure 12 The electronic device 1200 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0112] like Figure 12 As shown, the electronic device 1200 includes a processor 1201, a memory 1202, and a communication bus 1203; the communication bus 1203 is used to connect the processor 1201 and the memory 1202; the processor 1201 is used to execute a computer program stored in the memory 1202 to implement one or more methods as described in the above embodiments.

[0113] This embodiment also provides a computer-readable storage medium storing a computer program thereon. When executed by a computer's processor, the computer program causes the computer to perform the data writing method as described above. This computer-readable storage medium may be included in the electronic device described in the above embodiments, or it may exist independently and not assembled into the electronic device.

[0114] This embodiment also provides a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the data writing methods provided in the various embodiments described above.

[0115] The electronic device provided in this embodiment includes a processor, a memory, a transceiver, and a communication interface. The memory and the communication interface are connected to the processor and the transceiver and complete communication between them. The memory is used to store computer programs, the communication interface is used to perform communication, and the processor and the transceiver are used to run the computer programs, so that the electronic device performs the various steps of the above method.

[0116] In this embodiment, the memory may include random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage device.

[0117] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0118] As will be understood by those skilled in the art, the computer-readable storage medium described in this embodiment allows for the implementation of all or part of the steps in the above method embodiments by computer program-related hardware. The aforementioned computer program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM (Read-Only Memory), RAM (Random Access Memory), magnetic disks, or optical disks.

[0119] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A data writing method, characterized in that, The method is applied to a slave device, the slave device including at least a cache space and a storage medium, and the method includes: The cache space is pre-divided into at least three cache areas; each cache area is configured with a corresponding index value in sequence, wherein the index value of the first cache area is determined as the starting index value, and the index value corresponding to the last cache area is determined as the ending index value, wherein the starting index value is less than the ending index value; After receiving a write instruction for data to be written from the host by the first thread, the state of the cache space is monitored for the first time. The state of the cache space includes empty state, full state, or neither empty nor full state. If the cache space is empty or neither empty nor full, the host is triggered to send the data to be written, so that the data to be written can be received and cached through the cache space as cached data to be written. After receiving and caching the data to be written, data reception is stopped and instruction execution information for the write instruction is generated. The instruction execution information is then returned to the host to trigger the host to send the next write instruction for the next data to be written. The second thread performs a second monitoring of the state of the cache space. If the cache space is in a full state or a non-empty and non-full state, the cached data to be written is written to the storage medium. The monitoring methods for the first and second monitoring include: real-time acquisition of the head index and tail index of the cache queue in the cache space, wherein the cache queue is formed based on all cached data to be written in the cache space, the head index represents the index value of the cache area where the head of the cache queue is located, and the tail index represents the index value of the cache area where the tail of the cache queue is located; if the tail index is equal to the head index, the cache space is determined to be empty; if the tail index is not equal to the head index and is less than the end index value, the value of the tail index plus one is determined; if the value of the tail index plus one is equal to the head index, the cache space is determined to be full; if the value of the tail index plus one is not equal to the head index, the cache space is determined to be neither empty nor full; if the tail index is not equal to the head index and is equal to the end index value, the starting index value is compared with the head index; if the starting index value is equal to the head index, the cache space is determined to be full; if the starting index value is not equal to the head index, the cache space is determined to be neither empty nor full.

2. The data writing method according to claim 1, characterized in that, Receiving and caching the data to be written through the cache space includes: After receiving the data to be written sent by the host, the received data to be written is cached in the cache area pointed to by the tail index according to the tail index; After caching the received data to be written to the cache area pointed to by the tail index, the tail index is updated. The steps for updating the tail index include: The tail index is compared with the end index value. If the tail index is less than the end index value, the tail index is incremented by one. If the tail index is equal to the end index value, the tail index is set to the start index value.

3. The data writing method according to claim 1, characterized in that, Writing the cached data to be written to the storage medium from the cache space includes: According to the head-of-line index, read the cached data to be written from the cache area pointed to by the head-of-line index and write it to the storage medium; After writing the read cached data to the storage medium, the cache area pointed to by the head index is released, and the head index is updated. The steps for updating the head-of-queue index include: The head index is compared with the end index value. If the head index is less than the end index value, the head index is incremented by one. If the head index is equal to the end index value, the head index is set to the start index value.

4. The data writing method according to any one of claims 1-3, characterized in that, After performing the first monitoring of the state of the cache space, the method further includes: If the cache space is full, the host is triggered to wait to send the data to be written, and the status of the cache space is continuously monitored. When the cache space is detected to change from a full state to an empty state or a non-empty / non-full state, the host is triggered to send the data to be written, so that the data to be written can be received and cached through the cache space as cached data to be written.

5. The data writing method according to any one of claims 1-3, characterized in that, After the second thread performs a second monitoring of the state of the cache space, the method further includes: If the cache space is empty, the status of the cache space will be continuously monitored in the second way. When the cache space is detected to change from an empty state to a full state or a non-empty / non-full state, the cached data to be written is written to the storage medium.

6. A data writing device, characterized in that, The device is applied to a slave device, the slave device including at least a cache space and a storage medium, the device comprising: The first monitoring module is used to perform a first monitoring of the state of the cache space after receiving a write instruction for data to be written from the host. The state of the cache space includes an empty state, a full state, or a non-empty and non-full state. The receiving module is used to trigger the host to send the data to be written if the cache space is empty or not empty and not full, so as to receive and cache the data to be written through the cache space as cached data to be written. The feedback module is used to stop receiving data and generate instruction execution information for the write instruction after receiving and caching the data to be written, and return the instruction execution information to the host to trigger the host to send the next write instruction for the next data to be written. The second monitoring module is used to perform a second monitoring of the status of the cache space; The write module is used to write the cached data to be written to the storage medium if the cache space is full or neither empty nor full. The first monitoring module, the receiving module, and the feedback module are executed by a first thread, while the second monitoring module and the writing module are executed by a second thread. The cache space is pre-divided into at least three cache areas, each cache area having a corresponding index value. The index value of the first cache area is the starting index value, and the index value of the last cache area is the ending index value. The starting index value is less than the ending index value. The monitoring methods for the first and second monitoring include: real-time acquisition of the head index and tail index of the cache queue in the cache space, wherein the cache queue is formed based on all cached data to be written in the cache space, the head index represents the index value of the cache area where the head of the cache queue is located, and the tail index represents the index value of the cache area where the tail of the cache queue is located; if the tail index is equal to the head index, the cache space is determined to be empty; if the tail index is not equal to the head index and is less than the end index value, the value of the tail index plus one is determined; if the value of the tail index plus one is equal to the head index, the cache space is determined to be full; if the value of the tail index plus one is not equal to the head index, the cache space is determined to be neither empty nor full; if the tail index is not equal to the head index and is equal to the end index value, the starting index value is compared with the head index; if the starting index value is equal to the head index, the cache space is determined to be full; if the starting index value is not equal to the head index, the cache space is determined to be neither empty nor full.

7. A data writing system, characterized in that, The system includes a host and a slave, and the slave includes at least a cache space and a storage medium; The host is used to acquire a set of data to be written, split the set of data to be written into multiple sets of data to be written, and assign a write instruction to each set of data to be written. A write command for data to be written is sent to the slave device, and the data receiving enable / disable status of the slave device is monitored. If the slave device is in the data receiving enable state, the data to be written is sent to the slave device. After receiving the instruction execution information of the write instruction from the slave device, the next write instruction for the next data to be written is sent to the slave device, and the data receiving start / stop status of the slave device is monitored. If the slave device is in the data receiving start / stop state, the next data to be written is sent to the slave device, until all data to be written is sent. The slave device, upon receiving the write instruction via the first thread, performs a first monitoring of the state of the cache space, which includes an empty state, a full state, or a non-empty / non-full state. If the cache space is empty or non-empty / non-full, data reception is initiated, triggering the host to send the data to be written, so that the data to be written can be received and cached through the cache space as cached data to be written. After receiving and caching the data to be written, data reception is stopped, and the instruction execution information is generated and returned to the host to trigger the host to send the next write instruction. The second thread performs a second monitoring of the state of the cache space. If the cache space is in a full state or a non-empty and non-full state, the cached data to be written is written to the storage medium. The cache space is pre-divided into at least three cache areas, each with a corresponding index value. The index value of the first cache area is the starting index value, and the index value of the last cache area is the ending index value. The starting index value is less than the ending index value. The monitoring methods for the first and second monitoring include: real-time acquisition of the head index and tail index of the cache queue in the cache space, wherein the cache queue is formed based on all cached data to be written in the cache space, the head index represents the index value of the cache area where the head of the cache queue is located, and the tail index represents the index value of the cache area where the tail of the cache queue is located; if the tail index is equal to the head index, the cache space is determined to be empty; if the tail index is not equal to the head index and is less than the end index value, the value of the tail index plus one is determined; if the value of the tail index plus one is equal to the head index, the cache space is determined to be full; if the value of the tail index plus one is not equal to the head index, the cache space is determined to be neither empty nor full; if the tail index is not equal to the head index and is equal to the end index value, the starting index value is compared with the head index; if the starting index value is equal to the head index, the cache space is determined to be full; if the starting index value is not equal to the head index, the cache space is determined to be neither empty nor full.

8. An electronic device, characterized in that, The electronic device includes: One or more processors; A storage device for storing one or more programs, which, when executed by one or more processors, cause the electronic device to implement the data writing method as described in any one of claims 1-5.

9. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by the computer's processor, causes the computer to perform the data writing method as described in any one of claims 1-5.

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