Read, write and erase method for a memory

Abstract

A reading, writing and erasing method of memory, wherein the reading method comprises performing a first reading operation, obtaining a first reading result, the first reading operation comprising: applying a first voltage to a second word line connected with a first selection tube and a second selection tube in a storage unit to be read, applying a second voltage to a first word line and a third word line connected with a first storage tube and a second storage tube, and obtaining the first reading result; when the first reading result represents the storage data on the first storage tube and the second storage tube, ending the reading operation; when the first reading result does not represent the storage data on the first storage tube and the second storage tube, performing a second reading operation, and obtaining a second reading result. By obtaining the first reading current on the bit line end, the storage data on the first storage tube and the second storage tube is read at the same time, and the reading interference of the storage tube is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for reading, writing, and erasing a memory. Background Technology

[0002] SONOS (Silicon Oxide Nitride Oxide Silicon) technology, structurally speaking, mainly includes single-gate, multi-gate, and dual-gate technologies. With the development of mainstream process technologies and the urgent need for flash devices, multi-gate flash memory based on multi-gate structures has received widespread attention. Compared to traditional flash memory, multi-gate flash memory, as a type of flash memory, has gained more attention in both single-unit and embedded products due to its high programming speed and ability to completely avoid over-erasure.

[0003] However, the storage performance of current gate-separated memory needs to be improved. Summary of the Invention

[0004] The technical problem solved by this invention is to provide a method for reading, writing and erasing a memory to improve the storage performance of a gated memory.

[0005] To address the aforementioned technical problems, this invention provides a method for reading a memory, the memory comprising: a plurality of memory cells arranged in an array, each memory cell including a first word line, a second word line, a third word line, and a bit line; a first memory transistor, the gate of which is connected to the first word line, and one of its source or drain connected to the bit line; a first select transistor, the gate of which is connected to the second word line, and one of its source or drain connected to the other source or drain of the first memory transistor; a second select transistor, the gate of which is connected to the second word line, and one of its source or drain connected to the other source or drain of the first select transistor; and a second memory transistor, the gate of which is connected to the third word line, and one of its source or drain connected to the other source or drain of the second select transistor, the other source or drain connected to the bit line, the method comprising: performing a first read operation. The process involves obtaining a first read result. The first read operation includes: applying a first voltage to a second word line connected to the first and second select transistors in the memory cell to be read, so that the first and second select transistors are in a conducting state; applying a second voltage to the first and third word lines connected to the first and second memory transistors, so that a read current is generated in the first and second memory transistors; obtaining a first read current at the bit line terminal; and obtaining a first read result based on the first read current. If the first read result represents stored data on the first and second memory transistors, the read operation ends. If the first read result does not represent stored data on the first and second memory transistors, a second read operation is performed to obtain a second read result. The second read operation includes: continuing to obtain a second read current at the bit line terminal; and obtaining a second read result based on the second read current. The second read result represents stored data on the first and second memory transistors.

[0006] In one possible design, in another implementation of another aspect of the embodiments of this application, the first read result includes a first current, a second current, and a third current, wherein the first current is greater than the second current, and the third current is between the first current and the second current. Obtaining the first read result based on the first read current includes: in response to the first current at the bit line terminal, the stored data on the first memory tube and the second memory tube are both "0"; in response to the second current at the bit line terminal, the stored data on the first memory tube and the second memory tube are both "1"; and in response to the third current at the bit line terminal, continuing to obtain the second read result.

[0007] In one possible design, in another implementation of another aspect of the embodiments of this application, the method for obtaining the second read result based on the second read current includes: applying a third voltage to the third word line terminal, obtaining the second read current on the bit line terminal, wherein when the second read current is less than the third current, the stored data on the first memory tube is "1" and the stored data on the second memory tube is "0"; and when the second read current is equal to the third current, the stored data on the first memory tube is "0" and the stored data on the second memory tube is "1".

[0008] In one possible design, in another implementation of another aspect of the embodiments of this application, the reading method further includes: applying a second voltage to a first word line, a second word line, and a third word line connected to a non-read memory cell, and applying a floating voltage to a bit line connected to the non-read memory cell.

[0009] The present invention also provides a method for writing to a memory, the memory comprising: a plurality of memory cells arranged in an array, each memory cell including a first word line, a second word line, a third word line, and a bit line; a first memory transistor, the gate of which is connected to the first word line, and one of the sources or drains of which is connected to the bit line; a first select transistor, the gate of which is connected to the second word line, and one of the sources or drains of which is connected to the other source or drain of which is connected to the first memory cell; a second select transistor, the gate of which is connected to the second word line, and one of the sources or drains of which is connected to the other source or drain of which is connected to the first select transistor; and a second memory transistor, the gate of which is connected to the third word line, and one of the sources or drains of which is connected to the other source or drain of which is connected to the second select transistor; and a second memory cell... The other source or drain of the transistor is connected to the bit line, including: performing a first write operation, the first write operation method including: applying a first write negative voltage to a second word line connected to the memory cell to be written, applying a write positive voltage to a first word line or a third word line connected to the memory cell to be written, applying a first write negative voltage to a bit line connected to the memory cell to be written, so that a write current is generated in the memory cell to be written, so as to perform a first write operation on any row of memory cells in the memory, obtaining a write enable voltage on the memory cell to be written, and comparing the write enable voltage with a preset write enable voltage; when the write enable voltage is within the preset write enable voltage, the write operation is determined to be completed; when the write enable voltage is not within the preset write enable voltage, a second write operation is performed, the second write operation including: repeating the first write operation until the write enable voltage is within the preset write enable voltage.

[0010] In one possible design, in another implementation of another aspect of the embodiments of this application, the write enable voltage includes a first write enable voltage, the preset write enable voltage includes a first preset write enable voltage, and the method of obtaining the write enable voltage on the memory cell to be written and comparing the write enable voltage with the preset write enable voltage includes: after writing data "1", obtaining the first write enable voltage on the memory cell to be written, comparing the first write enable voltage with the first preset write enable voltage, when the first write enable voltage is greater than the first preset write enable voltage, the operation of writing data "1" is completed, when the first write enable voltage is less than or equal to the first preset write enable voltage, repeating the first write operation until the first write enable voltage is greater than the first preset write enable voltage.

[0011] In one possible design, in another implementation of another aspect of the embodiments of this application, the write enable voltage includes a second write enable voltage, the preset write enable voltage includes a second preset write enable voltage, and the method of obtaining the write enable voltage on the memory cell to be written and comparing the write enable voltage with the preset write enable voltage further includes: after writing data "0", obtaining the second write enable voltage on the memory cell to be written, comparing the second write enable voltage with the second preset write enable voltage, when the second write enable voltage is less than the second preset write enable voltage, the operation of writing data "0" is completed, when the second write enable voltage is greater than or equal to the second preset write enable voltage, repeating the first write operation until the second write enable voltage is less than the second preset write enable voltage.

[0012] In one possible design, in another implementation of another aspect of the embodiments of this application, the writing method further includes: applying a first write negative voltage to a second word line connected to a non-write memory cell, applying a second write negative voltage to a first word line and a third word line connected to a non-write memory cell, and applying a first write negative voltage to a bit line connected to a non-write memory cell.

[0013] The present invention also provides a method for erasing a memory, the memory comprising: a plurality of memory cells arranged in an array, each memory cell including a first word line, a second word line, a third word line, and a bit line; a first memory transistor, the gate of which is connected to the first word line, and one of its source or drain connected to the bit line; a first select transistor, the gate of which is connected to the second word line, and one of its source or drain connected to the other source or drain of the first memory transistor; a second select transistor, the gate of which is connected to the second word line, and one of its source or drain connected to the other source or drain of the first select transistor; and a second memory transistor, the gate of which is connected to the third word line, and one of its source or drain connected to the other source or drain of the second select transistor. The other source or drain of the second memory transistor is connected to the bit line. The erasure method includes: performing a first erasure operation, the first erasure operation including: applying a positive erasure voltage to a second word line connected to the memory cell to be erased, applying a negative erasure voltage to a first word line or a third word line connected to the memory cell to be erased, applying a positive erasure voltage to the bit line BL connected to the memory cell to be erased, performing a first erasure operation on any row of memory cells in the memory, obtaining the erasure enable voltage on the memory cell to be erased, and comparing the erasure enable voltage with a preset erasure enable voltage range; when the erasure enable voltage is within the preset erasure enable voltage range, the erasure operation is determined to be complete; when the erasure enable voltage is not within the preset erasure enable voltage range, a second erasure operation is entered, the second erasure operation including: repeating the first erasure operation until the erasure enable voltage is within the preset erasure enable voltage range.

[0014] In one possible design, in another implementation of another aspect of the embodiments of this application, the method of obtaining the erase enable voltage on the memory cell to be erased and comparing the erase enable voltage with a preset erase enable voltage range includes: if the erase enable voltage is greater than the preset erase enable voltage range, repeating the first erase operation until the erase enable voltage is within the preset erase enable voltage range; if the erase enable voltage is less than the preset erase enable voltage range, applying a compaction positive pressure to the first word line or the third word line connected to the memory cell to be erased until the erase enable voltage is within the preset erase enable voltage range.

[0015] In one possible design, in another implementation of another aspect of the embodiments of this application, the erasure method further includes: applying an erasure positive pressure to the second word line, the first word line, the third word line, and the bit line connected to the memory cell not to be erased.

[0016] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0017] The memory reading method provided by the present invention improves the reading efficiency of the memory cell and reduces reading interference between memory tubes by acquiring a first reading current at the bit line terminal. Furthermore, it determines whether the stored data on the first and second memory tubes has been read based on the first reading result. If the stored data on the first and second memory tubes has not been read, a second reading current is acquired at the bit line terminal, and the stored data on the first and second memory tubes is read again based on the second reading current, thus ensuring the accuracy of the reading.

[0018] Furthermore, by acquiring different values ​​of the read current at the bit line terminal, the stored data on the first and second memory transistors can be read. When the read current cannot clearly determine the stored data on the first and second memory transistors, the voltage at the bit line terminal is made to show a significant change trend by applying a half-off voltage (a third voltage) to the second memory transistor. Based on the change trend of the voltage at the bit line terminal, the different stored data on the first and second memory transistors can be acquired. This enables the simultaneous acquisition of stored data on the first and second memory transistors, improving the read efficiency of the memory cell, reducing read interference from memory transistors, and ensuring the accuracy of reading from different memory transistors.

[0019] The memory writing method provided by the present invention continuously acquires the write enable voltage on the memory cell to be written after writing different data, so that the write enable voltage on the memory cell to be written is within a preset write enable voltage, thereby reducing the dispersion of the write enable voltage and improving the storage performance of the memory.

[0020] The memory erasure method provided by the present invention continuously acquires the erase activation voltage on the memory cell to be erased and compares the erase activation voltage with a preset erase activation voltage range. When the erase activation voltage is within the preset erase activation voltage range, the erasure operation is determined to be complete. This reduces the dispersion of the erase activation voltage and improves the storage performance of the memory.

[0021] Furthermore, when the erase activation voltage is not within the preset erase activation voltage range, there is an over-erasing situation, that is, the erasure causes excessive loss of electrons on the floating gate, reducing the erase activation voltage, which leads to a false read of 1 during subsequent read operations. At this time, a compaction positive voltage is applied to the first word line or the third word line connected to the memory cell to be erased until the erase activation voltage is within the preset erase activation voltage range, that is, a portion of electrons are added to the floating gate, increasing the erase activation voltage to a normal value, reducing the dispersion of the erase activation voltage, and improving the storage performance of the memory. Attached Figure Description

[0022] Figure 1This is a flowchart illustrating the reading method in the technical solution of this invention;

[0023] Figure 2 This is a flowchart illustrating the writing method in the technical solution of this invention;

[0024] Figure 3 This is a flowchart illustrating the erasure method in the technical solution of this invention;

[0025] Figure 4 This is a schematic diagram of the memory structure in the technical solution of this invention;

[0026] Figure 5 This is a schematic diagram of the memory structure after entering the first read operation in the technical solution of this invention;

[0027] Figure 6 This is a schematic diagram of the memory structure after entering the second read operation in the technical solution of this invention;

[0028] Figure 7 This is a schematic diagram of the memory structure after the write operation in the technical solution of this invention;

[0029] Figure 8 This is a schematic diagram of the memory structure after entering the erase operation in the technical solution of this invention;

[0030] Figure 9 This is a schematic diagram of the semiconductor structure of the memory in the technical solution of this invention. Detailed Implementation

[0031] As mentioned in the background section, the storage performance of current gate-separated memory needs further improvement.

[0032] To reduce the size of memory cells, 2-bit split-gate flash memory has been widely researched and applied. Currently, 2-bit split-gate flash memory uses a single select gate to store two bits of data, enabling higher integration density. However, when reading data from one memory tube, this type of 2-bit split-gate flash memory requires turning off or on the other unselected memory tube, which causes significant read interference to the unselected memory tube and reduces the performance of the memory cell.

[0033] To address the aforementioned issues, the present invention provides a memory read, write, and erase method that simultaneously reads stored data from the first memory cell A1 and the second memory cell B1 by acquiring a first read current at the bit line BL terminal. This improves the read efficiency of the memory cell, reduces read interference from the memory cells, and determines whether the stored data on both the first memory cell A1 and the second memory cell B1 has been read based on the first read result. If the stored data on both memory cells A1 and B1 has not been read, a second read current is acquired at the bit line BL terminal, and the stored data on both memory cells A1 and B1 is read again based on the second read current, ensuring the accuracy of the read operation.

[0034] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0035] Figure 1 This is a flowchart illustrating the reading method in the technical solution of this invention.

[0036] Figure 4 This is a schematic diagram of the memory structure in the technical solution of this invention.

[0037] Please refer to Figure 1 as well as Figure 4 The present invention provides a method for reading a memory, the memory comprising: a plurality of arrayed memory cells 4, each memory cell 4 including a first word line WL1, a second word line WL2, a third word line WL3, and a bit line BL; a first memory transistor A1, the gate of the first memory transistor A1 being connected to the first word line WL1, and one of the source or drain of the first memory transistor A1 being connected to the bit line BL; and a first select transistor M1, the gate of the first select transistor M1 being connected to the second word line WL2, and one of the source or drain of the first select transistor M1 being connected to the bit line BL. The first memory transistor A1 has another source or drain; a second select transistor M2, the gate of which is connected to the second word line WL2, and one of the sources or drains of the second select transistor M2 is connected to the other source or drain of the first select transistor M1; a second memory transistor B1, the gate of which is connected to the third word line WL3, and one of the sources or drains of the second memory transistor B1 is connected to the other source or drain of the second select transistor M2, and the other source or drain of the second memory transistor B1 is connected to the bit line BL. The read method includes:

[0038] S101: Perform a first read operation and obtain a first read result. The first read operation includes: applying a first voltage to a second word line WL2 connected to the first selection transistor M1 and the second selection transistor M2 in the memory cell to be read, so that the first selection transistor M1 and the second selection transistor M2 are in a conducting state; applying a second voltage to the first word line WL1 and the third word line WL3 connected to the first memory transistor A1 and the second memory transistor B1, so that a read current is generated in the first memory transistor A1 and the second memory transistor B1; obtaining the first read current at the bit line BL terminal; and obtaining the first read result based on the first read current.

[0039] S102: When the first read result is represented as the stored data on the first storage tube A1 and the second storage tube B1, the read operation ends.

[0040] S103: When the first read result is not represented as stored data on the first storage tube A1 and the second storage tube B1, a second read operation is performed to obtain a second read result. The second read operation includes: continuing to obtain the second read current on the bit line BL terminal, and obtaining the second read result based on the second read current. The second read result is represented as stored data on the first storage tube A1 and the second storage tube B1.

[0041] The first reading result includes a first current, a second current, and a third current, wherein the first current is greater than the second current, and the third current is between the first current and the second current.

[0042] In this embodiment, the first select transistor M1 and the second select transistor M2 share a common source, and the source, gate, source, and gate of the first select transistor M1 are all connected to the second word line WL2, thereby using polysilicon to connect the gate and source of the first select transistor M1 and the gate and source of the second select transistor M2 together, so as to reduce the size of the memory.

[0043] Step S101, obtaining the first read result based on the first read current, includes: in response to the first current at the bit line BL terminal, the stored data on the first storage tube A1 and the second storage tube B1 are both "0"; in response to the second current at the bit line BL terminal, the stored data on the first storage tube A1 and the second storage tube B1 are both "1"; in response to the third current at the bit line BL terminal, continuing to obtain the second read result.

[0044] In this embodiment, the first current is a large current, which is 40 microamps; the second current is a small current, which is 40 nanoamps; and the third current is a medium current, which is 20 microamps.

[0045] The method for obtaining the second reading result based on the second reading current in step S103 includes: applying a third voltage to the third word line WL3 terminal, obtaining the second reading current on the bit line BL terminal; when the second reading current is less than the third current, the stored data on the first storage tube A1 is "1" and the stored data on the second storage tube B1 is "0"; when the second reading current is equal to the third current, the stored data on the first storage tube A1 is "0" and the stored data on the second storage tube B1 is "1".

[0046] In this embodiment, the third voltage is the voltage value that causes the second storage tube B1 to be partially turned off.

[0047] The reading method also includes:

[0048] Step S104: Apply a second voltage to the first word line WL1, the second word line WL2, and the third word line WL3 connected to the non-read memory cell, and apply a floating voltage to the bit line BL connected to the non-read memory cell.

[0049] In this embodiment, the storage units to be read are A1 and A2, and the other storage units in the memory are not storage units to be read. Of course, the technical solution of the present invention is not limited to this, and the selection of other storage units to be read is within the protection scope of the technical solution of the present invention.

[0050] In this embodiment, the voltages at the first word line WL1, the second word line WL2, the third word line WL3, and the bit line BL of the memory after the first read operation and the second read operation are shown in Table 1:

[0051]

[0052] Table 1

[0053] Where Vpwr is the first voltage, Vgnd is the second voltage, Vnegr is the third voltage, and Floating is the floating voltage.

[0054] In this embodiment, the voltage range of the first voltage is 1.5 volts to 2.5 volts, and the voltage range of the third voltage is -0.8 volts to -2 volts.

[0055] In this embodiment, the memory shares a common well region, and during a read operation, the value of the well voltage is the second voltage Vgnd.

[0056] The well region includes a P-type well region or an N-type well region.

[0057] In this embodiment, the well region is a P-type well region.

[0058] Figure 5This is a schematic diagram of the memory structure after entering the first read operation in the technical solution of this invention.

[0059] Figure 6 This is a schematic diagram of the memory structure after entering the second read operation in the technical solution of this invention.

[0060] The following is a reference to Table 1, Figure 5 as well as Figure 6 The method for reading the memory is described below:

[0061] In this embodiment, the storage units to be read 5 are A1 and B1, and the storage units not to be read are C1, D1, A2, B2, C2, and D2.

[0062] For the memory cell 5 to be read, a first voltage (2V) is applied to the second word line WL2 connected to the first selection transistor M1 and the second selection transistor M2 in the memory cell 5 to be read, so that the first selection transistor M1 and the second selection transistor M2 are in the conducting state. A second voltage (0V) is applied to the first word line WL1 and the third word line WL3 connected to the first memory transistor A1 and the second memory transistor B1, so that a read current is generated in the first memory transistor A1 and the second memory transistor B1. A second voltage (0V) is applied to the bit line BL terminal to obtain the first read current on the bit line BL terminal. Based on the first read current, the first read result is obtained.

[0063] When the first read result represents the stored data on the first storage tube A1 and the second storage tube B1, the read operation ends. Specifically: in response to the first current at the bit line BL, the stored data on the first storage tube A1 and the second storage tube B1 are both "0"; in response to the second current at the bit line BL, the stored data on the first storage tube A1 and the second storage tube B1 are both "1"; in response to the third current at the bit line BL, the second read result is obtained.

[0064] If the first read result does not represent the stored data on the first storage tube A1 and the second storage tube B1, a second read operation is performed. Specifically, a third voltage (-0.8V) is applied to the third word line WL3 terminal, and a second read current is obtained on the bit line BL terminal. When the second read current is less than the third current, the stored data on the first storage tube A1 is "1" and the stored data on the second storage tube B1 is "0". When the second read current is equal to the third current, the stored data on the first storage tube A1 is "0" and the stored data on the second storage tube B1 is "1".

[0065] For the non-read memory cell, a second voltage (0V) is applied to the first word line WL1, the second word line WL2, and the third word line WL3 connected to the non-read memory cell, and a floating voltage is applied to the bit line BL connected to the non-read memory cell.

[0066] In the above scheme, by obtaining the first read current at the bit line BL terminal, the stored data on the first storage tube A1 and the second storage tube B1 can be read simultaneously, which improves the read efficiency of the storage cell and reduces read interference of the storage tubes. Furthermore, the first read result is used to determine whether the stored data on the first storage tube A1 and the second storage tube B1 have been read. If the stored data on the first storage tube A1 and the second storage tube B1 have not been read, the second read current at the bit line BL terminal is obtained again. Based on the second read current, the stored data on the first storage tube A1 and the second storage tube B1 is read again, ensuring the accuracy of the read.

[0067] Furthermore, by acquiring the first read current at the bit line BL terminal, the stored data on the first storage tube A1 and the second storage tube B1 can be read simultaneously, which improves the read efficiency of the storage cell and reduces read interference of the storage tubes. The first read result is used to determine whether the stored data on the first storage tube A1 and the second storage tube B1 has been read. If the stored data on the first storage tube A1 and the second storage tube B1 has not been read, the second read current at the bit line BL terminal is acquired again. Based on the second read current, the stored data on the first storage tube A1 and the second storage tube B1 is read again, which ensures the accuracy of the read.

[0068] Please continue to refer to this. Figure 2 as well as Figure 4This invention provides a method for writing to a memory, the memory comprising: a plurality of memory cells arranged in an array, each memory cell including a first word line WL1, a second word line WL2, a third word line WL3, and a bit line BL; a first memory transistor A1, the gate of the first memory transistor A1 being connected to the first word line WL1, and one of the source or drain of the first memory transistor A1 being connected to the bit line BL; and a first select transistor M1, the gate of the first select transistor M1 being connected to the second word line WL2, and one of the source or drain of the first select transistor M1 being connected to the bit line BL. The first memory transistor A1 has another source or drain; a second select transistor M2, the gate of which is connected to the second word line WL2, and one of the sources or drains of the second select transistor M2 is connected to the other source or drain of the first select transistor M1; a second memory transistor B1, the gate of which is connected to the third word line WL3, and one of the sources or drains of the second memory transistor B1 is connected to the other source or drain of the second select transistor M2, and the other source or drain of the second memory transistor B1 is connected to the bit line BL; the writing method includes:

[0069] Step S201: Perform a first write operation. The first write operation method includes: applying a first write negative voltage to the second word line WL2 connected to the memory cell to be written, applying a write positive voltage to the first word line WL1 or the third word line WL3 connected to the memory cell to be written, applying a first write negative voltage to the bit line BL connected to the memory cell to be written, so that a write current is generated in the memory cell to be written, so as to perform a first write operation on any row of memory cells in the memory, obtaining the write enable voltage on the memory cell to be written, and comparing the write enable voltage with a preset write enable voltage.

[0070] Step S202: When the write enable voltage is within the preset write enable voltage, the write operation is considered complete.

[0071] Step S203: When the write enable voltage is not within the preset write enable voltage, a second write operation is performed. The second write operation includes repeating the first write operation until the write enable voltage is within the preset write enable voltage.

[0072] In this embodiment, the write enable voltage includes a first write enable voltage, and the preset write enable voltage includes a first preset write enable voltage.

[0073] The method for obtaining the write enable voltage on the storage cell to be written in step S201 and comparing the write enable voltage with the preset write enable voltage includes: after writing data "1", obtaining the first write enable voltage on the storage cell to be written, comparing the first write enable voltage with the first preset write enable voltage, and when the first write enable voltage is greater than the first preset write enable voltage, the operation of writing data "1" is completed; when the first write enable voltage is less than or equal to the first preset write enable voltage, repeating the first write operation until the first write enable voltage is greater than the first preset write enable voltage.

[0074] In this embodiment, the write enable voltage includes a second write enable voltage, and the preset write enable voltage includes a second preset write enable voltage.

[0075] The method of obtaining the write enable voltage on the storage cell to be written in step S203 and comparing the write enable voltage with the preset write enable voltage further includes: after writing data "0", obtaining the second write enable voltage on the storage cell to be written, comparing the second write enable voltage with the second preset write enable voltage, and when the second write enable voltage is less than the second preset write enable voltage, the operation of writing data "0" is completed; when the second write enable voltage is greater than or equal to the second preset write enable voltage, repeating the first write operation until the second write enable voltage is less than the second preset write enable voltage.

[0076] The writing method further includes:

[0077] Step S204: Apply a first write negative voltage to the second word line WL2 connected to the non-write memory cell, apply a second write negative voltage to the first word line WL1 and the third word line WL3 connected to the non-write memory cell, and apply a first write negative voltage to the bit line BL connected to the non-write memory cell.

[0078] In this embodiment, the voltages at the first word line WL1, the second word line WL2, the third word line WL3, and the bit line BL of the memory after the write operation are shown in Table 2:

[0079]

[0080] Table 2

[0081] Wherein, VnegP is the first write negative voltage, VposP is the write positive voltage, and VnegU is the second write negative voltage.

[0082] In this embodiment, the voltage range of the first write negative voltage is -3V to -5V, the voltage range of the write positive voltage is 4V to 7V, and the voltage range of the second write negative voltage is -2V to -3V.

[0083] In this embodiment, the memory shares a common well region, and during a write operation, the value of the well voltage is the first write negative voltage VnegP.

[0084] The well region includes a P-type well region or an N-type well region.

[0085] In this embodiment, the well region is a P-type well region.

[0086] Figure 7 This is a schematic diagram of the memory structure after the write operation in the technical solution of this invention.

[0087] The following is a combination of Table 2 and... Figure 7 The writing method to the memory is described below:

[0088] In this embodiment, the storage units to be written 6 are A1 and A2, and the storage units not to be written are B1, B2, C1, C2, D1, and D2.

[0089] For the memory cell 6 to be written, a first write negative voltage (-3.6V) is applied to the second word line WL2 connected to the memory cell 6 to be written, a write positive voltage (4.9V) is applied to the first word line WL1 connected to the memory cell 6 to be written, and a first write negative voltage (-3.6V) is applied to the bit line BL connected to the memory cell 6 to be written, so that a write current is generated in the memory cell 6 to perform a first write operation on any row of memory cells in the memory, obtain the write enable voltage on the memory cell 6 to be written, and compare the write enable voltage with the preset write enable voltage.

[0090] In this embodiment, when the data to be written to the memory cell 6 is 1, a voltage of -3.6V is applied to the bit line BL connected to the memory cell 6; when the data to be written to the memory cell 6 is 0, a voltage of 1.2V is applied to the bit line BL connected to the memory cell 6.

[0091] When the write enable voltage Vtp is within the preset write enable voltage, the write operation is considered complete; when the write enable voltage Vtp is not within the preset write enable voltage, a second write operation is performed, which includes repeating the first write operation until the write enable voltage Vtp is within the preset write enable voltage.

[0092] Specifically: After writing the data "1", the first write enable voltage on the storage unit 6 to be written is obtained, and the first write enable voltage is compared with the first preset write enable voltage Vtp1. When the first write enable voltage is greater than the first preset write enable voltage Vtp1, the operation of writing the data "1" is completed. When the first write enable voltage is less than or equal to the first preset write enable voltage Vtp1, the first write operation is repeated until the first write enable voltage is greater than the first preset write enable voltage Vtp1.

[0093] After writing the data "0", the second write enable voltage Vtp2 on the storage unit 6 to be written is obtained, and the second write enable voltage is compared with the second preset write enable voltage Vtp2. When the second write enable voltage is less than the second preset write enable voltage Vtp2, the operation of writing the data "0" is completed. When the second write enable voltage is greater than or equal to the second preset write enable voltage Vtp2, the first write operation is repeated until the second write enable voltage is less than the second preset write enable voltage Vtp2.

[0094] After entering the write operation, the channel in the memory tube is turned off. Since the write enable voltage Vtp is greater than the preset write enable voltage, the operating current is less than Idsp1 (small current).

[0095] After entering the write operation, the write enable voltage Vtp is greater than 1.6V, and the corresponding operating current Ids is less than 20nA.

[0096] For a non-write memory cell, a first write negative voltage (-3.6V) is applied to the second word line WL2 connected to the non-write memory cell, a second write negative voltage (-2.7V) is applied to the third word line WL3 connected to the non-write memory cell, and a first write negative voltage is applied to the bit line BL connected to the non-write memory cell.

[0097] In the above scheme, by continuously acquiring the write enable voltage on the memory cell to be written after writing different data, the write enable voltage on the memory cell to be written is kept within the preset write enable voltage, thereby reducing the dispersion of the write enable voltage and improving the storage performance of the memory.

[0098] Figure 9 This is a schematic diagram of the semiconductor structure of the memory in the technical solution of this invention.

[0099] Please refer to Figure 9 The memory includes: a substrate 800; a well region 801 located within the substrate; a select gate 804 located at least partially within the substrate; an insulating dielectric layer 803 located on the surface of the substrate 800 and the sidewall surface of the select gate 804; and a storage gate 802 located on the surface of the insulating dielectric layer 803.

[0100] The insulating dielectric layer 803 includes two silicon oxide layers and a silicon nitride layer located between the two silicon oxide layers.

[0101] The well region 801 includes a P-type well region or an N-type well region.

[0102] In this embodiment, the well region 801 is a P-type well region.

[0103] The writing process of the memory is as follows: First, the state of the memory cell after the erase operation is defined as state 0. The writing operation is divided into writing data "1" or writing data "0".

[0104] During a write operation, a first write negative voltage VnegP is applied to the well region 801 within the substrate 800, and a write positive voltage VposP is applied to the gate of the selected row of memory transistors. At this time, the channel of the memory gate 802 is open to receive the voltage at the bit line BL.

[0105] Therefore, when writing data "1", a first write negative voltage VnegP is applied to the bit line BL, and the voltage difference between the selected memory gate and the channel is (write positive voltage VposP - first write negative voltage VnegP) to tunnel electrons into the insulating dielectric layer 803 for storage.

[0106] When writing data "0", a second write voltage Vp0 is applied to the bit line BL. The voltage difference between the selected memory gate and the channel is (write positive voltage VposP - second write voltage Vp0), which is insufficient to tunnel electrons into the insulating dielectric layer 803. Therefore, the memory cell remains in the 0 state.

[0107] The second write voltage Vp0 is the voltage applied to the bit line BL when writing data "0".

[0108] In the above solution, the technical solution of the present invention determines the data writing status based on the current value on the storage tube, specifically:

[0109] For a memory transistor with a written data of "0", holes are stored in the insulating dielectric layer 803. Therefore, when 0V is applied to the gate of the selected memory transistor, electrons will be induced in the channel, causing a current to flow in the memory transistor (about 20 microamps per transistor).

[0110] For a memory transistor with a written data of "1", electrons are stored in the insulating dielectric layer 803. Therefore, when 0V is applied to the gate of the selected memory transistor, holes will be induced in the channel. At this time, the memory transistor is turned off and there is no current (less than 20 nanoamps for a single transistor). Therefore, it can be determined that the written data is "1" or "0".

[0111] Please continue to refer to this. Figure 3 as well as Figure 4This invention provides a method for erasing a memory, the memory comprising: a plurality of memory cells arranged in an array, each memory cell including a first word line WL1, a second word line WL2, a third word line WL3, and a bit line BL; a first memory transistor A1, the gate of the first memory transistor A1 being connected to the first word line WL1, and one of the source or drain of the first memory transistor A1 being connected to the bit line BL; and a first select transistor M1, the gate of the first select transistor M1 being connected to the second word line WL2, and one of the source or drain of the first select transistor M1 being connected to the bit line BL. The first memory transistor A1 has another source or drain; a second select transistor M2, the gate of which is connected to the second word line WL2, and one of the sources or drains of the second select transistor M2 is connected to the other source or drain of the first select transistor M1; a second memory transistor B1, the gate of which is connected to the third word line WL3, and one of the sources or drains of the second memory transistor B1 is connected to the other source or drain of the second select transistor M2, and the other source or drain of the second memory transistor B1 is connected to the bit line BL. The erasure method includes:

[0112] Step S301: Perform a first erase operation, the first erase operation including: applying a positive erase pressure to the second word line WL2 connected to the memory cell to be erased, applying a negative erase pressure to the first word line WL1 or the third word line WL3 connected to the memory cell to be erased, applying a positive erase pressure to the bit line BL connected to the memory cell to be erased, performing a first erase operation on any row of memory cells in the memory, obtaining the erase enable voltage on the memory cell to be erased, and comparing the erase enable voltage with a preset erase enable voltage range.

[0113] Step S302: When the erase activation voltage is within the preset erase activation voltage range, the erase operation is considered complete.

[0114] Step S303: When the erase activation voltage is not within the preset erase activation voltage range, proceed to the second erase operation. The second erase operation includes: repeating the first erase operation until the erase activation voltage is within the preset erase activation voltage range.

[0115] In this embodiment, the method of obtaining the erase enable voltage on the memory cell to be erased and comparing the erase enable voltage with a preset erase enable voltage range in step S301 includes: if the erase enable voltage is greater than the preset erase enable voltage range, repeating the first erase operation until the erase enable voltage is within the preset erase enable voltage range; if the erase enable voltage is less than the preset erase enable voltage range, applying a compaction positive pressure to the first word line WL1 or the third word line WL3 connected to the memory cell to be erased until the erase enable voltage is within the preset erase enable voltage range.

[0116] The erasure method further includes:

[0117] Step S304: Apply an erasure positive pressure to the second word line WL2, the first word line WL1, the third word line WL3, and the bit line BL, which are connected to the memory cell not to be erased.

[0118] In this embodiment, the voltages at the first word line WL1, the second word line WL2, the third word line WL3, and the bit line BL of the memory after the erase operation are shown in Table 3:

[0119]

[0120] Table 3

[0121] Where VposE is the positive erase pressure and VnegE is the negative erase pressure.

[0122] In this embodiment, the voltage range for the positive erasure voltage is 4 volts to 6 volts, and the voltage range for the negative erasure voltage is -3 volts to -5 volts.

[0123] In this embodiment, the memory shares a common well region, and during the erase operation, the value of the well voltage is the erase positive voltage VposE.

[0124] The well region includes a P-type well region or an N-type well region.

[0125] In this embodiment, the well region is a P-type well region.

[0126] Figure 8 This is a schematic diagram of the memory structure after entering the erase operation in the technical solution of this invention.

[0127] The following is a combination of Table 3 and... Figure 8 The method for erasing the memory is described below:

[0128] In this embodiment, the storage units 7 to be erased are A1 and A2, and the storage units not to be erased are B1, B2, C1, C2, D1, and D2.

[0129] For the memory cell 7 to be erased, a positive erase voltage (4.2V) is applied to the second word line WL2 connected to the memory cell 7 to be erased, a negative erase voltage (-3.6V) is applied to the first word line WL1 or the third word line WL3 connected to the memory cell 7 to be erased, and a positive erase voltage (4.2V) is applied to the bit line BL connected to the memory cell 7 to be erased. A first erase operation is performed on any row of memory cells in the memory, the erase enable voltage on the memory cell 7 to be erased is obtained, and the erase enable voltage Vte is compared with the preset erase enable voltage range Vte1 to Vte2.

[0130] When the erase enable voltage Vte is within the preset erase enable voltage range Vte1 to Vte2, the erase operation is considered complete; when the erase enable voltage Vte is not within the preset erase enable voltage range Vte1 to Vte2, a second erase operation is initiated, which includes repeating the first erase operation until the erase enable voltage Vte is within the preset erase enable voltage range Vte1 to Vte2.

[0131] Specifically, if the erase enable voltage Vte is greater than the absolute value of Vte2 ​​in the preset erase enable voltage range Vte1 to Vte2, the first erase operation is repeated until the erase enable voltage Vte is within the preset erase enable voltage range Vte1 to Vte2. If the erase enable voltage Vte is less than the absolute value of Vte1 in the preset erase enable voltage range Vte1 to Vte2, a compaction positive pressure is applied to the first word line WL1 or the third word line WL3 connected to the memory cell to be erased until the erase enable voltage Vte is within the preset erase enable voltage range Vte1 to Vte2.

[0132] In this embodiment, the preset erase activation voltage range Vte1 to Vte2 ​​is -1.4V to -1.5V.

[0133] After the erase operation is initiated, the channel inside the storage tube opens, and the corresponding operating current Ids is concentrated between the standard Idse1 and Idse2.

[0134] In this embodiment, after the erasure operation is completed, the erasure activation voltage Vte is concentrated between -1.4V and -1.5V, and the corresponding operating current Ids is concentrated between 18uA and 22uA.

[0135] For memory cells not to be erased, an erase positive voltage (4.2V) is applied to the second word line WL2, the first word line WL1, the third word line WL3, and the bit line BL connected to the memory cells not to be erased.

[0136] In this embodiment, both the write and erase operations adopt page mode (i.e., row operation). Specifically, A1, A2...An in any row of the memory are written or erased together.

[0137] Please continue to refer to this. Figure 9 The erasure process of the memory is as follows:

[0138] During the erase operation, a positive erase voltage VposE is applied to the well region 801 in the substrate 800, and a negative erase voltage VnegE is applied to the selected storage gate 802. The voltage difference between the storage gate 802 and the channel (negative erase voltage VnegE - positive erase voltage VposE) causes holes to tunnel into the insulating dielectric layer 803, reaching a zero state. In this scheme, by continuously acquiring the erase enable voltage on the storage cell to be erased and comparing it with a preset erase enable voltage range, the erase operation is considered complete when the erase enable voltage falls within the preset range. This reduces the dispersion of the erase enable voltage and improves the storage performance of the memory.

[0139] Furthermore, when the erase activation voltage is not within the preset erase activation voltage range, there is an over-erasing situation, that is, the erasure causes excessive loss of electrons on the floating gate, reducing the erase activation voltage, which leads to a false read of 1 during subsequent read operations. At this time, a compaction positive voltage is applied to the first word line WL1 or the third word line WL3 connected to the memory cell to be erased until the erase activation voltage is within the preset erase activation voltage range, that is, a portion of electrons are added to the floating gate, increasing the erase activation voltage to a normal value, reducing the dispersion of the erase activation voltage, and improving the storage performance of the memory.

[0140] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for reading from a memory, the memory comprising: A plurality of arrayed storage cells, wherein the storage cells include a first word line, a second word line, a third word line, and a bit line; A first memory transistor, wherein the gate of the first memory transistor is connected to the first word line, and one of the source or drain of the first memory transistor is connected to the bit line; The first select transistor has its gate connected to the second word line, and one of its source or drain is connected to the other source or drain of the first memory transistor. A second select transistor, the gate of which is connected to the second word line, and one of its sources or drains connected to the other source or drain of the first select transistor; a second memory transistor, the gate of which is connected to the third word line, and one of its sources or drains connected to the other source or drain of the second select transistor, and the other source or drain of the second memory transistor connected to the bit line, characterized in that it includes: Perform a first read operation and obtain a first read result. The first read operation includes: applying a first voltage to a second word line connected to the first and second select transistors in the memory cell to be read, so that the first and second select transistors are in a conducting state; applying a second voltage to the first and third word lines connected to the first and second memory transistors, so that a read current is generated in the first and second memory transistors; obtaining the first read current at the bit line terminal; and obtaining the first read result based on the first read current. When the first read result represents the stored data on the first and second storage tubes, the read operation ends. If the first read result is not represented as stored data on the first and second memory tubes, a second read operation is performed to obtain a second read result. The second read operation includes: continuing to obtain a second read current on the bit line terminal, and obtaining a second read result based on the second read current. The second read result is represented as stored data on the first and second memory tubes.

2. The memory reading method as described in claim 1, characterized in that, The first read result includes a first current, a second current, and a third current. The first current is greater than the second current, and the third current is between the first current and the second current. Based on the first read current, obtaining the first read result includes: in response to the first current at the bit line terminal, the stored data on the first and second memory tubes are both "0"; in response to the second current at the bit line terminal, the stored data on the first and second memory tubes are both "1"; in response to the third current at the bit line terminal, the second read result is obtained.

3. The memory reading method as described in claim 2, characterized in that, The method for obtaining the second read result based on the second read current includes: applying a third voltage to the third word line terminal, obtaining the second read current on the bit line terminal; when the second read current is less than the third current, the stored data on the first memory tube is "1" and the stored data on the second memory tube is "0"; when the second read current is equal to the third current, the stored data on the first memory tube is "0" and the stored data on the second memory tube is "1".

4. The memory reading method as described in claim 1, characterized in that, Also includes: A second voltage is applied to the first word line, the second word line, and the third word line connected to the non-read memory cell, and a floating voltage is applied to the bit line connected to the non-read memory cell.

5. A method for writing to a memory, the memory comprising: A plurality of arrayed storage cells, wherein the storage cells include a first word line, a second word line, a third word line, and a bit line; A first memory transistor, wherein the gate of the first memory transistor is connected to the first word line, and one of the source or drain of the first memory transistor is connected to the bit line; The first select transistor has its gate connected to the second word line, and one of its source or drain is connected to the other source or drain of the first memory transistor. A second select transistor, the gate of which is connected to the second word line, and one of its sources or drains connected to the other source or drain of the first select transistor; a second memory transistor, the gate of which is connected to the third word line, and one of its sources or drains connected to the other source or drain of the second select transistor, and the other source or drain of the second memory transistor connected to the bit line, characterized in that it includes: Perform a first write operation, the first write operation method including: applying a first write negative voltage to a second word line connected to the memory cell to be written, applying a write positive voltage to a first word line or a third word line connected to the memory cell to be written, applying a first write negative voltage to a bit line connected to the memory cell to be written, so that a write current is generated in the memory cell to be written, so as to perform a first write operation on any row of memory cells in the memory, obtaining the write enable voltage on the memory cell to be written, and comparing the write enable voltage with a preset write enable voltage; The write operation is considered complete when the write enable voltage is within the preset write enable voltage. When the write enable voltage is not within the preset write enable voltage, a second write operation is performed. The second write operation includes repeating the first write operation until the write enable voltage is within the preset write enable voltage.

6. The memory writing method as described in claim 5, characterized in that, The write enable voltage includes a first write enable voltage, and the preset write enable voltage includes a first preset write enable voltage. The method of obtaining the write enable voltage on the memory cell to be written and comparing the write enable voltage with the preset write enable voltage includes: after writing data "1", obtaining the first write enable voltage on the memory cell to be written, comparing the first write enable voltage with the first preset write enable voltage, and when the first write enable voltage is greater than the first preset write enable voltage, the operation of writing data "1" is completed. When the first write enable voltage is less than or equal to the first preset write enable voltage, the first write operation is repeated until the first write enable voltage is greater than the first preset write enable voltage.

7. The memory writing method as described in claim 5, characterized in that, The write enable voltage includes a second write enable voltage, and the preset write enable voltage includes a second preset write enable voltage. The method of obtaining the write enable voltage on the memory cell to be written and comparing the write enable voltage with the preset write enable voltage further includes: after writing data "0", obtaining the second write enable voltage on the memory cell to be written, comparing the second write enable voltage with the second preset write enable voltage, and when the second write enable voltage is less than the second preset write enable voltage, the operation of writing data "0" is completed; when the second write enable voltage is greater than or equal to the second preset write enable voltage, repeating the first write operation until the second write enable voltage is less than the second preset write enable voltage.

8. The method for writing to a memory as described in claim 5, characterized in that, Also includes: A first write negative voltage is applied to the second word line connected to the non-write memory cell, a second write negative voltage is applied to the first word line and the third word line connected to the non-write memory cell, and a first write negative voltage is applied to the bit line connected to the non-write memory cell.

9. A method for erasing a memory, the memory comprising: A plurality of arrayed storage cells, wherein the storage cells include a first word line, a second word line, a third word line, and a bit line; A first memory transistor, wherein the gate of the first memory transistor is connected to the first word line, and one of the source or drain of the first memory transistor is connected to the bit line; The first select transistor has its gate connected to the second word line, and one of its source or drain is connected to the other source or drain of the first memory transistor. The second select transistor has its gate connected to the second word line, and one of its source or drain is connected to the other source or drain of the first select transistor; the second memory transistor has its gate connected to the third word line, and one of its source or drain is connected to the other source or drain of the second select transistor, and the other source or drain of the second memory transistor is connected to the bit line. The erasure method comprises: performing a first erasure operation, which includes: applying a positive erasure voltage to the second word line connected to the memory cell to be erased; applying a negative erasure voltage to the first word line or third word line connected to the memory cell to be erased; applying a positive erasure voltage to the bit line BL connected to the memory cell to be erased; performing a first erasure operation on any row of memory cells in the memory; obtaining the erasure enable voltage on the memory cell to be erased; and comparing the erasure enable voltage with a preset erasure enable voltage range. When the erase activation voltage is within the preset erase activation voltage range, the erase operation is considered complete. When the erase activation voltage is not within the preset erase activation voltage range, a second erase operation is initiated. The second erase operation includes repeating the first erase operation until the erase activation voltage is within the preset erase activation voltage range.

10. The memory erasure method as described in claim 9, characterized in that, The method for obtaining the erase enable voltage on the memory cell to be erased and comparing the erase enable voltage with a preset erase enable voltage range includes: if the erase enable voltage is greater than the preset erase enable voltage range, repeating the first erase operation until the erase enable voltage is within the preset erase enable voltage range; if the erase enable voltage is less than the preset erase enable voltage range, applying a compaction positive pressure to the first word line or the third word line connected to the memory cell to be erased until the erase enable voltage is within the preset erase enable voltage range.

11. The memory erasure method as described in claim 9, characterized in that, Also includes: An erase positive pressure is applied to the second word line, first word line, third word line, and bit line connected to the memory cell not to be erased.

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