Flash memory refresh method, device and computer readable storage medium

Abstract

The application discloses a flash memory refreshing method, device and computer readable storage medium, and the flash memory refreshing method comprises the following steps: when reading data based on an initial reading voltage value is wrong, obtaining the error number and block information of the wrong data; when the error number is less than a preset threshold, determining an offset voltage value according to the block information and adjusting the initial reading voltage based on the offset voltage threshold; reading the data again based on the adjusted reading voltage value, and if the error number of the data read again is greater than or equal to the preset threshold, triggering a flash memory refreshing operation. Through the above steps, the number of bad blocks in the flash memory can be reduced, the service life of the flash memory and the amount of data that can be stored are improved by refreshing when the bit error number of the data reaches the threshold.

Description

Technical Field

[0001] This invention relates to the field of flash memory storage, and more particularly to flash memory refresh methods, devices, and computer-readable storage media. Background Technology

[0002] In flash memory, each storage cell consists of one or more bits used to store data. Due to lifespan or other reasons, bits may become faulty, leading to inaccuracies in data reading or writing. Therefore, flash memory devices typically have a threshold for faulty bits. When the number of faulty bits reaches or exceeds the threshold, the flash controller triggers a refresh operation.

[0003] In the past, flash memory refresh methods typically involved refreshing at fixed intervals or when the flash memory was running out of space. However, these methods are prone to data corruption or loss due to unreasonable time interval settings or insufficient remaining space.

[0004] The above content is only used to help understand the technical solution of the present invention and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main objective of this invention is to provide a flash memory refresh method, device, and computer-readable storage medium, which aims to solve the technical problem that data corruption or loss is easily caused by unreasonable time interval settings or insufficient remaining space in previous flash memory refresh methods.

[0006] To achieve the above objectives, the present invention provides a flash memory refresh method, the flash memory refresh method comprising the following steps:

[0007] When an error occurs while reading data based on the initial read voltage value, obtain the number of errors and block information of the erroneous data;

[0008] When the number of errors is less than a preset threshold, the offset voltage value is determined based on the block information, and the initial reading voltage is adjusted based on the offset voltage threshold.

[0009] The data is read again based on the adjusted read voltage value. If the number of errors in the data read again is greater than or equal to the preset threshold, a flash memory refresh operation is triggered.

[0010] Optionally, the step of determining the offset voltage value based on the block information and adjusting the initial read voltage based on the offset voltage threshold when the number of errors is less than a preset threshold includes:

[0011] Based on the block information, the target adjustment stage is determined by reading the voltage correspondence table;

[0012] The offset voltage value is determined based on the target adjustment stage;

[0013] The initial read voltage is corrected based on the offset voltage value.

[0014] Optionally, the step of triggering a flash memory refresh operation when the number of errors in the data read again based on the adjusted read voltage value is greater than or equal to the preset threshold includes:

[0015] Record the location and type of the erroneous data and read the data from the flash memory block;

[0016] Erase the data in the flash memory block;

[0017] Allocate a new flash memory block for the data and update the status of the data block.

[0018] Optionally, after the step of determining the offset voltage value based on the block information and adjusting the initial read voltage based on the offset voltage threshold when the number of errors is less than a preset threshold, the method further includes:

[0019] The data is read again based on the adjusted reading voltage value. If the data read again is error-free, the data is transmitted.

[0020] If the number of errors in the data read again is less than the preset threshold, the step of retrieving the number of errors and block information of the erroneous data is executed.

[0021] Optionally, before the step of triggering a flash memory refresh operation when the number of errors in the data read again based on the adjusted read voltage value is greater than or equal to the preset threshold, the method further includes:

[0022] The data is encoded, and the corresponding checksum is calculated.

[0023] Store the verification code into the data block;

[0024] Upon receiving an instruction to read the data already stored in the data block, the checksum of the data is verified based on the checksum.

[0025] If the data is found to contain errors, the errors are corrected based on the checksum.

[0026] Optionally, after the step of obtaining the number of errors and block information of the erroneous data when an error occurs while reading data based on the initial read voltage value, the method further includes:

[0027] Determine the error type and error code of the erroneous data;

[0028] Execute the corresponding retry strategy based on the error type and the error code;

[0029] Based on the retry table, the error type, error code, and parameters of the retry strategy are recorded.

[0030] Optionally, before the step of determining the offset voltage value based on the block information and adjusting the initial read voltage based on the offset voltage threshold when the number of errors is less than a preset threshold, the method further includes:

[0031] Obtain the retry information and retry data recorded in the retry table;

[0032] Based on the retry information and the retry data, a preset threshold is set, which is a threshold for the number of bit errors.

[0033] Optionally, the step of setting the preset threshold based on the retry information and the retry data, wherein the preset threshold is a threshold for the number of bit errors, includes:

[0034] Based on the characteristics of flash memory hardware, an initial threshold is set;

[0035] If the retry information and the retry data indicate that the number of data read errors after flash refresh exceeds the initial threshold, then the initial threshold is increased.

[0036] If the retry information and the retry data indicate that the number of data read errors after flash refresh does not exceed the initial threshold, then the preset threshold is set based on the initial threshold.

[0037] In addition, to achieve the above objectives, the present invention also provides a flash memory refresh device, the device comprising: a memory, a processor, and a flash memory refresh program stored on the memory and executable on the processor, the flash memory refresh program being configured to implement the steps of the flash memory refresh method as described above.

[0038] In addition, to achieve the above objectives, the present invention also provides a computer-readable storage medium on which a flash memory refresh program is stored, wherein the flash memory refresh program, when executed by a processor, implements the steps of the flash memory refresh method as described above.

[0039] This invention provides a flash memory refresh method, device, and computer-readable storage medium. When a data read error occurs based on an initial read voltage value, the method acquires the number of errors and block information of the erroneous data. If the number of errors is less than a preset threshold, an offset voltage value is determined based on the block information, and the initial read voltage is adjusted based on the offset voltage threshold. The data is then read again based on the adjusted read voltage value. If the number of errors in the reread data is greater than or equal to the preset threshold, a flash memory refresh operation is triggered. Through these steps, by refreshing when the number of bit errors in the data reaches a threshold, the number of bad blocks in the flash memory can be reduced, thereby increasing the lifespan of the flash memory and the amount of data that can be stored. Attached Figure Description

[0040] Figure 1 This is a flowchart illustrating the first embodiment of the flash memory refresh method of the present invention;

[0041] Figure 2 This is a flowchart illustrating the second embodiment of the flash memory refresh method of the present invention;

[0042] Figure 3 This is a flowchart illustrating the third embodiment of the flash memory refresh method of the present invention;

[0043] Figure 4 This is a schematic diagram of the terminal structure of the hardware operating environment involved in the embodiments of the present invention.

[0044] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0045] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0046] This invention provides a flash memory refresh method, referring to... Figure 1 , Figure 1 This is a flowchart illustrating a first embodiment of a flash memory refresh method according to the present invention.

[0047] In this embodiment, the flash memory refresh method includes:

[0048] Step S10: When an error occurs while reading data based on the initial reading voltage value, obtain the number of errors and block information of the erroneous data.

[0049] In flash memory, each storage cell consists of one or more bits used to store data. Due to lifespan or other reasons, bits may become faulty, leading to inaccuracies in data reading or writing. When the number of faulty bits in the flash memory reaches a preset threshold, a refresh operation is triggered, resetting the faulty bits to a normal state to ensure the reliability of the flash memory data.

[0050] In this embodiment, when reading data from the flash memory, an initial read voltage value is used to read data from the flash memory. Error checking is performed on the read data, using either ECC or CRC checksums. When a data error occurs, for each erroneous bit, the frequency of its occurrence is counted to determine the number of errors in the data. Simultaneously, the block information of the erroneous data is determined. This block information includes the block where the erroneous data is located, the number of erases for that block, the data retention time, etc. The corresponding offset voltage value can be determined using the block information. Optionally, the block information of the read error location can be pre-collected or recorded.

[0051] In this embodiment, by acquiring the number of errors and block information of the erroneous data, it is easier to determine the corresponding offset voltage value. By changing the offset voltage value, the reading voltage can be adjusted, and an appropriate voltage value can be used for error correction.

[0052] Step S20: When the number of errors is less than a preset threshold, determine the offset voltage value according to the block information and adjust the initial reading voltage based on the offset voltage threshold.

[0053] In this embodiment, after the flash memory has been used for a period of time, a voltage threshold offset may occur. This means that using the initial read voltage may result in bit flipping; what should be read as 0 may actually be read as 1. Therefore, we can sometimes resolve read errors by offsetting the original voltage threshold and changing the read voltage. However, this approach has limitations; if the offset is too large, it will still cause read errors. When the number of errors is less than a preset threshold, an appropriate offset voltage value is determined based on the data distribution and characteristics in the block information. The initial read voltage is then adjusted according to the determined offset voltage value to optimize data read performance and accuracy.

[0054] Furthermore, the offset voltage value to be adopted in the current stage can be determined through block information and a pre-defined read voltage correspondence table. The read voltage correspondence table contains the corresponding read voltage for each adjustment stage of the parameter that caused the error. By correcting the initial read voltage using the corresponding offset voltage value, the erroneous data can be reread using the corrected read voltage. The reread data is then verified again for errors. If an error is found, the number of errors and block information of the erroneous data are retrieved again to proceed to the next stage of voltage adjustment. If the read voltage is error-free when reading data after the second adjustment, no further adjustment is needed. Similarly, if read errors still occur after multiple adjustments and the number of errors exceeds a preset threshold, a flash refresh operation is triggered. In addition, information related to retrying voltage adjustments and data errors is recorded in a retry table (RRT) for later reference.

[0055] By adjusting the read voltage, we can attempt to alter the difficulty of the read operation, making it easier to succeed. Specifically, if we adjust the read voltage, more memory cells may generate enough voltage to exceed the threshold, thus increasing the probability of a successful read.

[0056] In this embodiment, the initial read voltage can be flexibly adjusted according to the data distribution and characteristics in the block information to adapt to data read requirements under different conditions. Simultaneously, it can avoid read failures or data corruption caused by an excessive number of errors, thereby improving data reliability and stability.

[0057] Step S30: Read the data again based on the adjusted read voltage value. If the number of errors in the data read again is greater than or equal to the preset threshold, trigger the flash memory refresh operation.

[0058] In this embodiment, the data is read again based on the adjusted read voltage value. If the number of errors in the read data is greater than or equal to a preset threshold, where the preset threshold is set based on the error correction range of ECC, and exceeds the error correction capability of ECC for data, then the error needs to be corrected by flash refresh, that is, clearing the erroneous data in the flash memory and rewriting the correct data.

[0059] Furthermore, when the number of faulty bits in the data reaches the bit error threshold, the location and type of the error are recorded, the faulty data is read out, and the block containing that data is marked as refreshed. Simultaneously, the read data is rewritten to a new flash memory block. The system also selects valid data pages and reads them into the SSD controller. During the refresh process, the error correction code is used to determine if a bit flip has occurred. If so, the original faulty data page is invalidated, and the value of that bit and its offset within the page are cached in non-volatile memory. It is then checked whether the non-volatile memory cache is full. If so, the cached data is written to flash memory, allocating a free data page for the data page containing the faulty bit. If not, it is checked whether the faulty bit is the last bit of the valid data page. If not, it is checked whether the newly written data page is the last data page of the flash memory block. If so, it is checked whether the data block containing the currently written data page is the last flash memory block. If so, the refresh ends. After the refresh operation is complete, the corresponding metadata and status information need to be updated to reflect the result of the refresh operation and the current state of the flash memory. For example, the flag bits of each data block in the flash memory need to be updated to indicate which data blocks have been refreshed. Optionally, after the refresh operation is completed, testing and monitoring should be performed to ensure that the refresh effect meets expectations. Partial or all of the data can be read and verified to confirm its integrity and correctness.

[0060] To facilitate understanding of the technical solution of this invention, the following is an explanation through a specific execution flow: When the controller reads data based on the initial read voltage, if a data read error occurs, the number of errors and block information are obtained. The parameters in the block information, such as the number of erase / write cycles, data retention time, number of interferences, and temperature, are matched with various stages in the read voltage correspondence table. For example, the second offset voltage value corresponding to the current target stage is queried, and the initial read voltage is adjusted using the second offset voltage value. The erroneous data is then reread using the adjusted read voltage, and it is determined whether the data is erroneous. If there is an error and the number of errors exceeds a preset threshold, a flash memory refresh operation is performed. If the number of errors does not exceed the preset threshold, a third offset voltage value matching the parameters of the current block information is queried based on the read voltage correspondence table. The read voltage is adjusted again using the third offset voltage value, and the read operation is performed to obtain a new read result. If it is determined that the read result is erroneous and the number of errors exceeds the preset threshold, a flash memory refresh operation is triggered.

[0061] In this embodiment, by refreshing the data when the number of bit errors reaches a threshold, the number of bad blocks in the flash memory can be reduced, thereby increasing the lifespan of the flash memory and the amount of data that can be stored.

[0062] Furthermore, refer to Figure 2 The second embodiment of the flash memory refresh method of the present invention is based on the above. Figure 1 In the embodiment shown, the following steps are included before step S30:

[0063] Step S40: Encode the data and calculate the corresponding check code;

[0064] Step S50: Store the verification code into the data block;

[0065] Step S60: Upon receiving an instruction to read the data already stored in the data block, verify the check bits of the data based on the check code;

[0066] Step S70: When it is found that there is erroneous data in the data, the erroneous data is corrected based on the check code.

[0067] In this embodiment, a preset threshold needs to be set or adjusted. First, an initial bit error threshold is set. This threshold can be set according to the application and hardware environment, and it is used to determine whether the number of bit errors exceeds a correctable range. A flash memory refresh operation is performed using the initial threshold. During the refresh process, the number of bit errors is recorded. If errors still exist in the refreshed data, or the refresh operation fails, error checking is required. This can be done using error detection methods such as CRC checksum or ECC checksum. The number of detected errors is compared with the current threshold. If the number of errors exceeds the threshold, it indicates that the current threshold may be too low and needs to be increased. If the number of errors exceeds the threshold, the threshold is increased by one level, and the flash memory refresh operation is performed again. If the refresh operation still fails, the above steps are repeated until a suitable threshold is found. Each time a new threshold is found, the threshold and the corresponding number of errors are recorded. This information can be used for reference and understanding of flash memory performance and behavior in future operations. When several consecutive refresh operations are successful and the number of errors is within an acceptable range, a suitable threshold can be considered to have been found.

[0068] Alternatively, in another feasible implementation, the optimal error threshold can be found using a retry table (RRT). First, sufficient retry table data needs to be collected, including information such as the location and frequency of read errors, and error correction status. This data can be obtained from the flash memory controller or related monitoring tools. The collected retry table data is analyzed and statistically processed to understand the read error situation, frequency, and error correction success rate at different locations. This helps determine which locations have more frequent errors and what error correction strategies to adopt for these locations. Based on the analysis results, appropriate error thresholds can be determined for different error locations and situations. This threshold can be determined based on factors such as error frequency, error correction success rate, and system performance requirements. Based on the determined threshold, a series of experiments are conducted to verify its effectiveness and applicability. This may involve evaluating system performance and comparing the error correction effects under different thresholds. Based on the experimental results, the determined threshold is adjusted and optimized to achieve the optimal balance between system performance and data reliability.

[0069] It should be noted that flash memory refresh operations can affect the lifespan of the flash memory. Therefore, once a suitable threshold is found, it is recommended to avoid frequent write / flash operations in practical applications. Additionally, more advanced error detection and correction methods can be considered to improve data reliability and stability.

[0070] In this embodiment, by setting a bit error threshold, the refresh timing of the flash memory can be better controlled, the number of bad blocks in the flash memory can be reduced, and the lifespan and amount of data that can be stored in the flash memory can be improved.

[0071] Reference Figure 3 The third embodiment of the flash memory refresh method of the present invention is based on the above. Figure 1 In the embodiment shown, the following steps are included before step S30:

[0072] Step S80: Obtain the retry information and retry data recorded in the retry table.

[0073] Step S90: Based on the retry information and the retry data, set the preset threshold, where the preset threshold is a threshold for the number of bit errors.

[0074] In this embodiment, for data that is read incorrectly, ECC correction will be performed within the capability range of the Error Correction Code (ECC) correction strategy. When data is written to the flash memory, redundant information is added to the data to be stored, generating coded data with error correction codes. This adds redundancy to the stored data to detect and correct errors when the data is read. When reading the stored data, the redundant error correction code is obtained, and a checksum is calculated using the same ECC algorithm. The redundant error correction code is compared with the checksum; if they match, the data is error-free. If the checksum does not match, it indicates that the read data contains errors, and the erroneous data needs to be automatically corrected using correction codes.

[0075] Furthermore, using ECC algorithms for error localization can pinpoint the location of errors in the data. The specific error localization method depends on the ECC algorithm and error correction capabilities used. Hamming codes, for example, use a binary tree-like structure to locate errors. During encoding, each data bit is mapped to a set of parity bits, arranged according to certain rules to form a Hamming matrix, with each data bit corresponding to one or more parity bits. If an error occurs in a data bit, some bits in the parity set will change, thus helping to locate and correct the error. Once the error is located, ECC can attempt to correct it. In parity-check codes, each byte has a parity bit used to detect errors in a single byte. If the parity bit of a byte does not match the actual data, it indicates that the byte has an error.

[0076] It's important to note that ECC's error correction capabilities are limited. It can detect and correct a certain number of errors, but when the number of errors exceeds its correction capacity, ECC may be unable to recover the original data. If it cannot automatically correct the error, the storage device will return an error code or fault information.

[0077] Furthermore, when an operation encounters an error, it's necessary to determine whether a retry is needed based on the error type and error code. For example, a retry can be attempted when a transient error (such as a flash memory bit flip) occurs; however, other measures are required when a persistent error (such as a hardware failure) occurs. Appropriate retry strategies need to be selected for different types of errors. For example, for transient errors, an exponential backoff strategy can be used, with the time interval between each retry gradually increasing until the maximum number of retries is reached or the operation succeeds. When performing retry operations, it's crucial to ensure data consistency. When an operation needs to operate on multiple resources, mechanisms such as transactions should be used to ensure that all resource operations complete successfully or are rolled back completely, thus guaranteeing data consistency. When the number of retries reaches a certain threshold, the retry loop needs to be exited to avoid infinite loops. During retry operations, relevant logs and exception information need to be recorded for troubleshooting and analysis. For example, information such as the number of retries, error type, and error code needs to be recorded.

[0078] In this embodiment, by using ECC to verify the data, the integrity and reliability of data storage can be improved. This reduces the number of flash memory refreshes and data migrations, and also extends the lifespan of the flash memory.

[0079] Reference Figure 4 , Figure 4 This is a schematic diagram of the flash memory refresh device structure in the hardware operating environment involved in the embodiments of the present invention.

[0080] like Figure 4 As shown, the flash memory refresh device may include: a processor 1001, such as a central processing unit (CPU), a communication bus 1002, and a memory 1003. The communication bus 1002 is used to enable communication between these components. The memory 1003 may be a high-speed random access memory (RAM) or a stable non-volatile memory (NVM), such as a disk drive. Optionally, the memory 1003 may also be a storage device independent of the aforementioned processor 1001.

[0081] Those skilled in the art will understand that Figure 4 The structure shown does not constitute a limitation on the flash refresh device and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0082] like Figure 4 As shown, the memory 1003, which serves as a storage medium, may include a flash memory refresh program.

[0083] exist Figure 4 In the flash memory refresh device shown, the processor 1001 and memory 1003 of the flash memory refresh device of the present invention can be disposed in the flash memory refresh device. The flash memory refresh device calls the flash memory refresh program stored in the memory 1003 through the processor 1001 and performs the following steps:

[0084] When an error occurs while reading data based on the initial read voltage value, obtain the number of errors and block information of the erroneous data;

[0085] When the number of errors is less than a preset threshold, the offset voltage value is determined based on the block information, and the initial reading voltage is adjusted based on the offset voltage threshold.

[0086] The data is read again based on the adjusted read voltage value. If the number of errors in the data read again is greater than or equal to the preset threshold, a flash memory refresh operation is triggered.

[0087] Furthermore, the flash memory refresh device, through processor 1001, calls the flash memory refresh program stored in memory 1003 and performs the following steps:

[0088] Based on the block information, the target adjustment stage is determined by reading the voltage correspondence table;

[0089] The offset voltage value is determined based on the target adjustment stage;

[0090] The initial read voltage is corrected based on the offset voltage value.

[0091] Furthermore, the flash memory refresh device, through processor 1001, calls the flash memory refresh program stored in memory 1003 and performs the following steps:

[0092] Record the location and type of the erroneous data and read the data from the flash memory block;

[0093] Erase the data in the flash memory block;

[0094] Allocate a new flash memory block for the data and update the status of the data block.

[0095] Furthermore, the flash memory refresh device, through processor 1001, calls the flash memory refresh program stored in memory 1003 and performs the following steps:

[0096] The data is read again based on the adjusted reading voltage value. If the data read again is error-free, the data is transmitted.

[0097] If the number of errors in the data read again is less than the preset threshold, the step of retrieving the number of errors and block information of the erroneous data is executed.

[0098] Furthermore, the flash memory refresh device, through processor 1001, calls the flash memory refresh program stored in memory 1003 and performs the following steps:

[0099] The data is encoded, and the corresponding checksum is calculated.

[0100] Store the verification code into the data block;

[0101] Upon receiving an instruction to read the data already stored in the data block, the checksum of the data is verified based on the checksum.

[0102] If the data is found to contain errors, the errors are corrected based on the checksum.

[0103] Furthermore, the flash memory refresh device, through processor 1001, calls the flash memory refresh program stored in memory 1003 and performs the following steps:

[0104] Determine the error type and error code of the erroneous data;

[0105] Execute the corresponding retry strategy based on the error type and the error code;

[0106] Based on the retry table, the error type, error code, and parameters of the retry strategy are recorded.

[0107] Furthermore, the flash memory refresh device, through processor 1001, calls the flash memory refresh program stored in memory 1003 and performs the following steps:

[0108] Obtain the retry information and retry data recorded in the retry table;

[0109] Based on the retry information and the retry data, a preset threshold is set, which is a threshold for the number of bit errors.

[0110] Furthermore, the flash memory refresh device, through processor 1001, calls the flash memory refresh program stored in memory 1003 and performs the following steps:

[0111] Based on the characteristics of flash memory hardware, an initial threshold is set;

[0112] If the retry information and the retry data indicate that the number of data read errors after flash refresh exceeds the initial threshold, then the initial threshold is increased.

[0113] If the retry information and the retry data indicate that the number of data read errors after flash refresh does not exceed the initial threshold, then the preset threshold is set based on the initial threshold.

[0114] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0115] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0116] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0117] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A flash memory refresh method, characterized in that, The flash memory refresh method includes the following steps: When an error occurs while reading data based on the initial reading voltage value, the number of errors and block information of the erroneous data are obtained. The block information includes the block where the erroneous data is located, the number of times the block is erased, and the data retention time. Retrieve retry information and retry data recorded in the retry table; Based on the characteristics of flash memory hardware, an initial threshold is set; If the retry information and the retry data indicate that the number of data read errors after flash refresh exceeds the initial threshold, then the initial threshold is increased. If the retry information and the retry data indicate that the number of read data errors after flash refresh does not exceed the initial threshold, then a preset threshold is set based on the initial threshold, and the preset threshold is a threshold for the number of bit errors. When the number of errors is less than a preset threshold, the offset voltage value is determined based on the block information, and the initial reading voltage is adjusted based on the offset voltage value; The data is read again based on the adjusted read voltage value. If the number of errors in the data read again is greater than or equal to the preset threshold, a flash memory refresh operation is triggered.

2. The flash memory refresh method as described in claim 1, characterized in that, The step of determining an offset voltage value based on the block information and adjusting the initial read voltage based on the offset voltage value when the number of errors is less than a preset threshold includes: Based on the block information, the target adjustment stage is determined by reading the voltage correspondence table; The offset voltage value is determined based on the target adjustment stage; The initial read voltage is corrected based on the offset voltage value.

3. The flash memory refresh method as described in claim 1, characterized in that, The step of triggering a flash memory refresh operation when the number of errors in the data read again based on the adjusted read voltage value is greater than or equal to the preset threshold includes: Record the location and type of the erroneous data and read the data from the flash memory block; Erase the data in the flash memory block; Allocate a new flash memory block for the data and update the state of the flash memory block.

4. The flash memory refresh method as described in claim 1, characterized in that, After the step of determining the offset voltage value based on the block information and adjusting the initial read voltage based on the offset voltage value when the number of errors is less than a preset threshold, the method further includes: The data is read again based on the adjusted reading voltage value. If the data read again is error-free, the data is transmitted. If the number of errors in the data read again is less than the preset threshold, the step of obtaining the number of errors and block information of the erroneous data is executed.

5. The flash memory refresh method as described in claim 1, characterized in that, Before the step of triggering a flash memory refresh operation when the number of errors in the data read again based on the adjusted read voltage value is greater than or equal to the preset threshold, the method further includes: The data is encoded, and the corresponding checksum is calculated. Store the verification code in a flash memory block; When an instruction to read data stored in the flash memory block is received, the checksum of the data is checked based on the checksum. If the data is found to contain errors, the errors are corrected based on the checksum.

6. The flash memory refresh method according to any one of claims 1 to 5, characterized in that, After the step of obtaining the number of errors and block information of the erroneous data when an error occurs while reading data based on the initial read voltage value, the method further includes: Determine the error type and error code of the erroneous data; Execute the corresponding retry strategy based on the error type and the error code; Based on the retry table, the error type, error code, and parameters of the retry strategy are recorded.

7. A flash memory refresh device, characterized in that, The flash refresh device includes: a memory, a processor, and a flash refresh program stored on the memory and executable on the processor, the flash refresh program being configured to implement the steps of the flash refresh method as described in any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a flash memory refresh program, which, when executed by a processor, implements the steps of the flash memory refresh method as described in any one of claims 1 to 6.

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