Method for producing indium gallium oxide polycrystal structure and method for producing transistor device
Patent Information
- Application Number
- CN202311830426.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-28
- Publication Date
- 2026-10-16
- Estimated Expiration
- 2043-12-28
AI Technical Summary
[0002]传统的半导体制造通常是采用非晶IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)制作沟道，尽管传统的非晶IGZO材料制作的晶体管器件的可靠性较好，但是由传统的非晶IGZO材料制作的晶体管器件的场效应迁移率低，因此，研发人员采用多晶IGO(Intergranular Oxidation，铟镓氧)氧化物半导体材料制作晶体管器件，在保证晶体管器件的可靠性的前提下，进一步的提升晶体管器件的场效应迁移率
[0015] According to the present disclosure, the method for fabricating polycrystalline indium gallium oxide (IGaO), the method for fabricating transistor devices, and the transistor devices themselves, an IGaO thin film with a channel-like structure is grown on the surface of the gate oxide layer of a substrate to obtain a material to be crystallized, which serves as the channel layer of a thin-film transistor. This material is then subjected to peak annealing to obtain the target material, namely, IGaO with a polycrystalline structure. Peak annealing of the IGaO thin film allows it to crystallize at low temperatures, generating a polycrystalline structure and improving the field-effect mobility. Furthermore, the channel layer of the thin-film transistor composed of the IGaO thin film after peak annealing exhibits higher compatibility with subsequent processes. Subsequent processing does not affect the channel layer of the thin-film transistor composed of the IGaO thin film after peak annealing, nor the transistor device itself, thus improving the manufacturing success rate and reliability of the transistor device.
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Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor manufacturing, and more specifically to a method for preparing polycrystalline indium gallium oxide, a method for preparing transistor devices, and transistor devices. Background Technology
[0002] Traditional semiconductor manufacturing typically uses amorphous IGZO (Indium Gallium Zinc Oxide) to create channels. Although transistors made from traditional amorphous IGZO materials have good reliability, they also have low field-effect mobility. Therefore, researchers use polycrystalline IGO (Intergranular Oxidation) semiconductor materials to fabricate transistors, thereby further improving the field-effect mobility of transistors while ensuring their reliability.
[0003] In the process of realizing the above-mentioned inventive concept, the inventors discovered that the related technologies have technical problems such as the difficulty in subsequent processing due to the continuous heating of indium gallium oxide materials, resulting in poor field-effect mobility and poor reliability of transistor devices. Summary of the Invention
[0004] In view of the above problems, this disclosure provides a method for preparing polycrystalline indium gallium oxide, a method for preparing transistor devices, and transistor devices.
[0005] According to a first aspect of this disclosure, a method for preparing polycrystalline indium gallium oxide (IGaO) is provided, comprising: growing an IGaO thin film on the surface of a gate oxide layer of a substrate to obtain a material to be crystallized; wherein the material to be crystallized is characterized as a channel layer of a thin-film transistor; and performing a spike annealing treatment on the material to be crystallized to obtain a target material, wherein the target material is characterized as IGaO having a polycrystalline structure.
[0006] According to an embodiment of this disclosure, the process of performing a spike annealing treatment on the channel to be treated to obtain the target material includes: heating the material to be crystallized at a first predetermined temperature for a first duration in a heating chamber under a nitrogen atmosphere to obtain a first crystallized material; using the residual heat in the heating chamber to heat the first crystallized material at a second predetermined temperature for a second duration to obtain a second crystallized material; and cooling the second crystallized material to a third predetermined temperature for a third duration to obtain the target material.
[0007] According to an embodiment of this disclosure, the first predetermined temperature is 420°C and the first duration is 1 second.
[0008] According to an embodiment of this disclosure, the second predetermined temperature is 490°C and the second duration is 1 second.
[0009] According to an embodiment of this disclosure, the third predetermined temperature is 280°C and the third duration is 25 seconds.
[0010] According to embodiments of this disclosure, growing an indium gallium oxide thin film on the surface of a gate oxide layer of a substrate to obtain a material to be crystallized includes: growing an indium gallium oxide thin film on the surface of a gate oxide layer of a substrate using a magnetron sputtering method to obtain a material to be crystallized.
[0011] According to embodiments of this disclosure, growing an indium gallium oxide thin film on the surface of a gate oxide layer of a substrate to obtain a material to be crystallized includes: growing an indium gallium oxide thin film on the surface of a gate oxide layer of a substrate using atomic layer deposition to obtain a material to be crystallized.
[0012] According to embodiments of this disclosure, the polycrystalline structure is a linear structure with repeating, regularly arranged structures.
[0013] A second aspect of this disclosure provides a method for fabricating a transistor device, comprising: growing a source and a drain on an indium gallium oxide target having a polycrystalline structure to obtain a transistor device, wherein the target is fabricated according to any one of claims 1-8.
[0014] A third aspect of this disclosure provides a transistor device comprising: a transistor device prepared by the method of claim 9.
[0015] According to the present disclosure, the method for fabricating polycrystalline indium gallium oxide (IGaO), the method for fabricating transistor devices, and the transistor devices themselves, an IGaO thin film with a channel-like structure is grown on the surface of the gate oxide layer of a substrate to obtain a material to be crystallized, which serves as the channel layer of a thin-film transistor. This material is then subjected to peak annealing to obtain the target material, namely, IGaO with a polycrystalline structure. Peak annealing of the IGaO thin film allows it to crystallize at low temperatures, generating a polycrystalline structure and improving the field-effect mobility. Furthermore, the channel layer of the thin-film transistor composed of the IGaO thin film after peak annealing exhibits higher compatibility with subsequent processes. Subsequent processing does not affect the channel layer of the thin-film transistor composed of the IGaO thin film after peak annealing, nor the transistor device itself, thus improving the manufacturing success rate and reliability of the transistor device. Attached Figure Description
[0016] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:
[0017] Figure 1 A flowchart illustrating a method for preparing a polycrystalline indium gallium oxide structure according to an embodiment of the present disclosure is shown schematically.
[0018] Figure 2 A flowchart illustrating the process of obtaining the target object according to an embodiment of the present disclosure is shown schematically;
[0019] Figure 3 A schematic diagram of spike annealing according to an embodiment of the present disclosure is shown;
[0020] Figure 4 The diagram illustrates the XRD patterns of IGO films that have undergone spike annealing and those that have not undergone spike annealing, according to embodiments of the present disclosure.
[0021] Figure 5 A schematic diagram illustrating the crystal structure of a channel without spike annealing according to an embodiment of the present disclosure is shown.
[0022] Figure 6 A schematic diagram illustrating the crystal structure of a channel subjected to spike annealing according to an embodiment of the present disclosure is shown.
[0023] Figure 7 This schematically illustrates a first schematic diagram of the reliability of a transistor device subjected to spike annealing according to an embodiment of the present disclosure;
[0024] Figure 8 This schematically illustrates a second diagram showing the reliability of a transistor device subjected to spike annealing according to an embodiment of the present disclosure;
[0025] Figure 9 A schematic diagram illustrating compatibility of downstream processes according to embodiments of the present disclosure is shown. Detailed Implementation
[0026] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.
[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.
[0028] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.
[0029] When using expressions such as "at least one of A, B, and C", they should generally be interpreted in accordance with the meaning that is commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B, and C, etc.).
[0030] In the technical solution of this invention, the user information (including but not limited to user personal information, user image information, user device information, such as location information) and data (including but not limited to data used for analysis, stored data, and displayed data) involved are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, storage, use, processing, transmission, provision, disclosure, and application of related data all comply with the relevant laws, regulations, and standards of the relevant countries and regions, take necessary confidentiality measures, do not violate public order and good morals, and provide corresponding operation entry points for users to choose to authorize or refuse.
[0031] In the semiconductor manufacturing process, amorphous IGZO material is usually used to make the channels in transistor devices. Although transistor devices made of traditional amorphous IGZO material have good reliability, they also have low field-effect mobility. Based on this, researchers have found that using polycrystalline indium gallium oxide material to prepare the channels in transistor devices can further improve the field-effect mobility of transistor devices while ensuring their reliability.
[0032] However, in the practical application of polycrystalline indium gallium oxide (IGaO) materials, researchers have discovered that channels obtained by continuously heating IGaO materials at high temperatures generally exhibit poor field-effect mobility in transistor devices. Furthermore, subsequent processing is difficult on channels created by continuous high-temperature heating of IGaO materials, resulting in suboptimal transistor device reliability. During the research and development process, researchers found that the continuous heating of IGaO materials in related technologies makes subsequent processing difficult, leading to poor field-effect mobility and reliability in transistor devices.
[0033] In view of this, embodiments of the present disclosure provide a method for preparing polycrystalline indium gallium oxide, comprising: growing an indium gallium oxide thin film on the surface of a gate oxide layer of a substrate to obtain a material to be crystallized; wherein the material to be crystallized is characterized as a channel layer of a thin-film transistor; and performing a spike annealing treatment on the material to be crystallized to obtain a target material, wherein the target material is characterized as indium gallium oxide having a polycrystalline structure.
[0034] The following will be through Figures 1-9 The preparation method of polycrystalline indium gallium oxide according to the disclosed embodiments is described in detail.
[0035] Figure 1 A flowchart illustrating a method for preparing a polycrystalline indium gallium oxide according to an embodiment of the present disclosure is shown.
[0036] like Figure 1 As shown, the method for preparing polycrystalline indium gallium oxide in this embodiment includes operations S110 to S120.
[0037] In operation S110, an indium gallium oxide thin film is grown on the surface of the gate oxide layer of the substrate to obtain the material to be crystallized.
[0038] According to embodiments of this disclosure, the material to be crystallized is characterized as the channel layer of a thin-film transistor.
[0039] According to embodiments of this disclosure, the channel layer of a thin-film transistor can be an indium gallium oxide thin film in the form of a channel.
[0040] According to embodiments of this disclosure, the material used to prepare the substrate can be Si, or other common materials used to prepare semiconductors.
[0041] According to embodiments of this disclosure, the gate oxide layer is obtained by thermal oxidation growth of the substrate.
[0042] For example, if the substrate is made of Si wafer, and the Si wafer is thermally oxidized to obtain SiO2, then SiO2 is the gate oxide layer on the Si wafer.
[0043] According to embodiments of this disclosure, an indium gallium oxide (IGaO) thin film can be grown on the upper surface of the gate oxide layer or on the lower surface of the gate oxide layer. That is, the channel layer of a thin-film transistor composed of an IGaO thin film can be above or below the gate oxide layer.
[0044] In operation S120, the material to be crystallized is subjected to peak annealing to obtain the target material.
[0045] According to embodiments of this disclosure, the target object is characterized as indium gallium oxide having a polycrystalline structure.
[0046] According to embodiments of this disclosure, after the crystallization material undergoes peak annealing, a polycrystalline structure will appear on the channel layer. That is, after the channel-shaped indium gallium oxide film undergoes peak annealing, a polycrystalline structure will appear on the channel-shaped indium gallium oxide film.
[0047] According to embodiments of this disclosure, since a channel-shaped indium gallium oxide (IGaO) thin film is grown on the surface of the gate oxide layer of the substrate, and the channel-shaped IGaO thin film is subjected to peak annealing, the target material, namely IGaO with a polycrystalline structure, is obtained. Peak annealing of the IGaO thin film enables the IGaO thin film to undergo crystallization reaction at low temperature to generate a polycrystalline structure, thereby improving the field-effect mobility. At the same time, the channel-shaped IGaO thin film after peak annealing has higher compatibility with subsequent processes. When performing subsequent processes, it will not affect the channel-shaped IGaO thin film after peak annealing or the transistor device itself, thereby improving the manufacturing success rate and reliability of the transistor device.
[0048] Based on the facts disclosed herein, the thickness of the indium gallium oxide thin film can be from 4 nm to 60 nm, for example: 4 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm.
[0049] According to embodiments of this disclosure, an indium gallium oxide thin film is grown on the surface of the gate oxide layer of a substrate to obtain a material to be crystallized, comprising:
[0050] According to embodiments of this disclosure, an indium gallium oxide thin film is grown on the surface of the gate oxide layer of a substrate using magnetron sputtering to obtain a material to be crystallized.
[0051] According to embodiments of this disclosure, indium gallium oxide material is fabricated onto a gate oxide layer using a magnetron sputtering method.
[0052] According to embodiments of this disclosure, before performing magnetron sputtering, a mask can be placed on the gate oxide layer, and then indium gallium oxide material can be grown on the gate oxide layer by magnetron sputtering to obtain the material to be crystallized. The indium gallium oxide thin film grown on the gate oxide layer is channel-shaped, that is, the material to be crystallized is the channel layer of the thin film transistor.
[0053] For example, the substrate of a transistor device is a Si wafer. The Si wafer is thermally oxidized to obtain SiO2 as the gate oxide layer. A mask is placed on the SiO2, and IGO material is grown on the SiO2 by magnetron sputtering to form the channel layer of the transistor device, thus obtaining the material to be crystallized.
[0054] According to embodiments of this disclosure, by using magnetron sputtering to grow an indium gallium oxide (IGO) thin film on the surface of the gate oxide layer of a substrate to obtain a material to be crystallized, the material to be crystallized is obtained precisely. By using magnetron sputtering, the IGO thin film can be grown more densely on the surface of the gate oxide layer. Furthermore, by using magnetron sputtering, the thickness of the IGO and the ratio of In to Ga can be adjusted by changing the growth conditions.
[0055] According to embodiments of this disclosure, an indium gallium oxide thin film is grown on the surface of the gate oxide layer of a substrate to obtain a material to be crystallized, comprising:
[0056] According to embodiments of this disclosure, an indium gallium oxide thin film is grown on the surface of the gate oxide layer of a substrate using atomic layer deposition to obtain a material to be crystallized.
[0057] According to embodiments of this disclosure, indium gallium oxide material is fabricated onto a gate oxide layer using an atomic layer deposition method.
[0058] According to embodiments of this disclosure, before performing atomic layer deposition, a mask can be placed on the gate oxide layer, and then indium gallium oxide material can be grown on the gate oxide layer by atomic layer deposition to obtain the material to be crystallized. The indium gallium oxide thin film grown on the gate oxide layer is channel-shaped, that is, the material to be crystallized is the channel layer of the thin film transistor.
[0059] For example, the substrate of a transistor device is a Si wafer. The Si wafer is thermally oxidized to obtain SiO2 as the gate oxide layer. A mask is placed on the SiO2, and IGO material is grown on the SiO2 by atomic layer deposition to form the channel layer of the transistor device, thus obtaining the material to be crystallized.
[0060] According to embodiments of this disclosure, by using atomic layer deposition (ALD) to grow an indium gallium oxide (IGO) thin film on the surface of the gate oxide layer of a substrate to obtain a material to be crystallized, the material to be crystallized is obtained precisely. ALD can grow the IGO thin film more uniformly on the surface of the gate oxide layer. Furthermore, ALD can adjust the thickness of IGO and the ratio of In to Ga by changing the growth conditions.
[0061] According to embodiments of this disclosure, indium gallium oxide thin films can also be grown on the gate oxide layer of a substrate using both magnetron sputtering and atomic layer deposition.
[0062] For example, using Si wafers as N +The Si wafer serves as the substrate and also as the gate electrode. SiO2 is thermally oxidized to grow as the gate oxide layer, and the thickness of the SiO2 gate oxide layer should be consistent. The channel-shaped IGO thin film grown by one or more methods of magnetron sputtering or atomic layer deposition is N-type doped. The thickness of IGO and the In to Ga ratio can be adjusted by changing the growth conditions using one or more methods of magnetron sputtering or atomic layer deposition.
[0063] Figure 2 A flowchart illustrating the process of obtaining the target object according to an embodiment of the present disclosure is shown schematically.
[0064] like Figure 2 As shown, obtaining the target object in this embodiment includes operations S210 to S230.
[0065] According to embodiments of this disclosure, the process of performing a peak annealing treatment on the material to be crystallized to obtain the target material includes:
[0066] In operation S210, under a nitrogen atmosphere, the material to be crystallized is heated at a first predetermined temperature for a first duration using a heating chamber to obtain a first crystallized material.
[0067] According to embodiments of this disclosure, a nitrogen atmosphere is characterized as a rapid thermal annealing furnace containing only nitrogen and no oxygen.
[0068] According to embodiments of this disclosure, the heating cavity is characterized as a rapid thermal annealing furnace.
[0069] According to embodiments of this disclosure, the material to be crystallized is placed in a rapid thermal annealing (RTA) furnace, and N2 is then introduced into the RTA furnace to ensure that there is no oxygen in the RTA furnace before the material to be crystallized is heated.
[0070] According to embodiments of this disclosure, the N2 introduced into the rapid thermal annealing furnace can be 0.1 Pa to 101 kPa.
[0071] According to an embodiment of this disclosure, the first predetermined temperature is 420°C.
[0072] According to an embodiment of this disclosure, the first duration is 1 second.
[0073] According to an embodiment of this disclosure, a rapid thermal annealing furnace is used to heat the material to be crystallized for 1 second, thereby rapidly raising the temperature of the material to be crystallized to 420°C, and obtaining the first crystallized material.
[0074] According to embodiments of this disclosure, the first crystallization material is characterized as a material to be crystallized that is rapidly heated to 420°C within 1 second.
[0075] In operation S220, the residual heat inside the heating chamber is used to heat the first crystallized material at a second predetermined temperature for a second duration to obtain the second crystallized material.
[0076] According to an embodiment of this disclosure, after obtaining the first crystallized material, heating of the rapid thermal annealing furnace is stopped, and the residual heat in the rapid thermal annealing furnace is used to heat the first crystallized material, so that the first crystallized material continues to heat up.
[0077] According to an embodiment of this disclosure, the second predetermined temperature is 490°C.
[0078] According to an embodiment of this disclosure, the second duration is 1 second.
[0079] According to an embodiment of this disclosure, the first crystallized material is heated for another second using the residual heat of a rapid thermal annealing furnace, i.e., within the second second, so that the temperature of the first crystallized material overshoots to 490°C, thereby obtaining the second crystallized material.
[0080] According to embodiments of this disclosure, the second crystallized material is characterized as the first crystallized material whose temperature overshoots to 490°C within 1 second.
[0081] In operation S230, the second crystallized material is cooled to a third predetermined temperature over a third duration to obtain the target material.
[0082] According to embodiments of this disclosure, after obtaining the second crystallized material, the second crystallized material in the rapid thermal annealing furnace is naturally cooled to reduce its temperature.
[0083] According to an embodiment of this disclosure, the third predetermined temperature is 280°C.
[0084] According to an embodiment of this disclosure, the third duration is 25 seconds.
[0085] According to an embodiment of this disclosure, the second crystallized material is subjected to natural cooling treatment in the next 25 seconds, i.e. from the 3rd to the 28th second, so that the temperature of the second crystallized material overshoots to 280°C, thereby obtaining the target material.
[0086] According to embodiments of this disclosure, the polycrystalline structure of the target object is a linear structure with repeating, regularly arranged structures.
[0087] According to embodiments of this disclosure, the material to be crystallized is heated in a nitrogen-filled rapid thermal annealing furnace, raising its temperature to 420°C within the first second to obtain a first crystallized material. Heating in the rapid thermal annealing furnace is then stopped, and the residual heat within the furnace is used to overshoot the temperature of the first crystallized material to 490°C within the second second to obtain a second crystallized material. The second crystallized material is then naturally cooled to 280°C within the third to 28th seconds, resulting in a target material with a polycrystalline structure. This achieves crystallization of the material under low-temperature conditions, thereby obtaining indium gallium oxide (IGaO) with a polycrystalline structure. This improves the field-effect mobility and reliability of transistor devices fabricated from IGaO with a polycrystalline structure. Furthermore, the IGaO with a polycrystalline structure obtained by this method has higher compatibility with subsequent processes.
[0088] According to embodiments of this disclosure, the channel-shaped IGO thin film can be subjected to peak annealing more than once, and the peak annealing can be performed according to the peak value of the IGO thin film used to fabricate the transistor device.
[0089] For example, if the IGO thin film of transistor A has 10 peaks, then the IGO thin film needs to be subjected to 10 peak annealing processes.
[0090] According to embodiments of this disclosure, a back-gate device can be used in N + A 20nm SiO2 gate oxide layer is grown on a Si wafer via thermal oxidation. An IGO thin film is then grown using magnetron sputtering. The IGO film undergoes a peak annealing process, comprising three stages: a rapid heating stage, an overshoot stage after heating is turned off, and a cooling stage. In the rapid annealing furnace, the IGO film is rapidly heated to 420°C within 1 second. After the furnace's heating power is turned off, the IGO film at 420°C continues to heat up within 1 second using residual heat, overshooting to 490°C. It is then cooled to approximately 280°C over the next 25 seconds, achieving low-temperature crystallization of the IGO film.
[0091] Figure 3 A schematic diagram of spike annealing according to an embodiment of the present disclosure is shown.
[0092] like Figure 3As shown in Example 300, the entire peak annealing process is illustrated. The horizontal axis represents time, and the vertical axis represents temperature. Within the first second, the material to be crystallized is rapidly heated to 420°C. Then, the heating source of the rapid thermal annealing furnace is turned off, and the residual heat in the furnace is used to overheat the first crystallized material in the furnace within the second second, so that the temperature reaches 490°C, achieving peak overheating. Then, the second crystallized material in the furnace is naturally cooled for 25 seconds, that is, from the third second to the 28th second, to achieve a complete peak annealing process for the material to be crystallized.
[0093] Figure 4 The diagram illustrates schematic XRD (X-ray diffraction) of an IGO thin film after peak annealing and an IGO thin film without peak annealing, according to embodiments of the present disclosure.
[0094] like Figure 4 As shown in Example 400, XRD patterns of IGO films after peak annealing and those without peak annealing are illustrated. The horizontal axis represents two diffraction halves, and the X-ray diffraction pattern is obtained by scanning the entire diffraction region at an angle of 2θ using an X-ray diffractometer. In the XRD, 2θ represents the normal scanning mode. The vertical axis represents the intensity of the X-ray diffraction. + A 20nm SiO2 gate oxide layer was grown on a Si wafer using thermal oxidation. An IGO thin film was then grown using magnetron sputtering. The IGO film underwent peak annealing, which included a rapid heating phase, an overshoot phase after the heating was turned off, and a cooling phase. The rapid heating reached 420°C within 1 second. After the heating power was turned off, the temperature continued to rise within 1 second, overshooting to 490°C. Finally, the temperature was cooled to around 280°C within 25 seconds. A total of 50 peaks were observed. Therefore, the IGO film underwent 50 peak annealing processes. XRD was then used to analyze the target material after peak annealing and the IGO film before peak annealing. The target material after peak annealing showed four distinct characteristic peaks located at approximately 30, 35, 50, and 60 on the horizontal axis. The IGO film before peak annealing only showed peaks at approximately 30 and 45 on the horizontal axis, but these peaks were actually peaks of the Si wafer serving as the substrate.
[0095] Figure 5 The schematic diagram illustrates a crystal structure of a channel without peak annealing under a transmission electron microscope according to an embodiment of the present disclosure.
[0096] like Figure 5As shown in Example 500, the structure of the channel crystal without the spike annealing treatment is an irregular and disordered arrangement, as observed by TEM (Transmission Electron Microscope).
[0097] Figure 6 The schematic diagram illustrates a crystal structure of a channel subjected to peak annealing under a transmission electron microscope according to an embodiment of the present disclosure.
[0098] like Figure 6 As shown in Example 600, the crystals of the channel treated by the spike annealing are observed by TEM (Transmission Electron Microscope) to be a linear structure with repeating regular arrangements.
[0099] Figure 7 This schematically illustrates a first schematic diagram of the reliability of a transistor device subjected to spike annealing according to an embodiment of the present disclosure.
[0100] like Figure 7 As shown in Example 700, the reliability of a transistor device after spike annealing is illustrated, with the gate-source voltage V on the horizontal axis. GS The vertical axis represents the channel current I. DS In the case of N + A 20nm SiO2 gate oxide layer was grown on a Si wafer using thermal oxidation. An IGO thin film was then grown using magnetron sputtering. The IGO film underwent peak annealing, which included a rapid heating phase, an overshoot phase after heating was turned off, and a cooling phase. The rapid heating reached 420°C within 1 second. After the heating power was turned off, the temperature was increased again within 1 second, overshooting to 490°C. Finally, the film was cooled to approximately 280°C within 25 seconds. A total of 50 peaks were observed, resulting in 50 peak annealing processes for the IGO film. The gate-source voltage V was measured during reliability testing. G,STR The voltage V between the source and drain of the field-effect transistor is +4V. DS Under the condition of 0.5V, from 0 seconds to 1000 seconds, it can be seen that the threshold voltage at 0 seconds and the threshold voltage at 1000 seconds are very small, while the difference ΔV between the threshold voltage at 0 seconds and the threshold voltage at 1000 seconds is large. th With a voltage of only 210mV, the transistor device that has undergone peak annealing has high reliability.
[0101] Figure 8 A second schematic diagram illustrating the reliability of a transistor device subjected to spike annealing according to an embodiment of the present disclosure is shown.
[0102] like Figure 8As shown in Example 800, the gate-source voltage V of a transistor device subjected to spike annealing is demonstrated during reliability testing. G,STR For reliability at -4V, the horizontal axis represents the gate-source voltage V. GS The vertical axis represents the channel current I. DS In the case of N + A 20nm SiO2 gate oxide layer was grown on a Si wafer using thermal oxidation. An IGO thin film was then grown using magnetron sputtering. The IGO film underwent peak annealing, which included a rapid heating phase, an overshoot phase after heating was turned off, and a cooling phase. The rapid heating reached 420°C within 1 second. After the heating power was turned off, the temperature was increased again within 1 second, overshooting to 490°C. Finally, the film was cooled to approximately 280°C within 25 seconds. A total of 50 peaks were observed, resulting in 50 peak annealing processes for the IGO film. The gate-source voltage V was measured during reliability testing. G,STR When the voltage is -4V, the voltage V between the source and drain of the field-effect transistor is DS Under the condition of 0.5V, from 0 seconds to 1000 seconds, the difference ΔV between the threshold voltage at second 0 and the threshold voltage at second 1000 can be observed. th The difference is still very small; the difference between the threshold voltage at second 0 and the threshold voltage at second 1000 is only -420mV, indicating that the transistor device after peak annealing has high reliability.
[0103] Figure 9 A schematic diagram illustrating compatibility of downstream processes according to embodiments of the present disclosure is shown.
[0104] like Figure 9 As shown in Example 900, the channel-shaped IGO thin film with a polycrystalline structure after peak annealing exhibits high compatibility with subsequent processes. The horizontal axis represents the gate-source voltage V. GS The vertical axis represents the channel current I. DS In the case of a back-gate device, the transistor device with a polycrystalline structure and a channel layer composed of IGO thin film was first subjected to peak annealing, with a total of 50 peaks, and 50 peak annealing processes were performed. After measuring its transfer characteristic curve using a semiconductor device parameter analyzer, the transistor device was then subjected to traditional isothermal heating annealing, i.e., annealing at 400°C for 1 hour. Subsequently, its transfer characteristic curve was measured again using a semiconductor device parameter analyzer. It can be seen that the voltage V between the drain and source of the field-effect transistor is... DS 500mV, channel thickness T chUnder the condition of 30nm, the two transfer characteristic curves are not much different, which means that the polycrystalline IGO film with channel shape after the peak annealing treatment has a good crystallization effect. At the same time, when other devices are stacked on the transistor device, the transistor device can also withstand the annealing treatment of the stacked other devices. The transistor device has good stability and reliability and high compatibility with subsequent processes.
[0105] According to an embodiment of this disclosure, a method for fabricating a transistor device includes: growing a source and a drain on an indium gallium oxide target having a polycrystalline structure to obtain a transistor device.
[0106] According to embodiments of this disclosure, a substrate for use as a transistor device is first determined, and then the substrate is subjected to thermal oxidation to obtain a gate oxide layer. An indium gallium oxide thin film is grown on the surface of the gate oxide layer by one or more methods, such as magnetron sputtering or atomic layer deposition, to obtain a material to be crystallized. The material to be crystallized is the channel layer of the transistor device. The material to be crystallized is placed in a rapid thermal annealing furnace and heated. The rapid thermal annealing furnace is heated to 420°C within 1 second to obtain a first crystallized material. The heating of the rapid thermal annealing furnace is then stopped, and the temperature of the first crystallized material is over-over-temperatured to 490°C within 2 seconds using the residual heat in the furnace to obtain a second crystallized material. The second crystallized material is then allowed to cool naturally to 280°C within 3 to 28 seconds to obtain a polycrystalline structure with a repeating, regularly arranged linear structure on the channel layer composed of an indium gallium oxide thin film. The source and drain electrodes are grown on the channel layer to obtain a transistor device.
[0107] According to embodiments of this disclosure, the source and drain materials can be one or more of ITO, IZO, Al, Au, and Ti, so as to facilitate good ohmic contact with a channel-shaped indium gallium oxide thin film with a polycrystalline structure.
[0108] According to the embodiments of this disclosure, the transistor devices prepared by the above-described transistor device preparation method achieve high field-effect mobility and high reliability.
[0109] According to an embodiment of this disclosure, a transistor device includes a transistor device prepared by the method described above.
[0110] According to the embodiments of this disclosure, the transistor device prepared by the above-described method has high field-effect mobility and strong reliability. When the transistor device is subjected to back-end processing, it can withstand the temperature of the annealing process without damaging the polycrystalline structure on the channel-shaped IGO thin film in the transistor device or affecting the field-effect mobility of the transistor device.
[0111] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.
[0112] The above specific embodiments further illustrate the purpose, technical solutions and beneficial effects of this disclosure. It should be understood that the above are only specific embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.
Claims
1. A method for preparing polycrystalline indium gallium oxide, comprising: An indium gallium oxide thin film is grown on the surface of the gate oxide layer of a substrate to obtain a material to be crystallized; wherein, the material to be crystallized is characterized as the channel layer of a thin film transistor; The material to be crystallized is subjected to a peak annealing process to obtain a target material, wherein the target material is characterized as indium gallium oxide with a polycrystalline structure. The peak annealing process of the material to be crystallized includes: heating the material to be crystallized at a first predetermined temperature for a first duration in a heating chamber under a nitrogen atmosphere to obtain a first crystallized material; using the residual heat in the heating chamber, heating the first crystallized material at a second predetermined temperature for a second duration to obtain a second crystallized material; and cooling the second crystallized material to a third predetermined temperature for a third duration to obtain the target material. The first predetermined temperature is 420°C, the first duration is 1 second, the second predetermined temperature is 490°C, the second duration is 1 second, the third predetermined temperature is 280°C, and the third duration is 25 seconds.
2. The method according to claim 1, wherein, The process of growing the indium gallium oxide thin film on the surface of the gate oxide layer of the substrate to obtain the material to be crystallized includes: The indium gallium oxide thin film is grown on the surface of the gate oxide layer of the substrate using magnetron sputtering to obtain the material to be crystallized.
3. The method according to claim 1, wherein, The process of growing the indium gallium oxide thin film on the surface of the gate oxide layer of the substrate to obtain the material to be crystallized includes: The indium gallium oxide thin film is grown on the surface of the gate oxide layer of the substrate using atomic layer deposition to obtain the material to be crystallized.
4. The method according to claim 1, wherein, The polycrystalline structure is a linear structure with a repeating, regular arrangement.
5. A method for fabricating a transistor device, comprising: A source and drain electrode are grown on an indium gallium oxide target material having a polycrystalline structure to obtain a transistor device, wherein the target material is prepared by any one of claims 1-4.
6. A transistor device, comprising: The transistor device prepared by the method of claim 5.