ESD protection circuit and chip

Abstract

The present application relates to the field of integrated circuits and chips, and provides an ESD protection circuit and chip. The ESD protection circuit comprises a control signal input unit, an RC delay unit and a discharge unit, the discharge unit comprises at least two ESD discharge paths, the control signal input unit is used for controlling the discharge unit to open the corresponding ESD discharge path for ESD discharge according to the input chip power-on state signal, and the RC delay unit is used for generating an RC time constant for enabling the discharge unit to open the ESD discharge. Different ESD protections are designed for the two states of power-off and power-on, different ESD discharge modes can be switched according to different application scenarios, the occurrence of false triggering events caused by glitches in the ESD power-on process is eliminated, and the problem of excessive source-drain voltage and excessive power consumption of the NMOS discharge tube caused by the voltage rise of the Active Clamp clamp voltage in the power-on process is solved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits and chips, specifically to an ESD protection circuit and a chip. Background Technology

[0002] Electrostatic discharge (ESD) is a phenomenon caused by the generation of an electrostatic voltage between an object and its surrounding environment, which then spontaneously discharges as a current pulse. Static electricity is characterized by prolonged accumulation, high voltage, low charge, small current, and short duration. Human movement or contact, separation, friction, or induction with other objects can generate static electricity of several thousand or even tens of thousands of volts. Frictional charging and static electricity from the human body are two major hazards in the electronics industry, often causing instability or even damage to electronic and electrical products. Because ESD can cause significant losses, ESD protection is necessary during chip manufacturing and use.

[0003] In existing technologies, active clamp circuits are commonly used for ESD protection. A drawback of traditional active clamp circuits is that even a small spike pulse on the power supply can be mistaken for an ESD pulse, causing the ESD protection circuit to trigger falsely. This frequent false triggering not only increases the circuit's power consumption but also increases the operating frequency of the ESD protection circuit, causing it to age faster. When a real ESD pulse arrives, the ESD discharge effect is weakened. Summary of the Invention

[0004] To overcome the above-mentioned technical defects, the present invention provides an ESD protection circuit.

[0005] The ESD protection circuit provided by the present invention includes: a control signal input unit, an RC delay unit, and a discharge unit;

[0006] The discharge unit includes at least two ESD discharge paths;

[0007] The control signal input unit is used to control the discharge unit to open the corresponding ESD discharge path for ESD discharge according to the input chip power-on status signal.

[0008] The RC delay unit is used to generate the RC time constant that enables the discharge unit to start ESD discharge.

[0009] In this embodiment of the invention, the RC delay unit includes a first capacitor C1 and a first resistor R1;

[0010] The first terminal of the first capacitor C1 is connected to the power supply terminal VDD, the second terminal of the first capacitor C1 is connected to the first terminal of the first resistor R1, and the second terminal of the first resistor R1 is grounded.

[0011] The common point VRC, where the second terminal of the first capacitor C1 and the first terminal of the first resistor R1 are connected, is connected to the control signal input unit and the discharge unit.

[0012] In this embodiment of the invention, the control signal input unit includes: a first NMOS transistor N1, a second NMOS transistor N2, and a second capacitor C2;

[0013] The gate of the first NMOS transistor N1 is connected to the POC signal, which is a level signal reflecting the power-on state of the chip;

[0014] The source of the first NMOS transistor N1 is connected to the gate of the second NMOS transistor N2 and to the first terminal of the second capacitor C2. The drain of the second NMOS transistor N2 is connected to the common point VRC where the second terminal of the first capacitor C1 and the first terminal of the first resistor R1 are connected.

[0015] The drain of the first NMOS transistor N1 is connected to the power supply terminal VDD, the second terminal of the second capacitor C2 and the source of the second NMOS transistor N2 are grounded to GND.

[0016] In this embodiment of the invention, the discharge unit includes: a third NMOS transistor N3, a fourth NMOS transistor N4, and a second resistor R2; the gate of the third NMOS transistor N3 is connected to the common point VRC where the second end of the first capacitor C1 and the first end of the first resistor R1 are connected; the source of the third NMOS transistor N3 is connected to the gate of the fourth NMOS transistor N4 and the first end of the second resistor R2; the drain of the third NMOS transistor N3 and the drain of the fourth NMOS transistor N4 are connected to the power supply terminal VDD; and the second end of the second resistor R2 and the source of the fourth NMOS transistor N4 are grounded to GND.

[0017] In this embodiment of the invention, the discharge unit further includes: a fifth NMOS transistor N5 and a third resistor R3; the gate of the fifth NMOS transistor N5 is connected to the first end of the third resistor R3 and connected to the common point VRC where the second end of the first capacitor C1 and the first end of the first resistor R1 are connected; the drain of the fifth NMOS transistor N5 is connected to the power supply terminal VDD; and the source of the fifth NMOS transistor N5 and the second end of the third resistor R3 are grounded to GND.

[0018] In this embodiment of the invention, the POC signal is a high-level signal or a low-level signal.

[0019] In this embodiment of the invention, when the POC signal is high and the power supply is high, the first NMOS transistor N1 is turned on, and the ESD current flows into the second capacitor C2 through the first NMOS transistor N1, raising the voltage of the gate of the second NMOS transistor N2. The second NMOS transistor N2 is turned on, and the voltage at the common point VRC where the second terminal of the first capacitor C1 and the first terminal of the first resistor R1 are connected is pulled down to ground, causing the fifth NMOS transistor N5 to form a GGNMOS, which discharges the ESD.

[0020] In this embodiment of the invention, when the POC signal is low, the power supply terminal VDD is low, and the ESD pulse comes from the power supply terminal VDD, the first NMOS transistor N1 and the second NMOS transistor N2 are turned off. The first capacitor C1 and the first resistor R1 form an RC delay structure. After a delay of τ = R1 * C1, the voltage at the common point VRC connected to the second terminal of the first capacitor C1 and the first terminal of the first resistor R1 is raised by the ESD pulse, causing the third NMOS transistor N3 and the fourth NMOS transistor N4 to turn on, and the ESD is discharged through the fourth NMOS transistor N4.

[0021] In this embodiment of the invention, the voltage at the common point VRC where the second terminal of the first capacitor C1 and the first terminal of the first resistor R1 are connected is raised by the ESD pulse, which also turns on the fifth NMOS transistor N5. At the same time, the ESD is discharged through the fourth NMOS transistor N4 and the fifth NMOS transistor N5.

[0022] The present invention also provides a chip that includes the above-described ESD protection circuit.

[0023] Through the above technical solution, the present invention provides an ESD protection circuit that can switch different ESD discharge modes according to different application scenarios. Different ESD protections are designed for the two states of power-off and power-on, eliminating the occurrence of false triggering events caused by glitches during ESD power-on, and solving the problem of excessive source-drain cross-voltage and excessive power consumption of NMOS discharge tube caused by the increase of Active Clamp clamp voltage during power-on.

[0024] Other features and advantages of the technical solution of the present invention will be described in detail in the following detailed embodiments section. Attached Figure Description

[0025] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0026] Figure 1 This is a schematic diagram of the ESD protection circuit provided in an embodiment of the present invention;

[0027] Figure 2 This is a schematic diagram of the ESD protection circuit provided in an embodiment of the present invention. Detailed Implementation

[0028] To make the technical solutions and advantages of the embodiments of the present invention clearer, the exemplary embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0029] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0030] In this invention, unless otherwise explicitly specified and limited, terms such as "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0031] As described in the background section, traditional active clamp circuits have drawbacks. Even a small spike pulse on the power supply can be mistaken for an ESD pulse, causing the ESD protection circuit to be falsely triggered. This not only increases the circuit's power consumption but also increases the frequency of use of the ESD protection circuit, leading to faster aging of the ESD circuit. Furthermore, during power-up, the active clamp circuit may experience excessively high clamping voltage due to insufficient RC constant, resulting in an excessively high source-drain voltage across the NMOS transistor discharging current, exceeding its withstand voltage and ultimately damaging the NMOS transistor. To overcome these technical deficiencies, this invention provides an ESD protection circuit that can switch between different ESD discharge modes according to different application scenarios. It designs different ESD protection for the power-off and power-on states, eliminating false triggering events caused by spikes during ESD discharge during power-up and solving the problems of excessive source-drain voltage and power consumption of the NMOS discharge transistor caused by the increased clamping voltage of the active clamp during power-up.

[0032] Figure 1This is a schematic diagram of the ESD protection circuit provided in an embodiment of the present invention. Figure 1 As shown, the ESD protection circuit provided in this embodiment of the invention includes a control signal input unit, an RC delay unit, and a discharge unit. The discharge unit includes at least two ESD discharge paths. The control signal input unit is used to control the discharge unit to open the corresponding ESD discharge path for ESD discharge according to the input chip power-on status signal. The RC delay unit is used to generate an RC time constant that enables the discharge unit to open ESD discharge.

[0033] like Figure 2 As shown, in one specific embodiment, the ESD protection circuit includes a control signal input unit, a discharge unit, and an RC delay unit. The control signal input unit includes a first NMOS transistor N1, a second NMOS transistor N2, and a second capacitor C2. The gate of the first NMOS transistor N1 is connected to the POC signal, which is a level signal reflecting the chip's power-on state. The source of the first NMOS transistor N1 is connected to the gate of the second NMOS transistor N2 and to the first terminal of the second capacitor C2. The drain of the second NMOS transistor N2 is connected to the common point VRC where the second terminal of the first capacitor C1 and the first terminal of the first resistor R1 are connected. The drain of the first NMOS transistor N1 is connected to the power supply terminal VDD. The second terminal of the second capacitor C2 and the source of the second NMOS transistor N2 are grounded to GND.

[0034] The RC delay unit includes a first capacitor and a first resistor. The first end of the first capacitor is connected to the power supply terminal, the second end of the first capacitor is connected to the first end of the first resistor, the second end of the first resistor is grounded, and the common point connecting the second end of the first capacitor and the first end of the first resistor is connected to the control signal input unit and the discharge unit.

[0035] The discharge unit includes a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a second resistor R2, and a third resistor R3. The gate of the third NMOS transistor N3 is connected to the common point VRC where the second terminal of the first capacitor C1 and the first terminal of the first resistor R1 are connected. The source of the third NMOS transistor N3 is connected to the gate of the fourth NMOS transistor N4 and the first terminal of the second resistor R2. The drains of the third NMOS transistor N3 and the drains of the fourth NMOS transistor N4 are connected to the power supply terminal VDD. The second terminal of the second resistor R2 and the source of the fourth NMOS transistor N4 are grounded to GND. The gate of the fifth NMOS transistor N5 is connected to the first terminal of the third resistor R3 and is connected to the common point VRC where the second terminal of the first capacitor C1 and the first terminal of the first resistor R1 are connected. The drain of the fifth NMOS transistor N5 is connected to the power supply terminal VDD. The source of the fifth NMOS transistor N5 and the second terminal of the third resistor R3 are grounded to GND.

[0036] The POC signal is a signal that reflects whether the chip is powered on or not. During chip transportation and storage, the POC signal is low; when the chip is powered on and operating normally, the POC signal is high. When the POC signal is high and the power supply terminal VDD is high, the first NMOS transistor N1 is turned on, and the ESD current flows through the first NMOS transistor N1 into the second capacitor C2, raising the gate voltage of the second NMOS transistor N2, turning on the second NMOS transistor N2. The voltage at the common point VRC, where the second terminal of the first capacitor C1 and the first terminal of the first resistor R1 are connected, is pulled down to ground, causing the fifth NMOS transistor N5 to form a GGNMOS, which discharges the ESD. When the POC signal is low, the power supply terminal VDD is low, and the ESD pulse originates from the power supply terminal VDD, the first NMOS transistor N1 and the second NMOS transistor N2 are turned off. The first capacitor C1 and the first resistor R1 form an RC delay structure. After a delay of τ = R1 * C1, the voltage at the common point VRC connecting the second terminal of the first capacitor C1 and the first terminal of the first resistor R1 is raised by the ESD pulse, causing the third NMOS transistor N3 and the fourth NMOS transistor N4 to turn on. The ESD is discharged through the fourth NMOS transistor N4. Furthermore, the voltage at the common point VRC connecting the second terminal of the first capacitor C1 and the first terminal of the first resistor R1 is raised by the ESD pulse, also causing the fifth NMOS transistor N5 to turn on. The ESD can be discharged simultaneously through the fourth NMOS transistor N4 and the fifth NMOS transistor N5. When VDD is low, the fourth NMOS transistor N4 and the fifth NMOS transistor N5 turn on simultaneously when an ESD occurs. This causes N5, which should be operating in the discharge path when VDD is high, to also be included in the ESD protection when VDD is low, thus increasing the ESD discharge capability.

[0037] The ESD protection circuit provided in this embodiment includes two different ESD discharge paths, and different ESD discharge methods can be switched in different application scenarios.

[0038] During chip transportation and storage, i.e., when the chip is powered off, the power supply VDD = 0V and the signal input terminal POC is 0V. When an ESD pulse arrives, because POC is low, N1 and N2 are turned off. The VRC voltage is raised by the ESD pulse, causing N3 and N5 to turn on. The turning on of N3 raises the voltage at the Vg terminal, causing N4 to turn on. At this time, both N4 and N5 are in the on state, and the ESD pulse will be discharged through the branches connected to N4 and N5 respectively. The discharge method at this time is ActiveClamp. When VDD is low, N4 and N5 turn on simultaneously when an ESD occurs. This allows N5, which should be operating in the discharge path when VDD is high, to also join the ESD protection when VDD is low. Discharge is carried out through the two branches of N4 and N5 respectively, greatly increasing the ESD discharge capability. Since the power is off at this time, it can effectively protect the circuit from ESD damage. This protection method protects the circuit when it is not powered on, and is suitable for ESD discharge during transportation, storage, and other processes.

[0039] The chip spends only a small portion of its time in transit; it operates with power on most of the time. When the circuit is powered on and functioning normally, the system switches to a different discharge mode, avoiding the risk of excessively high clamping voltage across the NMOS transistors, which could cause them to become unbearably low. During normal operation, POC and VDD are both high. A high POC turns on N1, allowing a large ESD current to flow through N1 into capacitor C2, raising the gate voltage of N2 and turning it on. At this time, the VRC voltage is pulled to ground, causing N5 to form a GGNMOS in form. The GGNMOS connection is caused by avalanche breakdown due to the NMOS gate-source grounding. When an ESD pulse occurs, N5 discharges the ESD through the GGNMOS, preventing the risk of excessively high source-drain voltage across the NMOS transistors. After power-on, the discharge method changes from Active Clamp to GGNMOS. The trigger voltage of GGNMOS is higher than that of Active Clamp, making it far more resistant to small power supply glitches than Active Clamp. This significantly reduces the probability of false triggering of the ESD protection circuit, decreases the increase in circuit power consumption caused by frequent false triggering of ESD, and reduces the usage frequency of the ESD protection circuit. It also prevents the ESD circuit from aging prematurely, truly protecting against ESD events during power-on.

[0040] Compared with traditional ESD protection circuits, the ESD protection circuit provided in this embodiment of the invention has the following advantages: It employs two switchable discharge methods, Active Clamp and GGNMOS, avoiding ESD false triggering events caused by spikes during normal operation; the switchable ESD discharge method allows for different discharge paths, resulting in different MOS transistors performing ESD protection, thus reducing the usage frequency of some components in the circuit, slowing down the aging of MOS transistors, and making the ESD protection circuit less prone to damage; it solves the problem of excessive source-drain cross-voltage of the NMOS discharge transistor caused by the increased clamping voltage of the Active Clamp during normal operation, preventing the electronic components in the circuit from aging too quickly.

[0041] This invention also provides a chip that includes the ESD protection circuit described in the above embodiments.

[0042] The optional embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details described above. Within the scope of the technical concept of the embodiments of the present invention, various simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all fall within the protection scope of the embodiments of the present invention. Furthermore, it should be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. As long as such combination does not violate the spirit of the embodiments of the present invention, it should also be considered as the content disclosed by the embodiments of the present invention.

Claims

1. An ESD protection circuit, characterized in that, include: Control signal input unit, RC delay unit, and discharge unit; The discharge unit includes at least two ESD discharge paths; The control signal input unit is used to control the discharge unit to open the corresponding ESD discharge path for ESD discharge according to the input chip power-on status signal. The RC delay unit is used to generate an RC time constant that enables the discharge unit to start ESD discharge; The RC delay unit includes: a first capacitor and a first resistor. The first end of the first capacitor is connected to the power supply terminal. The second end of the first capacitor is connected to the first end of the first resistor. The second end of the first resistor is grounded. The common point connecting the second end of the first capacitor and the first end of the first resistor is connected to the control signal input unit and the discharge unit. The control signal input unit includes a first NMOS transistor, a second NMOS transistor, and a second capacitor. The gate of the first NMOS transistor is connected to a POC signal, which is a level signal reflecting the power-on state of the chip. The source of the first NMOS transistor is connected to the gate of the second NMOS transistor and to the first terminal of the second capacitor. The drain of the second NMOS transistor is connected to the common point where the second terminal of the first capacitor and the first terminal of the first resistor are connected. The drain of the first NMOS transistor is connected to the power supply terminal, and the second terminal of the second capacitor and the source of the second NMOS transistor are grounded. The discharge unit includes: a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a second resistor, and a third resistor. The gate of the third NMOS transistor is connected to the common point where the second terminal of the first capacitor and the first terminal of the first resistor are connected. The source of the third NMOS transistor is connected to the gate of the fourth NMOS transistor and the first terminal of the second resistor. The drain of the third NMOS transistor and the drain of the fourth NMOS transistor are connected to the power supply terminal. The second terminal of the second resistor and the source of the fourth NMOS transistor are grounded. The gate of the fifth NMOS transistor is connected to the first terminal of the third resistor and is connected to the common point where the second terminal of the first capacitor and the first terminal of the first resistor are connected. The drain of the fifth NMOS transistor is connected to the power supply terminal. The source of the fifth NMOS transistor and the second terminal of the third resistor are grounded.

2. The ESD protection circuit according to claim 1, characterized in that, The POC signal can be a high-level signal or a low-level signal.

3. The ESD protection circuit according to claim 2, characterized in that, When the POC signal is high and the power supply is high, the first NMOS transistor is turned on. The ESD current flows into the second capacitor through the first NMOS transistor, raising the gate voltage of the second NMOS transistor. The second NMOS transistor is turned on, and the voltage at the common point connected to the first capacitor and the first resistor is pulled down to ground, causing the fifth NMOS transistor to form a GGNMOS. The ESD is discharged through the GGNMOS.

4. The ESD protection circuit according to claim 2, characterized in that, When the POC signal is low, the power supply is low, and the ESD pulse originates from the power supply, the first and second NMOS transistors are turned off. The first capacitor and the first resistor form an RC delay structure, which delays the signal by τ=R1. After the delay of C1, the voltage at the common point connecting the first capacitor and the first resistor is raised by the ESD pulse, causing the third NMOS transistor and the fourth NMOS transistor to turn on, and the ESD is discharged through the fourth NMOS transistor; where R1 represents the resistance value of the first resistor and C1 represents the capacitance value of the first capacitor.

5. The ESD protection circuit according to claim 4, characterized in that, The voltage at the common point where the first capacitor and the first resistor are connected is raised by the ESD pulse, which also turns on the fifth NMOS transistor. At the same time, the ESD is discharged through the fourth and fifth NMOS transistors.

6. A chip, characterized in that, The chip includes the ESD protection circuit as described in any one of claims 1-5.

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