Reconfigurable packet protocol parser device for gigabit rate network switch chips

Abstract

The application discloses a kind of gigabit rate network switching chip reconfigurable packet protocol parser equipment, including multiple parallel pipeline analysis unit, for responding to analysis task and being parsed to data packet and obtaining analysis intermediate result and output;Reordering module is used to collect and summarize the analysis intermediate result, and the analysis intermediate result of out-of-order in it is reordered and output to packet header field extractor;Packet header field extractor is used to extract PHV content from analysis intermediate result, and metadata is aligned with PHV content and output to external later stage module.The application uses multiple parallel pipeline analysis unit to realize protocol-independent reconfigurable packet protocol analysis, and uses Benes network to extract packet header field, realizes the highly flexible reconfigurable packet protocol analysis capability.Multiple parallel out-of-order processing structure is combined with large bit width byte level Benes network structure, and the throughput performance of packet parser equipment is significantly improved.

Description

Technical Field

[0001] This invention belongs to the field of network switch technology, specifically relating to a reconfigurable packet protocol parser device for a 100 gigabit rate network switching chip. Background Technology

[0002] Current edge network devices require network switches to provide switching speeds exceeding 100Gbps, while switching devices in enterprise core networks need to provide switching speeds of over 1Tbps. Simultaneously, to support higher data rates and provide services across a wide range of scenarios, a series of new network protocols for data switching have been proposed. Traditional chips designed for single-protocol identification and processing may become prematurely obsolete due to their inability to handle new network protocols, while high-end network equipment is prohibitively expensive, and frequent hardware upgrades due to network protocol updates are unacceptable. For these reasons, network switches have shifted from fixed-function, protocol-dependent network hardware to programmable network hardware.

[0003] High-speed, reconfigurable network packet protocol parsers are an important component of high-speed reconfigurable network switching application-specific integrated circuit (ASIC) chips. Under the new trend of network technology, there is a need to design a packet parser that balances flexibility and high performance to meet the urgent needs of future network communication equipment application scenarios.

[0004] There are two main implementation architectures for existing reconfigurable network packet protocol parsers: state machines and pipelines. The methods for achieving reconfigurability primarily fall into two categories: FPGA-dependent reconfiguration and protocol-independent hardware-based reconfiguration. FPGA-dependent reconfigurable packet parsers require updating the circuit structure to support network protocol updates. Since the circuit structure is not fixed, this cannot be implemented in ASIC chips. Packet parsers implemented using protocol-independent hardware, on the other hand, can support new network protocols without modifying the circuit structure.

[0005] The basic method for implementing a packet parser using protocol-independent hardware is as follows: use RAM or other memory to store specific packet protocol parsing methods (state transition information, field extraction rules, etc.), use protocol-independent packet parsing circuitry to parse the packet protocol according to the parsing methods in memory, and finally extract the relevant fields in the packet header (such as MAC address, IP address, TTL field, etc.) into PHV for use by subsequent circuits.

[0006] Reference 1 (Gibb G, Varghese G, Horowitz M. Design principles for packet parsers[C]. Architectures for Networking and Communications Systems. IEEE, 2013.) proposes a method for implementing packet parsers using finite state machines, mapping packet header protocol transitions to state transitions in the state machine. The structure of this packet parser is as follows: Figure 1 As shown, the state machine starts parsing the packet header from a default state (e.g., the state of parsing Ethernet packets). This state controls the packet parser to extract specific fields from the header. The extracted protocol type field and the current state of the packet parser are used as keys to obtain the parsing action index through a lookup table. Based on the parsing action index, the next state of the state machine is read from RAM, along with the location of the field to be extracted by the header extractor. Finally, the header field extractor extracts the specified fields into the PHV (Protocol Value Vehicle), and the state machine transitions to the next state. By repeating the above process, the packet parser eventually completes the parsing of all protocols in the packet header and generates the corresponding PHV.

[0007] Reference 2 (Configurable FPGA packet parser for terabit networks with guaranteed wire-speed throughput[C]. Proceedings of the 2018 ACM / SIGDA International Symposium on Field-Programmable Gate Arrays. 2018:249-258) proposes a pipelined packet parser for FPGA platforms. The designers write VHDL code templates for dedicated parsing modules for various packet protocols, compile the P4 language, and call these VHDL templates to generate VHDL code for parsing packet parsers specific to certain protocols. This code is then synthesized and implemented on the FPGA.

[0008] Reference 3 (Zolfaghari H, Rossi D, Cerroni W. Flexible software-defined packet processing using low-area hardware[J].IEEE Access, 2020) proposes using a pipelined architecture in conjunction with a "parse control word" to achieve the reconfigurable characteristics of packet parsing. This method uses a multi-stage pipeline, and the packet parser structure is as follows: Figure 2As shown, each stage of the pipeline includes a header protocol identification unit, a header size calculation unit, and a field extraction unit, using parsing control words to control each internal functional unit. Each data packet is transmitted within the pipeline; the first header is parsed by the first stage, the second by the second, and so on, until the data packet is parsed. The field extraction unit in each pipeline stage extracts specific fields from the header into the PHV (Programmable Value Vehicle).

[0009] In the above methods, for the packet parser in Reference 1, due to the dependency of header protocol parsing, the process of header protocol identification, keyword composition and table lookup and state machine transition is carried out in a blocking sequence. This means that the packet parser needs to consume multiple clock cycles to parse the protocol layer of the packet header. The hardware parallelism is low, so the parser cannot meet the high throughput requirements.

[0010] The packet parser in Reference 2 relies on the characteristics of the FPGA device itself to provide reconfigurability and high flexibility of packet parsing. When modifying the supported protocols, it is often necessary to reconfigure the FPGA with a new bitstream. This parser does not achieve protocol independence in its architecture, and its application scenarios are relatively limited.

[0011] The scheme in Reference 3 uses a pipelined structure to improve the throughput of the packet parser, but it uses a deep pipeline. Its performance is optimal when the number of protocol layers in the network data packet is equal to the number of pipeline stages. If the number of protocol layers in the packet header exceeds the number of pipeline stages, the packet parser cannot complete the parsing of all protocols in the data packet, and the data packet is returned to the pipeline for further parsing, which will halve the throughput. If the data packet is parsed at the front stage of the pipeline, the long pipeline stage circuit may be in a short-term idle state and cannot be fully utilized. This phenomenon indicates that the traditional pipelined structure lacks flexibility and there is still room for improvement in throughput.

[0012] Furthermore, the pipeline structure in Reference 3 will encounter bottlenecks in terms of circuit area and power consumption when scaling up performance. This is because the pipeline depth is relatively large, packet data is transmitted throughout the entire pipeline, and multiple sets of field extraction units are used on the pipeline. When using a large-width bus to further expand the throughput, the number of registers and multiplexers consumed by the pipeline will increase significantly. Summary of the Invention

[0013] To address the aforementioned problems in the prior art, this invention provides a reconfigurable packet protocol parser device for a 100 Gigabit network switching chip. The technical problem to be solved by this invention is achieved through the following technical solution:

[0014] This invention provides a reconfigurable packet protocol parser device for a 100 Gigabit network switching chip, comprising: a reordering module, a packet header field extractor, and a multi-channel parallel pipeline parsing unit;

[0015] The multi-path parallel pipeline parsing unit is used to parse data packets in response to the parsing task, obtain intermediate parsing results, and output them.

[0016] The reordering module is used to collect and summarize the intermediate parsing results, and reorder the disordered intermediate parsing results and output them to the header field extractor.

[0017] The header field extractor is used to extract PHV content from the intermediate parsing results, align the metadata with the PHV content, and output it to an external back-end module.

[0018] Beneficial effects:

[0019] This invention discloses a reconfigurable packet protocol parser device applicable to high-speed network switching ASIC chips. This device employs a dedicated processor architecture for packet parsing to achieve protocol-independent reconfigurable packet protocol parsing, and uses a Benes reordering network to extract packet header fields, achieving highly flexible reconfigurable packet protocol parsing capabilities. Simultaneously, by combining a multi-path parallel out-of-order processing structure with a large-width byte-level Benes network structure, the throughput performance of the packet parser device is significantly improved. Compared with existing traditional methods, it achieves a better balance between high flexibility and high throughput. The invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0020] Figure 1 This is a diagram of the state machine parser structure proposed in document 1 of the prior art;

[0021] Figure 2 This is a diagram of the state machine parser structure proposed in reference 3 in the prior art;

[0022] Figure 3 This is a schematic diagram of a reconfigurable packet protocol parser device for a 100 gigabit rate network switching chip provided by the present invention;

[0023] Figure 4 This is a schematic diagram of the functional structure of the network switching ASIC provided by the present invention;

[0024] Figure 5 This is a schematic diagram illustrating the implementation steps of packet parsing provided by the present invention;

[0025] Figure 6 This is a schematic diagram of the functional structure of the reordering module provided by the present invention;

[0026] Figure 7 This is a schematic diagram of the functional structure of the header field extractor provided by the present invention. Detailed Implementation

[0027] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0028] Before introducing the details of the present invention, a brief introduction will be given to the overall technical concept and inventive points of the present invention.

[0029] This invention uses a packet parsing processor core to respond to parsing tasks, realizing reconfigurable network packet protocol identification based on protocol-independent hardware; it employs multiple packet parsing processor cores and a reordering module to achieve parallel processing of parsing tasks, thereby improving the packet protocol parsing and identification performance of the parser device; it introduces a Benes reorderable network into the packet header field extraction circuit to achieve reconfigurable packet header field extraction at gigabit speeds; and it combines the packet parsing processor core with the Benes reorderable network to enable the parser device to simultaneously meet the requirements of packet protocol reconfigurability and gigabit line speed.

[0030] The technical details of the present invention are described in detail below.

[0031] Combination Figures 3-7 The present invention provides a reconfigurable packet protocol parser device for a 100 Gigabit network switching chip, comprising: a reordering module, a packet header field extractor, and a multi-channel parallel pipeline parsing unit;

[0032] The multi-path parallel pipeline parsing unit is used to parse data packets in response to the parsing task, obtain intermediate parsing results, and output them.

[0033] The reordering module is used to collect and summarize the intermediate parsing results, and reorder the disordered intermediate parsing results and output them to the header field extractor.

[0034] The packet header field extractor is used to extract PHV content from packet data using the intermediate parsing results, align metadata with the PHV content, and output it to an external back-end module.

[0035] In one specific implementation, reference is made to... Figure 3 The multi-path parallel pipeline parsing unit of the present invention includes a parsing task distribution module, an instruction memory, and multiple parallel packet parsing processor cores;

[0036] The parsing task distribution module is used to accept parsing tasks and distribute the parsing tasks to each packet parsing processor;

[0037] The instruction memory is used to store the instructions of the packet parsing processor core;

[0038] The packet parsing processor core is used to execute a parsing program on the data packet according to the corresponding instructions, and output the intermediate parsing result containing the parsing state vector and the payload offset to the reordering module.

[0039] In one specific implementation, reference is made to... Figure 3 The packet header field extractor of the present invention includes a hash matching Benes network configuration circuit, a packet buffer read control circuit, a Benes network, and a bypass module;

[0040] The hash matching Benes network configuration circuit is used to match the intermediate parsing result output by the reordering module with the configuration information of the Benes network to obtain the Benes network configuration information and output it to the Benes network.

[0041] The packet buffer read control circuit is used to read packet data and align it with the Benes network configuration information in timing before outputting it to the Benes network;

[0042] The Benes network is used to extract fields from packet data and assemble them into a PHV according to the Benes network configuration information;

[0043] The bypass module is used to bypass the packet cache address, metadata, and payload offset in the intermediate parsing results, align them with the PHV output by the Benes network, and output them to the subsequent module of the parser device.

[0044] refer to Figure 4 , Figure 4 This is an application diagram of the parser device of the present invention for network switching ASIC chips. Figure 3 The multi-path parallel pipeline parsing unit further includes a configuration circuit. The input of the instruction memory is connected to the configuration circuit, and the input of the configuration circuit is connected to a control module. The input of the parsing task distribution module is connected to a cache control module, and the output of the cache control module is also connected to a packet cache module. The control module controls the configuration circuit so that the configuration circuit performs initialization configuration on the instruction memory and hash matching Benes network configuration circuit within the multi-path parallel pipeline parsing unit.

[0045] It is worth noting that the multi-path parallel pipelined parsing unit internally includes a parsing task distribution module, multiple packet parsing processor cores, and an instruction memory. The parsing task distribution module accepts parsing tasks submitted by the cache control module and distributes them to the packet parsing processors. The instruction memory stores the instructions for the packet parsing processors. The packet parsing processor core is a multi-stage pipelined processor containing instruction fetch, execution, write-back, and branching functions. It can execute parsing programs on data packets and output intermediate parsing results containing information such as the parsing state vector and payload offset. The data bus of the packet parsing processor is designed as a large-width bus (e.g., 2048 bits) to achieve packet header parsing at 100 GHz line speed.

[0046] exist Figure 4 In the network switching ASIC functional architecture shown, Figure 3 The parser device and its main peripheral modules shown are as follows:

[0047] The parser consists of three main components: multiple protocol-independent symmetric packet parsing processors, a reordering module, and a Benes network. It is used to identify the packet header protocols at each layer of the data packet, extract the header fields into the PHV for modification by the subsequent MAU, and output the payload offset position of the data packet to the inverse parser.

[0048] The packet caching module is used to temporarily store data to be parsed.

[0049] The cache control module is used to transfer data frames from the MAC to the packet cache, generate parsing tasks, and submit them to the task queue of the packet parsing processor.

[0050] MAU (Match-Action Unit) is used to perform matching-action behavior on PHV and metadata, and pass the modified PHV to the inverse parser;

[0051] The inverse parser is used to edit and update packet headers. It reassembles the modified PHV (Programmable Message Object) from the MAU (Manual User Account) into a header, and then, based on the payload offset provided by the parser, assembles the new header with the packet's payload to generate a new packet.

[0052] The queue scheduling and crossover nodes complete the enqueueing, dequeueing, and port forwarding of data packets, and finally output the data packets to the MAC-PHY for transmission from the switch port.

[0053] The control module and configuration circuitry are used by an external controller (CPU or other controller capable of register read / write operations) to initialize and configure the parser. The configuration includes the instruction memory of the packet parser, the hash matching module of the packet header field extractor, and the Benes configuration information RAM.

[0054] refer to Figure 3 In one specific implementation,

[0055] The cache control module is used to move data packets from the MAC to the packet cache module and to generate parsing tasks and submit them to the multi-channel parallel pipeline parsing unit.

[0056] The multi-path parallel pipeline parsing unit is used to accept and execute parsing tasks and output intermediate parsing results;

[0057] The reordering module is used to collect and summarize multiple intermediate parsing results, and sort the disordered intermediate parsing results to restore the disordered intermediate parsing results to the order before the data packet enters the multi-parallel pipeline parsing unit.

[0058] The packet header field extractor is used to extract packet cache address and metadata from the sorted intermediate parsing results, and to generate PHV content using the packet cache address and metadata; the metadata, packet cache address, payload offset and PHV content are time-aligned and output to the external back-end module.

[0059] Combination Figure 3 and Figure 4 The PHY-MAC receives incoming data streams and transmits the data packets to the buffer control module. The buffer control module stores the data packets in the packet buffer and submits the parsing task to the parser. The parser executes the parsing task, parses the packet header in the packet buffer to obtain the PHV, and transmits the PHV and metadata to the MAU. At the same time, it bypasses and passes information such as the payload offset to the reverse parser. The MAU pipeline updates and modifies the PHV and metadata, and outputs the updated PHV. The reverse parser retrieves the payload of the original data packet from the packet buffer, converts the new PHV into a packet header, assembles a new data packet, and submits it to the bus management. The data packet enters the queue buffer, passes through the queue buffer, cross-connect node, and MAC-PHY, and is then output from the switch.

[0060] refer to Figure 5 The packet parsing implementation steps of the reconfigurable packet protocol parser device for a 100 Gigabit network switching chip provided by this invention are as follows: Step 1 to Step 5 are as follows:

[0061] Step 1: The control module initializes and configures the parser through the configuration circuit on the parser. The configured modules include the instruction memory, hash matching module, and Benes configuration information RAM within the parser.

[0062] Step 2: The cache control module moves data packets from the MAC address to the packet cache, generates a parsing task, and submits it to the packet parsing processor. The functional implementation steps of the cache control module are as follows:

[0063] (2a) Move the data packets from the MAC to the packet cache module and generate a packet cache address;

[0064] (2b) Count the moved data packets and generate data packet count markers as the basis for restoring the parsing result order, and synchronously record the MAC port number and data packet length of the data packets as the packet metadata;

[0065] (2c) The packet cache address, packet count flag, metadata and initial parsing instruction address are combined into a parsing task, and the parsing task is submitted to the multi-path parallel pipeline parsing unit.

[0066] Step 3: The multi-path parallel pipeline parsing unit receives and executes the parsing task, outputting intermediate results. The main steps are as follows:

[0067] (3a) The parsing task distribution module is used to accept the parsing task submitted by the cache control module, and select the highest priority packet parsing processor core from the idle packet parsing processor cores according to the idle status of the packet parsing processor cores using the RR polling method, distribute the parsing task to the packet parsing processor core, and set the priority of the packet parsing processor core to the lowest.

[0068] (3b) The instruction memory is used to store the instructions of the packet parsing processor core;

[0069] (3c) The packet parsing processor core that receives the parsing task is used to retrieve the instruction and the data packet to be parsed from the instruction memory and the packet cache module respectively according to the instruction address and the packet cache address in the parsing task;

[0070] (3d) Execute the instruction to parse the data packet to obtain the upper-layer protocol type and current header size information of the data packet; concatenate multiple sets of upper-layer protocol type and current header size information data pairs and record them as a parsing state vector;

[0071] It is worth noting that after the instruction is executed, the upper-layer protocol type and the current header size information of the data packet are obtained. This information is then written back to the register file. The two pieces of information in each layer's header are usually multiple sets of "upper-layer protocol type - current header size" data pairs. These multiple sets of data pairs are concatenated and recorded as a parsed state vector.

[0072] (3e) The position offset when parsing the data packet is used as the payload offset, and the parsing state vector, payload offset, packet cache address, packet count flag and metadata contained in the parsing task are merged to obtain the intermediate parsing result and output it.

[0073] refer to Figure 6 The reordering module of the present invention includes a write control module, a ping-pong RAM and a read counter, wherein the input of the write control module is connected to the output of the plurality of parallel packet parsing processor cores.

[0074] Step 4, the reordering module, collects and summarizes the intermediate parsing results output by the multiple packet parsing processors mentioned above, and sorts the out-of-order intermediate results to restore them to the order in which the packets entered the parser. The sorting is based on the packet count marker. Specific steps include:

[0075] (4a) The write control module is used to receive all parsing intermediate results and determine the parsing intermediate results to be sorted; take the packet count flag in the parsing intermediate results to be sorted as the address and set the valid bit of the address to 1; write the parsing intermediate results to be sorted and the valid bit into the ping-pong RAM;

[0076] (4b) The ping-pong RAM is used to store the intermediate parsing results to be sorted and the valid bits of each address in data form;

[0077] (4c) The read counter is used to start counting from the initial value 0, use the count value as the read address of the ping-pong RAM, read the current row from the ping-pong RAM in a loop until the valid bit of the read data is 1, output the data with the valid bit of 1, write the valid bit of the output row data back to 0 and feed it back to the write control module, and increment the count value by 1 so that the parsing intermediate results in the ping-pong RAM are output in a sequential manner.

[0078] For example, the read counter initially reads intermediate parsing results and valid bits from address 0 of the ping-pong RAM in a loop, waiting for the write controller to write valid intermediate parsing results to address 0. Assuming the reordering module has collected two intermediate parsing results marked as 1 and 0, the write controller sequentially writes these intermediate parsing results to addresses 1 and 0 of the ping-pong RAM, setting the valid bits stored in addresses 1 and 0 to 1. While the write controller writes intermediate parsing results and valid bits to address 1, the read counter remains in a waiting state until the write controller writes these intermediate parsing results and valid bits to address 0. The valid bits read from address 0 then become 1, the intermediate parsing results in address 0 are output, and the write controller is notified to write the valid bits back to 0. Finally, the counter value is incremented by 1, and the read counter continues reading intermediate parsing results and valid bits from address 1. In this way, the read counter can eventually read the intermediate parsing results stored in the ping-pong RAM sequentially.

[0079] In this way, the read counter can eventually read out the intermediate parsing results stored in the ping-pong RAM sequentially.

[0080] This step repeats the processes of (4a), (4b) and (4c). The reordering module can sort the disordered intermediate parsing results, restore them to their original order, and output the ordered intermediate parsing results to the header field extractor.

[0081] refer to Figure 7 The packet header field extractor of the present invention includes a hash matching Benes network configuration circuit, a bypass module, a packet buffer read control circuit, and a Benes network;

[0082] The inputs of the hash matching Benes network configuration circuit, the bypass module, and the packet cache read control circuit are all connected to the output of the reordering module. The input of the hash matching Benes network configuration circuit is also connected to the output of the configuration circuit, and the input of the packet cache read control circuit is also connected to the output of the packet cache module. The outputs of the hash matching Benes network configuration circuit and the packet cache read control circuit are both connected to the input of the Benes network. The bypass module outputs the packet cache address, metadata, and payload offset, and the Benes network outputs PHV content.

[0083] Step 5: Extract the PHV using the header field extractor. Specific steps include:

[0084] (5a) The bypass module is used to parse the packet cache address from the reordered intermediate parsing results (including parsing state vector, packet cache address, metadata and other information);

[0085] (5b) The hash matching Benes network configuration circuit is used to parse the parsing state vector from the reordered parsing intermediate results; to match the parsing state vector with the Benes network configuration information address using a hash matching algorithm; if a match is found, the corresponding Benes network configuration information RAM address is passed forward; the hash matching Benes network configuration circuit retrieves the final Benes network configuration information from the Benes network configuration information RAM and transmits it to the Benes network.

[0086] The matching process is as follows: The parsed state vector is processed using a hash function (such as CRC), and the hash function result is used to look up the hash table. That is, the hash function result is used as the address of the hash table RAM, and the parsed state vector and the Benes network configuration information RAM address stored at that address are read out. The input parsed state vector is compared with the parsed state vector retrieved from the hash table. If the two are completely consistent, the corresponding Benes network configuration information RAM address is passed forward.

[0087] (5c) The packet buffer read control circuit is used to perform timing alignment of the packet buffer address output by the reordering module using a pipeline register in a timing manner; according to the packet buffer address passed by the timing, it retrieves the packet header data from the packet buffer module and aligns the retrieved packet header data with the final Benes network configuration information in timing; and sends the final Benes network configuration information and the packet header data into the Benes network together.

[0088] (5d) The Benes network is used to extract and rearrange fields in parallel from the packet header data to generate PHV content;

[0089] (5e) The Benes network aligns the metadata, packet cache address, and payload offset in the parsed intermediate results with the PHV content in a timing manner by using register slapping, and outputs them together with the PHV content to the external MAU module.

[0090] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0091] Although this application has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality.

[0092] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A reconfigurable packet protocol parser device for a 100 Gigabit network switching chip, characterized in that, include: Reordering module, header field extractor, and multi-path parallel pipeline parsing unit; The multi-path parallel pipeline parsing unit is used to parse data packets in response to the parsing task, obtain intermediate parsing results, and output them. The reordering module is used to collect and summarize the intermediate parsing results, and reorder the disordered intermediate parsing results and output them to the header field extractor. The packet header field extractor is used to extract PHV content from packet data using the intermediate parsing results, align metadata with the PHV content, and output it to an external back-end module. The multi-path parallel pipeline parsing unit includes a parsing task distribution module, an instruction memory, and multiple parallel packet parsing processor cores; The parsing task distribution module is used to accept parsing tasks and distribute the parsing tasks to each packet parsing processor; The instruction memory is used to store the instructions of the packet parsing processor core; The packet parsing processor core is used to execute a parsing program on the data packet according to the corresponding instructions, and output the intermediate parsing result containing the parsing state vector and the payload offset to the reordering module; The multi-path parallel pipeline parsing unit further includes a configuration circuit. The input of the instruction memory is connected to the configuration circuit, and the input of the configuration circuit is connected to a control module. The input of the parsing task distribution module is connected to a cache control module, and the output of the cache control module is also connected to a packet cache module. The control module controls the configuration circuit so that the configuration circuit performs initialization configuration on the instruction memory and hash matching Benes network configuration circuit in the multi-path parallel pipeline parsing unit. The parsing task distribution module is used to accept the parsing tasks submitted by the cache control module, and select the highest priority packet parsing processor core from the idle packet parsing processor cores using the RR polling method according to the idle status of the packet parsing processor cores, distribute the parsing task to the packet parsing processor core, and set the priority of the packet parsing processor core to the lowest. The instruction memory is used to store the instructions of the packet parsing processor core; The packet parsing processor core that receives the parsing task is used to retrieve the instruction and the data packet to be parsed from the instruction memory and the packet cache module respectively, according to the instruction address and packet cache address in the parsing task; execute the instruction to parse the data packet to obtain the upper-layer protocol type and current header size information of the data packet; concatenate multiple sets of upper-layer protocol type and current header size information data pairs to record a parsing state vector; use the position offset when parsing the data packet as the payload offset, and merge the parsing state vector, payload offset, packet cache address, packet count flag and metadata contained in the parsing task to obtain the parsing intermediate result and output it.

2. The reconfigurable packet protocol parser device for a 100 Gigabit network switching chip according to claim 1, characterized in that, The cache control module is used to move data packets from the MAC to the packet cache module and to generate parsing tasks and submit them to the multi-channel parallel pipeline parsing unit. The multi-path parallel pipeline parsing unit is used to accept and execute parsing tasks and output intermediate parsing results; The reordering module is used to collect and summarize multiple intermediate parsing results, and sort the disordered intermediate parsing results to restore the disordered intermediate parsing results to the order before the data packet enters the multi-parallel pipeline parsing unit. The packet header field extractor is used to extract the packet cache address and metadata from the sorted intermediate parsing results, and to generate PHV content using the packet cache address and metadata; The metadata, packet cache address, payload offset, and PHV content are time-aligned and output to the external back-end module.

3. The reconfigurable packet protocol parser device for a 100 Gigabit network switching chip according to claim 1, characterized in that, The reordering module includes a write control module, a ping-pong RAM, and a read counter. The input of the write control module is connected to the output of the multiple parallel packet parsing processor cores.

4. The reconfigurable packet protocol parser device for a 100 Gigabit network switching chip according to claim 1, characterized in that, The packet header field extractor includes a hash matching Benes network configuration circuit, a bypass module, a packet buffer read control circuit, a Benes network, and a bypass module; The inputs of the hash matching Benes network configuration circuit, the bypass module, and the packet cache read control circuit are all connected to the output of the reordering module. The input of the hash matching Benes network configuration circuit is also connected to the output of the configuration circuit, and the input of the packet cache read control circuit is also connected to the output of the packet cache module. The outputs of the hash matching Benes network configuration circuit and the packet cache read control circuit are both connected to the input of the Benes network. The bypass module outputs the packet cache address, metadata, and payload offset, and the Benes network outputs PHV content.

5. The reconfigurable packet protocol parser device for a 100 Gigabit network switching chip according to claim 1, characterized in that, The cache control module is specifically used for: (2a) Move the data packets from the MAC to the packet cache module and generate the packet cache address; (2b) Count the moved data packets and generate data packet count markers as the basis for restoring the parsing result order, and synchronously record the MAC port number and data packet length of the data packets as the packet metadata; (2c) The packet cache address, packet count flag, metadata and initial parsing instruction address are combined into a parsing task, and the parsing task is submitted to the multi-path parallel pipeline parsing unit.

6. The reconfigurable packet protocol parser device for a 100 Gigabit network switching chip according to claim 3, characterized in that, The write control module is used to receive all intermediate parsing results and determine the intermediate parsing results to be sorted; it uses the packet count flag in the intermediate parsing results to be sorted as an address and sets the valid bit of the address to 1. Write the intermediate parsing results and valid bits to be sorted into the Ping Pong RAM; The ping-pong RAM is used to store the intermediate parsing results to be sorted and the valid bits of each address in data form; The read counter is used to count from an initial value of 0, and the count value is used as the read address of the ping-pong RAM. It reads the current row from the ping-pong RAM in a loop until the valid bit of the read data is 1. The data with the valid bit of 1 is output, and the valid bit of the output row data is written back to 0 and fed back to the write control module. The count value is incremented by 1 so that the parsing intermediate results in the ping-pong RAM are output in a sequential manner.

7. The reconfigurable packet protocol parser device for a 100 Gigabit network switching chip according to claim 4, characterized in that, The hash matching Benes network configuration circuit is used to match the intermediate parsing result output by the reordering module with the configuration information of the Benes network to obtain the Benes network configuration information and output it to the Benes network. The packet buffer read control circuit is used to read packet data and align it with the Benes network configuration information in timing before outputting it to the Benes network; The Benes network is used to extract fields from packet data and assemble them into a PHV according to the Benes network configuration information; The bypass module is used to bypass and pass the packet cache address, metadata, and payload offset in the intermediate parsing results, align them with the PHV output by the Benes network, and output them to the external back-end module.

Images