BIT circuit and testing method of 28v / open discrete quantity output interface

Abstract

The application provides a BIT circuit and a test method of a 28V / open discrete quantity output interface, the BIT circuit comprising a busbar voltage acquisition circuit, a 28V / open discrete quantity output acquisition circuit, an AD acquisition circuit and a CPU, the 28V / open discrete quantity output acquisition circuit comprising a current sampling resistor and a BIT acquisition circuit, one end of the current sampling resistor being connected with the BIT acquisition circuit in series and the other end being grounded; wherein the BIT acquisition circuit comprises a plurality of parallel current limiting resistors, each current limiting resistor being connected with one 28V / open discrete quantity output interface respectively; the test method comprising the following steps: designing the BIT acquisition circuit; establishing a calibration table and / or a calibration curve; calculating a current output voltage of the 28V / open discrete quantity output acquisition circuit; and performing BIT test and analysis on the output test result. The circuit and the method of the application greatly reduce the hardware cost, reduce the hardware resource expenditure, improve the hardware resource utilization rate and improve the detection efficiency.

Description

Technical Field

[0001] This invention belongs to the field of airborne electronic equipment technology, and relates to a BIT circuit and testing method for a 28V / open discrete output interface. Background Technology

[0002] Electromechanical systems (EMS) are the collective term for subsystems in an aircraft that perform flight support functions. They are essential and fundamental conditions for ensuring the proper functioning of all aircraft features, and their reliability directly impacts flight safety. EMS typically involve the control of various valves and pumps, such as solenoid valves, combination valves, and relays. These actuators are generally controlled using 28V / open discrete output interfaces from EMS products. Therefore, aviation EMS products contain numerous 28V / open discrete output interface circuits to meet the requirements of EMS systems.

[0003] Currently, the BIT detection of the 28V / open discrete output interface circuit of onboard products is mostly implemented using discrete quantity acquisition chips, via SPI or I... 2 While the C-bus communication method is simple for acquiring output status, it results in higher hardware implementation costs for the BIT detection circuit and requires additional system communication resources. Summary of the Invention

[0004] To address the technical issues of high hardware design costs and excessive system communication resource consumption associated with using discrete quantity acquisition chips for BIT testing of 28V / on discrete quantity output interface circuits, this invention discloses a BIT circuit and testing method for a 28V / on discrete quantity output interface.

[0005] The technical solution to achieve the purpose of the invention is as follows:

[0006] The first aspect of this invention discloses a BIT circuit for a 28V / on discrete output interface, including a busbar voltage acquisition circuit, a 28V / on discrete output retrieval circuit, an AD acquisition circuit, and a CPU;

[0007] One end of the busbar voltage acquisition circuit is connected to the 28V busbar, and the other end is connected to the AD acquisition circuit;

[0008] The 28V / on discrete output sampling circuit includes a current sampling resistor and a BIT sampling circuit. One end of the current sampling resistor is connected in series with the BIT sampling circuit, and the other end is grounded. The BIT sampling circuit includes multiple parallel current-limiting resistors, and each current-limiting resistor is connected to a 28V / on discrete output interface.

[0009] One end of the AD acquisition circuit is connected to the 28V / on discrete output sampling circuit, and the other end is connected to the CPU. The CPU outputs the current output voltage of each 28V / on discrete output interface based on the sampling voltage of the 28V busbar output by the AD acquisition circuit and the sampling voltage of the 28V / on discrete output sampling circuit, and performs a BIT test based on the current output voltage.

[0010] Furthermore, the busbar voltage acquisition circuit includes a first voltage divider resistor RH and a second voltage divider resistor RL with different resistance values;

[0011] One end of the first voltage divider resistor RH is connected to the 28V busbar, and the other end is connected to the AD acquisition circuit;

[0012] One end of the second voltage divider resistor RL is grounded, and the other end is connected to the AD acquisition circuit.

[0013] Furthermore, in the BIT sampling circuit, according to the numbering order of the plurality of 28V / on discrete output interfaces, the resistance value of each current-limiting resistor connected to each 28V / on discrete output interface is assigned sequentially in a multiplicative manner according to the numbering order.

[0014] Furthermore, in two adjacent current-limiting resistors, the resistance value of the first current-limiting resistor is twice the resistance value of the second current-limiting resistor.

[0015] The second aspect of this invention discloses a test method for a 28V / on discrete output interface, which uses the BIT circuit of the 28V / on discrete output interface described in the first aspect for BIT testing. The test method includes:

[0016] S1. Number the 28V / on discrete output interfaces, and assign the resistance value of the current limiting resistor connected to each 28V / on discrete output interface in a multiplicative manner according to the numbering order to obtain the BIT retrieval circuit.

[0017] S2. Based on the current sampling resistor, the BIT retrieval circuit, and the busbar voltage acquisition circuit, establish a calibration table and / or calibration curve for the 28V / open discrete output retrieval signal;

[0018] S3. Condition, amplify and convert the sampled voltages of the 28V busbar and the 28V / on discrete output sampling circuit respectively to obtain the voltage digital signal of the 28V busbar and the voltage digital signal of the 28V / on discrete output sampling circuit.

[0019] S4. Based on the voltage digital signal of the 28V busbar, the voltage digital signal of the 28V / on discrete output sampling circuit, the calibration table or the calibration curve, obtain the current output voltage of the 28V / on discrete output sampling circuit.

[0020] S5. Perform BIT test analysis based on the current output voltage, and output a BIT test pass signal or a circuit fault signal.

[0021] Further, in step S2 above, establishing a calibration table and / or calibration curve for the 28V / open discrete output retrieval signal based on the current sampling resistor, the BIT retrieval circuit, and the busbar voltage acquisition circuit includes:

[0022] S21. Calculate the sampling voltage of the 28V / on discrete output sampling circuit in multiple set output states, wherein the set output states are the output states defined in the BIT sampling circuit for each of the 28V / on discrete output interfaces.

[0023] S22. Normalize the sampling voltage of each set output state to obtain the normalized sampling voltage of each set output state.

[0024] S23. Based on each set output state and its normalized sampling voltage, establish a calibration table and / or calibration curve for 28V / on discrete output sampling.

[0025] Furthermore, in step S21 above, the calculation of the sampling voltage of the 28V / on discrete output sampling circuit in multiple set output states includes:

[0026] S211. Define the output state of each of the 28V / on discrete output interfaces in the BIT sampling circuit to obtain the set output state of the BIT sampling circuit;

[0027] S212. Calculate the resistance value of the BIT retrieval circuit according to the set output state;

[0028] S213. Based on the resistance value of the current sampling resistor, the resistance value of the BIT sampling circuit, and the sampling voltage of the busbar voltage acquisition circuit in the set output state, calculate the sampling voltage of the BIT sampling circuit in the set output state.

[0029] S214. Repeat steps S211 to S213 to obtain multiple sampling voltages of the set output states.

[0030] Further, in step S5 above, BIT test analysis is performed based on the current output voltage, and a BIT test pass signal or circuit fault signal is output, including:

[0031] S51. Compare the current output voltage with the sampling voltage of the 28V busbar;

[0032] S52. When the comparison result in step S51 is within the set tolerance range, the current output voltage is compared with the 28V / on output command. If the comparison result is the same, a BIT test pass signal is output. If the comparison result is different, a circuit fault signal is output.

[0033] S53. If the comparison result in step S51 exceeds the set tolerance range, a circuit fault signal is output.

[0034] Compared with the prior art, the beneficial effects that at least one of the above-mentioned technical solutions adopted in the embodiments of this specification can achieve include at least the following: The BIT circuit disclosed in this invention uses the sampling voltage collected by the 28V / on discrete output sampling circuit composed of the BIT sampling circuit and the current sampling resistor, and the sampling voltage of the 28V busbar collected by the busbar voltage acquisition circuit, and performs BIT testing on the current output voltage obtained by the AD acquisition circuit and CPU processing. The BIT circuit and its detection method of this invention can perform BIT testing on all 28V / on discrete output interfaces by using only one sampling voltage of the output collected by the 28V / on discrete output sampling circuit, which can significantly reduce hardware costs, greatly reduce hardware resource expenditures, improve hardware resource utilization, and improve detection efficiency. Attached Figure Description

[0035] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of the BIT circuit for the 28V / on discrete output interface disclosed in an embodiment of the present invention;

[0037] Figure 2 This is a flowchart of the test method for the 28V / on discrete output interface disclosed in an embodiment of the present invention;

[0038] Figure 3 This is a schematic diagram of the program operation of the test method for the 28V / on discrete output interface disclosed in an embodiment of the present invention;

[0039] Figure 4This is a schematic diagram of the calibration curve disclosed in an embodiment of the present invention. Detailed Implementation

[0040] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0041] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features of the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0042] This invention discloses a BI T circuit for a 28V / on discrete output interface. The BI T circuit includes a busbar voltage acquisition circuit, a 28V / on discrete output acquisition circuit, an AD acquisition circuit, and a CPU.

[0043] See Figure 1 As shown, one end of the busbar voltage acquisition circuit is connected to the 28V busbar, and the other end is connected to the AD acquisition circuit (e.g., Figure 1 The AD conversion shown in the figure is connected.

[0044] See Figure 1 As shown, the 28V / on discrete output sampling circuit includes a current sampling resistor R010 and a BIT sampling circuit. One end of the current sampling resistor R010 is connected in series with the BIT sampling circuit, and the other end is grounded. The BIT sampling circuit includes multiple parallel current-limiting resistors (such as...). Figure 1 As shown in R1 to R8), each of the current-limiting resistors is connected to a 28V / on discrete output interface (e.g., R1 to R8). Figure 1 The 28VK output shown is connected.

[0045] See Figure 1 As shown, one end of the AD acquisition circuit is connected to the 28V / on discrete output retrieval circuit, and the other end is connected to the CPU. The CPU outputs the current output voltage of each 28V / on discrete output interface based on the sampling voltage of the 28V busbar output by the AD acquisition circuit and the sampling voltage of the 28V / on discrete output retrieval circuit, and performs BIT testing based on the current output voltage.

[0046] In an optional embodiment, see Figure 1 As shown, the busbar voltage acquisition circuit includes a first voltage divider resistor RH and a second voltage divider resistor RL with different resistance values. One end of the first voltage divider resistor RH is connected to the 28V busbar, and the other end is connected to the AD acquisition circuit. One end of the second voltage divider resistor RL is grounded, and the other end is connected to the AD acquisition circuit. In specific implementation, the resistance value of the first voltage divider resistor RH can be selected as 49.9KΩ, and the resistance value of the second voltage divider resistor RL can be selected as 100Ω. The voltage of the 28V busbar is divided and then supplied to the AD acquisition circuit. The voltage division ratio of the two voltage divider resistors is 1 / 500.

[0047] Furthermore, in the BIT sampling circuit, according to the numbering order of the plurality of 28V / on discrete output interfaces, the resistance value of each current-limiting resistor connected to each 28V / on discrete output interface is assigned sequentially in a multiplicative manner according to the numbering order.

[0048] Furthermore, in two adjacent current-limiting resistors, the resistance value of the preceding current-limiting resistor is twice the resistance value of the following current-limiting resistor. For specific implementation details, see [link to implementation details]. Figure 1 As shown, the eight 28V / on discrete output interfaces are numbered sequentially. The current-limiting resistors R1 to R8 on interfaces numbered 1 through 8 can be assigned values ​​in a 2x relationship. For example, the current-limiting resistor R1 for interface number 1 is 128K, R2 for interface number 2 is 64K, and so on, with R8 for interface number 8 being 1K. It should be noted that the resistance value of the current-limiting resistor for each 28V / on discrete output interface will vary depending on the number of interfaces, and this invention does not limit this value.

[0049] In practical implementation, the AD acquisition circuit mainly conditions, amplifies, and converts the acquired sampling voltage to obtain a digital voltage signal, which is then output to the CPU. The CPU is mainly used to complete the acquisition control of the circuit and the data processing after acquisition, calculate the current output voltage of the 28V / open discrete output retrieval circuit, analyze the current output voltage, output the analysis results, and complete the BIT test.

[0050] This invention also discloses a test method for a 28V / on discrete output interface, which uses the aforementioned BIT circuit for the 28V / on discrete output interface for BIT testing. (See [link to relevant documentation]). Figure 2 and Figure 3 As shown, the test method includes:

[0051] S1. Number the 28V / on discrete output interfaces, and assign the resistance value of the current limiting resistor connected to each 28V / on discrete output interface in a multiplicative manner according to the numbering order to obtain the BIT retrieval circuit.

[0052] S2. Based on the current sampling resistor, the BIT retrieval circuit, and the busbar voltage acquisition circuit, establish a calibration table and / or calibration curve for the 28V / open discrete output retrieval signal;

[0053] S3. Condition, amplify and convert the sampled voltages of the 28V busbar and the 28V / on discrete output sampling circuit respectively to obtain the voltage digital signal of the 28V busbar and the voltage digital signal of the 28V / on discrete output sampling circuit.

[0054] S4. Based on the voltage digital signal of the 28V busbar, the voltage digital signal of the 28V / on discrete output sampling circuit, the calibration table or the calibration curve, obtain the current output voltage of the 28V / on discrete output sampling circuit.

[0055] S5. Perform BIT test analysis based on the current output voltage, and output a BIT test pass signal or a circuit fault signal.

[0056] Further, in step S2 above, establishing a calibration table and / or calibration curve for the 28V / open discrete output retrieval signal based on the current sampling resistor, the BIT retrieval circuit, and the busbar voltage acquisition circuit includes:

[0057] S21. Calculate the sampling voltage of the 28V / on discrete output sampling circuit in multiple set output states, wherein the set output states are the output states defined in the BIT sampling circuit for each of the 28V / on discrete output interfaces.

[0058] S22. Normalize the sampling voltage of each set output state to obtain the normalized sampling voltage of each set output state.

[0059] S23. Based on each set output state and its normalized sampling voltage, establish a calibration table and / or calibration curve for 28V / on discrete output sampling.

[0060] Furthermore, in step S21 above, the calculation of the sampling voltage of the 28V / on discrete output sampling circuit in multiple set output states includes:

[0061] S211. Define the output state of each of the 28V / on discrete output interfaces in the BIT sampling circuit to obtain the set output state of the BIT sampling circuit;

[0062] S212. Based on the set output state, calculate the resistance value of the BIT retrieval circuit. Specifically, the formula for calculating the resistance value of the BIT retrieval circuit is: R a =R T1 ||R T2 ||…||R T8 , where R a R is the resistance value of the bit retrieval circuit in the current output state. Tx Let be the equivalent resistance of the current-limiting resistor in the x-th path, which is given by the formula. The calculation yields the result, where x∈[1,8].

[0063] S213. Based on the resistance value of the current sampling resistor, the resistance value of the BIT sampling circuit, and the sampling voltage of the busbar voltage acquisition circuit in the set output state, calculate the sampling voltage of the BIT sampling circuit in the set output state.

[0064] In practical implementation, the formula for calculating the sampling voltage in the output state is set as follows: Among them, V OUT U0 is the sampling voltage of the 28V busbar, and R0 is the resistance value of the current sampling resistor. In this embodiment, U0 is 28V.

[0065] S214. Repeat steps S211 to S213 to obtain multiple sampled voltages of the set output states;

[0066] In practice, by traversing all output states defined by the 8-channel 28V / open discrete output interface, i.e., 00000000~11111111 (0 is open output, 1 is 28V output), and repeating steps S211 to S213, a one-to-one correspondence between the output and the busbar voltage acquisition circuit under different output states can be established.

[0067] In specific implementation, in step S22 above, the formula V is used. BIT =K·V OUT / V BUS Normalization is performed, where V BIT For the normalized sampling voltage, V BUS The voltage collected by the busbar voltage acquisition circuit is K, which is a scaling factor. In this embodiment, K is set to 500, and the following relationship exists: V BUS =U0·RL / (RL+RH), In this embodiment, V can be calculated.BUS =56mV.

[0068] In specific implementation, step S23 involves traversing calculations to obtain the normalized voltage V. BIT The calibration table for the 28V / on-state output of the circuit is shown in Table 1 below. The normalized voltage V is then plotted. BIT The calibration curve with 28V / on-state output is as follows: Figure 4 As shown.

[0069] Table 1: Calibration Table

[0070]

[0071] In specific implementation of steps S3 and S4 above, the sampling voltage V of the 28V busbar is acquired. bus And the sampling voltage V of the 28V / on discrete output retrieval circuit. out V is obtained by filtering it. bus0 and V out0 Preferably, the voltage filtering in this embodiment is performed using a sliding window averaging filtering algorithm.

[0072] The voltage of the 28V / open discrete output sampling circuit is normalized, V bit =K·V out0 / V bus0 , to obtain V bit In the formula, K is a scaling factor, which is 500 in this embodiment.

[0073] Using normalized voltage V bit By consulting the calibration curve, the current output voltage of the 28V / open discrete output sampling circuit can be obtained.

[0074] Further, in step S5 above, a BIT test analysis is performed based on the current output voltage, and a BIT test pass signal or a circuit fault signal is output, including:

[0075] S51. Compare the current output voltage with the sampling voltage of the 28V busbar;

[0076] S52. When the comparison result in step S51 is within the set tolerance range, the current output voltage is compared with the 28V / on output command. If the comparison result is the same, a BIT test pass signal is output. If the comparison result is different, a circuit fault signal is output. In specific implementation, the set tolerance range can be [26.5V, 29.5V].

[0077] S53. If the comparison result in step S51 exceeds the set tolerance range, a circuit fault signal is output.

[0078] The embodiments of this invention achieve the following technical effects: The BIT circuit disclosed in this invention uses a 28V / on discrete output retrieval circuit composed of a BIT retrieval circuit and a current sampling resistor to collect the sampled voltage, and a busbar voltage acquisition circuit to collect the sampled voltage of the 28V busbar. The current output voltage obtained through AD acquisition circuit and CPU processing is then used for BIT testing. The BIT circuit and its detection method of this invention can perform BIT testing on all 28V / on discrete output interfaces using only one sampled voltage collected by the 28V / on discrete output retrieval circuit. This can significantly reduce hardware costs, greatly reduce hardware resource expenditures, improve hardware resource utilization, and improve detection efficiency.

[0079] Obviously, those skilled in the art should understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Various modifications and variations of the embodiments of the present invention are possible for those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A BIT circuit with a 28V / open discrete output interface, characterized in that: Includes a busbar voltage acquisition circuit, a 28V / open discrete output acquisition circuit, an AD acquisition circuit, and a CPU; One end of the busbar voltage acquisition circuit is connected to the 28V busbar, and the other end is connected to the AD acquisition circuit; The 28V / on discrete output feedback circuit includes a current sampling resistor and a BIT feedback circuit. One end of the current sampling resistor is connected in series with the BIT feedback circuit, and the other end is grounded. The BIT feedback circuit includes multiple parallel current-limiting resistors, each connected to a 28V / on discrete output interface. In the BIT feedback circuit, according to the numbering order of the multiple 28V / on discrete output interfaces, the resistance value of each current-limiting resistor connected to each 28V / on discrete output interface is assigned sequentially in a multiplicative manner according to the numbering order. In two adjacent current-limiting resistors, the resistance value of the preceding current-limiting resistor is twice the resistance value of the following current-limiting resistor. One end of the AD acquisition circuit is connected to the 28V / on discrete output sampling circuit, and the other end is connected to the CPU. The CPU outputs the current output voltage of each 28V / on discrete output interface based on the sampling voltage of the 28V busbar output by the AD acquisition circuit and the sampling voltage of the 28V / on discrete output sampling circuit, and performs a BIT test based on the current output voltage.

2. The BIT circuit for the 28V / on discrete output interface according to claim 1, characterized in that: The busbar voltage acquisition circuit includes a first voltage divider resistor RH and a second voltage divider resistor RL with different resistance values; One end of the first voltage divider resistor RH is connected to the 28V busbar, and the other end is connected to the AD acquisition circuit; One end of the second voltage divider resistor RL is grounded, and the other end is connected to the AD acquisition circuit.

3. A test method for a 28V / open discrete output interface, characterized in that: The BIT test is performed using the BIT circuit with a 28V / on discrete output interface as described in claim 1 or 2, and the test method includes: S1. Number the 28V / on discrete output interfaces, and assign the resistance value of the current limiting resistor connected to each 28V / on discrete output interface in a multiplicative manner according to the numbering order to obtain the BIT retrieval circuit. S2. Based on the current sampling resistor, the BIT retrieval circuit, and the busbar voltage acquisition circuit, establish a calibration table and / or calibration curve for the 28V / open discrete output retrieval signal; S3. Condition, amplify and convert the sampled voltages of the 28V busbar and the 28V / on discrete output sampling circuit respectively to obtain the voltage digital signal of the 28V busbar and the voltage digital signal of the 28V / on discrete output sampling circuit. S4. Based on the voltage digital signal of the 28V busbar, the voltage digital signal of the 28V / on discrete output sampling circuit, the calibration table or the calibration curve, obtain the current output voltage of the 28V / on discrete output sampling circuit. S5. Perform BIT test analysis based on the current output voltage, and output a BIT test pass signal or a circuit fault signal.

4. The test method for the 28V / on discrete output interface according to claim 3, characterized in that: In step S2, establishing a calibration table and / or calibration curve for the 28V / open discrete output retrieval signal based on the current sampling resistor, the BIT retrieval circuit, and the busbar voltage acquisition circuit includes: S21. Calculate the sampling voltage of the 28V / on discrete output sampling circuit in multiple set output states, wherein the set output states are the output states defined in the BIT sampling circuit for each of the 28V / on discrete output interfaces. S22. Normalize the sampling voltage of each set output state to obtain the normalized sampling voltage of each set output state. S23. Based on each set output state and its normalized sampling voltage, establish a calibration table and / or calibration curve for 28V / on discrete output sampling.

5. The test method for the 28V / on discrete output interface according to claim 4, characterized in that: In step S21, calculating the sampling voltage of the 28V / on discrete output sampling circuit in multiple set output states includes: S211. Define the output state of each of the 28V / on discrete output interfaces in the BIT sampling circuit to obtain the set output state of the BIT sampling circuit; S212. Calculate the resistance value of the BIT retrieval circuit according to the set output state; S213. Based on the resistance value of the current sampling resistor, the resistance value of the BIT sampling circuit, and the sampling voltage of the busbar voltage acquisition circuit in the set output state, calculate the sampling voltage of the BIT sampling circuit in the set output state. S214. Repeat steps S211 to S213 to obtain multiple sampling voltages of the set output states.

6. The test method for the 28V / on discrete output interface according to claim 3, characterized in that: In step S5, a BIT test analysis is performed based on the current output voltage, and a BIT test pass signal or a circuit fault signal is output, including: S51. Compare the current output voltage with the sampling voltage of the 28V busbar; S52. When the comparison result in step S51 is within the set tolerance range, the current output voltage is compared with the 28V / on output command. If the comparison result is the same, a BIT test pass signal is output. If the comparison result is different, a circuit fault signal is output. S53. If the comparison result in step S51 exceeds the set tolerance range, a circuit fault signal is output.

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