Parallel fast time dimension constant false alarm rate implementation method based on barrel buffer processing structure

Abstract

The application discloses a parallel fast time dimension constant false alarm realization method based on a barrel-shaped buffer processing structure, which is applied to an FPGA, and the method comprises the following steps: converting first data output by a moving target detection unit and represented by a distance dimension and a Doppler dimension into second data represented by a distance dimension, a Doppler dimension and a sub-Doppler dimension; dividing the second data according to the sub-Doppler dimension by using a serial-parallel conversion module to obtain a plurality of sub-data groups; inputting each sub-data group into a CFAR detection and buffer; in the CFAR detection and buffer: constructing a barrel-shaped buffer processing structure model, buffering and detecting the input sub-data group based on the barrel-shaped buffer processing structure model to obtain a detection result; and in an information synthesis module, merging the detection result with corresponding speed dimension and distance dimension information to obtain a constant false alarm detection result. The application improves the FPGA processing efficiency and reduces the FPGA resource occupation.

Description

Technical Field

[0001] This invention belongs to the field of radar signal processing technology, specifically relating to a parallel fast time-dimensional constant false alarm rate implementation method based on a barrel buffer processing structure. Background Technology

[0002] In recent years, Field Programmable Gate Arrays (FPGAs) have continued to develop, integrating rich logic resources and various hard cores, and have very powerful processing capabilities. Radar signal processing based on FPGA platforms has the characteristics of high real-time performance and large bandwidth, and has been widely used in various radar signal processing systems.

[0003] Radar signal processing typically includes digital down-conversion, pulse compression, moving target detection (MTD), and constant false alarm rate (CFAR) detection (CVD). In the digital down-conversion, pulse compression, and CFAR stages, data is processed along the range dimension. However, when the data passes through the MTD stage, it is output along the Doppler dimension. The CFAR stage is usually placed after the MTD stage. This means that when there is a large amount of pulse data, the input data to the CFAR stage is Doppler data transposed through Double Data Rate SDRAM (DDR). The data output for the next cycle after DDR transposition is the next Doppler data. In FPGA platforms, an external DDR is typically used to implement the data direction conversion from the range dimension to the Doppler dimension in the MTD stage. For the FPGA implementation of the CFAR algorithm, the main considerations are implementation time delay and resource consumption. In this context, to achieve constant false alarm rate (CFAR) detection along the distance dimension, existing technologies employ a "ping-pong" approach when pulse data is limited. This involves using the on-chip Block RAM (BRAM) of the FPGA to convert the data from the Doppler dimension to the distance dimension before detection. However, when the number of pulses is high, the conversion from the Doppler dimension to the distance dimension is typically accomplished using DDR buffer data before CFAR detection.

[0004] However, existing design schemes have two drawbacks. First, the matrix transpose processing takes too long, which negatively impacts the real-time processing and data caching structure of the system and reduces the efficiency of the FPGA signal processing system. Second, when there are many pulses, the matrix transpose needs to be completed using DDR. The matrix transpose implementation method of DDR read / write controller requires a lot of additional buffering and resource consumption, which may lead to excessive use of internal logic resources in the FPGA and result in timing deterioration. Summary of the Invention

[0005] To address the aforementioned problems in the existing technology, this invention provides a parallel fast-time dimensionless constant false alarm rate implementation method based on a barrel-buffered processing structure. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] This invention provides a parallel fast-time constant false alarm rate (CFAR) implementation method based on a barrel-buffered processing structure, applied in an FPGA. The FPGA includes a serial-to-parallel conversion module, several CFAR detection and buffers, and an information synthesis module. The output of the serial-to-parallel conversion module is connected to one of the CFAR detection and buffers, and the output of each CFAR detection and buffer is connected to the information synthesis module. The method includes:

[0007] The first data output by the moving target detection unit, characterized by two dimensions, distance dimension and Doppler dimension, is transformed into second data characterized by three dimensions, distance dimension, Doppler dimension and sub-Doppler dimension.

[0008] The second data is divided into several sub-data groups by sub-Doppler dimensions using a serial-to-parallel conversion module;

[0009] Each sub-data set is input into a CFAR detection and buffer; in the CFAR detection and buffer: a barrel-shaped buffer processing structure model is constructed, and the input sub-data sets are buffered and detected based on the barrel-shaped buffer processing structure model to obtain the detection result;

[0010] In the information integration module, the detection result is combined with the corresponding velocity dimension and distance dimension information to obtain the constant false alarm rate (CFAR) detection result.

[0011] In one embodiment of the present invention, constructing a barrel-shaped buffer processing structure model includes:

[0012] Determine the length of the constant false alarm detection window;

[0013] Based on the length of the constant false alarm rate (CFAR) detection window, a barrel-shaped buffer processing structure characterized by two dimensions, distance and Doppler, is constructed; wherein, the distance dimension of the barrel-shaped buffer processing structure is the length of the CFAR detection window, and the Doppler dimension of the barrel-shaped buffer processing structure is the length of the sub-Doppler data.

[0014] In one embodiment of the present invention, each CFAR detection and buffer includes: a selector, a CFAR barrel shifter module, a CFAR buffer module, and a CFAR detection module, wherein the CFAR barrel shifter module includes a plurality of barrel shift register groups, each barrel shift register group being constructed according to the barrel buffer processing structure model; the input terminal of the selector is connected to the output terminal of the CFAR buffer module and the output terminal of the serial-to-parallel conversion module, the output terminal of the selector is connected to the input terminal of the CFAR barrel shifter module, the output terminal of the CFAR barrel shifter module is connected to the input terminal of the CFAR buffer module and the input terminal of the CFAR detection module, and the output terminal of the CFAR detection module is connected to the information synthesis module; the processing of the sub-data group input to the serial-to-parallel conversion module in each CFAR detection and buffer includes:

[0015] The selector selects between the input sub-data group and the data output by the CFAR buffer module:

[0016] If the data output by the CFAR buffer module is selected, the data output by the CFAR buffer module will overwrite the data of the CFAR barrel shifter module. At the same time, the data stored in the CFAR barrel shifter module will overwrite the data buffered and stored in the CFAR buffer module. The data stored in the CFAR barrel shifter module will then be input into the CFAR detection module for detection to obtain the detection result.

[0017] If the sub-data group input to the serial-to-parallel conversion module is selected, the data stored in the CFAR barrel shifter module is updated using the sub-data group input to the serial-to-parallel conversion module. At the same time, the data stored in the CFAR barrel shifter module is used to overwrite the data stored in the CFAR buffer module, and the data stored in the CFAR barrel shifter module is input into the CFAR detection module for detection to obtain the detection result.

[0018] In one embodiment of the present invention, updating the data stored in the CFAR barrel shifter module using the sub-data group input by the serial-to-parallel conversion module includes:

[0019] The sub-data group input by the serial-to-parallel conversion module is used to cover the data stored in the least significant bit register group of the barrel shift register group;

[0020] The data stored in the nth register group of the barrel shift register group is used to overwrite the data stored in the (n+1)th register group of the barrel shift register group. The value of n is from 1 to N-1, and N represents the number of register groups in the barrel shift register group; N is an integer greater than 1.

[0021] Discard the data stored in the highest bit register of the barrel shift register group.

[0022] In one embodiment of the present invention, the least significant bit register group of the barrel shift register group is covered by the input sub-data group, as expressed by the formula: B(0,p)|a=D(m,n,a);

[0023] Where m = 0, 1, 2, 3, ..., M-1, and M represents the number of distance cells. N represents the number of Doppler units, A represents the number of sub-Doppler units, a = 0, 1, 2, 3, ..., A-1, D(m,n,a) represents the second data corresponding to the m distance units, the nth Doppler unit, and the ath sub-Doppler unit, B(0,p)|a represents the data stored in the least significant register group of the barrel shift register group corresponding to the ath sub-Doppler unit, and p represents the length of each barrel shift register group.

[0024] In one embodiment of the present invention, the nth register group of the barrel shift register group is used to cover the (n+1)th register group of the barrel shift register group, as expressed by the formula: B(q,p)|a=B(q-1,p)|a;

[0025] Where B(q,p)|a represents the data stored in the q-th register group of the barrel shift register group corresponding to the a-th sub-Doppler unit, B(q-1,p)|a represents the data stored in the (q-1)-th register group of the barrel shift register group corresponding to the a-th sub-Doppler unit, and p represents the length of each barrel shift register group.

[0026] In one embodiment of the present invention, the data stored in the CFAR barrel shifter module is input into the CFAR detection module for detection to obtain the detection result, including:

[0027] For each barrel shift register group in the CFAR barrel shifter module, including:

[0028] Each row of data in the barrel shift register group is input into the CFAR detection module for detection, completing the CFAR detection of all sub-Doppler dimensions corresponding to the current distance dimension; switch to the barrel shift register group corresponding to the next distance dimension, and return to the step of inputting each row of data in the barrel shift register group into the CFAR detection module for detection.

[0029] The final detection result is obtained after CFAR detection of all sub-Doppler dimensions corresponding to all distance dimensions is completed.

[0030] In one embodiment of the present invention, the CFAR buffer module is composed of several BRAMs in the FPGA.

[0031] The beneficial effects of this invention are:

[0032] This invention proposes a parallel fast time-dimensional constant false alarm rate (CFAR) implementation method based on a barrel-shaped buffer processing structure, applied to an FPGA. The FPGA includes a serial-to-parallel conversion module, several CFAR detection and buffers, and an information synthesis module. The output of the serial-to-parallel conversion module is connected to a CFAR detection and buffer, and the output of each CFAR detection and buffer is connected to the information synthesis module. The method includes: converting the first data output by the moving target detection unit, characterized by two dimensions (range and Doppler), into second data characterized by three dimensions (range, Doppler, and sub-Doppler); using the serial-to-parallel conversion module to divide the second data into several sub-data groups according to the sub-Doppler dimension; inputting each sub-data group into a CFAR detection and buffer; in the CFAR detection and buffer: constructing a barrel-shaped buffer processing structure model, and performing buffering and detection processing on the input sub-data groups based on the barrel-shaped buffer processing structure model to obtain the detection result; and in the information synthesis module, merging the detection result with the corresponding velocity and range dimension information to obtain the constant false alarm rate (CFAR) detection result. As can be seen, this invention buffers the required data by constructing a barrel-shaped buffer processing structure model, avoiding data loss. Utilizing the inherent data flow characteristics of the barrel-shaped buffer processing structure, continuous data sliding in the fast time dimension can be achieved without transposing the buffered data. Because data transposition operations are avoided, processing latency is greatly reduced, and the resource consumption caused by using DDR is eliminated. This invention introduces the concept of sub-Doppler dimensions, dividing Doppler-dimensional data into multiple sub-Doppler spaces. Based on the barrel-shaped buffer structure, to efficiently process the multiple sub-Doppler space data of each Doppler channel, this invention employs parallel CFAR detection and buffering to sequentially process the multiple sub-Doppler space data of each Doppler channel, further reducing processing latency. Furthermore, processing data in three dimensions—Doppler dimension, sub-Doppler dimension, and distance dimension—significantly reduces the number of barrel-shaped buffer processing structures, effectively reducing FPGA logic resource consumption and thus significantly optimizing timing performance. The invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the overall circuit structure for implementing parallel fast-time constant false alarm provided by an example of the present invention;

[0034] Figure 2 This is a schematic diagram of the circuit structure of a single CFAR detection and buffer in a parallel fast-time constant false alarm realization circuit provided by an example of the present invention;

[0035] Figure 3 This is a flowchart illustrating a parallel fast-time constant false alarm method based on a barrel-shaped buffer processing structure provided in an embodiment of the present invention.

[0036] Figure 4 This is a schematic diagram of the moving target detection output data divided according to the sub-Doppler space provided in the embodiments of the present invention;

[0037] Figure 5 This is a schematic diagram of the flow of a single sub-data in the barrel shift register group of the CFAR barrel shifter module provided in this embodiment of the invention;

[0038] Figure 6 This is a schematic diagram of the parallel flow of sub-data groups in the barrel shift register group of the CFAR barrel shifter module provided in the embodiment of the present invention;

[0039] Figure 7 This is a schematic diagram of data transfer and storage of a single barrel-shaped buffer processing structure provided in an embodiment of the present invention;

[0040] Figure 8 This is a schematic diagram of the storage address division of the sub-Doppler spatial detection window provided in an embodiment of the present invention. Detailed Implementation

[0041] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0042] For implementing constant false alarm rate (CFAR) detection along the fast time dimension on an FPGA, since data is input into the CFAR detection stage along the slow time dimension after the moving target detection stage, all slow time dimension data needs to be cached sequentially into the FPGA's internal storage resources before being read out along the fast time dimension. This means that CFAR detection can only be performed after all slow time dimension data storage is complete, increasing processing latency and reducing the efficiency of the FPGA signal processing system. As the amount of pulse data processed increases, the FPGA requires more storage resources. Existing FPGAs cannot meet these requirements, and external storage chips are typically used to expand storage resources. This consumes FPGA resources to generate a storage controller, does not utilize timing convergence, and further increases processing latency due to the use of external storage chips. To address the above research, the inventors propose a new approach to implement CFAR detection processing along the fast time dimension on an FPGA, solving the problems of increased latency and resource consumption in CFAR detection processing along the slow time dimension. Specifically:

[0043] This invention is applied to FPGAs, and a circuit structure for implementing constant false alarm detection along the slow time dimension is designed on an FPGA. Please refer to [link to relevant documentation]. Figure 1 The FPGA includes a serial-to-parallel conversion module, several CFAR detectors and buffers, and an information synthesis module. The outputs of the serial-to-parallel conversion module are each connected to a CFAR detector and buffer. The output of each CFAR detector and buffer is connected to the information synthesis module. Please refer to [link to relevant documentation]. Figure 2 Each CFAR detection and buffer includes: a selector, a CFAR barrel shifter module, a CFAR buffer module, and a CFAR detection module. The CFAR barrel shifter module includes several barrel shift register groups. The input of the selector is connected to the output of the CFAR buffer module and the output of the serial-to-parallel conversion module. The output of the selector is connected to the input of the CFAR barrel shifter module. The output of the CFAR barrel shifter module is connected to the input of the CFAR buffer module and the input of the CFAR detection module. The output of the CFAR detection module is connected to the information synthesis module.

[0044] Based on the above Figure 1 and Figure 2 Please see Figure 3 This invention provides a parallel fast-time dimensionless false alarm method based on a barrel-buffered processing structure, specifically including the following steps:

[0045] S10. The first data output by the moving target detection unit, characterized by two dimensions, distance dimension and Doppler dimension, is transformed into the second data characterized by three dimensions, distance dimension, Doppler dimension and sub-Doppler dimension.

[0046] Assuming the radar has M range cells and N Doppler cells, using a two-dimensional "range-Doppler dimension" approach to process data, after passing through the moving target detection unit within one coherent time processing period, the first data of the m-th range dimension and n'-th Doppler dimension can be represented as D(m,n'), where m = 0, 1, 2, 3, ..., M-1, and n' = 0, 1, 2, 3, ..., N-1. This embodiment of the invention introduces a sub-Doppler dimension based on the range and Doppler dimensions, dividing the Doppler dimension into A equal parts. The sequence number of each part is the sub-Doppler number. After this sub-Doppler dimension division, the dimension of the Doppler dimension changes from the original N to... The output of the moving target detection unit can then be characterized by three dimensions: range dimension, Doppler dimension, and sub-Doppler dimension. Therefore, the second data of the m-th range dimension, n-th Doppler dimension, and a-th sub-Doppler dimension of the output after passing through the moving target detection unit can be represented as D(m,n,a). a = 0, 1, 2, 3, ..., A-1.

[0047] for example, Figure 4 This diagram illustrates the Doppler data of the m-th distance dimension output by the moving target detection unit. The N Doppler data dimensions are then divided into sub-Doppler dimensions. Figure 4 The right side of the image illustrates the result of dividing a Doppler dimension of data into sub-Doppler dimensions. It can be seen that each sub-Doppler dimension contains N / A data points.

[0048] As can be seen, in this embodiment of the invention, the data D output by the N slave target detection stages, with distance dimension numbered m, is... 0m D 1m D 2m , ...D N-1m The data is accumulated serially and then converted into parallel data, which is then divided into A sub-Doppler spaces. Each sub-Doppler space contains one parallel data stream, which is the result of serial-to-parallel conversion of N / A serial data streams. Let the bit width of one serial data stream be *a*, then the width of the parallel data stream is *a*N / A. N is the number of radar Doppler channels, i.e., the number of pulses. A is the number of sub-Doppler spaces, and N / A is the number of channels in each sub-Doppler space. The sub-Doppler space is numbered i, where i = 0, 1, ..., A-1. The range of Doppler channel numbers in sub-Doppler space i is from i*N / A to (i+1)*N / A-1. For every N / A data streams accumulated, a parallel data stream is generated, consisting of D... (i+0)m D (i+1)m D (i+2)m , ...D (i+N / A-1)m The time required to generate parallel data from serial data is N / A clock cycles for every two parallel data conversions.

[0049] S20. The second data is divided into several sub-data groups by sub-Doppler values ​​using the serial-to-parallel conversion module, and each sub-data group is input into a CFAR detection and buffer.

[0050] like Figure 1 As shown, the second data of S10 is divided into several sub-data groups according to sub-Doppler values ​​using a serial-to-parallel conversion module, for example, into K sub-data groups. Each sub-data group is then input into a CFAR detector and buffer. For example... Figure 4 The diagram illustrates that each sub-Doppler dimension contains N / A data points, which are then divided into K groups.

[0051] S30. In CFAR detection and buffering: Construct a barrel-shaped buffer processing structure model, and perform buffering and detection processing on the input sub-data groups based on the barrel-shaped buffer processing structure model to obtain the detection results.

[0052] In CFAR detection and buffering, this invention proposes to construct a barrel-shaped buffer processing structure model. The construction of the barrel-shaped buffer processing structure model includes: determining the length of the constant false alarm rate (CFAR) detection window; constructing a barrel-shaped buffer processing structure characterized by two dimensions, distance dimension and Doppler dimension, based on the length of the CFAR detection window; wherein, the distance dimension length of the barrel-shaped buffer processing structure is the length of the CFAR detection window, and the Doppler dimension length of the barrel-shaped buffer processing structure is the length of the sub-Doppler data.

[0053] For example, assuming the length of the constant false alarm rate (CFAR) detection window is WL, the barrel buffer processing structure has two dimensions, similar to a traditional two-dimensional radar data processing matrix. One dimension is called the range dimension, and the other is called the Doppler dimension. Then, the q-th (q = 0, 1, 2, 3, ..., WL-1) range dimension and the... A Doppler value can be represented by the symbol B(q,p).

[0054] Here, we first introduce the concept of processing time slots. In a data representation model based on range dimension, Doppler dimension, and sub-Doppler dimension, a processing time slot represents the time segment used to process all sub-Doppler dimension data using a bucket-buffered processing structure. The number of processing time slots is the same as the number of sub-Doppler dimensions. Therefore, the relationship between the bucket-buffered processing structure and the second data output by the moving target detection unit can be described by the following formula:

[0055] B(0,p)|a=D(m,n,a) (1);

[0056] Equation (1) indicates that, in the current time slot a, i.e., the data of the current sub-Doppler a, will be received by the first unit of the barrel buffer processing structure. In the current time slot a, the data flow relationship between the barrel buffer processing structure and the adjacent distance units of the Doppler dimension can be expressed by the following formula:

[0057] B(q,p)|a=B(q-1,p)|a (2);

[0058] In the current time slot a, the same row of data (same Doppler data) B(0,p), B(1,p), B(2,p), ..., B(WL-1,p) in the barrel buffer processing structure are subjected to constant false alarm rate (CFAR) processing. Within one time slot, the CFAR detection of all Doppler dimensions is completed. Following this processing procedure, the CFAR detection of all time slots (all sub-Doppler dimensions) is completed.

[0059] Furthermore, to ensure the independence of data processing in preceding and following clock cycles, the embodiments of the present invention are based on Figure 2 Circuit design, Figure 2 Each barrel shift register group is constructed based on a barrel buffer processing structure model. The processing of the sub-data groups input to the serial-to-parallel conversion module in each CFAR detection and buffer includes:

[0060] The selector chooses between the input sub-data group and the data output from the CFAR buffer module: If the data output from the CFAR buffer module is selected, the data output from the CFAR buffer module overwrites the data from the CFAR barrel shifter module. Simultaneously, the data stored in the CFAR barrel shifter module overwrites the data buffered in the CFAR buffer module, and the data stored in the CFAR barrel shifter module is input into the CFAR detection module for detection to obtain the detection result. If the sub-data group input from the serial-to-parallel conversion module is selected, the data input from the serial-to-parallel conversion module updates the data stored in the CFAR barrel shifter module. Simultaneously, the data stored in the CFAR barrel shifter module overwrites the data buffered in the CFAR buffer module, and the data stored in the CFAR barrel shifter module is input into the CFAR detection module for detection to obtain the detection result. Therefore, until the sub-data group input from the serial-to-parallel conversion module arrives in the next cycle, the data detected by the CFAR detection module is always processed from the sub-data group input from the serial-to-parallel conversion module in the current cycle.

[0061] In this embodiment of the invention, the CFAR buffer module is composed of several BRAMs in the FPGA. For example... Figure 5 As shown, Figure 5 The direction of PN increment is the direction of Doppler dimension increase. In this embodiment of the invention, the address range for storing the i-th sub-Doppler data (column-wise) output by the CFAR barrel shifter module into the BRAM in real time is from i*WL to (i+1)*WL-1. The address range for storing all sub-Doppler data into the BRAM is as follows: Figure 6 As shown. After storage, before the sub-data group input from the serial-to-parallel conversion module arrives in the next cycle, the (i+1)th sub-Doppler data in the output BRAM address range (i+1)*WL to (2*i-1)*WL covers the data in the corresponding barrel shift register group in the CFAR barrel shifter module. Through this processing, the data in the barrel shift register group is switched to the detection window corresponding to sub-Doppler space i+1. The "dimensional switching" operation in the above operation outputs the barrel shift register group along the Doppler dimension to the BRAM for storage. Therefore, when the BRAM outputs data to the corresponding barrel shift register group, it also follows the Doppler dimension, thus realizing lossless data transmission and switching in the barrel buffer processing structure. This invention employs a small amount of BRAM resources in the FPGA to design a CFAR buffer module, which stores multiple sub-Doppler spatial detection window data in segments and utilizes the gaps between adjacent sub-Doppler spatial data inputs to complete the switching of adjacent sub-Doppler spatial detection windows. This can save a considerable amount of lookup table and register resources, which is beneficial for the placement, routing, and timing convergence of the FPGA program and improves the performance of the FPGA signal processing system.

[0062] Furthermore, upon the arrival of the sub-data group input to the serial-to-parallel conversion module, the data stored in the CFAR barrel shifter module is updated using the sub-data group input to the serial-to-parallel conversion module, including:

[0063] The input sub-data group from the serial-to-parallel conversion module overwrites the data stored in the least significant register group of the barrel shift register group; the data stored in the nth register group of the barrel shift register group overwrites the data stored in the (n+1)th register group of the barrel shift register group, where n ranges from 1 to N-1, and N represents the number of register groups in the barrel shift register group; N is an integer greater than 1; the data stored in the most significant register group of the barrel shift register group is discarded. The formula for overwriting the least significant register group of the barrel shift register group with the input sub-data group is: B(0,p)|a=D(m,n,a); m=0,1,2,3,...,M-1, where M represents the number of distance units. N represents the number of Doppler units, A represents the number of sub-Doppler units, a = 0, 1, 2, 3, ..., A-1, D(m,n,a) represents the second data corresponding to the m distance units, the nth Doppler unit, and the ath sub-Doppler unit, B(0,p)|a represents the data stored in the least significant bit register group of the barrel shift register group corresponding to the ath sub-Doppler unit. The least significant bit register group is the first unit of the barrel buffer processing structure described above, and p represents the length of each barrel shift register group; using the barrel... The nth register group of the barrel shift register group covers the (n+1)th register group of the barrel shift register group, as expressed by the formula: B(q,p)|a=B(q-1,p)|a; where B(q,p)|a represents the data stored in the qth register group of the barrel shift register group corresponding to the ath sub-Doppler unit, B(q-1,p)|a represents the data stored in the (q-1)th register group of the barrel shift register group corresponding to the ath sub-Doppler unit, and p represents the length of each barrel shift register group.

[0064] Figure 7 This diagram illustrates the flow of a single sub-data item within the barrel shift register group of the CFAR barrel shifter module. For example, if the input sub-data is D'0, and the data enters at position D0, then after sub-data D'0 enters, D'0 overwrites D0 to become the new D0, D0 overwrites D1 to become the new D1, D1 overwrites D2 to become the new D2, and so on. WL-2 Covered D WL-1 Become the new D WL-1 The original D WL-1 throw away. Figure 8 This diagram illustrates the parallel flow of multiple sub-data groups within the barrel shift register group of the CFAR barrel shifter module. The flow of each sub-data group is as follows: Figure 7As shown, the flow processing of all data input into the CFAR barrel shifter module is realized.

[0065] As can be seen, in this embodiment of the invention, a single barrel shift register group stores the fast time dimension data of the detection window length corresponding to a single sub-Doppler channel, and N / A / K barrel shift register groups store a data matrix of the fast time dimension data of the detection window lengths corresponding to all sub-Doppler channels in a sub-Doppler space.

[0066] Furthermore, the data stored in the CFAR barrel shifter module is input into the CFAR detection module for detection to obtain the detection results, including:

[0067] For each barrel shift register group in the CFAR barrel shifter module, the process includes: inputting each row of data in the barrel shift register group into the CFAR detection module for detection, completing the CFAR detection of all sub-Doppler dimensions corresponding to the current distance dimension; repeating the above CFAR detection of all sub-Doppler dimensions for each distance dimension until the CFAR detection of all sub-Doppler dimensions corresponding to all distance dimensions is completed, obtaining the final detection result. The CFAR detection module can be a pipelined CFAR detector.

[0068] In this embodiment of the invention, the data of sub-Doppler space i in the barrel shift register group is input into the CFAR detection module row by row. Each row of data is processed after N / A / K+T cycles to complete the CFAR detection of all rows of sub-Doppler space i, where T is the calculation delay of the CFAR detection module. The system then switches to the next sub-Doppler space i+1, inputting its data into the barrel shift register group. This process is repeated until all sub-Doppler spaces corresponding to the current distance dimension have been processed, and then switches to the next distance dimension. More specifically, during implementation, corresponding distance and Doppler numbers are added to the detection results. The rule is as follows: when a valid CFAR detection result is detected, the Doppler number is incremented by 1. When the Doppler number accumulates to N-1, it is cleared to 0, and the distance number is incremented by 1. The Doppler number is incremented by 1 for the next CFAR detection result output, and this process is repeated until the distance dimension number accumulates to M-1, at which point the distance number is cleared to 0.

[0069] S40. In the information integration module, the detection result is merged with the corresponding velocity and distance dimension information to obtain the constant false alarm rate (CFAR) detection result. How to merge the detection result with the corresponding velocity and distance dimension information can be found in existing technologies and will not be elaborated here.

[0070] To verify the effectiveness of the parallel fast time-dimensional constant false alarm method based on a barrel buffer processing structure provided in this embodiment of the invention, the following experiments were conducted.

[0071] (1) Simulation conditions

[0072] Assume the simulated data to be processed after passing through the moving target detection unit has a distance dimension of 4096 and a Doppler dimension of 512, totaling 4096 * 512 = 2097152 data points. The constant false alarm rate (CFAR) detection window length is 39. Design the corresponding FPGA program according to the above operations and perform behavioral-level simulation to check its timing. Simultaneously, perform synthesis, placement, and routing to check its resource usage.

[0073] (2) Simulation content

[0074] The effectiveness of the proposed parallel fast-time constant false alarm method based on the barrel buffer processing structure is determined by the time delay and the amount of FPGA resources used in the method proposed in this invention.

[0075] Simulation 1: Under the current simulation conditions, a parallel fast-time dimension constant false alarm rate (CFAR) implementation method based on a barrel buffer processing structure is adopted. The number of sub-Doppler spaces is set to 4, and 8 CFAR detectors and buffers are configured for parallel processing (A=4, K=8). Behavioral-level simulation is performed to observe the number of clock cycles from data input to detection result output. Under the same simulation conditions, a behavioral-level simulation is performed using the method proposed in the prior art, and the number of clock cycles from data input to detection result output is observed. The clock cycles used by the two methods are shown in Table 1 below.

[0076] Table 1 Comparison of clock cycles used by the two methods

[0077]

[0078] As can be clearly seen from Table 1, compared with the methods mentioned in the existing technical solutions, the method proposed in this invention does not require buffering all the data, thus reducing the latency by 2,087,450 cycles. This greatly reduces the time delay of FPGA processing and effectively improves performance.

[0079] Simulation 2: Select the target FPGA chip model as Xilinx xcz100, set A=4 and K=8 for the method proposed in this invention, and evaluate the FPGA resource usage under these parameters; Under the same simulation conditions, set A=2 and K=8 for the method proposed in this invention, and evaluate the FPGA resources used in the two cases. The resource comparison between the two cases is shown in Table 2 below.

[0080] Table 2 Comparison of resources under different sub-Doppler conditions

[0081]

[0082] As shown in Table 2, when the number of sub-Doppler spaces increases from 2 to 4, 38.7% of lookup table resources, 71.1% of register resources, and 52% of BRAM resources are saved, respectively. This indicates that by increasing the number of sub-Doppler spaces, the resource consumption of the FPGA, especially the register resources, can be effectively reduced. This will benefit the placement, routing, and timing convergence of the FPGA program, and improve the performance of the FPGA signal processing system.

[0083] In summary, the parallel fast time dimension constant false alarm rate (CFAR) implementation method based on a barrel-shaped buffer processing structure proposed in this invention is applied to an FPGA. The FPGA includes a serial-to-parallel conversion module, several CFAR detection and buffers, and an information synthesis module. The output of the serial-to-parallel conversion module is connected to a CFAR detection and buffer, and the output of each CFAR detection and buffer is connected to the information synthesis module. The method includes: converting the first data output by the moving target detection unit, characterized by two dimensions (range dimension and Doppler dimension), into second data characterized by three dimensions (range dimension, Doppler dimension, and sub-Doppler dimension); using the serial-to-parallel conversion module to divide the second data according to the sub-Doppler dimension to obtain several sub-data groups; inputting each sub-data group into a CFAR detection and buffer; in the CFAR detection and buffer: constructing a barrel-shaped buffer processing structure model, and performing buffering and detection processing on the input sub-data groups based on the barrel-shaped buffer processing structure model to obtain the detection result; and in the information synthesis module, merging the detection result with the corresponding velocity dimension and range dimension information to obtain the constant false alarm rate (CFAR) detection result. As can be seen, this embodiment of the invention buffers the required data by constructing a barrel-shaped buffer processing structure model, avoiding data loss. Utilizing the inherent data flow characteristics of the barrel-shaped buffer processing structure, continuous sliding of data in the fast time dimension can be achieved without transposing the cached data. Since the data transposition operation is avoided, the processing latency is greatly reduced, and the resource consumption caused by using DDR is eliminated. This embodiment of the invention introduces the concept of sub-Doppler dimensions, dividing the Doppler dimension data into multiple sub-Doppler spaces. Based on the barrel-shaped buffer structure, in order to efficiently process the multiple sub-Doppler space data of each Doppler channel, this invention uses parallel CFAR detection and buffers to sequentially process the multiple sub-Doppler space data of each Doppler channel, further reducing processing latency. Furthermore, processing is performed in the form of Doppler dimension, sub-Doppler dimension, and distance dimension data, greatly reducing the number of barrel-shaped buffer processing structures, effectively reducing FPGA logic resource occupation, and thus significantly optimizing timing performance.

[0084] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0085] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the specification and accompanying drawings, will understand and implement other variations of the disclosed embodiments in carrying out the claimed invention. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. While certain measures are described in different embodiments, this does not mean that these measures cannot be combined to produce good results.

[0086] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A parallel fast-time constant false alarm rate implementation method based on a barrel buffer processing structure, characterized in that, The method is applied in an FPGA, wherein the FPGA includes a serial-to-parallel conversion module, several CFAR detection and buffers, and an information synthesis module; the output of the serial-to-parallel conversion module is connected to one of the CFAR detection and buffers, and the output of each CFAR detection and buffer is connected to the information synthesis module; the method includes: The first data output by the moving target detection unit, characterized by two dimensions, distance dimension and Doppler dimension, is transformed into the second data characterized by three dimensions, distance dimension, Doppler dimension and sub-Doppler dimension. The second data is divided into several sub-data groups by sub-Doppler dimensions using a serial-to-parallel conversion module; Each sub-data set is input into a CFAR detection and buffer; in the CFAR detection and buffer: a barrel-shaped buffer processing structure model is constructed, and the input sub-data sets are buffered and detected based on the barrel-shaped buffer processing structure model to obtain the detection result; wherein, constructing the barrel-shaped buffer processing structure model includes: determining the length of the constant false alarm rate (CFAR) detection window; constructing a barrel-shaped buffer processing structure characterized by two dimensions, distance dimension and Doppler dimension, according to the length of the CFAR detection window; the distance dimension length of the barrel-shaped buffer processing structure is the length of the CFAR detection window, and the Doppler dimension length of the barrel-shaped buffer processing structure is the length of the sub-Doppler data; In the information integration module, the detection result is combined with the corresponding velocity dimension and distance dimension information to obtain the constant false alarm rate (CFAR) detection result.

2. The parallel fast-time dimension constant false alarm rate implementation method based on a barrel buffer processing structure according to claim 1, characterized in that, Each CFAR detection and buffer includes: a selector, a CFAR barrel shifter module, a CFAR buffer module, and a CFAR detection module; wherein, the CFAR barrel shifter module includes several barrel shift register groups, each barrel shift register group being constructed according to the barrel buffer processing structure model; the input of the selector is connected to the output of the CFAR buffer module and the output of the serial-to-parallel conversion module, the output of the selector is connected to the input of the CFAR barrel shifter module, the output of the CFAR barrel shifter module is connected to the input of the CFAR buffer module and the input of the CFAR detection module, and the output of the CFAR detection module is connected to the information synthesis module; the processing of the sub-data groups input to the serial-to-parallel conversion module in each CFAR detection and buffer includes: The selector selects between the input sub-data group and the data output by the CFAR buffer module: If the data output by the CFAR buffer module is selected, the data output by the CFAR buffer module will overwrite the data of the CFAR barrel shifter module. At the same time, the data stored in the CFAR barrel shifter module will overwrite the data buffered and stored in the CFAR buffer module. The data stored in the CFAR barrel shifter module will then be input into the CFAR detection module for detection to obtain the detection result. If the sub-data group input to the serial-to-parallel conversion module is selected, the data stored in the CFAR barrel shifter module is updated using the sub-data group input to the serial-to-parallel conversion module. At the same time, the data stored in the CFAR barrel shifter module is used to overwrite the data stored in the CFAR buffer module, and the data stored in the CFAR barrel shifter module is input into the CFAR detection module for detection to obtain the detection result.

3. The parallel fast-time dimensionless false alarm method based on a barrel-buffered processing structure according to claim 2, characterized in that, Updating the data stored in the CFAR barrel shifter module using the sub-data group input from the serial-to-parallel conversion module includes: The sub-data group input by the serial-to-parallel conversion module is used to cover the data stored in the least significant bit register group of the barrel shift register group; Using the first barrel shift register group n The data stored in the bit register group covers the first bit of the barrel shift register group. n The data stored in the +1 bit register group n The value ranges from 1 to N-1, where N represents the number of register groups in the barrel shift register group; N is an integer greater than 1. Discard the data stored in the highest bit register of the barrel shift register group.

4. The parallel fast-time dimension constant false alarm rate implementation method based on a barrel buffer processing structure according to claim 3, characterized in that, The least significant bit register group of the barrel shift register group is covered by the input sub-data group, as expressed by the formula: ; in, M represents the number of distance units. , Indicates the number of Doppler elements, and A represents the number of sub-Doppler elements. , express m The distance unit, the first The first Doppler unit, the first a The second data corresponding to each Doppler unit Indicates the first a Each Doppler cell corresponds to the data stored in the least significant bit register of the barrel shift register group. p This indicates the length of each barrel shift register group.

5. The parallel fast-time constant false alarm rate implementation method based on a barrel buffer processing structure according to claim 3, characterized in that, Using the first barrel shift register group n The bit register group covers the first bit of the barrel shift register group. n The +1 bit register group is expressed by the formula: ; in, Indicates the first a The first Doppler unit corresponds to the first in the barrel shift register group. q Data stored in the bit register group Indicates the first a The first Doppler unit corresponds to the first in the barrel shift register group. q The data stored in the -1 bit register group p This indicates the length of each barrel shift register group.

6. The parallel fast-time dimension constant false alarm rate implementation method based on a barrel buffer processing structure according to claim 2, characterized in that, The data stored in the CFAR barrel shifter module is input into the CFAR detection module for detection to obtain the detection results, including: For each barrel shift register group in the CFAR barrel shifter module, including: Each row of data in the barrel shift register group is input into the CFAR detection module for detection, completing the CFAR detection of all sub-Doppler dimensions corresponding to the current distance dimension; switch to the barrel shift register group corresponding to the next distance dimension, and return to the step of inputting each row of data in the barrel shift register group into the CFAR detection module for detection. The final detection result is obtained after CFAR detection of all sub-Doppler dimensions corresponding to all distance dimensions is completed.

7. The parallel fast-time dimension constant false alarm rate implementation method based on a barrel buffer processing structure according to claim 2, characterized in that, The CFAR buffer module is composed of several BRAMs in the FPGA.

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