A high-transient response regulator circuit

Abstract

A high transient response Regulator circuit, by setting the first resistance and the first NMOS tube group transient response acceleration circuit, using the change of the internal voltage of the circuit acting on the gate of the first NMOS tube, when the power supply voltage Vdd rises rapidly, the first NMOS tube can produce the conduction current and timely supplement to the Regulator circuit current source, and compensate for the current source, so that the loop response is accelerated, the output low voltage source Vreg quickly returns to the normal voltage value, and the first NMOS tube can be closed to reduce the static power consumption of the circuit when the circuit reaches the equilibrium state.

Description

Technical Field

[0001] This invention relates to the field of voltage regulator circuit technology, and in particular to a high transient response regulator circuit. Background Technology

[0002] High-voltage products often require an internally integrated initial regulator circuit to generate a stable low-voltage source Vreg (regulator is a voltage regulator), and the low-voltage circuit is then implemented under this low-voltage source Vreg. When the power supply voltage Vdd changes, the regulator's response speed will affect the stability of the low-voltage source Vreg. When the low-voltage source Vreg changes too much, it will affect the performance of the low-voltage circuit and may even cause the circuit to malfunction. Summary of the Invention

[0003] This invention addresses the deficiencies or shortcomings of existing technologies by providing a high transient response regulator circuit. By utilizing changes in the internal voltage of the circuit to determine the circuit state, it can promptly compensate the current source when the power supply voltage Vdd rises rapidly, thereby achieving a high transient response.

[0004] The technical solution of the present invention is as follows:

[0005] A high transient response regulator circuit is characterized by including an output low-voltage source Vreg node, wherein the Vreg node is connected to a source follower and a common-source amplifier, the common-source amplifier is connected to a transient response acceleration circuit, and the transient response acceleration circuit accelerates the loop response by compensating the current source, thereby enabling the output low-voltage source Vreg to quickly return to the normal voltage value.

[0006] The transient response acceleration circuit consists of a first resistor and a first NMOS transistor.

[0007] The source follower consists of a second current source I2 and a third NMOS transistor.

[0008] The common-source amplifier consists of a first current source I1 and a fourth NMOS transistor.

[0009] The Vreg node is grounded through the second current source I2 and connected to the source of the third NMOS transistor and the gate of the fourth NMOS transistor, respectively. The drain of the fourth NMOS transistor is connected to the gate of the second PMOS transistor and the output of the first current source I1 through node Y. The input of the first current source I1 and the drain of the third NMOS transistor are both connected to the power supply voltage Vdd. The source of the second PMOS transistor, the gate of the third NMOS transistor, and the drain of the first PMOS transistor are interconnected to form node V1. The gate of the first PMOS transistor, the drain of the fifth PMOS transistor, and the drain of the sixth NMOS transistor are interconnected to form node Pg. The gate of the sixth NMOS transistor is connected to the bias voltage VB. The fifth PMOS transistor, the fourth PMOS transistor, and the third PMOS transistor are interconnected to form node Pg. After the gates of the transistors are interconnected, they are connected to the drains of the third PMOS transistor and the first NMOS transistor, respectively, and then grounded through a reference current source Iref. The source of the first NMOS transistor is grounded through a first resistor. The gate of the first NMOS transistor is connected to node X. Node X is connected to the drain of the second NMOS transistor, the drain of the second PMOS transistor, and the source of the sixth NMOS transistor. The gates of the second NMOS transistor and the fifth NMOS transistor are interconnected and then connected to the drains of the fourth PMOS transistor and the fifth NMOS transistor, respectively. The sources of the second NMOS transistor, the fifth NMOS transistor, and the fourth NMOS transistor are all grounded. The sources of the first PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor are all connected to the power supply voltage Vdd terminal.

[0010] When Vdd rises rapidly, it causes V1 to rise, which in turn causes Vreg to rise, which in turn causes Vx to rise. The rise in Vx causes the first NMOS transistor to turn on and generate a conduction current I. I compensates for the current source to bring Vreg back to normal, thus achieving a high transient response.

[0011] I = (Vx - Vgsn1) / R1, where Vgsn1 is the gate-source voltage of the first NMOS transistor, R1 is the first resistor, Vx > Vthn1, and Vthn1 is the threshold voltage of the first NMOS transistor.

[0012] When the circuit returns to equilibrium, Vx = VB - Vgsn6, where Vgsn6 is the gate-source voltage of the sixth NMOS transistor. By setting VB - Vgsn6 < Vthn1, the first NMOS transistor is turned off when the circuit reaches equilibrium, thereby reducing the static power consumption of the circuit.

[0013] The technical effects of this invention are as follows: This invention provides a high transient response regulator circuit. By setting a transient response acceleration circuit composed of a first resistor and a first NMOS transistor, the change in the internal voltage of the circuit acts on the gate of the first NMOS transistor. When the power supply voltage Vdd rises rapidly, it can generate the conduction current of the first NMOS transistor and timely supplement the current source of the regulator circuit to compensate the current source, thereby speeding up the loop response. The low voltage source Vreg output quickly returns to the normal voltage value. It can also turn off the first NMOS transistor when the circuit reaches a balanced state to reduce the static power consumption of the circuit. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a high transient response regulator circuit that implements the present invention.

[0015] The markings in the diagram are explained as follows: Vdd - power supply voltage; MP0~MP4 - first to fifth PMOS transistors; MN1~MN6 - first to sixth NMOS transistors; R1 - first resistor (when Vx > Vthn1, Vthn1 is the threshold voltage of MN1, MN1 conducts, generating a conduction current I = (Vx - Vgsn1) / R1, where Vgsn1 is the gate-source voltage of MN1); Iref - reference current source; I1~I2 - first current source to second current source; Vx - node X voltage (Vx is the voltage input to the first NMOS transistor MN1). Gate, Vx = VB - Vgsn6, Vgsn6 is the gate-source voltage of the sixth NMOS transistor MN6, VB is the gate voltage of MN6 (i.e., bias voltage); VB - bias voltage; V1 - node designation or node voltage (if Vdd increases, V1 increases; if V1 increases, Vreg increases; if Vreg increases, Vx increases; if Vx increases, MN1 turns on, generating a conduction current I, which causes Vreg to drop back to normal); X - node designation; Y - node designation; Vreg - low-voltage output source; Pg - node designation or node voltage (gate voltage of the first PMOS transistor MP0). Detailed Implementation

[0016] The following is in conjunction with the attached diagram ( Figure 1 The invention will be described in the following sections and examples.

[0017] In this application, structural elements with the same or similar characteristics may be identified using the same or different reference numerals. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more features.

[0018] Figure 1This is a schematic diagram of a high transient response regulator circuit implementing the present invention. (Reference) Figure 1 As shown, a high transient response regulator circuit includes an output low-voltage source Vreg node. The Vreg node is grounded through a second current source I2 and connected to the source of a third NMOS transistor MN3 and the gate of a fourth NMOS transistor MN4. The drain of the fourth NMOS transistor MN4 is connected to the gate of a second PMOS transistor MP1 and the output of a first current source I1 through node Y. The input of the first current source I1 and the drain of the third NMOS transistor are both connected to the power supply voltage Vdd. The source of the second PMOS transistor MP1, the gate of the third NMOS transistor MN3, and the drain of the first PMOS transistor MP0 are interconnected to form node V1. The gate of the first PMOS transistor MP0, the drain of the fifth PMOS transistor MP4, and the drain of the sixth NMOS transistor MN6 are interconnected to form node Pg. The gate of the sixth NMOS transistor MN6 is connected to the bias voltage VB. The fifth PMOS transistor MP4 and the fourth PMOS transistor MP1 are connected to the source of the third NMOS transistor MP3 and the drain of the fourth NMOS transistor MP4. After the gates of the third PMOS transistor MP2 are interconnected, they are connected to the drain of the third PMOS transistor MP2 and the drain of the first NMOS transistor MN1, respectively, and then grounded through the reference current source Iref. The source of the first NMOS transistor MN1 is grounded through the first resistor R1. The gate of the first NMOS transistor MN1 is connected to node X. The node X is connected to the drain of the second NMOS transistor MN2, the drain of the second PMOS transistor MP1, and the source of the sixth NMOS transistor MN6. The gates of the second NMOS transistor MN2 and the fifth NMOS transistor MN5 are interconnected and then connected to the drain of the fourth PMOS transistor MP3 and the drain of the fifth NMOS transistor MP4, respectively. The sources of the second NMOS transistor MN2, the fifth NMOS transistor MN5, and the fourth NMOS transistor MN4 are all grounded. The sources of the first PMOS transistor MP0, the third PMOS transistor MP2, the fourth PMOS transistor MP3, and the fifth PMOS transistor MP4 are all connected to the power supply voltage Vdd terminal.

[0019] The first resistor R1 and the first NMOS transistor MN1 form a transient response acceleration circuit. The second current source I2 and the third NMOS transistor MN3 form a source follower. The first current source I1 and the fourth NMOS transistor form a common-source amplifier. When Vdd rises rapidly, it causes V1 to rise, which in turn causes Vreg to rise, which in turn causes Vx to rise. The rise in Vx causes the first NMOS transistor MN1 to turn on, generating a conduction current I. I compensates for the current source, causing Vreg to return to normal, thereby achieving a high transient response.

[0020] I=(Vx-Vgsn1) / R1, where Vgsn1 is the gate-source voltage of the first NMOS transistor MN1, R1 is the first resistor, Vx>Vthn1, and Vthn1 is the threshold voltage of the first NMOS transistor MN1. When the circuit returns to equilibrium, Vx=VB-Vgsn6, where Vgsn6 is the gate-source voltage of the sixth NMOS transistor MN6. By setting VB-Vgsn6<Vthn1, the first NMOS transistor MN1 is turned off when the circuit reaches an equilibrium state to reduce the static power consumption of the circuit.

[0021] The present invention judges the circuit state according to the change of the internal voltage of the circuit, compensates the current source, and improves the transient response of the regulator.

[0022] As Figure 1 shown is a Regulator circuit with high transient response, wherein the resistor R1 and the transistor MN1 form a transient response acceleration circuit to improve the transient response of the Regulator. Vdd is the power supply voltage, and Vreg is the low-voltage source generated by the Regulator.

[0023] When Vdd rises rapidly, due to the response delay of the loop, the gate pg of the transistor MP0 cannot change immediately, resulting in an increase in the gate-source voltage of MP0, enhanced conduction capability, and V1 rising following Vdd. The current source I2 and MN3 form a source follower, with V1 as the input and Vreg as the output. Vreg=V1-Vgsn3, so Vreg rises following V1, where Vgsn3 is the gate-source voltage of MN3. The current source I1 and MN4 form a common-source amplifier, Vreg is inverted with the node Y. When Vreg rises, the voltage Vy at Y decreases. As Vy decreases and V1 rises, the gate-source voltage of the MP1 transistor increases, the current Idsp1 flowing through the MP1 transistor increases (Idsp1 is the drain-source current of the MP1 transistor), and the voltage Vx at node X rises. The gate of the transistor MN1 is connected to the X node. When Vx rises to be greater than Vthn1 (the threshold voltage of MN1), the MN1 transistor is turned on, generating a current I=(Vx-Vgsn1) / R1. The current I is supplemented to the current source of the Regulator circuit to accelerate the loop response, so that Vreg quickly returns to the normal voltage value. Vgsn1 is the gate-source voltage of the MN1 transistor.

[0024] When the circuit returns to equilibrium, Vx=VB-Vgsn6, where Vgsn6 is the gate-source voltage of MN6. By setting VB to make VB-Vgsn6<Vthn1, the MN1 transistor can be turned off when the circuit reaches an equilibrium state, reducing the static power consumption of the circuit.

[0025] Contents not described in detail in this specification are prior art known to those skilled in the art. It is hereby indicated that the above description is intended to help those skilled in the art understand this invention, but does not limit the scope of protection of this invention. Any equivalent substitutions, modifications, improvements, and / or simplifications of the above descriptions that do not depart from the essential content of this invention fall within the scope of protection of this invention.

Claims

1. A high transient response regulator circuit, characterized in that, It includes an output low-voltage source Vreg node, which is connected to a source follower and a common-source amplifier respectively. The common-source amplifier is connected to a transient response acceleration circuit. The transient response acceleration circuit compensates for the current source to speed up the loop response, thereby enabling the output low-voltage source Vreg to quickly return to the normal voltage value. The Vreg node is grounded through the second current source I2 and connected to the source of the third NMOS transistor and the gate of the fourth NMOS transistor, respectively. The drain of the fourth NMOS transistor is connected to the gate of the second PMOS transistor and the output of the first current source I1 through node Y. The input of the first current source I1 and the drain of the third NMOS transistor are both connected to the power supply voltage Vdd. The source of the second PMOS transistor, the gate of the third NMOS transistor, and the drain of the first PMOS transistor are interconnected to form node V1. The gate of the first PMOS transistor, the drain of the fifth PMOS transistor, and the drain of the sixth NMOS transistor are interconnected to form node Pg. The gate of the sixth NMOS transistor is connected to the bias voltage VB. The fifth PMOS transistor, the fourth PMOS transistor, and the third PMOS transistor are interconnected to form node Pg. After the gates of the transistors are interconnected, they are connected to the drains of the third PMOS transistor and the first NMOS transistor, respectively, and then grounded through a reference current source Iref. The source of the first NMOS transistor is grounded through a first resistor. The gate of the first NMOS transistor is connected to node X. Node X is connected to the drain of the second NMOS transistor, the drain of the second PMOS transistor, and the source of the sixth NMOS transistor. The gates of the second NMOS transistor and the fifth NMOS transistor are interconnected and then connected to the drains of the fourth PMOS transistor and the fifth NMOS transistor, respectively. The sources of the second NMOS transistor, the fifth NMOS transistor, and the fourth NMOS transistor are all grounded. The sources of the first PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor are all connected to the power supply voltage Vdd terminal.

2. The high transient response regulator circuit according to claim 1, characterized in that, The transient response acceleration circuit consists of a first resistor and a first NMOS transistor.

3. The high transient response regulator circuit according to claim 1, characterized in that, The source follower consists of a second current source I2 and a third NMOS transistor.

4. The high transient response regulator circuit according to claim 1, characterized in that, The common-source amplifier consists of a first current source I1 and a fourth NMOS transistor.

5. The high transient response regulator circuit according to claim 1, characterized in that, When Vdd rises rapidly, it causes V1 to rise, which in turn causes Vreg to rise, which in turn causes Vx to rise. The rise in Vx causes the first NMOS transistor to turn on and generate a conduction current I. I compensates for the current source to bring Vreg back to normal, thus achieving a high transient response.

6. The high transient response regulator circuit according to claim 5, characterized in that, I = (Vx - Vgsn1) / R1, where Vgsn1 is the gate-source voltage of the first NMOS transistor, R1 is the first resistor, Vx > Vthn1, and Vthn1 is the threshold voltage of the first NMOS transistor.

7. The high transient response regulator circuit according to claim 6, characterized in that, When the circuit returns to equilibrium, Vx = VB - Vgsn6, where Vgsn6 is the gate-source voltage of the sixth NMOS transistor. By setting VB - Vgsn6 < Vthn1, the first NMOS transistor is turned off when the circuit reaches equilibrium, thereby reducing the static power consumption of the circuit.

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