A self-biased reference circuit

Abstract

The application provides a self-bias reference circuit, which comprises a reference generation module for generating a reference current according to a mirror current and outputting; and a feedback power supply module connected to a bias output end of the reference generation module, for copying the mirror current and generating a stable power supply voltage according to the copied mirror current to supply power for the reference generation module. The self-bias reference circuit provided by the application solves the problem that the reference current is sensitive to the change of a power supply voltage in the existing self-bias current reference circuit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and in particular to a self-biased reference circuit. Background Technology

[0002] In the field of analog integrated circuit or mixed-signal design, reference voltage sources are very important and commonly used modules. They are used in circuits such as analog-to-digital converters, power converters, and power amplifiers. Their function is to provide the system with a voltage reference that does not change with temperature and supply voltage.

[0003] As an important part of analog circuits, reference voltage sources generally need to operate normally over a wide temperature range. Therefore, they not only require low power consumption, but also stable performance and good temperature characteristics.

[0004] Traditionally, bandgap reference circuits are used for design. The working principle of a bandgap reference source is: based on the characteristic that the bandgap voltage of silicon material is independent of voltage and temperature, the positive temperature coefficient of the difference between the base-emitter voltages of the two transistors ΔVBE is used to cancel out the negative temperature coefficient of the emitter bias voltage VBE of the bipolar transistor, thereby achieving a low-temperature drift and high-precision voltage reference.

[0005] A bipolar junction transistor (BJT) provides VBE, and a thermal voltage VT is generated by ΔVBE between the two transistors. VT is amplified by a factor of 'a' through a resistor network. Finally, the two voltages are added together, i.e., VREF = VBE + aVT. By appropriately selecting the amplification factor 'a', the temperature drift of the two voltages can be canceled out, thus obtaining a voltage reference with zero temperature coefficient at a certain temperature. However, its power consumption is relatively high, and it requires multiple transistors, resulting in a large chip area.

[0006] To reduce costs, traditional methods also employ self-biased current reference circuits in their design, such as... Figure 1 As shown, the principle of a self-biased current reference source is to generate a reference current that is relatively insensitive to the power supply voltage through positive feedback with a feedback coefficient of less than 1. This current is related to the transistor process factor, resistance, and size. However, the reference current generated by the self-biased current reference source is sensitive to changes in the power supply voltage. A more serious drawback is that it varies greatly with temperature. The large positive temperature coefficient limits its application and makes it difficult to use in applications with a wide power supply voltage range and drastic temperature changes. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a self-biased reference circuit to solve the problem that the reference current of the existing self-biased current reference circuit is sensitive to changes in power supply voltage.

[0008] To achieve the above and other related objectives, the present invention provides a self-biased reference circuit, the self-biased reference circuit comprising:

[0009] The reference generation module is used to generate and output a reference current based on the mirror current.

[0010] The feedback power supply module is connected to the bias output terminal of the reference generation module. It is used to replicate the mirror current and generate a stable power supply voltage based on the replicated mirror current to power the reference generation module.

[0011] Optionally, the reference generation module includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a first resistor; the source of the first PMOS transistor is connected to the power supply voltage, the drain is connected to the drain of the first NMOS transistor, and the gate is connected to the gate of the second PMOS transistor and the gate of the third PMOS transistor; the source of the first NMOS transistor is grounded, the drain is connected to its gate, and the gate is connected to the gate of the second NMOS transistor and serves as the bias output terminal of the reference generation module; the source of the second PMOS transistor is connected to the power supply voltage, the drain is connected to its gate and is connected to the drain of the second NMOS transistor; the source of the second NMOS transistor is grounded through the first resistor; the source of the third PMOS transistor is connected to the power supply voltage, and the drain serves as the current output terminal of the reference generation module.

[0012] Optionally, the reference generation module further includes: a first capacitor, a third NMOS transistor, and a fourth NMOS transistor; a first terminal of the first capacitor is connected to the power supply voltage, and a second terminal is connected to the drain of the third NMOS transistor and the gate of the fourth NMOS transistor; the source of the third NMOS transistor is grounded, and its gate is connected to the gate of the first NMOS transistor; the source of the fourth NMOS transistor is grounded, and its drain is connected to the gate of the third NMOS transistor.

[0013] Optionally, the reference generation module includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a first resistor; the source of the first PMOS transistor is connected to the power supply voltage, the drain is connected to the drain of the first NMOS transistor, and the gate is connected to the gate of the second PMOS transistor and the gate of the third PMOS transistor; the source of the first NMOS transistor is grounded, the drain is connected to its gate, and the gate is connected to the gate of the second NMOS transistor and serves as the bias output terminal of the reference generation module; the source of the second PMOS transistor is connected to the power supply voltage, the drain is connected to its gate and serves as the drain of the second NMOS transistor; the source of the second NMOS transistor is grounded through the first resistor; the source of the third PMOS transistor is connected to the power supply voltage, and the drain serves as the current output terminal of the reference generation module; the source of the fourth PMOS transistor is connected to the power supply voltage, the drain is connected to the gate of the first PMOS transistor, and the gate is connected to a first reference enable signal; the source of the third NMOS transistor is grounded, the drain is connected to the gate of the first NMOS transistor, and the gate is connected to a second reference enable signal.

[0014] Optionally, the reference generation module further includes: a first capacitor, a fifth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; a first terminal of the first capacitor is connected to the power supply voltage, and a second terminal is connected to the drain of the fourth NMOS transistor and the gate of the fifth NMOS transistor; the source of the fourth NMOS transistor is grounded, and its gate is connected to the gate of the first NMOS transistor; the source of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor, and its drain is connected to the gate of the third PMOS transistor; the source of the sixth NMOS transistor is grounded, and its gate is connected to the first reference enable signal; the source of the fifth PMOS transistor is connected to the power supply voltage, its drain is connected to the second terminal of the first capacitor, and its gate is connected to the first reference enable signal.

[0015] Optionally, the reference generation module further includes: a first MOS capacitor and a second MOS capacitor, wherein the first MOS capacitor is connected between the power supply voltage and the gate of the first PMOS transistor, and the second MOS capacitor is connected between the gate of the first NMOS transistor and ground; and / or, the reference generation module further includes: a filter capacitor connected between the power supply voltage and ground.

[0016] Optionally, the feedback power supply module includes:

[0017] A current replication unit is connected to the bias output terminal of the reference generation module and is used to replicate the mirror current.

[0018] A power supply generating unit is connected to the output terminal of the current replication unit and is used to generate the power supply voltage based on the replicated mirror current.

[0019] The start control unit is connected between the output terminal of the current replication unit and the output terminal of the power generation unit, and is used to pull the power supply voltage to the power supply voltage in the initial stage of power-on.

[0020] Optionally, the current replication unit includes a sixth PMOS transistor and a seventh NMOS transistor; the source of the sixth PMOS transistor is connected to the power supply voltage, the drain is connected to its gate and connected to the drain of the seventh NMOS transistor, and the gate serves as the output terminal of the current replication unit; the source of the seventh NMOS transistor is grounded, and the gate is connected to the bias output terminal of the reference generation module.

[0021] Optionally, the power supply generation unit includes: a seventh PMOS transistor, an eighth PMOS transistor, and an eighth NMOS transistor; the source of the seventh PMOS transistor is connected to the power supply voltage, the drain is connected to the source of the eighth PMOS transistor and serves as the output terminal of the power supply generation unit, and the gate is connected to the output terminal of the current replication unit; the drain of the eighth PMOS transistor is connected to the drain of the eighth NMOS transistor, and the gate is connected to its drain; the source of the eighth NMOS transistor is grounded, and the gate is connected to its drain.

[0022] Alternatively, the power supply generation unit includes: a seventh PMOS transistor, an eighth PMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor; the source of the seventh PMOS transistor is connected to the power supply voltage, the drain is connected to the source of the eighth PMOS transistor and serves as the output terminal of the power supply generation unit, and the gate is connected to the output terminal of the current replication unit; the drain of the eighth PMOS transistor is connected to the drain of the eighth NMOS transistor, and the gate is connected to its drain; the source of the eighth NMOS transistor is connected to the drain of the ninth NMOS transistor, and the gate is connected to its drain; the source of the ninth NMOS transistor is grounded, and the gate is connected to a first reference enable signal.

[0023] Optionally, the power generation unit further includes a third MOS capacitor connected between the drain of the seventh PMOS transistor and ground.

[0024] Optionally, the startup control unit includes: a ninth PMOS transistor, a tenth PMOS transistor, and a tenth NMOS transistor; the source of the ninth PMOS transistor is connected to the power supply voltage, the drain is connected to the drain of the tenth NMOS transistor and the gate of the tenth PMOS transistor, and the gate is connected to the output terminal of the current replication unit; the source of the tenth NMOS transistor is grounded, and the gate is connected to the bias output terminal of the reference generation module; the source of the tenth PMOS transistor is connected to the power supply voltage, and the drain is connected to the output terminal of the power supply generation unit.

[0025] Optionally, the startup control unit further includes a fourth MOS capacitor connected between the gate of the tenth PMOS transistor and ground.

[0026] As described above, the self-biased reference circuit of the present invention, through the design of the reference generation module and the feedback power supply module, achieves the use of a relatively stable self-biased current feedback as a current source to generate a stable supply voltage as the power supply for the reference generation module. Compared with directly using the power supply voltage, this greatly improves the power supply stability. The present invention can achieve wide power supply voltage and has high voltage stability, high temperature stability and low power consumption characteristics. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of an existing self-biased current reference source.

[0028] Figure 2 The diagram shown is a schematic of a reference generation module in the self-biased reference circuit of the present invention.

[0029] Figure 3 This is another schematic diagram of the reference generation module in the self-biased reference circuit of the present invention.

[0030] Figure 4 The diagram shown is a schematic of a feedback power supply module in the self-biased reference circuit of the present invention.

[0031] Figure 5 This is another schematic diagram of the feedback power supply module in the self-biased reference circuit of the present invention.

[0032] Component designation explanation

[0033] 10 Self-biased reference circuit

[0034] 100 Reference Generation Module

[0035] 200 Feedback Power Supply Module

[0036] 201 Current Replication Unit

[0037] 202 Power Generation Unit

[0038] 203 Start Control Unit Detailed Implementation

[0039] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] Please see Figures 2 to 5 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation, the shape, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0041] like Figures 2 to 5 As shown, this embodiment provides a self-biased reference circuit 10, which includes a reference generation module 100 and a feedback power supply module 200.

[0042] like Figure 2 and Figure 3 As shown, the reference generation module 100 is used to generate and output a reference current Iout based on the mirror current.

[0043] As an example, such as Figure 2 As shown, the reference generation module 100 includes: a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor MN1, a second NMOS transistor MN2, and a first resistor R1; the source of the first PMOS transistor MP1 is connected to the power supply voltage VDD1, the drain is connected to the drain of the first NMOS transistor MN1, and the gate is connected to the gate of the second PMOS transistor MP2 and the gate of the third PMOS transistor MP3; the source of the first NMOS transistor MN1 is grounded, the drain is connected to its gate, and the gate is connected to the gate of the second NMOS transistor MN2 and serves as the bias output terminal of the reference generation module 100; the source of the second PMOS transistor MP2 is connected to the power supply voltage VDD1, the drain is connected to its gate and is connected to the drain of the second NMOS transistor MN2; the source of the second NMOS transistor MN2 is grounded through the first resistor R1; the source of the third PMOS transistor MP3 is connected to the power supply voltage VDD1, and the drain serves as the current output terminal of the reference generation module 100.

[0044] In this example, the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the first NMOS transistor MN1, the second NMOS transistor MN2, and the first resistor R1 constitute a self-biased power supply circuit. A current mirror structure is used to generate a mirror current, a reference current Iout, and a bias voltage. The width-to-length ratio of the first PMOS transistor MP1 and the second PMOS transistor MP2 is equal, and the width-to-length ratio of the first NMOS transistor MN1 and the second NMOS transistor MN2 is equal. Furthermore, the first PMOS transistor MP1, the second PMOS transistor MP2, the first NMOS transistor MN1, and the second NMOS transistor MN2 are all implemented using inverting transistors, thereby generating a reference current Iout in the nA range.

[0045] In practical applications, the first resistor R1 can be a resistor with a fixed resistance or a resistor with an adjustable resistance. However, to overcome the effects of process variations, the first resistor R1 is set to have an adjustable resistance, and its resistance is adjusted via a trimming signal. This enables the provision of a reference current Iout for calibration during process variations. Furthermore, to improve the circuit's temperature stability, the first resistor R1 is a combination of a positive temperature coefficient trap resistor and a negative temperature coefficient high-resistance polycrystalline resistor to obtain a zero temperature coefficient resistor, thereby overcoming the influence of temperature on the resistance value and, consequently, on the reference current Iout.

[0046] Furthermore, such as Figure 2 As shown, the reference generation module 100 further includes: a first capacitor C1, a third NMOS transistor MN3, and a fourth NMOS transistor MN4; the first terminal of the first capacitor C1 is connected to the power supply voltage VDD1, and the second terminal is connected to the drain of the third NMOS transistor MN3 and the gate of the fourth NMOS transistor MN4; the source of the third NMOS transistor MN3 is grounded, and its gate is connected to the gate of the first NMOS transistor MN1; the source of the fourth NMOS transistor MN4 is grounded, and its drain is connected to the gate of the third PMOS transistor MP3.

[0047] In this example, the first capacitor C1, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 constitute a power-on startup circuit, which is used to provide a given state for the third PMOS transistor MP3 in the initial stage of power-on so that the reference generation module 100 can start working normally.

[0048] Furthermore, such as Figure 2 As shown, the reference generation module 100 further includes: a first MOS capacitor MC1 and a second MOS capacitor MC2, wherein the first MOS capacitor MC1 is connected between the power supply voltage VDD1 and the gate of the first PMOS transistor MP1, and the second MOS capacitor MC2 is connected between the gate of the first NMOS transistor MN1 and ground; and / or, the reference generation module 100 further includes: a filter capacitor C0, which is connected between the power supply voltage VDD1 and ground.

[0049] In this example, the first MOS capacitor MC1 and the second MOS capacitor MC2 are used as capacitors to filter and regulate the voltage, thereby improving the stability of the gate voltage of the corresponding MOS transistor; while the filter capacitor C0 filters and regulates the supply voltage VDD1.

[0050] As another example, such as Figure 3As shown, the reference generation module 100 includes: a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, and a first resistor R1; the source of the first PMOS transistor MP1 is connected to the power supply voltage VDD1, the drain is connected to the drain of the first NMOS transistor MN1, and the gate is connected to the gates of the second PMOS transistor MP2 and the third PMOS transistor MP3; the source of the first NMOS transistor MN1 is grounded, the drain is connected to its gate, and the gate is connected to the gate of the second NMOS transistor MN2 and serves as the bias of the reference generation module 100. The output terminal is set; the source of the second PMOS transistor MP2 is connected to the power supply voltage VDD1, and its drain is connected to its gate and then to the drain of the second NMOS transistor MN2; the source of the second NMOS transistor MN2 is grounded through the first resistor R1; the source of the third PMOS transistor MP3 is connected to the power supply voltage VDD1, and its drain serves as the current output terminal of the reference generation module 100; the source of the fourth PMOS transistor MP4 is connected to the power supply voltage VDD1, and its drain is connected to the gate of the first PMOS transistor MP1, with the gate connected to the first reference enable signal ENH; the source of the third NMOS transistor MN3 is grounded, and its drain is connected to the gate of the first NMOS transistor MN1, with the gate connected to the second reference enable signal ENL.

[0051] The first reference enable signal ENH and the second reference enable signal ENL are a pair of inverted signals. The first reference enable signal ENH is obtained by inverting the initial reference enable signal ENB using the first inverter INV1, and the second reference enable signal ENL is obtained by inverting the first reference enable signal ENH using the second inverter INV2.

[0052] In this example, the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the first NMOS transistor MN1, the second NMOS transistor MN2, and the first resistor R1 constitute a self-biased power supply circuit, which uses a current mirror structure to generate a mirrored current, a reference current Iout, and a bias voltage. The fourth PMOS transistor MP4 and the third NMOS transistor MN3 constitute the control circuit of this self-biased power supply circuit. When the first reference enable signal ENH is high and the second reference enable signal ENL is low, the self-biased power supply circuit is controlled to work. When the first reference enable signal ENH is low and the second reference enable signal ENL is high, the self-biased power supply circuit is controlled to turn off. The width-to-length ratio of the first PMOS transistor MP1 and the second PMOS transistor MP2 is equal, and the width-to-length ratio of the first NMOS transistor MN1 and the second NMOS transistor MN2 is equal. The first PMOS transistor MP1, the second PMOS transistor MP2, the first NMOS transistor MN1, and the second NMOS transistor MN2 are all implemented using inverting transistors to generate a reference current Iout in the nA range.

[0053] In practical applications, the first resistor R1 can be a resistor with a fixed resistance or a resistor with an adjustable resistance. However, to overcome the effects of process variations, the first resistor R1 is set to have an adjustable resistance, and its resistance is adjusted via a trimming signal. This enables the provision of a reference current Iout for calibration during process variations. Furthermore, to improve the circuit's temperature stability, the first resistor R1 is a combination of a positive temperature coefficient trap resistor and a negative temperature coefficient high-resistance polycrystalline resistor to obtain a zero temperature coefficient resistor, thereby overcoming the influence of temperature on the resistance value and, consequently, on the reference current Iout.

[0054] Furthermore, such as Figure 3 As shown, the reference generation module 100 further includes: a first capacitor C1, a fifth PMOS transistor MP5, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, and a sixth NMOS transistor MN6; the first terminal of the first capacitor C1 is connected to the power supply voltage VDD1, and the second terminal is connected to the drain of the fourth NMOS transistor MN4 and the gate of the fifth NMOS transistor MN5; the source of the fourth NMOS transistor MN4 is grounded, and its gate is connected to the gate of the first NMOS transistor MN1; the source of the fifth NMOS transistor MN5 is connected to the drain of the sixth NMOS transistor MN6, and its drain is connected to the gate of the third PMOS transistor MP3; the source of the sixth NMOS transistor MN6 is grounded, and its gate is connected to the first reference enable signal ENH; the source of the fifth PMOS transistor MP5 is connected to the power supply voltage VDD1, its drain is connected to the second terminal of the first capacitor C1, and its gate is connected to the first reference enable signal ENH.

[0055] In this example, the first capacitor C1, the fourth NMOS transistor MN4, and the fifth NMOS transistor MN5 constitute a power-on startup circuit, which provides a given state for the third PMOS transistor MP3 during the initial power-on phase, so that the reference generation module 100 can start working normally. The fifth PMOS transistor MP5 and the sixth NMOS transistor MN6 constitute the control circuit of the power-on startup circuit. When the first reference enable signal ENH is high, the power-on startup circuit is controlled to work; when the first reference enable signal ENH is low, the power-on startup circuit is controlled to shut down.

[0056] Furthermore, such as Figure 3 As shown, the reference generation module 100 further includes: a first MOS capacitor MC1 and a second MOS capacitor MC2, wherein the first MOS capacitor MC1 is connected between the power supply voltage VDD1 and the gate of the first PMOS transistor MP1, and the second MOS capacitor MC2 is connected between the gate of the first NMOS transistor MN1 and ground; and / or, the reference generation module 100 further includes: a filter capacitor C0, which is connected between the power supply voltage VDD1 and ground.

[0057] In this example, the first MOS capacitor MC1 and the second MOS capacitor MC2 are used as capacitors to filter and regulate the voltage, thereby improving the stability of the gate voltage of the corresponding MOS transistor; while the filter capacitor C0 filters and regulates the supply voltage VDD1.

[0058] like Figure 4 and Figure 5 As shown, the feedback power supply module 200 is connected to the bias output terminal of the reference generation module 100. It is used to replicate the mirror current and generate a stable supply voltage VDD1 based on the replicated mirror current to power the reference generation module 100. It should be noted that, for ease of writing, "replicated mirror current" is simplified to "replicated current" here. Those skilled in the art should understand that "replicated current" in the following text actually refers to "replicated mirror current".

[0059] Specifically, the feedback power supply module 200 includes: a current replication unit 201, a power generation unit 202, and a start control unit 203.

[0060] like Figure 4 and Figure 5 As shown, the current replication unit 201 is connected to the bias output terminal of the reference generation module 100 and is used to replicate the mirror current.

[0061] As an example, the current replication unit 201 includes a sixth PMOS transistor MP6 and a seventh NMOS transistor MN7. The source of the sixth PMOS transistor MP6 is connected to the power supply voltage VDD0, and its drain is connected to its gate and then to the drain of the seventh NMOS transistor MN7. The gate serves as the output terminal of the current replication unit 201. The source of the seventh NMOS transistor MN7 is grounded, and its gate is connected to the bias output terminal of the reference generation module 100. In this example, a current mirror structure is used to replicate the mirrored current to the drain of the sixth PMOS transistor MP6.

[0062] like Figure 4 and Figure 5 As shown, the power supply generating unit 202 is connected to the output terminal of the current replication unit 201 and is used to generate the power supply voltage VDD1 according to the replication current.

[0063] As an example, such as Figure 4 As shown, the power generation unit 202 includes: a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, and an eighth NMOS transistor MN8; the source of the seventh PMOS transistor MP7 is connected to the power supply voltage VDD0, the drain is connected to the source of the eighth PMOS transistor MP8 and serves as the output terminal of the power generation unit 202, and the gate is connected to the output terminal of the current replication unit 201; the drain of the eighth PMOS transistor MP8 is connected to the drain of the eighth NMOS transistor MN8, and the gate is connected to its drain; the source of the eighth NMOS transistor MN8 is grounded, and the gate is connected to its drain.

[0064] In this example, the seventh PMOS transistor MP7 and the sixth PMOS transistor MP6 in the current replication unit 201 form a current mirror structure, which mirrors the replicated current to the drain of the seventh PMOS transistor MP7; while the eighth PMOS transistor MP8 and the eighth NMOS transistor MN8 are used as resistors to convert the drain current of the seventh PMOS transistor MP7 into a voltage output.

[0065] It should be noted that since the current supply capability of the seventh PMOS transistor MP7 is the sum of the current consumed by each branch powered by the supply voltage VDD1, the driving capability of the seventh PMOS transistor MP7 should be guaranteed, such as by making the width-to-length ratio of the seventh PMOS transistor MP7 sufficiently large.

[0066] Furthermore, the power supply generation unit 202 also includes a third MOS capacitor MC3, connected between the drain of the seventh PMOS transistor MP7 and ground. In this example, the third MOS capacitor MC3 is used as a capacitor to filter and regulate the power supply voltage VDD1.

[0067] As another example, such as Figure 5 As shown, the power supply generation unit 202 includes: a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, an eighth NMOS transistor MN8, and a ninth NMOS transistor MN9; the source of the seventh PMOS transistor MP7 is connected to the power supply voltage VDD0, the drain is connected to the source of the eighth PMOS transistor MP8 and serves as the output terminal of the power supply generation unit 202, and the gate is connected to the output terminal of the current replication unit 201; the drain of the eighth PMOS transistor MP8 is connected to the drain of the eighth NMOS transistor MN8, and the gate is connected to its drain; the source of the eighth NMOS transistor MN8 is connected to the drain of the ninth NMOS transistor MN9, and the gate is connected to its drain; the source of the ninth NMOS transistor MN9 is grounded, and the gate is connected to the first reference enable signal ENH.

[0068] In this example, the seventh PMOS transistor MP7 and the sixth PMOS transistor MP6 in the current replication unit 201 form a current mirror structure, mirroring the replicated current to the drain of the seventh PMOS transistor MP7; the eighth PMOS transistor MP8 and the eighth NMOS transistor MN8 are used as resistors to convert the drain current of the seventh PMOS transistor MP7 into a voltage output; while the ninth NMOS transistor MN9 is used as a switch. When the first reference enable signal ENH is high, it controls the power supply generation unit 202 to work, and when the first reference enable signal ENH is low, it controls the power supply generation unit 202 to be completely turned off, thereby reducing circuit power consumption.

[0069] It should be noted that since the current supply capability of the seventh PMOS transistor MP7 is the sum of the current consumed by each branch powered by the supply voltage VDD1, the driving capability of the seventh PMOS transistor MP7 should be guaranteed, such as by making the width-to-length ratio of the seventh PMOS transistor MP7 sufficiently large.

[0070] Furthermore, the power supply generation unit also includes a third MOS capacitor MC3, connected between the drain of the seventh PMOS transistor MP7 and ground. In this example, the third MOS capacitor MC3 is used as a capacitor to filter and regulate the supply voltage VDD1.

[0071] like Figure 4 and Figure 5 As shown, the start control unit 203 is connected between the output terminal of the current replication unit 201 and the output terminal of the power generation unit 202, and is used to pull the power supply voltage VDD1 to the power supply voltage VDD0 in the initial stage of power-on.

[0072] As an example, the start control unit 203 includes: a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, and a tenth NMOS transistor MN10; the source of the ninth PMOS transistor MP9 is connected to the power supply voltage VDD0, the drain is connected to the drain of the tenth NMOS transistor MN10 and the gate of the tenth PMOS transistor MP10, and the gate is connected to the output terminal of the current replication unit 201; the source of the tenth NMOS transistor MN10 is grounded, and the gate is connected to the bias output terminal of the reference generation module 100; the source of the tenth PMOS transistor MP10 is connected to the power supply voltage VDD0, and the drain is connected to the output terminal of the power supply generation unit 202.

[0073] Furthermore, the start-up control unit 203 also includes a fourth MOS capacitor MC4, connected between the gate of the tenth PMOS transistor MP10 and ground. In this example, the fourth MOS capacitor MC4 is used as a capacitor to filter and regulate the voltage, thereby improving the stability of the gate voltage of the tenth PMOS transistor MP10.

[0074] The following is based on Figure 3 and Figure 5 Taking the circuit structure shown as an example, the working process of the self-biased reference circuit in this embodiment will be described in detail.

[0075] After the circuit is powered on:

[0076] If the initial reference enable signal ENB is high, the first reference enable signal ENH is low, and the second reference enable signal ENL is high, then the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, and the third NMOS transistor MN3 are turned on, the sixth NMOS transistor MN6 is turned off, the self-biased power supply circuit and the power-on start-up circuit in the reference generation module 100 are turned off, the voltage at node A is 0, there is no current in the sixth PMOS transistor MP6 and the ninth PMOS transistor MP9, the voltage at node B is pulled to 0, and the tenth PMOS transistor MP10 is turned on, pulling VDD1 up to VDD0.

[0077] If the initial reference enable signal ENB is low, the first reference enable signal ENH is high, and the second reference enable signal ENL is low, then the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, and the third NMOS transistor MN3 are turned off, and the sixth NMOS transistor MN6 is turned on. The self-biased power supply circuit and the power-on startup circuit in the reference generation module 100 start working, and the mirrored current is copied to the drain of the sixth PMOS transistor MP6 using the current mirror structure. Since the resistance of the NMOS transistor (such as the tenth NMOS transistor MN10) is relatively large, the voltage at node B is gradually pulled up to VDD0, the tenth PMOS transistor MP10 is turned off, and VDD1 is obtained based on the copied current, thus completing the startup.

[0078] Since the mirror current provided by the reference generation module 100 is relatively stable, VDD1 obtained based on the mirror current is fixed. Subsequently, the fixed VDD1 is used as the power supply to replace VDD0 to power the reference generation module 100, so that the reference circuit 10 of this embodiment is basically unaffected by voltage.

[0079] In summary, the self-biased reference circuit of this invention, through the design of a reference generation module and a feedback power supply module, achieves the use of a relatively stable self-biased current feedback as a current source to generate a stable supply voltage for the reference generation module. Compared with directly using the power supply voltage, this significantly improves power supply stability. This invention can achieve wide power supply voltage operation and features high voltage stability, high temperature stability, and low power consumption. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0080] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A self-biased reference circuit, characterized in that, The self-biased reference circuit includes: The reference generation module is used to generate and output a reference current based on the mirror current. The feedback power supply module is connected to the bias output terminal of the reference generation module. It is used to replicate the mirror current and generate a stable power supply voltage based on the replicated mirror current to power the reference generation module. The reference generation module includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a first resistor; the source of the first PMOS transistor is connected to the power supply voltage, the drain is connected to the drain of the first NMOS transistor, and the gate is connected to the gate of the second PMOS transistor and the gate of the third PMOS transistor; the source of the first NMOS transistor is grounded, the drain is connected to its gate, and the gate is connected to the gate of the second NMOS transistor and serves as the bias output terminal of the reference generation module; the source of the second PMOS transistor is connected to the power supply voltage, the drain is connected to its gate and is connected to the drain of the second NMOS transistor; the source of the second NMOS transistor is grounded through the first resistor; the source of the third PMOS transistor is connected to the power supply voltage, and the drain serves as the current output terminal of the reference generation module.

2. The self-biased reference circuit according to claim 1, characterized in that, The reference generation module further includes: a first capacitor, a third NMOS transistor, and a fourth NMOS transistor; the first terminal of the first capacitor is connected to the power supply voltage, and the second terminal is connected to the drain of the third NMOS transistor and the gate of the fourth NMOS transistor; the source of the third NMOS transistor is grounded, and its gate is connected to the gate of the first NMOS transistor; the source of the fourth NMOS transistor is grounded, and its drain is connected to the gate of the third NMOS transistor.

3. The self-biased reference circuit according to claim 1 or 2, characterized in that, The benchmark generation module further includes: A first MOS capacitor and a second MOS capacitor, wherein the first MOS capacitor is connected between the power supply voltage and the gate of the first PMOS transistor, and the second MOS capacitor is connected between the gate of the first NMOS transistor and ground; And / or, the reference generation module further includes: a filter capacitor connected between the power supply voltage and ground.

4. The self-biased reference circuit according to claim 1, characterized in that, The feedback power supply module includes: A current replication unit is connected to the bias output terminal of the reference generation module and is used to replicate the mirror current. A power supply generating unit is connected to the output terminal of the current replication unit and is used to generate the power supply voltage based on the replicated mirror current. The start control unit is connected between the output terminal of the current replication unit and the output terminal of the power generation unit, and is used to pull the power supply voltage to the power supply voltage in the initial stage of power-on.

5. The self-biased reference circuit according to claim 4, characterized in that, The current replication unit includes a sixth PMOS transistor and a seventh NMOS transistor; the source of the sixth PMOS transistor is connected to the power supply voltage, the drain is connected to its gate and connected to the drain of the seventh NMOS transistor, and the gate serves as the output terminal of the current replication unit; the source of the seventh NMOS transistor is grounded, and the gate is connected to the bias output terminal of the reference generation module.

6. The self-biased reference circuit according to claim 4, characterized in that, The power supply generation unit includes a seventh PMOS transistor, an eighth PMOS transistor, and an eighth NMOS transistor; the source of the seventh PMOS transistor is connected to the power supply voltage, the drain is connected to the source of the eighth PMOS transistor and serves as the output terminal of the power supply generation unit, and the gate is connected to the output terminal of the current replication unit; the drain of the eighth PMOS transistor is connected to the drain of the eighth NMOS transistor, and the gate is connected to its drain; the source of the eighth NMOS transistor is grounded, and the gate is connected to its drain. Alternatively, the power supply generation unit includes: a seventh PMOS transistor, an eighth PMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor; the source of the seventh PMOS transistor is connected to the power supply voltage, the drain is connected to the source of the eighth PMOS transistor and serves as the output terminal of the power supply generation unit, and the gate is connected to the output terminal of the current replication unit; the drain of the eighth PMOS transistor is connected to the drain of the eighth NMOS transistor, and the gate is connected to its drain; the source of the eighth NMOS transistor is connected to the drain of the ninth NMOS transistor, and the gate is connected to its drain; the source of the ninth NMOS transistor is grounded, and the gate is connected to a first reference enable signal.

7. The self-biased reference circuit according to claim 6, characterized in that, The power generation unit further includes a third MOS capacitor, which is connected between the drain of the seventh PMOS transistor and ground.

8. The self-biased reference circuit according to claim 4, characterized in that, The startup control unit includes a ninth PMOS transistor, a tenth PMOS transistor, and a tenth NMOS transistor; the source of the ninth PMOS transistor is connected to the power supply voltage, the drain is connected to the drain of the tenth NMOS transistor and the gate of the tenth PMOS transistor, and the gate is connected to the output terminal of the current replication unit; the source of the tenth NMOS transistor is grounded, and the gate is connected to the bias output terminal of the reference generation module; the source of the tenth PMOS transistor is connected to the power supply voltage, and the drain is connected to the output terminal of the power supply generation unit.

9. The self-biased reference circuit according to claim 8, characterized in that, The startup control unit further includes a fourth MOS capacitor, connected between the gate of the tenth PMOS transistor and ground.

10. A self-biased reference circuit, characterized in that, The self-biased reference circuit includes: The reference generation module is used to generate and output a reference current based on the mirror current. The feedback power supply module is connected to the bias output terminal of the reference generation module. It is used to replicate the mirror current and generate a stable power supply voltage based on the replicated mirror current to power the reference generation module. The reference generation module includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a first resistor; the source of the first PMOS transistor is connected to the power supply voltage, the drain is connected to the drain of the first NMOS transistor, and the gate is connected to the gate of the second PMOS transistor and the gate of the third PMOS transistor; the source of the first NMOS transistor is grounded, the drain is connected to its gate, and the gate is connected to the gate of the second NMOS transistor and serves as the bias output terminal of the reference generation module; the source of the second PMOS transistor is connected to the power supply voltage, the drain is connected to its gate and serves as the drain of the second NMOS transistor; the source of the second NMOS transistor is grounded through the first resistor; the source of the third PMOS transistor is connected to the power supply voltage, and the drain serves as the current output terminal of the reference generation module; the source of the fourth PMOS transistor is connected to the power supply voltage, the drain is connected to the gate of the first PMOS transistor, and the gate is connected to a first reference enable signal; the source of the third NMOS transistor is grounded, the drain is connected to the gate of the first NMOS transistor, and the gate is connected to a second reference enable signal.

11. The self-biased reference circuit according to claim 10, characterized in that, The reference generation module further includes: a first capacitor, a fifth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; the first terminal of the first capacitor is connected to the power supply voltage, and the second terminal is connected to the drain of the fourth NMOS transistor and the gate of the fifth NMOS transistor; the source of the fourth NMOS transistor is grounded, and its gate is connected to the gate of the first NMOS transistor; the source of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor, and its drain is connected to the gate of the third PMOS transistor; the source of the sixth NMOS transistor is grounded, and its gate is connected to the first reference enable signal; the source of the fifth PMOS transistor is connected to the power supply voltage, its drain is connected to the second terminal of the first capacitor, and its gate is connected to the first reference enable signal.

12. The self-biased reference circuit according to claim 10 or 11, characterized in that, The benchmark generation module further includes: A first MOS capacitor and a second MOS capacitor, wherein the first MOS capacitor is connected between the power supply voltage and the gate of the first PMOS transistor, and the second MOS capacitor is connected between the gate of the first NMOS transistor and ground; And / or, the reference generation module further includes: a filter capacitor connected between the power supply voltage and ground.

13. The self-biased reference circuit according to claim 10, characterized in that, The feedback power supply module includes: A current replication unit is connected to the bias output terminal of the reference generation module and is used to replicate the mirror current. A power supply generating unit is connected to the output terminal of the current replication unit and is used to generate the power supply voltage based on the replicated mirror current. The start control unit is connected between the output terminal of the current replication unit and the output terminal of the power generation unit, and is used to pull the power supply voltage to the power supply voltage in the initial stage of power-on.

14. The self-biased reference circuit according to claim 13, characterized in that, The current replication unit includes a sixth PMOS transistor and a seventh NMOS transistor; the source of the sixth PMOS transistor is connected to the power supply voltage, the drain is connected to its gate and connected to the drain of the seventh NMOS transistor, and the gate serves as the output terminal of the current replication unit; the source of the seventh NMOS transistor is grounded, and the gate is connected to the bias output terminal of the reference generation module.

15. The self-biased reference circuit according to claim 13, characterized in that, The power supply generation unit includes a seventh PMOS transistor, an eighth PMOS transistor, and an eighth NMOS transistor; the source of the seventh PMOS transistor is connected to the power supply voltage, the drain is connected to the source of the eighth PMOS transistor and serves as the output terminal of the power supply generation unit, and the gate is connected to the output terminal of the current replication unit; the drain of the eighth PMOS transistor is connected to the drain of the eighth NMOS transistor, and the gate is connected to its drain; the source of the eighth NMOS transistor is grounded, and the gate is connected to its drain. Alternatively, the power supply generation unit includes: a seventh PMOS transistor, an eighth PMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor; the source of the seventh PMOS transistor is connected to the power supply voltage, the drain is connected to the source of the eighth PMOS transistor and serves as the output terminal of the power supply generation unit, and the gate is connected to the output terminal of the current replication unit; the drain of the eighth PMOS transistor is connected to the drain of the eighth NMOS transistor, and the gate is connected to its drain; the source of the eighth NMOS transistor is connected to the drain of the ninth NMOS transistor, and the gate is connected to its drain; the source of the ninth NMOS transistor is grounded, and the gate is connected to a first reference enable signal.

16. The self-biased reference circuit according to claim 15, characterized in that, The power generation unit further includes a third MOS capacitor, which is connected between the drain of the seventh PMOS transistor and ground.

17. The self-biased reference circuit according to claim 13, characterized in that, The startup control unit includes a ninth PMOS transistor, a tenth PMOS transistor, and a tenth NMOS transistor; the source of the ninth PMOS transistor is connected to the power supply voltage, the drain is connected to the drain of the tenth NMOS transistor and the gate of the tenth PMOS transistor, and the gate is connected to the output terminal of the current replication unit; the source of the tenth NMOS transistor is grounded, and the gate is connected to the bias output terminal of the reference generation module; the source of the tenth PMOS transistor is connected to the power supply voltage, and the drain is connected to the output terminal of the power supply generation unit.

18. The self-biased reference circuit according to claim 17, characterized in that, The startup control unit further includes a fourth MOS capacitor, connected between the gate of the tenth PMOS transistor and ground.

Images