A high-speed, large-capacity, low-latency data storage method

Abstract

The application provides a high-speed large-capacity low-delay data storage method, and belongs to the technical field of data storage. Specifically, an intelligent network card is configured on each data source or access node and a storage node; a logical partition function module of the intelligent network card of the back end is configured according to the storage data capacity of each data source or access node, so that each data source or access node and the corresponding logical partition of the memory of the storage node are bound; the data source or access node sends a storage instruction, and the intelligent network card of the front end sends the command to the storage node through NVMe over RDMA; and the network card of the back end storage node forwards the storage instruction to the corresponding storage logical partition. The storage equipment based on the method of the application can simultaneously provide end-to-end high-bandwidth and low-delay data storage services to multiple data sources or access nodes, and can support adaptive and flexible upgrade and expansion of computing and storage resources according to requirements in the later period.

Description

Technical Field

[0001] This application relates to the field of data storage, and in particular to a high-speed, large-capacity, low-latency data storage method. Background Technology

[0002] The future belongs to intelligence, and computing devices will transform towards intelligence. Data, as one of the three driving forces behind the development of artificial intelligence (algorithms, computing power, and data), is increasingly demonstrating its asset value. Environmental information, equipment fault prediction and health management information, and related process information captured by multi-source sensor systems form the foundation of comprehensive situational awareness and are the cornerstone of artificial intelligence algorithm training and evolution. With the rapid development of information technology, the scale and types of data will continue to grow in the future. Against this backdrop, the need for in-depth research into high-performance storage technologies is becoming increasingly urgent.

[0003] In the embedded systems field, storage devices are generally categorized into two main types: local storage and network storage. Local storage directly connects to the processor via a local bus such as PCIe, serving only the processor's local needs. While this results in relatively low latency, the binding of storage and computing resources leads to low resource utilization and makes future upgrades and expansions inconvenient and costly. Network storage devices typically employ a client / server (C / S) architecture, where the storage device integrates high-performance computing resources to host storage and data management software, providing shared storage services to multiple data sources or access nodes. However, this architecture results in a heavy software stack on the storage device side, making it difficult to guarantee end-to-end data storage latency. Furthermore, with the widespread application of new sensing devices, the bandwidth requirements for recorded data are rapidly increasing, putting significant pressure on devices under high-concurrency access scenarios, potentially creating bottlenecks and impacting service quality. Summary of the Invention

[0004] In view of this, this application provides a high-speed, large-capacity, low-latency data storage method, which solves the problems in the prior art. The storage device based on the method of this application can provide end-to-end high-bandwidth, low-latency data storage services to multiple data sources or access nodes at the same time, and can support flexible and adaptive upgrades and expansions of computing and storage resources according to needs in the future.

[0005] This application provides a high-speed, large-capacity, low-latency data storage method using the following technical solution:

[0006] A high-speed, high-capacity, low-latency data storage method includes the following steps:

[0007] The back-end storage nodes are interconnected with the various data sources or access nodes at the front end via an RDMA network.

[0008] Configure smart network interface cards (NICs) on each data source or access node at the front end and on the storage nodes at the back end. The smart NICs at the front end implement RDMA and NVMe Initiator, while the smart NICs at the back end implement RDMA, NVMe Target, and logically partition the memory of the storage nodes at the back end.

[0009] Using the storage capacity requirements of each front-end data source or access node as prior information, configure the logical partitioning function module of the back-end smart network card so that each front-end data source or access node is bound to the corresponding logical partition of the back-end storage node's memory.

[0010] The front-end data source or access node issues a storage command and sends the command to the back-end storage node via NVMe over RDMA through the front-end smart network card.

[0011] The smart network interface card of the backend storage node forwards storage commands to the corresponding logical storage partition;

[0012] The storage logical partition completes the parsing of the corresponding data source or access node instructions from the front end, and executes subsequent data storage I / O operations.

[0013] Optionally, a file system can be run on the host CPU of each front-end data source or access node to organize data in the form of files.

[0014] Optionally, the back-end storage node's memory includes DDR and Nand Flash, and subsequent data storage I / O operations include first writing the data to be stored to DDR and then transferring it to Nand Flash.

[0015] Optionally, after the front-end data source or access node initiates a data read command, the target data is moved from the Nand Flash of the back-end storage node to the DDR, and then sent to the front-end data source or access node for processing via the RDMA network.

[0016] Optionally, multiple electrons can be grouped together to form an electron disk array, which can then be used as the memory for the back-end storage nodes.

[0017] Optionally, the smart network card is programmed based on an FPGA.

[0018] In summary, this application includes the following beneficial technical effects:

[0019] This application adopts an RDMA-based NVMe-oF storage architecture to provide end-to-end high-bandwidth, low-latency block storage services; it uses a custom smart network card based on FPGA to offload RDMA and NVMe-oF functions, freeing up host CPU resources for upper-layer applications; it decouples computing and storage resources, enabling flexible and adaptive upgrades and expansions of computing and storage resources as needed in the future. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a system architecture block diagram of the high-speed, high-capacity, low-latency data storage method of this application;

[0022] Figure 2 This application stores a data flow diagram;

[0023] Figure 3 This is a schematic diagram of the logical partitioning of the storage nodes in this application. Detailed Implementation

[0024] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0025] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0027] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The illustrations only show the components related to this application and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0028] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0029] This application provides a method for high-speed, large-capacity, low-latency data storage.

[0030] like Figure 1 and Figure 2 As shown, a high-speed, large-capacity, low-latency data storage method includes the following steps:

[0031] The backend storage nodes are interconnected with the various data sources or access nodes at the front end through an RDMA network. RDMA stands for Remote Direct Memory Access.

[0032] Smart network interface cards (NICs) are configured on various data sources or access nodes at the front end and on storage nodes at the back end. The front-end smart NICs implement RDMA and NVMe Initiator, while the back-end smart NICs implement RDMA, NVMe Target, and logical partitioning of the memory on the back-end storage nodes. The smart NICs are programmed based on FPGAs. NVMe stands for Non-Volatile Memory Express, which is a non-volatile memory host controller interface specification. Initiator refers to the source end, and Target refers to the destination end.

[0033] Using the storage capacity requirements of each front-end data source or access node as prior information, the logical partitioning function module of the back-end smart network card is configured so that each front-end data source or access node is bound to the corresponding logical partition of the back-end storage node.

[0034] The front-end data source or access node issues storage commands and sends the commands to the back-end storage node via NVMe over RDMA through the front-end smart network card.

[0035] The smart network interface card of the backend storage node forwards storage commands to the corresponding logical storage partition;

[0036] The storage logical partition completes the parsing of the corresponding data source or access node instructions from the front end, and executes subsequent data storage I / O operations.

[0037] The back-end storage node's memory includes DDR and Nand Flash. Subsequent data storage I / O operations involve first writing the data to be stored to DDR and then transferring it to Nand Flash.

[0038] When the front-end data source or access node initiates a data read command, the target data is moved from the Nand Flash of the back-end storage node to the DDR, and then sent to the front-end data source or access node for processing via the RDMA network.

[0039] This application adopts an RDMA-based NVMe-oF storage architecture to provide end-to-end high-bandwidth, low-latency block storage services. It employs a custom FPGA-based smart network interface card (NIC) to offload RDMA and NVMe-oF functions, freeing up host CPU resources for upper-layer applications. This decoupling of computing and storage resources allows for flexible and adaptive upgrades and expansions of computing and storage resources as needed. NVMe-oF stands for NVMe over Fabrics.

[0040] The storage data flow in this application can be divided into uplink and downlink, corresponding to data reading and storage scenarios, respectively. Taking the downlink as an example, NVMe storage is initiated by the Host CPU of each data source node. Then, the NVMe-oF Initiator of the front-end smart network card is responsible for the command conversion from NVMe to NVMe-oF. After that, it is transmitted in the form of RDMA messages to the NVMe-oF Target on the back-end smart network card, which is converted into NVMe commands to execute the subsequent disk storage process, writing the data to be stored to DDR first and then transferring it to NAND Flash. Here, Host CPU refers to the CPU of a single physical host.

[0041] To facilitate data management in storage nodes, a file system can be run on the host CPU of each front-end data source or access node to organize data in the form of files. Uplink transfer is the reverse process of downlink transfer: when the source node initiates a data read command, the target data is moved from the Nand Flash to the DDR of the electronic disk, and then sent to the source / access node for processing via the RDMA network.

[0042] like Figure 3 As shown, multiple electronic disks are grouped together to form an electronic disk array, which serves as the storage for the back-end storage nodes. Block storage services are provided to the front-end data source or access node based on NVMe-oF. Because NVMe-oF technology features a one-to-one binding between the front-end data source or access node and the back-end storage node, this system first needs to estimate the total amount of data to be stored based on parameters such as the data type and working duration of each data source node before deployment. This prior information is then used to pre-divide the electronic disk array logically, allocating and mapping storage resources.

[0043] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A high-speed, large-capacity, low-latency data storage method, characterized in that, Includes the following steps: The back-end storage nodes are interconnected with the various data sources or access nodes at the front end via an RDMA network. Configure smart network interface cards (NICs) on each data source or access node at the front end and on the storage nodes at the back end. The smart NICs at the front end implement RDMA and NVMe Initiator, while the smart NICs at the back end implement RDMA, NVMe Target, and logically partition the memory of the storage nodes at the back end. Using the storage capacity requirements of each front-end data source or access node as prior information, configure the logical partitioning function module of the back-end smart network card to bind each front-end data source or access node to the corresponding logical partition of the back-end storage node's memory. The front-end data source or access node issues storage commands and sends the commands to the back-end storage node via NVMe over RDMA through the front-end smart network card. The smart network interface card of the backend storage node forwards storage commands to the corresponding logical storage partition; The storage logical partition completes the parsing of the corresponding data source or access node instructions from the front end, and executes subsequent data storage I / O operations.

2. The high-speed, large-capacity, low-latency data storage method according to claim 1, characterized in that, The file system runs on the host CPU of each front-end data source or access node to organize data in the form of files.

3. The high-speed, large-capacity, low-latency data storage method according to claim 1, characterized in that, The back-end storage node's memory includes DDR and Nand Flash. Subsequent data storage I / O operations involve first writing the data to be stored to DDR and then transferring it to Nand Flash.

4. The high-speed, large-capacity, low-latency data storage method according to claim 3, characterized in that, When the front-end data source or access node initiates a data read command, the target data is moved from the Nand Flash of the back-end storage node to the DDR, and then sent to the front-end data source or access node for processing via the RDMA network.

5. The high-speed, large-capacity, low-latency data storage method according to claim 1, characterized in that, Multiple electrons are placed together to form an electron disk array, which is then used as the memory for the back-end storage nodes.

6. The high-speed, large-capacity, low-latency data storage method according to claim 1, characterized in that, Smart network cards are programmed based on FPGAs.

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