A method for processing instruction information of a charging test device

Abstract

This invention relates to a method for processing instruction information in a charging test device. The method includes: configuring and saving a register list for the charging test device; configuring an instruction receiving / returning interface; identifying the instruction receiving / returning interface each time a connection with a scheduling device is successfully established; if the instruction receiving / returning interfaces are the same, instruction receiving and polling are performed based on that interface, and upon receiving an instruction, polling is paused while instruction parsing and execution are performed to obtain instruction feedback data, which is then sent back to the scheduling device; polling is restarted upon completion of the return. If the instruction receiving / returning interfaces are different, upon receiving an instruction, it is stored in a first buffer queue, and the instructions in the first buffer queue are parsed and executed sequentially, with the instruction feedback data stored in a second buffer queue; and the instruction feedback data in the second buffer queue is then sent back sequentially. This invention improves the protection of register data and increases instruction transmission and reception efficiency.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and in particular to a method for processing instruction information of a charging test device. Background Technology

[0002] Before leaving the factory, charging equipment (such as charging piles) needs to complete a series of functional tests by connecting to charging testing equipment. During operation, the charging testing equipment also connects to a test scheduling device. During testing, the test scheduling device first writes a set of test case configuration parameters to the charging testing equipment. Then, the charging testing equipment performs a test based on these parameters and saves the results. Subsequently, the test scheduling device reads the test results to evaluate whether the current test case passed. Currently, some charging testing equipment uses custom registers to store different test configuration parameters and test results, and provides the test scheduling device with a set of register access instructions to perform read and write operations on each register.

[0003] In practice, we found some technical defects in these charging test devices when customizing registers and parsing register access instructions: 1) They do not differentiate between register types. The test scheduling device can write to any register through register access instructions, but in actual testing, the test scheduling device should only be able to read the test results and not modify them. If the register types are not differentiated and the register access instructions are not managed in detail according to different register types, the existing test results may be destroyed when an incorrect instruction is received; 2) The register access method is singular, only providing address-based access. This access method requires modification of all test case instructions when the register storage space is adjusted; 3) They only provide single-instruction operation mode and do not provide multi-instruction asynchronous operation mode. That is, after receiving a register access instruction, the charging test device will stop receiving the next instruction and will only continue to receive and execute the next register access instruction after the current instruction is completed. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing technologies by providing a method for processing instruction information in a charging test device, an electronic device, and a computer-readable storage medium. This invention subdivides the registers of the charging test device into three categories: read-only registers, type I read-write registers, and type II read-write registers. It restricts the access permissions and processing methods of different register access instructions for different types of registers. Read-only registers can only be read, not written. Type I read-write registers can be read and their data can be updated. Type II read-write registers can be read and their data can be set using AND / OR operations based on given AND / OR mask data. This invention also provides two register access methods in the instruction parameters of register access instructions: an address access method compatible with conventional processing methods and a newly added access method based on register identifiers. Furthermore, this invention provides two instruction receiving and execution processing methods: a single-instruction operation method compatible with conventional processing methods and a newly added multi-instruction asynchronous operation method. This invention offers several advantages. First, it restricts access permissions for register access instructions to protect stored data. Second, it enhances the AND / OR configuration capabilities of registers. Third, it enables data access based on register identifiers, eliminating the need to modify all test case instructions when register storage space is adjusted, thus reducing test modification workload and increasing test flexibility. Fourth, it improves instruction sending and receiving efficiency and test efficiency through the newly added multi-instruction asynchronous operation mode.

[0005] To achieve the above objectives, a first aspect of the present invention provides a method for processing instruction information of a charging test device, the method comprising: The first charging test device pre-configures the device registers locally and generates and saves the corresponding first register list; it also pre-configures a corresponding first instruction receiving interface and a corresponding first instruction sending back interface locally; the first charging test device is connected to a corresponding first test scheduling device; both the first instruction receiving interface and the first instruction sending back interface are connected to the first test scheduling device. And each time a connection with the first test scheduling device is successfully established, it is determined whether the first instruction receiving interface and the first instruction sending back interface configured locally are the same interface; If the first instruction receiving interface and the first instruction sending back interface are the same interface, then that interface is used as the corresponding first instruction sending and receiving interface; and a receiving polling operation is performed on the first register access instruction sent by the first test scheduling device based on the first instruction sending and receiving interface; and each time the first instruction sending and receiving interface receives a first register access instruction, the first register access instruction received at that time is used as the corresponding current register access instruction, and the receiving polling operation of the first instruction sending and receiving interface is paused; and instruction parsing and execution processing is performed based on the current register access instruction and the first register list to obtain the corresponding first instruction feedback data; and the first instruction feedback data is sent back to the first test scheduling device through the first instruction sending and receiving interface; and the receiving polling operation of the first instruction sending and receiving interface for the first test scheduling device is restarted when the sending back is finished. If the first instruction receiving interface and the first instruction sending back interface are not the same interface, then a polling operation is performed on the first register access instruction sent by the first test scheduling device based on the first instruction receiving interface; and each time the first instruction receiving interface receives a first register access instruction, the received first register access instruction is stored in a locally preset first cache queue; when the number of first register access instructions in the first cache queue is not 0, the earliest first register access instruction in the cache queue is extracted as the corresponding current register access instruction, and instruction parsing and execution processing is performed based on the current register access instruction and the first register list to obtain the corresponding first instruction feedback data, and the first instruction feedback data obtained at this time is stored in a locally preset second cache queue, and the current register access instruction is deleted from the first cache queue; when the number of first instruction feedback data in the second cache queue is not 0, the earliest first instruction feedback data in the cache queue is extracted as the corresponding current instruction feedback data, and the current instruction feedback data is sent back to the first test scheduling device through the first instruction sending back interface, and the current instruction feedback data is deleted from the second cache queue when the sending back ends.

[0006] Preferably, the first register list includes multiple first register records; the first register record includes a first register identifier field, a first register address field, and a first register type field; the first register address field includes a register start address and a register end address, and the sum of the difference between the register end address and the register start address plus 1 is consistent with the preset register byte width; the first register type field includes read-only register type, type I read-write register type, and type II read-write register type; The first register access instruction includes a first instruction type and a first instruction parameter; The first instruction type includes read instruction type by address, read instruction type by identifier, type I write instruction type by address, type I write instruction type by identifier, type II write instruction type by address, and type II write instruction type by identifier; When the first instruction type is a read instruction type by address, the corresponding first instruction parameters include a first starting address and a first number of registers; when the first instruction type is a read instruction type by identifier, the corresponding first instruction parameters include a first set of register identifiers; the first number of registers is an integer greater than 0; the first set of register identifiers includes multiple first register identifiers; When the first instruction type is a write instruction type based on address, the corresponding first instruction parameters include a second starting address and a first write data; when the first instruction type is a write instruction type based on identifier, the corresponding first instruction parameters include a second register identifier and the first write data; the first write data is a hexadecimal data with a data length consistent with the byte width of the register. When the first instruction type is a type II write instruction by address, the corresponding first instruction parameters include a third starting address, a first AND mask data, and a first OR mask data; when the first instruction type is a type II write instruction by identifier, the corresponding first instruction parameters include a third register identifier, a first AND mask data, and a first OR mask data; the first AND mask data and the first OR mask data are each a hexadecimal data with a data length consistent with the byte width of the register.

[0007] Preferably, the first charging test device pre-configures the device registers locally and generates and saves the corresponding first register list, specifically including: The first charging test device uses a local contiguous address storage area as the corresponding first storage area; The first storage area is divided into multiple first register storage areas in sequence according to the register byte width; the starting address of the first first register storage area is the starting address of the first storage area, the ending address of the last first register storage area is the ending address of the first storage area, and the starting address of the next first register storage area is the ending address of the previous first register storage area plus 1; the storage space size of all first register storage areas is equal and matches the register byte width; Each of the first register storage areas is assigned a start and end address within the first storage area, which together form a corresponding first register address field. Each of the first register storage areas is also assigned a unique register identifier and a corresponding register type, which together form the corresponding first register identifier field and first register type field. A corresponding first register record is formed by the first register identifier field, the first register address field, and the first register type field for each of the first register storage areas. The register types include read-only register type, type I read-write register type, and type II read-write register type. The first register list is composed of all the first register records obtained and then saved.

[0008] Preferably, when the register type is a read-only register type, the stored data in the corresponding first register storage area can be accessed by the first register access instruction of the first instruction type being read by address or read by identifier, but cannot be accessed by the first register access instruction of the first instruction type being one type of write by address, one type of write by identifier, two types of write by address, and two types of write by identifier. When the register type is a type of read / write register, the stored data in the corresponding first register storage area can be accessed by the first register access instructions of the first instruction type, which are read instruction type by address, read instruction type by identifier, type of write instruction type by address, and type of write instruction type by identifier, but cannot be accessed by the first register access instructions of the first instruction type, which are type of write instruction type by address and type of write instruction type by identifier. When the register type is a type II read / write register, the stored data in the corresponding first register storage area can be accessed by the first register access instruction of the first instruction type being read by address, read by identifier, type II write by address, and type II write by identifier, but cannot be accessed by the first register access instruction of the first instruction type being type I write by address and type I write by identifier.

[0009] Preferably, the step of obtaining the corresponding first instruction feedback data by performing instruction parsing and execution processing based on the current register access instruction and the first register list specifically includes: Extract the corresponding first instruction type and first instruction parameters from the current register access instruction; And identify the first instruction type; If the first instruction type is an address-based read instruction type, then the first read instruction parsing and execution processing is performed based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data; If the first instruction type is a read instruction type by identifier, then the second read instruction parsing and execution processing is performed based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data; If the first instruction type is a type of address-based write instruction, then based on the first instruction parameters and the first register list, the first type of write instruction parsing and execution processing is performed to obtain the corresponding first instruction feedback data; If the first instruction type is a type of write instruction by identifier, then the second type of write instruction parsing and execution processing is performed based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data; If the first instruction type is a type II write instruction by address, then the first type II write instruction parsing and execution processing is performed based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data; If the first instruction type is a type II write instruction by identifier, then the second type II write instruction parsing and execution processing is performed based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data.

[0010] Furthermore, the step of performing first read instruction parsing and execution processing based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data specifically includes: Step 61: Extract the corresponding first starting address and the number of first registers from the first instruction parameters; Step 62: The product of the number of the first registers and the width of the register bytes is taken as the corresponding first data length; and the difference between the sum of the first start address and the first data length minus 1 is taken as the corresponding first end address; Step 63: Identify whether the first start address and the first end address are both storage addresses in the first local storage area; if the first start address and the first end address are both storage addresses in the first storage area, proceed to step 64; if the first start address or the first end address is not a storage address in the first storage area, set the corresponding first feedback data to a preset address error code, and proceed to step 65. Step 64: Extract all byte data from the first start address to the first end address in the first storage area as the corresponding first read data; identify the data byte length of the first read data to obtain the corresponding first read data length; and form the corresponding first feedback data by the first read data length and the first read data. Step 65: Identify whether the obtained first feedback data is an error code; if yes, then the first instruction feedback data is composed of a preset first read instruction error feedback identifier corresponding to the address read instruction type and the first feedback data; if no, then the first instruction feedback data is composed of the first instruction type and the first feedback data.

[0011] Furthermore, the step of performing a second read instruction parsing and execution process based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data specifically includes: Step 71: Extract the corresponding first register identifier set from the first instruction parameters; Step 72: Traverse the first register identifiers in the first register identifier set; during traversal, use the currently traversed first register identifier as the corresponding current register identifier; use the first register record in the first register list whose first register identifier field matches the current register identifier as the corresponding current register record; and identify whether the current register record is empty; if the current register record is empty, stop traversal and set the corresponding second feedback data to a preset identifier error code, and proceed to step 73; if the current register record is not empty, extract all byte data in the first storage area corresponding to the current register record as the corresponding second read data; and at the end of traversal, sequentially concatenate all the obtained second read data to form the corresponding first concatenated data, identify the data byte length of the first concatenated data to obtain the corresponding first concatenated data length, and use the first concatenated data length and the first concatenated data to form the corresponding second feedback data; Step 73: Identify whether the obtained second feedback data is an error code; if yes, the first instruction feedback data is composed of a preset second read instruction error feedback identifier corresponding to the read instruction type and the second feedback data; if no, the first instruction feedback data is composed of the first instruction type and the second feedback data.

[0012] Furthermore, the step of performing first type I write instruction parsing and execution processing based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data specifically includes: Step 81: Extract the corresponding second starting address and the first written data from the first instruction parameters; Step 82: Identify whether the second starting address is a storage address in the first local storage area; if yes, proceed to step 83; if no, set the corresponding third feedback data to a preset address error code and proceed to step 87. Step 83: Identify the length of the first written data bytes to obtain the corresponding first written data length; and identify whether the first written data length matches the register byte width; if yes, proceed to step 84; if no, set the corresponding third feedback data to a preset data length error code, and proceed to step 87. Step 84: Take the first register record in the first register list whose register start address matches the second start address as the corresponding current register record; and identify whether the current register record is empty; if the current register record is not empty, proceed to step 85; if the current register record is empty, set the corresponding third feedback data to the preset address error code, and proceed to step 87. Step 85: Identify whether the first register type field recorded in the current register is a type of read / write register; if the first register type field is a type of read / write register, proceed to step 86; if the first register type field is not a type of read / write register, set the corresponding third feedback data to a preset register type error code, and proceed to step 87. Step 86: The first register storage area corresponding to the current register record in the first storage area is taken as the corresponding current register storage area; the stored data in the register storage area is backed up to obtain the corresponding current backup data; the stored data in the current register storage area is updated to the corresponding first write data; when the data update is completed, all bytes of data in the current register storage area are extracted as the corresponding third read data; and the matching between the third read data and the first write data is identified; if they match, the corresponding third feedback data is set to the first instruction parameter; if they do not match, the stored data in the current register storage area is restored to the corresponding current backup data, and the corresponding third feedback data is set to a preset write failure error code. Step 87: Identify whether the obtained third feedback data is an error code; if yes, then the first instruction feedback data is composed of a preset first type of write instruction error feedback identifier corresponding to a type of address write instruction and the third feedback data; if no, then the first instruction type and the third feedback data are used to compose the first instruction feedback data.

[0013] Furthermore, the step of performing a second type of write instruction parsing and execution based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data specifically includes: Step 91: Extract the corresponding second register identifier and the first write data from the first instruction parameters; Step 92: Identify the length of the first written data bytes to obtain the corresponding first written data length; and identify whether the first written data length matches the register byte width; if the first written data length matches the register byte width, proceed to step 93; if the first written data length does not match the register byte width, set the corresponding fourth feedback data to a preset data length error code, and proceed to step 96. Step 93: Take the first register record in the first register list whose first register identifier field matches the second register identifier as the corresponding current register record; and identify whether the current register record is empty; if the current register record is not empty, proceed to step 94; if the current register record is empty, set the corresponding fourth feedback data to the preset identifier error code, and proceed to step 96. Step 94: Identify whether the first register type field recorded in the current register is a type of read / write register; if the first register type field is a type of read / write register, proceed to step 95; if the first register type field is not a type of read / write register, set the corresponding fourth feedback data to a preset register type error code, and proceed to step 96. Step 95: The first register storage area corresponding to the current register record in the first storage area is taken as the corresponding current register storage area; the stored data in the register storage area is backed up to obtain the corresponding current backup data; the stored data in the current register storage area is updated to the corresponding first write data; when the data update is completed, all bytes of data in the current register storage area are extracted as the corresponding fourth read data; and the matching between the fourth read data and the first write data is identified; if they match, the corresponding fourth feedback data is set to the first instruction parameter; if they do not match, the stored data in the current register storage area is restored to the corresponding current backup data, and the corresponding fourth feedback data is set to a preset write failure error code. Step 96: Identify whether the obtained fourth feedback data is an error code; if yes, then the first instruction feedback data is composed of a preset second type of write instruction error feedback identifier corresponding to a type of write instruction identified by the identifier and the fourth feedback data; if no, then the first instruction type and the fourth feedback data are used to compose the first instruction feedback data.

[0014] Furthermore, the step of performing first type II write instruction parsing and execution processing based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data specifically includes: Step 101: Extract the corresponding third starting address, the first and mask data, and the first or mask data from the first instruction parameters; Step 102: Identify whether the third starting address is a storage address in the first local storage area; if yes, proceed to step 103; if no, set the corresponding fifth feedback data to a preset address error code and proceed to step 107. Step 103: Identify the data byte lengths of the first and mask data and the first or mask data to obtain the corresponding first and mask data lengths and first or mask data lengths; and identify whether the first and mask data lengths and the first or mask data lengths both match the register byte width; if the first and mask data lengths and the first or mask data lengths both match the register byte width, proceed to step 104; if the first and mask data lengths or the first or mask data lengths do not match the register byte width, set the corresponding fifth feedback data to a preset data length error code, and proceed to step 107; Step 104: Take the first register record in the first register list whose register start address matches the third start address as the corresponding current register record; and identify whether the current register record is empty; if the current register record is not empty, proceed to step 105; if the current register record is empty, set the corresponding fifth feedback data to a preset address error code, and proceed to step 107. Step 105: Identify whether the first register type field recorded in the current register is a type II read / write register; if the first register type field is a type II read / write register, proceed to step 106; if the first register type field is not a type II read / write register, set the corresponding fifth feedback data to a preset register type error code, and proceed to step 107. Step 106: The first register storage area corresponding to the current register record in the first storage area is taken as the corresponding current register storage area; the stored data in the register storage area is backed up to obtain the corresponding current backup data; the stored data in the current register storage area is updated according to the first and mask data and the first or mask data; when the data update is complete, all bytes of data in the current register storage area are extracted as the corresponding current read data; the current read data is verified according to the current backup data, the first and mask data, and the first or mask data to obtain the corresponding current verification result; the current verification result is checked to determine if the verification is successful; if yes, the corresponding fifth feedback data is set to the first instruction parameter; if no, the stored data in the current register storage area is restored to the corresponding current backup data, and the corresponding fifth feedback data is set to a preset write failure error code. Step 107: Identify whether the obtained fifth feedback data is an error code; if yes, then the first instruction feedback data is composed of the preset first type II write instruction error feedback identifier corresponding to the type II address write instruction and the fifth feedback data; if no, then the first instruction type and the fifth feedback data are used to compose the first instruction feedback data.

[0015] Furthermore, the step of performing a second type II write instruction parsing and execution process based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data specifically includes: Step 111: Extract the corresponding third register identifier, the first and mask data, and the first or mask data from the first instruction parameters; Step 112: Identify the data byte lengths of the first and mask data and the first or mask data to obtain the corresponding second and mask data lengths; and identify whether the second and mask data lengths and the second or mask data lengths both match the register byte width; if the second and mask data lengths and the second or mask data lengths both match the register byte width, proceed to step 113; if the second and mask data lengths or the second or mask data lengths do not match the register byte width, set the corresponding sixth feedback data to a preset data length error code, and proceed to step 116. Step 113: Take the first register record in the first register list whose first register identifier field matches the third register identifier as the corresponding current register record; and identify whether the current register record is empty; if the current register record is not empty, proceed to step 114; if the current register record is empty, set the corresponding sixth feedback data to a preset identifier error code, and proceed to step 116. Step 114: Identify whether the first register type field recorded in the current register is a type II read / write register; if the first register type field is a type II read / write register, proceed to step 115; if the first register type field is not a type II read / write register, set the corresponding sixth feedback data to a preset register type error code, and proceed to step 116. Step 115: The first register storage area corresponding to the current register record in the first storage area is taken as the corresponding current register storage area; the stored data in the register storage area is backed up to obtain the corresponding current backup data; the stored data in the current register storage area is updated according to the first and mask data and the first or mask data; when the data update is complete, all bytes of data in the current register storage area are extracted as the corresponding current read data; the current read data is verified according to the current backup data, the first and mask data, and the first or mask data to obtain the corresponding current verification result; the current verification result is checked to determine if the verification is successful; if yes, the corresponding sixth feedback data is set to the first instruction parameter; if no, the stored data in the current register storage area is restored to the corresponding current backup data, and the corresponding sixth feedback data is set to a preset write failure error code. Step 116: Identify whether the obtained sixth feedback data is an error code; if yes, the first instruction feedback data is composed of the preset second type of write instruction error feedback identifier corresponding to the second type of write instruction type and the sixth feedback data; if no, the first instruction type and the sixth feedback data are used to compose the first instruction feedback data.

[0016] Furthermore, updating the stored data in the current register storage area based on the first and mask data and the first or mask data specifically includes: Extract the stored data from the current register storage area as the corresponding first original data; invert the first and mask data to obtain the corresponding first and mask inverted data; substitute the first and mask data, the first and mask data, the first and mask inverted data, and the first original data into the preset transformation formula F to calculate the corresponding first updated data; and update the stored data in the current register storage area to the corresponding first updated data.

[0017] Furthermore, the step of verifying the currently read data based on the current backup data, the first or mask data, and the first or mask data to obtain the corresponding current verification result specifically includes: Step 131: Take the current backup data as the corresponding first original data; and invert the first and mask data to obtain the corresponding first and mask inverted data; and substitute the first and mask data, the first and mask data, the first and mask data, the first and mask inverted data, and the first original data into the preset transformation formula F to calculate the corresponding first updated data; Step 132: Identify whether the first updated data matches the currently read data; if they match, set the corresponding current verification result to verification success; if they do not match, set the corresponding current verification result to verification failure.

[0018] Furthermore, The transformation formula F is: , AND and OR are bitwise AND and bitwise OR operators, respectively. D am For the first and mask data, D om For the first or mask data, The first is the inverted data of the mask. D old The first original data, D newThis refers to the first updated data.

[0019] A second aspect of the present invention provides an electronic device, including: a memory, a processor, and a transceiver; The processor is configured to be coupled to the memory, read and execute instructions in the memory to implement the method described in the first aspect above; The transceiver is coupled to the processor, and the processor controls the transceiver to send and receive messages.

[0020] A third aspect of the present invention provides a computer-readable storage medium storing computer instructions that, when executed by a computer, cause the computer to perform the method described in the first aspect.

[0021] This invention provides a method for processing instruction information in a charging test device, an electronic device, and a computer-readable storage medium. As described above, this invention categorizes the registers of the charging test device into three types: read-only registers, type I read-write registers, and type II read-write registers. It restricts the access permissions and processing methods of different register access instructions for different types of registers. Read-only registers can only be read, not written. Type I read-write registers can be read and their data can be updated. Type II read-write registers can be read and their data can be set using AND / OR operations based on given AND / OR mask data. This invention also provides two register access methods in the instruction parameters of the register access instructions: an address access method compatible with conventional processing methods and a newly added access method based on register identifiers. Furthermore, this invention provides two instruction receiving and execution processing methods: a single-instruction operation method compatible with conventional processing methods and a newly added multi-instruction asynchronous operation method. Through the embodiments of the present invention, on the one hand, access permissions for register access instructions can be restricted, thereby improving the device's ability to protect test data; on the other hand, the AND / OR configuration capability of registers can be increased, improving the flexibility of register configuration; furthermore, data access can be performed based on register identifiers, and when the register storage space is adjusted, it is not necessary to modify the instructions of all test cases, thereby reducing the workload of test modification and improving test flexibility; furthermore, the newly added multi-instruction asynchronous operation mode can improve instruction sending and receiving efficiency and test efficiency. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of an instruction information processing method for a charging test device provided in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the structure of an electronic device provided in Embodiment 2 of the present invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0024] Embodiment 1 of the present invention provides a method for processing instruction information of a charging test device, as follows: Figure 1 The schematic diagram of the instruction information processing method for a charging test device provided in Embodiment 1 of the present invention mainly includes the following steps: Step 1: The first charging test device pre-configures the device registers locally and generates and saves the corresponding first register list; and pre-configures a corresponding first instruction receiving interface and a corresponding first instruction sending back interface locally. The first charging test device is connected to a corresponding first test scheduling device; the first instruction receiving interface and the first instruction sending back interface are both connected to the first test scheduling device. Specifically, this includes: Step 11, pre-configuring the device registers locally and generating and saving the corresponding first register list; The first register list includes multiple first register records; each first register record includes a first register identifier field, a first register address field, and a first register type field; the first register address field includes the register start address and the register end address, and the sum of the difference between the register end address and the register start address plus 1 is consistent with the preset register byte width; the first register type field includes read-only register type, type I read-write register type, and type II read-write register type. Specifically, this includes: Step 111, using a local contiguous address storage area of ​​the device as the corresponding first storage area; Step 112, and divide the first storage area into multiple first register storage areas in sequence according to the register byte width; In this first storage area, the starting address of the first first register storage area is the starting address of the first storage area, the ending address of the last first register storage area is the ending address of the first storage area, and the starting address of the next first register storage area is the ending address of the previous first register storage area plus 1; the storage space size of all first register storage areas is equal and matches the width of the register byte; Step 113: The start and end addresses of each first register storage area in the first storage area are used as the corresponding register start address and register end address to form a corresponding first register address field; and a unique register identifier and a corresponding register type are assigned to each first register storage area as the corresponding first register identifier field and first register type field; and a corresponding first register record is formed by the first register identifier field, first register address field and first register type field corresponding to each first register storage area. Among them, register types include read-only register type, type I read-write register type and type II read-write register type; It should be noted that when the register type is a read-only register type, the stored data in the corresponding first register storage area can be accessed by first register access instructions with the first instruction type of read by address or read by identifier, but cannot be accessed by first register access instructions with the first instruction type of type I write by address, type I write by identifier, type II write by address, and type II write by identifier. When the register type is a type 1 read / write register, the data stored in the corresponding first register storage area can be accessed by first register access instructions of the first instruction type, such as read instruction type by address, read instruction type by identifier, type 1 write instruction type by address, and type 1 write instruction type by identifier, but cannot be accessed by first register access instructions of the first instruction type, such as type 2 write instruction type by address and type 2 write instruction type by identifier. When the register type is a type II read / write register, the data stored in the corresponding first register storage area can be accessed by first register access instructions with first instruction types of address read instruction type, identifier read instruction type, type II address write instruction type, and type II identifier write instruction type, but cannot be accessed by first register access instructions with first instruction types of type I address write instruction type and type I identifier write instruction type. Step 114, and then the corresponding first register list is composed of all the obtained first register records and saved; Step 12, and pre-configure a corresponding first instruction receiving interface and a corresponding first instruction sending back interface locally; Here, the first instruction receiving interface and the first instruction sending back interface can be the same or different; they can be software communication interfaces, hardware communication interfaces, or communication processing interfaces composed of one or more software and hardware modules.

[0025] Step 2: Each time a connection with the first test scheduling device is successfully established, it is determined whether the locally configured first instruction receiving interface and first instruction sending back interface are the same interface.

[0026] Step 3: If the first instruction receiving interface and the first instruction sending back interface are the same interface, then this interface is used as the corresponding first instruction receiving and sending interface; and a receiving and polling operation is performed on the first register access instruction sent by the first test scheduling device based on the first instruction receiving and sending interface; and each time the first instruction receiving and sending interface receives a first register access instruction, the received first register access instruction is used as the corresponding current register access instruction, and the receiving and polling operation of the first instruction receiving and sending interface is paused; and instruction parsing and execution processing is performed based on the current register access instruction and the first register list to obtain the corresponding first instruction feedback data; and the first instruction feedback data is sent back to the first test scheduling device through the first instruction receiving and sending interface; and the receiving and polling operation of the first instruction receiving and sending interface for the first test scheduling device is restarted when the sending back is finished.

[0027] Step 4: If the first instruction receiving interface and the first instruction sending back interface are not the same interface, then a polling operation is performed on the first register access instruction sent by the first test scheduling device based on the first instruction receiving interface; and each time the first instruction receiving interface receives a first register access instruction, the received first register access instruction is stored in a locally preset first cache queue; when the number of first register access instructions in the first cache queue is not 0, the earliest first register access instruction in the cache queue is extracted as the corresponding current register access instruction, and instruction parsing and execution processing is performed based on the current register access instruction and the first register list to obtain the corresponding first instruction feedback data, and the obtained first instruction feedback data is stored in a locally preset second cache queue, and the current register access instruction is deleted from the first cache queue; when the number of first instruction feedback data in the second cache queue is not 0, the earliest first instruction feedback data in the cache queue is extracted as the corresponding current instruction feedback data, and the current instruction feedback data is sent back to the first test scheduling device through the first instruction sending back interface, and the current instruction feedback data is deleted from the second cache queue when the sending back ends.

[0028] The instruction format of the first register access instruction mentioned in steps 3 and 4 above is as follows: The first register access instruction includes a first instruction type and a first instruction parameter; The first instruction type includes read instruction type by address, read instruction type by identifier, type I write instruction type by address, type I write instruction type by identifier, type II write instruction type by address, and type II write instruction type by identifier; When the first instruction type is a read instruction type by address, the corresponding first instruction parameters include the first starting address and the number of first registers; when the first instruction type is a read instruction type by identifier, the corresponding first instruction parameters include the set of first register identifiers; the number of first registers is an integer greater than 0; the set of first register identifiers includes multiple first register identifiers; When the first instruction type is a write instruction type based on address, the corresponding first instruction parameters include the second starting address and the first write data; when the first instruction type is a write instruction type based on identifier, the corresponding first instruction parameters include the second register identifier and the first write data; the first write data is a hexadecimal data with a data length consistent with the width of the register byte; When the first instruction type is a type II write instruction by address, the corresponding first instruction parameters include the third starting address, the first AND mask data, and the first OR mask data; when the first instruction type is a type II write instruction by identifier, the corresponding first instruction parameters include the third register identifier, the first AND mask data, and the first OR mask data; the first AND mask data and the first OR mask data are each a hexadecimal data with a data length consistent with the width of the register byte.

[0029] The processing steps mentioned in steps 3 and 4 above, which involve parsing and executing the instruction based on the current register access instruction and the first register list to obtain the corresponding first instruction feedback data, specifically include: Step A1: Extract the corresponding first instruction type and first instruction parameters from the current register access instruction; Step A2, and identify the first instruction type; Step A3: If the first instruction type is an address-based read instruction type, then the first read instruction is parsed and executed based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data; Step A4: If the first instruction type is a read instruction type by identifier, then the second read instruction parsing and execution processing is performed based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data; Step A5: If the first instruction type is a type of address-based write instruction, then based on the first instruction parameters and the first register list, perform first type of write instruction parsing and execution to obtain the corresponding first instruction feedback data. Step A6: If the first instruction type is a type of write instruction by identifier, then the second type of write instruction parsing and execution processing is performed based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data. Step A7: If the first instruction type is a type II write instruction by address, then the first type II write instruction parsing and execution processing is performed based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data; Step A8: If the first instruction type is a type II write instruction by identifier, then the second type II write instruction parsing and execution processing is performed based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data.

[0030] Specifically, step A3, which involves parsing and executing the first read instruction based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data, includes: Step A3-1: Extract the corresponding first starting address and the number of first registers from the first instruction parameters; Step A3-2: The product of the number of first registers and the width of the register bytes is taken as the corresponding first data length; and the difference between the sum of the first start address and the first data length minus 1 is taken as the corresponding first end address; Step A3-3: Identify whether the first start address and the first end address are both storage addresses in the local first storage area; if the first start address and the first end address are both storage addresses in the first storage area, proceed to step A3-4; if the first start address or the first end address is not a storage address in the first storage area, set the corresponding first feedback data to the preset address error code, and proceed to step A3-5. Step A3-4: Extract all bytes of data from the first start address to the first end address in the first storage area as the corresponding first read data; identify the length of the data bytes of the first read data to obtain the corresponding first read data length; and combine the first read data length and the first read data to form the corresponding first feedback data. Step A3-5: Identify whether the obtained first feedback data is an error code; if yes, the first instruction feedback data is composed of the preset first read instruction error feedback identifier corresponding to the address read instruction type and the first feedback data; if no, the first instruction feedback data is composed of the first instruction type and the first feedback data.

[0031] Step A4, which involves parsing and executing the second read instruction based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data, specifically includes: Step A4-1: Extract the corresponding first register identifier set from the first instruction parameters; Step A4-2: Iterate through the first register identifiers in the first register identifier set; during the iteration, use the currently iterated first register identifier as the corresponding current register identifier; use the first register record in the first register list whose first register identifier field matches the current register identifier as the corresponding current register record; and identify whether the current register record is empty; if the current register record is empty, stop the iteration and set the corresponding second feedback data to the preset identifier error code, and proceed to step A4-3; if the current register record is not empty, extract all byte data in the first storage area corresponding to the current register record as the corresponding second read data; at the end of the iteration, concatenate all the obtained second read data in order to form the corresponding first concatenated data, identify the length of the first concatenated data bytes to obtain the corresponding first concatenated data length, and use the first concatenated data length and the first concatenated data to form the corresponding second feedback data; Step A4-3: Identify whether the obtained second feedback data is an error code; if yes, the corresponding first instruction feedback data is composed of the preset second read instruction error feedback identifier and the second feedback data corresponding to the read instruction type; if no, the corresponding first instruction feedback data is composed of the first instruction type and the second feedback data.

[0032] Step A5, which involves parsing and executing the first type of write instruction based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data, specifically includes: Step A5-1: Extract the corresponding second starting address and first write data from the first instruction parameters; Step A5-2: Identify whether the second starting address is a storage address in the local first storage area; if yes, proceed to step A5-3; if no, set the corresponding third feedback data to the preset address error code and proceed to step A5-7. Step A5-3: Identify the length of the first written data byte to obtain the corresponding first written data length; and identify whether the first written data length matches the register byte width; if yes, proceed to step A5-4; if no, set the corresponding third feedback data to the preset data length error code, and proceed to step A5-7. Step A5-4: Take the first register record whose register start address in the first register address field of the first register list matches the second start address as the corresponding current register record; and identify whether the current register record is empty; if the current register record is not empty, go to step A5-5; if the current register record is empty, set the corresponding third feedback data to the preset address error code, and go to step A5-7. Step A5-5: Identify whether the first register type field of the current register record is a type of read / write register; if the first register type field is a type of read / write register, proceed to step A5-6; if the first register type field is not a type of read / write register, set the corresponding third feedback data to the preset register type error code and proceed to step A5-7. Steps A5-6: The first register storage area corresponding to the current register record in the first storage area is taken as the corresponding current register storage area; the stored data in the register storage area is backed up to obtain the corresponding current backup data; the stored data in the current register storage area is updated to the corresponding first write data; and when the data update is complete, all bytes of data in the current register storage area are extracted as the corresponding third read data; the third read data and the first write data are checked for matching; if they match, the corresponding third feedback data is set as the first instruction parameter; if they do not match, the stored data in the current register storage area is restored to the corresponding current backup data, and the corresponding third feedback data is set to the preset write failure error code. Step A5-7: Identify whether the obtained third feedback data is an error code; if yes, the corresponding first instruction feedback data is composed of the preset first type of write instruction error feedback identifier corresponding to a type of address write instruction and the third feedback data; if no, the corresponding first instruction feedback data is composed of the first instruction type and the third feedback data.

[0033] Step A6, which involves parsing and executing a second type of write instruction based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data, specifically includes: Step A6-1: Extract the corresponding second register identifier and the first write data from the first instruction parameters; Step A6-2: Identify the length of the first written data byte to obtain the corresponding first written data length; and identify whether the first written data length matches the register byte width; if the first written data length matches the register byte width, proceed to step A6-3; if the first written data length does not match the register byte width, set the corresponding fourth feedback data to the preset data length error code, and proceed to step A6-6. Step A6-3: Take the first register record in the first register list whose first register identifier field matches the second register identifier as the corresponding current register record; and identify whether the current register record is empty; if the current register record is not empty, proceed to step A6-4; if the current register record is empty, set the corresponding fourth feedback data to the preset identifier error code, and proceed to step A6-6. Step A6-4: Identify whether the first register type field of the current register record is a type of read / write register; if the first register type field is a type of read / write register, proceed to step A6-5; if the first register type field is not a type of read / write register, set the corresponding fourth feedback data to the preset register type error code and proceed to step A6-6. Step A6-5: The first register storage area corresponding to the current register record in the first storage area is taken as the corresponding current register storage area; the stored data in the register storage area is backed up to obtain the corresponding current backup data; the stored data in the current register storage area is updated to the corresponding first write data; when the data update is complete, all bytes of data in the current register storage area are extracted as the corresponding fourth read data; and the matching between the fourth read data and the first write data is identified; if they match, the corresponding fourth feedback data is set as the first instruction parameter; if they do not match, the stored data in the current register storage area is restored to the corresponding current backup data, and the corresponding fourth feedback data is set to the preset write failure error code. Step A6-6: Identify whether the obtained fourth feedback data is an error code; if yes, then the corresponding first instruction feedback data is composed of the preset second type of write instruction error feedback identifier corresponding to a type of write instruction by identifier and the fourth feedback data; if no, then the corresponding first instruction feedback data is composed of the first instruction type and the fourth feedback data.

[0034] Step A7, which involves parsing and executing the first type II write instruction based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data, specifically includes: Step A7-1: Extract the corresponding third starting address, first AND mask data, and first OR mask data from the first instruction parameters; Step A7-2: Identify whether the third starting address is a storage address in the local first storage area; if yes, proceed to step A7-3; if no, set the corresponding fifth feedback data to the preset address error code and proceed to step A7-7. Step A7-3: Identify the data byte lengths of the first and mask data and the first or mask data to obtain the corresponding first and mask data lengths and first or mask data lengths; and identify whether the first and mask data lengths and first or mask data lengths both match the register byte width; if the first and mask data lengths and first or mask data lengths both match the register byte width, proceed to step A7-4; if the first and mask data lengths or first or mask data lengths do not match the register byte width, set the corresponding fifth feedback data to the preset data length error code, and proceed to step A7-7; Step A7-4: Take the first register record whose register start address in the first register address field of the first register list matches the third start address as the corresponding current register record; and identify whether the current register record is empty; if the current register record is not empty, go to step A7-5; if the current register record is empty, set the corresponding fifth feedback data to the preset address error code, and go to step A7-7. Step A7-5: Identify whether the first register type field of the current register record is a type II read / write register; if the first register type field is a type II read / write register, proceed to step A7-6; if the first register type field is not a type II read / write register, set the corresponding fifth feedback data to the preset register type error code and proceed to step A7-7. Step A7-6: The first register storage area corresponding to the current register record in the first storage area is taken as the corresponding current register storage area; the stored data in the register storage area is backed up to obtain the corresponding current backup data; the stored data in the current register storage area is updated according to the first AND mask data and the first OR mask data; when the data update is complete, all bytes of data in the current register storage area are extracted as the corresponding current read data; the current read data is verified according to the current backup data, the first AND mask data, and the first OR mask data to obtain the corresponding current verification result; the verification result is checked to see if it is successful; if yes, the corresponding fifth feedback data is set as the first instruction parameter; if no, the stored data in the current register storage area is restored to the corresponding current backup data, and the corresponding fifth feedback data is set to the preset write failure error code. Step A7-7: Identify whether the obtained fifth feedback data is an error code; if yes, the first instruction feedback data is composed of the preset first type II write instruction error feedback identifier corresponding to the type II address write instruction and the fifth feedback data; if no, the first instruction type and the fifth feedback data are used to compose the corresponding first instruction feedback data.

[0035] Step A8, which involves parsing and executing a second type II write instruction based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data, specifically includes: Step A8-1: Extract the corresponding third register identifier, first AND mask data, and first OR mask data from the first instruction parameters; Step A8-2: Identify the data byte lengths of the first and mask data and the first or mask data to obtain the corresponding second and mask data lengths and second or mask data lengths; and identify whether the second and mask data lengths and second or mask data lengths both match the register byte width; if the second and mask data lengths and second or mask data lengths both match the register byte width, proceed to step A8-3; if the second and mask data lengths or second or mask data lengths do not match the register byte width, set the corresponding sixth feedback data to the preset data length error code, and proceed to step A8-6; Step A8-3: Take the first register record in the first register list that matches the first register identifier field with the third register identifier as the corresponding current register record; and identify whether the current register record is empty; if the current register record is not empty, proceed to step A8-4; if the current register record is empty, set the corresponding sixth feedback data to the preset identifier error code, and proceed to step A8-6. Step A8-4: Identify whether the first register type field of the current register record is a type II read / write register; if the first register type field is a type II read / write register, proceed to step A8-5; if the first register type field is not a type II read / write register, set the corresponding sixth feedback data to the preset register type error code and proceed to step A8-6. Step A8-5: The first register storage area corresponding to the current register record in the first storage area is taken as the corresponding current register storage area; the stored data in the register storage area is backed up to obtain the corresponding current backup data; the stored data in the current register storage area is updated according to the first AND mask data and the first OR mask data; when the data update is complete, all bytes of data in the current register storage area are extracted as the corresponding current read data; the current read data is verified according to the current backup data, the first AND mask data, and the first OR mask data to obtain the corresponding current verification result; the verification result is checked to see if it is successful; if yes, the corresponding sixth feedback data is set as the first instruction parameter; if no, the stored data in the current register storage area is restored to the corresponding current backup data, and the corresponding sixth feedback data is set to the preset write failure error code. Step A8-6: Identify whether the obtained sixth feedback data is an error code; if yes, the corresponding first instruction feedback data is composed of the preset second type write instruction error feedback identifier corresponding to the second type write instruction type and the sixth feedback data; if no, the corresponding first instruction feedback data is composed of the first instruction type and the sixth feedback data.

[0036] Furthermore, updating the stored data in the current register storage area based on the first and mask data and the first or mask data in steps A7-6 and A8-5 specifically includes: Step B1: Extract the stored data from the current register storage area as the corresponding first original data; Step B2, and invert the first and mask data to obtain the corresponding inverted first and mask data; Step B3, and substitute the first data with the mask, the first data with the mask, the first data with the mask inverted, and the first original data into the preset transformation formula F to calculate the corresponding first updated data; in, , AND and OR are bitwise AND and bitwise OR operators, respectively. D am For the first and mask data, D om For the first or mask data, The first is the inverted data of the mask. D old This is the first set of raw data. D new This is the first updated data; Step B4, and update the stored data in the current register storage area to the corresponding first updated data.

[0037] In addition, the verification of the currently read data based on the current backup data, the first and mask data, and the first or mask data in steps A7-6 and A8-5 above to obtain the corresponding current verification result specifically includes: Step C1: Use the current backup data as the corresponding first original data; invert the first and mask data to obtain the corresponding first and mask inverted data; and substitute the first and mask data, the first or mask data, the first and mask inverted data, and the first original data into the preset transformation formula F to calculate the corresponding first updated data. Here, the calculation method for the first updated data in the current step is the same as the calculation method for the first updated data in step B3 above; Step C2: Identify whether the data after the first update matches the currently read data; if they match, set the corresponding current verification result to verification success; if they do not match, set the corresponding current verification result to verification failure.

[0038] Figure 2This is a schematic diagram of an electronic device provided in Embodiment 2 of the present invention. This electronic device can be the aforementioned terminal device or server, or it can be a terminal device or server connected to the aforementioned terminal device or server that implements the method of the embodiments of the present invention. Figure 2 As shown, the electronic device may include: a processor 301 (e.g., CPU), a memory 302, and a transceiver 303; the transceiver 303 is coupled to the processor 301, and the processor 301 controls the transmission and reception operations of the transceiver 303. The memory 302 may store various instructions for performing various processing functions and implementing the processing steps described in the foregoing method embodiments. Preferably, the electronic device involved in the embodiments of the present invention further includes: a power supply 304, a system bus 305, and a communication port 306. The system bus 305 is used to realize communication connections between components. The communication port 306 is used for communication between the electronic device and other peripherals.

[0039] exist Figure 2 The system bus 305 mentioned can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This system bus can be divided into address bus, data bus, control bus, etc. For ease of representation, it is represented by only one thick line in the figure, but this does not indicate that there is only one bus or one type of bus. The communication interface is used to enable communication between the database access device and other devices (e.g., clients, read-write libraries, and read-only libraries). Memory may include Random Access Memory (RAM) and may also include Non-Volatile Memory, such as at least one disk storage device.

[0040] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), graphics processing units (GPUs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0041] It should be noted that the embodiments of the present invention also provide a computer-readable storage medium storing instructions that, when run on a computer, cause the computer to perform the methods and processes provided in the above embodiments.

[0042] This invention also provides a chip for executing instructions, which is used to perform the processing steps described in the foregoing method embodiments.

[0043] This invention provides a method for processing instruction information of a charging test device, an electronic device, and a computer-readable storage medium. As described above, this invention categorizes the registers of the charging test device into three types: read-only registers, type I read-write registers, and type II read-write registers. It restricts the access permissions and processing methods of different register access instructions for different types of registers. Read-only registers can only be read, not written. Type I read-write registers can be read and their data can be updated. Type II read-write registers can be read and their data can be set using AND / OR operations based on given AND / OR mask data. This invention also provides two register access methods in the instruction parameters of the register access instructions: an address access method compatible with conventional processing methods and a newly added access method based on register identifiers. Furthermore, this invention provides two instruction receiving and execution processing methods: a single-instruction operation method compatible with conventional processing methods and a newly added multi-instruction asynchronous operation method. Through the embodiments of the present invention, on the one hand, access permissions for register access instructions can be restricted, thereby improving the device's ability to protect test data; on the other hand, the AND / OR configuration capability of registers can be increased, improving the flexibility of register configuration; furthermore, data access can be performed based on register identifiers, and when the register storage space is adjusted, it is not necessary to modify the instructions of all test cases, thereby reducing the workload of test modification and improving test flexibility; furthermore, the newly added multi-instruction asynchronous operation mode can improve instruction sending and receiving efficiency and test efficiency.

[0044] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0045] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented in hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0046] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for processing instruction information of a charging test device, characterized in that, The method includes: The first charging test device pre-configures the device registers locally and generates and saves the corresponding first register list; it also pre-configures a corresponding first instruction receiving interface and a corresponding first instruction sending back interface locally; the first charging test device is connected to a corresponding first test scheduling device; both the first instruction receiving interface and the first instruction sending back interface are connected to the first test scheduling device. And each time a connection with the first test scheduling device is successfully established, it is determined whether the first instruction receiving interface and the first instruction sending back interface configured locally are the same interface; If the first instruction receiving interface and the first instruction sending back interface are the same interface, then that interface is used as the corresponding first instruction sending and receiving interface; and a receiving polling operation is performed on the first register access instruction sent by the first test scheduling device based on the first instruction sending and receiving interface; and each time the first instruction sending and receiving interface receives a first register access instruction, the first register access instruction received at that time is used as the corresponding current register access instruction, and the receiving polling operation of the first instruction sending and receiving interface is paused; and instruction parsing and execution processing is performed based on the current register access instruction and the first register list to obtain the corresponding first instruction feedback data; and the first instruction feedback data is sent back to the first test scheduling device through the first instruction sending and receiving interface; and the receiving polling operation of the first instruction sending and receiving interface for the first test scheduling device is restarted when the sending back is finished. If the first instruction receiving interface and the first instruction sending back interface are not the same interface, then a polling operation is performed on the first register access instruction sent by the first test scheduling device based on the first instruction receiving interface; and each time the first instruction receiving interface receives a first register access instruction, the received first register access instruction is stored in a locally preset first cache queue; when the number of first register access instructions in the first cache queue is not 0, the earliest first register access instruction in the cache queue is extracted as the corresponding current register access instruction, and instruction parsing and execution processing is performed based on the current register access instruction and the first register list to obtain the corresponding first instruction feedback data, and the first instruction feedback data obtained at this time is stored in a locally preset second cache queue, and the current register access instruction is deleted from the first cache queue; when the number of first instruction feedback data in the second cache queue is not 0, the earliest first instruction feedback data in the cache queue is extracted as the corresponding current instruction feedback data, and the current instruction feedback data is sent back to the first test scheduling device through the first instruction sending back interface, and the current instruction feedback data is deleted from the second cache queue when the sending back ends.

2. The instruction information processing method for the charging test equipment according to claim 1, characterized in that, The first register list includes multiple first register records; each first register record includes a first register identifier field, a first register address field, and a first register type field; the first register address field includes a register start address and a register end address, wherein the sum of the difference between the register end address and the register start address plus 1 is consistent with the preset register byte width; the first register type field includes read-only register type, type I read-write register type, and type II read-write register type. The first register access instruction includes a first instruction type and a first instruction parameter; The first instruction type includes read instruction type by address, read instruction type by identifier, type I write instruction type by address, type I write instruction type by identifier, type II write instruction type by address, and type II write instruction type by identifier; When the first instruction type is a read instruction type by address, the corresponding first instruction parameters include a first starting address and a first number of registers; when the first instruction type is a read instruction type by identifier, the corresponding first instruction parameters include a first set of register identifiers; the first number of registers is an integer greater than 0; the first set of register identifiers includes multiple first register identifiers; When the first instruction type is a write instruction type based on address, the corresponding first instruction parameters include a second starting address and a first write data; when the first instruction type is a write instruction type based on identifier, the corresponding first instruction parameters include a second register identifier and the first write data; the first write data is a hexadecimal data with a data length consistent with the byte width of the register. When the first instruction type is a type II write instruction by address, the corresponding first instruction parameters include a third starting address, a first AND mask data, and a first OR mask data; when the first instruction type is a type II write instruction by identifier, the corresponding first instruction parameters include a third register identifier, a first AND mask data, and a first OR mask data; the first AND mask data and the first OR mask data are each a hexadecimal data with a data length consistent with the byte width of the register.

3. The instruction information processing method for the charging test equipment according to claim 2, characterized in that, The first charging test device pre-configures its device registers locally, generates and saves the corresponding first register list, specifically including: The first charging test device uses a local contiguous address storage area as the corresponding first storage area; The first storage area is divided into multiple first register storage areas in sequence according to the register byte width; the starting address of the first first register storage area is the starting address of the first storage area, the ending address of the last first register storage area is the ending address of the first storage area, and the starting address of the next first register storage area is the ending address of the previous first register storage area plus 1; the storage space size of all first register storage areas is equal and matches the register byte width; Each of the first register storage areas is assigned a start and end address within the first storage area, which together form a corresponding first register address field. Each of the first register storage areas is also assigned a unique register identifier and a corresponding register type, which together form the corresponding first register identifier field and first register type field. A corresponding first register record is formed by the first register identifier field, the first register address field, and the first register type field for each of the first register storage areas. The register types include read-only register type, type I read-write register type, and type II read-write register type. The first register list is composed of all the first register records obtained and then saved.

4. The instruction information processing method for the charging test equipment according to claim 3, characterized in that, When the register type is a read-only register type, the stored data in the corresponding first register storage area can be accessed by the first register access instruction of the first instruction type being read by address or read by identifier, but cannot be accessed by the first register access instruction of the first instruction type being one type of write by address, one type of write by identifier, two types of write by address, and two types of write by identifier. When the register type is a type of read / write register, the stored data in the corresponding first register storage area can be accessed by the first register access instructions of the first instruction type, which are read instruction type by address, read instruction type by identifier, type of write instruction type by address, and type of write instruction type by identifier, but cannot be accessed by the first register access instructions of the first instruction type, which are type of write instruction type by address and type of write instruction type by identifier. When the register type is a type II read / write register, the stored data in the corresponding first register storage area can be accessed by the first register access instruction of the first instruction type being read by address, read by identifier, type II write by address, and type II write by identifier, but cannot be accessed by the first register access instruction of the first instruction type being type I write by address and type I write by identifier.

5. The instruction information processing method for the charging test equipment according to claim 3, characterized in that, The step of parsing and executing the instruction based on the current register access instruction and the first register list to obtain the corresponding first instruction feedback data specifically includes: Extract the corresponding first instruction type and first instruction parameters from the current register access instruction; And identify the first instruction type; If the first instruction type is an address-based read instruction type, then the first read instruction parsing and execution processing is performed based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data; If the first instruction type is a read instruction type by identifier, then the second read instruction parsing and execution processing is performed based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data; If the first instruction type is a type of address-based write instruction, then based on the first instruction parameters and the first register list, the first type of write instruction parsing and execution processing is performed to obtain the corresponding first instruction feedback data; If the first instruction type is a type of write instruction by identifier, then the second type of write instruction parsing and execution processing is performed based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data; If the first instruction type is a type II write instruction by address, then the first type II write instruction parsing and execution processing is performed based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data; If the first instruction type is a type II write instruction by identifier, then the second type II write instruction parsing and execution processing is performed based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data.

6. The instruction information processing method for the charging test equipment according to claim 5, characterized in that, The process of parsing and executing the first read instruction based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data specifically includes: Step 61: Extract the corresponding first starting address and the number of first registers from the first instruction parameters; Step 62: The product of the number of the first registers and the width of the register bytes is taken as the corresponding first data length; and the difference between the sum of the first start address and the first data length minus 1 is taken as the corresponding first end address; Step 63: Identify whether the first start address and the first end address are both storage addresses in the first local storage area; if the first start address and the first end address are both storage addresses in the first storage area, proceed to step 64; if the first start address or the first end address is not a storage address in the first storage area, set the corresponding first feedback data to a preset address error code, and proceed to step 65. Step 64: Extract all byte data from the first start address to the first end address in the first storage area as the corresponding first read data; identify the data byte length of the first read data to obtain the corresponding first read data length; and form the corresponding first feedback data by the first read data length and the first read data. Step 65: Identify whether the obtained first feedback data is an error code; if yes, then the first instruction feedback data is composed of a preset first read instruction error feedback identifier corresponding to the address read instruction type and the first feedback data; if no, then the first instruction feedback data is composed of the first instruction type and the first feedback data.

7. The instruction information processing method for the charging test equipment according to claim 5, characterized in that, The step of performing second read instruction parsing and execution based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data specifically includes: Step 71: Extract the corresponding first register identifier set from the first instruction parameters; Step 72: Traverse the first register identifiers in the first register identifier set; during traversal, use the currently traversed first register identifier as the corresponding current register identifier; use the first register record in the first register list whose first register identifier field matches the current register identifier as the corresponding current register record; and identify whether the current register record is empty; if the current register record is empty, stop traversal and set the corresponding second feedback data to a preset identifier error code, and proceed to step 73; if the current register record is not empty, extract all byte data in the first storage area corresponding to the current register record as the corresponding second read data; and at the end of traversal, sequentially concatenate all the obtained second read data to form the corresponding first concatenated data, identify the data byte length of the first concatenated data to obtain the corresponding first concatenated data length, and use the first concatenated data length and the first concatenated data to form the corresponding second feedback data; Step 73: Identify whether the obtained second feedback data is an error code; if yes, the first instruction feedback data is composed of a preset second read instruction error feedback identifier corresponding to the read instruction type and the second feedback data; if no, the first instruction feedback data is composed of the first instruction type and the second feedback data.

8. The instruction information processing method for the charging test equipment according to claim 5, characterized in that, The process of parsing and executing a first type of write instruction based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data specifically includes: Step 81: Extract the corresponding second starting address and the first written data from the first instruction parameters; Step 82: Identify whether the second starting address is a storage address in the first local storage area; if yes, proceed to step 83; if no, set the corresponding third feedback data to a preset address error code and proceed to step 87. Step 83: Identify the length of the first written data bytes to obtain the corresponding first written data length; and identify whether the first written data length matches the register byte width; if yes, proceed to step 84; if no, set the corresponding third feedback data to a preset data length error code, and proceed to step 87. Step 84: Take the first register record in the first register list whose register start address matches the second start address as the corresponding current register record; and identify whether the current register record is empty; if the current register record is not empty, proceed to step 85; if the current register record is empty, set the corresponding third feedback data to the preset address error code, and proceed to step 87. Step 85: Identify whether the first register type field recorded in the current register is a type of read / write register; if the first register type field is a type of read / write register, proceed to step 86; if the first register type field is not a type of read / write register, set the corresponding third feedback data to a preset register type error code, and proceed to step 87. Step 86: The first register storage area corresponding to the current register record in the first storage area is taken as the corresponding current register storage area; the stored data in the register storage area is backed up to obtain the corresponding current backup data; the stored data in the current register storage area is updated to the corresponding first write data; when the data update is completed, all bytes of data in the current register storage area are extracted as the corresponding third read data; and the matching between the third read data and the first write data is identified; if they match, the corresponding third feedback data is set to the first instruction parameter; if they do not match, the stored data in the current register storage area is restored to the corresponding current backup data, and the corresponding third feedback data is set to a preset write failure error code. Step 87: Identify whether the obtained third feedback data is an error code; if yes, then the first instruction feedback data is composed of a preset first type of write instruction error feedback identifier corresponding to a type of address write instruction and the third feedback data; if no, then the first instruction type and the third feedback data are used to compose the first instruction feedback data.

9. The instruction information processing method for the charging test equipment according to claim 5, characterized in that, The step of performing a second type of write instruction parsing and execution based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data specifically includes: Step 91: Extract the corresponding second register identifier and the first write data from the first instruction parameters; Step 92: Identify the length of the first written data bytes to obtain the corresponding first written data length; and identify whether the first written data length matches the register byte width; if the first written data length matches the register byte width, proceed to step 93; if the first written data length does not match the register byte width, set the corresponding fourth feedback data to a preset data length error code, and proceed to step 96. Step 93: Take the first register record in the first register list whose first register identifier field matches the second register identifier as the corresponding current register record; and identify whether the current register record is empty; if the current register record is not empty, proceed to step 94; if the current register record is empty, set the corresponding fourth feedback data to the preset identifier error code, and proceed to step 96. Step 94: Identify whether the first register type field recorded in the current register is a type of read / write register; if the first register type field is a type of read / write register, proceed to step 95; if the first register type field is not a type of read / write register, set the corresponding fourth feedback data to a preset register type error code, and proceed to step 96. Step 95: The first register storage area corresponding to the current register record in the first storage area is taken as the corresponding current register storage area; the stored data in the register storage area is backed up to obtain the corresponding current backup data; the stored data in the current register storage area is updated to the corresponding first write data; when the data update is completed, all bytes of data in the current register storage area are extracted as the corresponding fourth read data; and the matching between the fourth read data and the first write data is identified; if they match, the corresponding fourth feedback data is set to the first instruction parameter; if they do not match, the stored data in the current register storage area is restored to the corresponding current backup data, and the corresponding fourth feedback data is set to a preset write failure error code. Step 96: Identify whether the obtained fourth feedback data is an error code; if yes, then the first instruction feedback data is composed of a preset second type of write instruction error feedback identifier corresponding to a type of write instruction identified by the identifier and the fourth feedback data; if no, then the first instruction type and the fourth feedback data are used to compose the first instruction feedback data.

10. The instruction information processing method for the charging test equipment according to claim 5, characterized in that, The process of parsing and executing the first type II write instruction based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data specifically includes: Step 101: Extract the corresponding third starting address, the first and mask data, and the first or mask data from the first instruction parameters; Step 102: Identify whether the third starting address is a storage address in the first local storage area; if yes, proceed to step 103; if no, set the corresponding fifth feedback data to a preset address error code and proceed to step 107. Step 103: Identify the data byte lengths of the first and mask data and the first or mask data to obtain the corresponding first and mask data lengths and first or mask data lengths; and identify whether the first and mask data lengths and the first or mask data lengths both match the register byte width; if the first and mask data lengths and the first or mask data lengths both match the register byte width, proceed to step 104; if the first and mask data lengths or the first or mask data lengths do not match the register byte width, set the corresponding fifth feedback data to a preset data length error code, and proceed to step 107; Step 104: Take the first register record in the first register list whose register start address matches the third start address as the corresponding current register record; and identify whether the current register record is empty; if the current register record is not empty, proceed to step 105; if the current register record is empty, set the corresponding fifth feedback data to a preset address error code, and proceed to step 107. Step 105: Identify whether the first register type field recorded in the current register is a type II read / write register; if the first register type field is a type II read / write register, proceed to step 106; if the first register type field is not a type II read / write register, set the corresponding fifth feedback data to a preset register type error code, and proceed to step 107. Step 106: The first register storage area corresponding to the current register record in the first storage area is taken as the corresponding current register storage area; the stored data in the register storage area is backed up to obtain the corresponding current backup data; the stored data in the current register storage area is updated according to the first and mask data and the first or mask data; when the data update is complete, all bytes of data in the current register storage area are extracted as the corresponding current read data; the current read data is verified according to the current backup data, the first and mask data, and the first or mask data to obtain the corresponding current verification result; the current verification result is checked to determine if the verification is successful; if yes, the corresponding fifth feedback data is set to the first instruction parameter; if no, the stored data in the current register storage area is restored to the corresponding current backup data, and the corresponding fifth feedback data is set to a preset write failure error code. Step 107: Identify whether the obtained fifth feedback data is an error code; if yes, then the first instruction feedback data is composed of the preset first type II write instruction error feedback identifier corresponding to the type II address write instruction and the fifth feedback data; if no, then the first instruction type and the fifth feedback data are used to compose the first instruction feedback data.

11. The instruction information processing method for the charging test equipment according to claim 5, characterized in that, The process of parsing and executing a second type of write instruction based on the first instruction parameters and the first register list to obtain the corresponding first instruction feedback data specifically includes: Step 111: Extract the corresponding third register identifier, the first and mask data, and the first or mask data from the first instruction parameters; Step 112: Identify the data byte lengths of the first and mask data and the first or mask data to obtain the corresponding second and mask data lengths; and identify whether the second and mask data lengths and the second or mask data lengths both match the register byte width; if the second and mask data lengths and the second or mask data lengths both match the register byte width, proceed to step 113; if the second and mask data lengths or the second or mask data lengths do not match the register byte width, set the corresponding sixth feedback data to a preset data length error code, and proceed to step 116. Step 113: Take the first register record in the first register list whose first register identifier field matches the third register identifier as the corresponding current register record; and identify whether the current register record is empty; if the current register record is not empty, proceed to step 114; if the current register record is empty, set the corresponding sixth feedback data to a preset identifier error code, and proceed to step 116. Step 114: Identify whether the first register type field recorded in the current register is a type II read / write register; if the first register type field is a type II read / write register, proceed to step 115; if the first register type field is not a type II read / write register, set the corresponding sixth feedback data to a preset register type error code, and proceed to step 116. Step 115: The first register storage area corresponding to the current register record in the first storage area is taken as the corresponding current register storage area; the stored data in the register storage area is backed up to obtain the corresponding current backup data; the stored data in the current register storage area is updated according to the first and mask data and the first or mask data; when the data update is complete, all bytes of data in the current register storage area are extracted as the corresponding current read data; the current read data is verified according to the current backup data, the first and mask data, and the first or mask data to obtain the corresponding current verification result; the current verification result is checked to determine if the verification is successful; if yes, the corresponding sixth feedback data is set to the first instruction parameter; if no, the stored data in the current register storage area is restored to the corresponding current backup data, and the corresponding sixth feedback data is set to a preset write failure error code. Step 116: Identify whether the obtained sixth feedback data is an error code; if yes, the first instruction feedback data is composed of the preset second type of write instruction error feedback identifier corresponding to the second type of write instruction type and the sixth feedback data; if no, the first instruction type and the sixth feedback data are used to compose the first instruction feedback data.

12. The instruction information processing method for the charging test equipment according to any one of claims 10 and 11, characterized in that, The step of updating the stored data in the current register storage area based on the first and mask data and the first or mask data specifically includes: Extract the stored data from the current register storage area as the corresponding first original data; invert the first and mask data to obtain the corresponding first and mask inverted data; substitute the first and mask data, the first and mask data, the first and mask inverted data, and the first original data into the preset transformation formula F to calculate the corresponding first updated data; and update the stored data in the current register storage area to the corresponding first updated data.

13. The instruction information processing method for the charging test equipment according to any one of claims 10 and 11, characterized in that, The step of verifying the currently read data based on the current backup data, the first or mask data, and the first or mask data to obtain the corresponding current verification result specifically includes: Step 131: Take the current backup data as the corresponding first original data; and invert the first and mask data to obtain the corresponding first and mask inverted data; and substitute the first and mask data, the first and mask data, the first and mask data, the first and mask inverted data, and the first original data into the preset transformation formula F to calculate the corresponding first updated data; Step 132: Identify whether the first updated data matches the currently read data; if they match, set the corresponding current verification result to verification success; if they do not match, set the corresponding current verification result to verification failure.

14. The instruction information processing method for the charging test equipment according to any one of claims 12 and 13, characterized in that, The transformation formula F is: ， AND and OR are bitwise AND and bitwise OR operators, respectively. D am For the first and mask data, D om For the first or mask data, The first is the inverted data of the mask. D old The first original data, D new This refers to the first updated data.

15. An electronic device, characterized in that, include: Memory, processor, and transceiver; The processor is configured to be coupled to the memory, read and execute instructions in the memory to implement the method according to any one of claims 1-14; The transceiver is coupled to the processor, and the processor controls the transceiver to send and receive messages.

16. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed by a computer, cause the computer to perform the method described in any one of claims 1-14.

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