Driving method of display panel and display device

Abstract

The application discloses a display panel driving method and a display device. The driving method comprises the following steps: a first voltage output to a first voltage line in a first period is different from a second voltage output to the first voltage line in a second period; one picture refresh period comprises a refresh frame; one refresh frame comprises an effective stage and a first blank stage; the first period is located in the effective stage; at least part of the second period is located in the first blank stage; the voltage output to the first voltage line starts to gradually change from the first voltage to the second voltage at a first time point; the first time point is located between the first period and the second period; the first time point is before the first blank stage; and / or the voltage output to the first voltage line starts to gradually change from the second voltage to the first voltage at a second time point; the second time point is after the second period; and the second time point is after the first blank stage. Through the above arrangement, the display effect of the display panel can be improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a driving method for a display panel and a display device. Background Technology

[0002] With the development of display technology, people have increasingly higher requirements for the display quality of display panels.

[0003] Currently, existing display panels suffer from uneven display. Summary of the Invention

[0004] This application provides a driving method for a display panel and a display device, which can improve the display uniformity of the display panel.

[0005] The first aspect of this application provides a driving method for a display panel, the display panel comprising: a plurality of pixel circuits arranged in an array; a plurality of first scan lines electrically connected to pixel circuits in corresponding rows; a first voltage line electrically connected to the pixel circuits, the pixel circuits being configured to write a voltage on the first voltage line into the pixel circuits in response to a pulse signal of a first scan signal on the first scan line; the driving method comprising: a first voltage output to the first voltage line in a first time period being different from a second voltage output to the first voltage line in a second time period; a screen refresh cycle comprising a refresh frame; a refresh frame comprising an active phase and a first blank phase, the first time period being located in the active phase, at least a portion of the second time period being located in the first blank phase, the voltage output to the first voltage line gradually changing from the first voltage to the second voltage at a first moment, the first moment being located between the first time period and the second time period, the first moment being before the first blank phase, and / or, the voltage output to the first voltage line gradually changing from the second voltage to the first voltage at a second moment, the second moment being located after the second time period, the second moment being after the first blank phase.

[0006] Optionally, a screen refresh cycle may also include a hold frame; the driving method may also include: within a hold frame, the voltage output to the first voltage line in the third time period is different from the voltage output to the first voltage line in the first time period.

[0007] Optionally, within a hold frame, the voltage output to the first voltage line may include one or more third pulses.

[0008] Optionally, the display area of ​​the display panel includes N first areas and M second areas arranged alternately along a first direction, where N is greater than M and N and M are positive integers;

[0009] Within a hold frame, during the third time period, a first scan signal is output to the pixel circuit of the second region, so that the pixel circuit of the second region responds to the pulse signal of the first scan signal and writes the voltage on the first voltage line into the pixel circuit.

[0010] Optionally, the driving method further includes: within a holding frame, in a fourth time period, outputting a first scan signal to the pixel circuit of the first region, so that the pixel circuit of the first region responds to the pulse signal of the first scan signal and writes the voltage on the first voltage line into the pixel circuit; the voltage output to the first voltage line in the fourth time period is different from the voltage output to the first voltage line in the third time period; the voltage output to the first voltage line in the fourth time period is the same as the voltage output to the first voltage line in the first time period.

[0011] Optionally, the absolute value of the voltage output to the first voltage line in the third time period is less than the absolute value of the voltage output to the first voltage line in the first time period.

[0012] Optionally, within a single frame, the first scan signal corresponding to the same pixel circuit includes multiple second pulses.

[0013] Optionally, the display area of ​​the display panel includes N first areas and M second areas arranged alternately along a first direction, where N is greater than M and N and M are positive integers; the driving method includes: in a first time period, simultaneously outputting a first scan signal to the pixel circuits of the N spaced-apart first areas, so that the pixel circuits of the first areas respond to the pulse signal of the first scan signal and write the voltage on the first voltage line into the pixel circuit; in a second time period, simultaneously outputting a first scan signal to the pixel circuits of the M spaced-apart second areas, so that the pixel circuits of the second areas respond to the pulse signal of the first scan signal and write the voltage on the first voltage line into the pixel circuit.

[0014] Optionally, the absolute value of the first voltage is greater than the absolute value of the second voltage.

[0015] Optionally, the absolute value of the first voltage output to the first voltage line in the first time period is greater than the absolute value of the second voltage output to the first voltage line in the second time period.

[0016] Optionally, the first voltage line is a first initialization signal line, and the pixel circuit responds to the pulse signal of the first scan signal by writing the voltage on the first voltage line into the first electrode of the light-emitting device of the pixel circuit.

[0017] Optionally, the first voltage is less than the second voltage.

[0018] Optionally, the first voltage output to the first voltage line in the first time period is less than the second voltage output to the first voltage line in the second time period.

[0019] Optionally, the time interval between the first moment and the start moment of the first blank phase is greater than or equal to 1 hour and less than or equal to 100 hours, where 1 hour is the line scan time of the first scan signal; and / or, the time interval between the second moment and the end moment of the first blank phase is greater than or equal to 1 hour and less than or equal to 100 hours, where 1 hour is the line scan time of the first scan signal.

[0020] Optionally, within a refresh frame, the first scan signal corresponding to the same pixel circuit includes multiple first pulses.

[0021] Optionally, the pulse width of the first pulse is greater than or equal to 4h, where 1h is the row scan time of the first scan signal.

[0022] Optionally, within a refresh frame, after the data writing phase, the first scan signal corresponding to the same pixel circuit includes multiple first pulses.

[0023] Optionally, the number of first pulses of the first scan signal corresponding to the same pixel circuit after the data writing stage is greater than or equal to 2.

[0024] Optionally, N equals the number of the first pulses.

[0025] Optional, M = N-1.

[0026] Optionally, the pixel circuit includes a first initialization module, the control terminal of the first initialization module is connected to the first scan line, the first terminal of the first initialization module is connected to the first initialization signal line, and the second terminal of the first initialization module is connected to the first electrode of the light-emitting device.

[0027] Optionally, the pixel circuit further includes a driving module and a second initialization module. The driving module is connected between the first power signal line and the first electrode of the light-emitting device. The control terminal of the second initialization module is connected to the first scan line. The first terminal of the second initialization module is connected to the second initialization signal line. The second terminal of the second initialization module is connected to the first or second terminal of the driving module.

[0028] Optionally, the pixel circuit also includes a data writing module, the control terminal of which is connected to the second scan line, the first terminal of which is connected to the data signal line, and the second terminal of which is connected to the first terminal of the drive module.

[0029] Optionally, the pixel circuit also includes a storage module, with a first end connected to a first power signal line and a second end connected to the control terminal of the drive module.

[0030] Optionally, the pixel circuit also includes a threshold compensation module, the control terminal of which is connected to the third scan line, the first terminal of which is connected to the second terminal of the driving module, and the second terminal of which is connected to the control terminal of the driving module.

[0031] Optionally, the pixel circuit also includes a third initialization module, the control terminal of which is connected to the fourth scan line, the first terminal of which is connected to the third initialization signal line, and the second terminal of which is connected to the first terminal of the threshold compensation module.

[0032] Optionally, the pixel circuit further includes a first light-emitting control module and / or a second light-emitting control module. The control terminal of the first light-emitting control module is connected to the light-emitting control signal line, the first end of the first light-emitting control module is connected to the first power signal line, the second end of the first light-emitting control module is connected to the first end of the driving module, the control terminal of the second light-emitting control module is connected to the light-emitting control signal line, the first end of the second light-emitting control module is connected to the second end of the driving module, and the second end of the second light-emitting control module is connected to the first electrode of the light-emitting device.

[0033] A second aspect of this application provides a driving method for a display panel. The display area of ​​the display panel includes N first areas and M second areas arranged alternately along a first direction, where N is greater than M and N and M are positive integers. Each first area includes a first boundary area, a first intermediate area, and a second boundary area arranged sequentially along the first direction. A screen refresh cycle includes a refresh frame. The driving method includes: within a refresh frame, in a first time period, simultaneously outputting a first scan signal to the first intermediate area of ​​the N spaced-apart first areas, so that the pixel circuit of the first intermediate area of ​​the first area responds to the pulse signal of the first scan signal and writes the voltage on a first voltage line into the pixel circuit; in a second time period different from the first time period, simultaneously outputting a first scan signal to the second intermediate area of ​​the M spaced-apart second areas, so that the pixel circuit of the second intermediate area of ​​the second area responds to the pulse signal of the first scan signal and writes the voltage on a first voltage line into the pixel circuit. The voltage on the voltage line is written into the pixel circuit; the driving method further includes: at a first moment between a first time period and a second time period, simultaneously outputting a first scan signal to at least N second boundary regions of the first region, so that the pixel circuit of the second boundary region of the first region responds to the pulse signal of the first scan signal and writes the voltage on the first voltage line into the pixel circuit; the voltage output to the first voltage line gradually changes from a first voltage to a second voltage at the first moment, and / or, at a second moment after the second time period, simultaneously outputting a first scan signal to at least a portion of the first boundary regions and / or the first intermediate regions of the first region, so that the pixel circuit of the first boundary regions and / or the first intermediate regions of the first region responds to the pulse signal of the first scan signal and writes the voltage on the first voltage line into the pixel circuit; the voltage output to the first voltage line gradually changes from a second voltage to a first voltage at the second moment.

[0034] Optionally, a screen refresh cycle may further include a hold frame; the driving method may further include: within a hold frame, in a third time period, outputting a first scan signal to the second area, so that the pixel circuit of the second area responds to the pulse signal of the first scan signal and writes the voltage on the first voltage line into the pixel circuit; the voltage output to the first voltage line in the third time period is different from the voltage output to the first voltage line in the first time period.

[0035] Optionally, the driving method further includes: within a holding frame, in a fourth time period, outputting a first scan signal to the first region, so that the pixel circuit of the first region responds to the pulse signal of the first scan signal and writes the voltage on the first voltage line into the pixel circuit; the voltage output to the first voltage line in the fourth time period is different from the voltage output to the first voltage line in the third time period; the voltage output to the first voltage line in the fourth time period is the same as the voltage output to the first voltage line in the first time period.

[0036] Optionally, the absolute value of the voltage output to the first voltage line in the third time period is less than the absolute value of the voltage output to the first voltage line in the first time period.

[0037] Optionally, within a single frame, the first scan signal corresponding to the same pixel circuit includes multiple second pulses.

[0038] Optionally, a second region includes a third boundary region, a second intermediate region, and a fourth boundary region arranged sequentially along a first direction. In adjacent first and second regions, the second boundary region and the third boundary region are adjacent, or the first boundary region and the fourth boundary region are adjacent.

[0039] At the first moment between the first and second time periods, a first scan signal is simultaneously output to the third boundary regions of M second regions and the second boundary regions of N first regions, so that the pixel circuits of the third boundary regions of the second regions and the second boundary regions of the first regions respond to the pulse signal of the first scan signal and write the voltage on the first voltage line into the pixel circuit; the voltage output to the first voltage line gradually changes from the first voltage to the second voltage at the first moment.

[0040] Optionally, the first voltage is different from the second voltage.

[0041] Optionally, the absolute value of the first voltage is greater than the absolute value of the second voltage.

[0042] Optionally, the first voltage output to the first voltage line in the first time period is different from the second voltage output to the first voltage line in the second time period.

[0043] Optionally, the absolute value of the first voltage output to the first voltage line in the first time period is greater than the absolute value of the second voltage output to the first voltage line in the second time period.

[0044] Optionally, the first voltage line is a first initialization signal line, and the pixel circuit responds to the pulse signal of the first scan signal by writing the voltage on the first voltage line into the first electrode of the light-emitting device of the pixel circuit.

[0045] Optionally, the first voltage is less than the second voltage.

[0046] Optionally, the first voltage output to the first voltage line in the first time period is less than the second voltage output to the first voltage line in the second time period.

[0047] Optionally, a refresh frame includes an active phase and a first blank phase, a first time period is located in the active phase, at least a portion of the second time period is located in the first blank phase, a first moment is located before the first blank phase, and / or, the second moment is located after the first blank phase and after the second time period.

[0048] Optionally, the second boundary region is provided with more than or equal to 1 row of pixel circuits and less than or equal to 100 rows of pixel circuits; and / or, the first boundary region is provided with more than or equal to 1 row of pixel circuits and less than or equal to 100 rows of pixel circuits; the first direction is perpendicular to the row direction.

[0049] Optionally, the time interval between the first moment and the start moment of the first blank phase is greater than or equal to 1 hour and less than or equal to 100 hours, where 1 hour is the line scan time of the first scan signal; and / or, the time interval between the second moment and the end moment of the first blank phase is greater than or equal to 1 hour and less than or equal to 100 hours, where 1 hour is the line scan time of the first scan signal.

[0050] Optionally, within a refresh frame, the first scan signal corresponding to the same pixel circuit includes multiple first pulses.

[0051] Optionally, the pulse width of the first pulse is greater than or equal to 4h, where 1h is the row scan time of the first scan signal.

[0052] Optionally, within a refresh frame, after the data writing phase, the first scan signal corresponding to the same pixel circuit includes multiple first pulses.

[0053] Optionally, the number of first pulses of the first scan signal corresponding to the same pixel circuit after the data writing stage is greater than or equal to 2.

[0054] Optionally, N equals the number of the first pulses.

[0055] Optional, M = N-1.

[0056] Optionally, the pixel circuit includes a first initialization module, the control terminal of the first initialization module is connected to the first scan line, the first terminal of the first initialization module is connected to the first initialization signal line, and the second terminal of the first initialization module is connected to the first electrode of the light-emitting device.

[0057] Optionally, the pixel circuit further includes a driving module and a second initialization module. The driving module is connected between the first power signal line and the first electrode of the light-emitting device. The control terminal of the second initialization module is connected to the first scan line. The first terminal of the second initialization module is connected to the second initialization signal line. The second terminal of the second initialization module is connected to the first or second terminal of the driving module.

[0058] Optionally, the pixel circuit also includes a data writing module, the control terminal of which is connected to the second scan line, the first terminal of which is connected to the data signal line, and the second terminal of which is connected to the first terminal of the drive module.

[0059] Optionally, the pixel circuit also includes a storage module, with a first end connected to a first power signal line and a second end connected to the control terminal of the drive module.

[0060] Optionally, the pixel circuit also includes a threshold compensation module, the control terminal of which is connected to the third scan line, the first terminal of which is connected to the second terminal of the driving module, and the second terminal of which is connected to the control terminal of the driving module.

[0061] Optionally, the pixel circuit also includes a third initialization module, the control terminal of which is connected to the fourth scan line, the first terminal of which is connected to the third initialization signal line, and the second terminal of which is connected to the first terminal of the threshold compensation module.

[0062] Optionally, the pixel circuit further includes a first light-emitting control module and / or a second light-emitting control module. The control terminal of the first light-emitting control module is connected to the light-emitting control signal line, the first end of the first light-emitting control module is connected to the first power signal line, the second end of the first light-emitting control module is connected to the first end of the driving module, the control terminal of the second light-emitting control module is connected to the light-emitting control signal line, the first end of the second light-emitting control module is connected to the second end of the driving module, and the second end of the second light-emitting control module is connected to the first electrode of the light-emitting device.

[0063] This application provides a third-party method for driving a display panel. The display area of ​​the display panel includes N first areas and M second areas arranged alternately along a first direction, where N is greater than M and N and M are positive integers. A screen refresh cycle includes a refresh frame and a hold frame. The driving method includes: within a refresh frame, in a first time period, simultaneously outputting a first scan signal to the N spaced first areas, so that the pixel circuit of the first area responds to the pulse signal of the first scan signal and writes the voltage on the first voltage line into the pixel circuit; in a second time period different from the first time period, simultaneously outputting a first scan signal to the M spaced second areas, so that the pixel circuit of the second area responds to the pulse signal of the first scan signal and writes the voltage on the first voltage line into the pixel circuit; within a hold frame, in a third time period, outputting a first scan signal to the second area, so that the pixel circuit of the second area responds to the pulse signal of the first scan signal and writes the voltage on the first voltage line into the pixel circuit; the voltage output to the first voltage line in the second time period is different from the voltage output to the first voltage line in the first time period; the voltage output to the first voltage line in the third time period is different from the voltage output to the first voltage line in the first time period.

[0064] Optionally, the absolute value of the first voltage output to the first voltage line in the first time period is greater than the absolute value of the second voltage output to the first voltage line in the second time period.

[0065] Optionally, the absolute value of the voltage output to the first voltage line in the third time period is less than the absolute value of the voltage output to the first voltage line in the first time period.

[0066] Optionally, a refresh frame includes an active phase and a first blank phase, with the first time period located in the active phase and at least a portion of the second time period located in the first blank phase.

[0067] Optionally, within a refresh frame, after the data writing phase, the first scan signal corresponding to the same pixel circuit includes multiple first pulses.

[0068] Optionally, the number of first pulses of the first scan signal corresponding to the same pixel circuit after the data writing stage is greater than or equal to 2.

[0069] Optionally, N equals the number of the first pulses.

[0070] Optional, M = N-1.

[0071] Optionally, within a single frame, the first scan signal corresponding to the same pixel circuit includes multiple second pulses.

[0072] A fourth aspect of this application provides a display device, including a display panel and a display driving module, wherein the display driving module is used to execute the driving method of the display panel of any of the above embodiments.

[0073] The beneficial effects are as follows: the first voltage output to the first voltage line in the first time period is different from the second voltage output to the first voltage line in the second time period. Furthermore, the voltage output to the first voltage line gradually changes from the first voltage to the second voltage at the first moment, which is between the first and second time periods and before the first blanking phase. And / or, the voltage output to the first voltage line gradually changes from the second voltage to the first voltage at the second moment, which is after the second time period and after the first blanking phase. It can be understood that compensating for the voltage of the first voltage line before the first blanking phase, and / or restoring the voltage of the first voltage line to its pre-compensation value after the first blanking phase, can improve the problem of prominent screen boundaries. Attached Figure Description

[0074] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0075] Figure 1 This is a schematic diagram of the working state of the display panel in the first time period in related technologies;

[0076] Figure 2 This is a schematic diagram illustrating the working state of the display panel in the second time period in the relevant technology.

[0077] Figure 3 This is a schematic diagram illustrating the protruding boundaries of multi-screen display panels in related technologies;

[0078] Figure 4 This is a schematic diagram of the electrical connection structure of the display panel circuitry in this application;

[0079] Figure 5 This is a flowchart illustrating one embodiment of the driving method for the display panel in this application;

[0080] Figure 6 This is a schematic diagram of the voltage output to the first voltage line in the refresh frame, representing a first embodiment of the signal.

[0081] Figure 7 This is a schematic diagram of the second embodiment of the voltage output to the first voltage line in the refresh frame;

[0082] Figure 8 This is a schematic diagram of the voltage signal of the third embodiment output to the first voltage line in the refresh frame;

[0083] Figure 9This is a schematic diagram of one working state of the display panel in the first time period of this application;

[0084] Figure 10 This is a schematic diagram of one working state of the display panel in the second time period of this application;

[0085] Figure 11 This is a flowchart illustrating another embodiment of the driving method for the display panel in this application;

[0086] Figure 12 This is a waveform diagram of one embodiment of the voltage output to the first voltage line under refresh frame + hold frame.

[0087] Figure 13 This is a schematic diagram of one embodiment of the pixel circuit of this application;

[0088] Figure 14 It is a waveform diagram of the voltage output to the first voltage line and part of the first scan signal;

[0089] Figure 15 This is a schematic diagram of another embodiment of the pixel circuit of this application;

[0090] Figure 16 This is a schematic diagram of another embodiment of the pixel circuit of this application;

[0091] Figure 17 It is a timing diagram corresponding to the pixel circuit in the second region;

[0092] Figure 18 It is a timing diagram corresponding to the pixel circuit in the first region;

[0093] Figure 19 This is a schematic diagram of another working state of the display panel during the first period;

[0094] Figure 20 This is a schematic diagram of another working state of the display panel in the second time period;

[0095] Figure 21 This is a schematic diagram of the display panel's working state at a given moment;

[0096] Figure 22 This is a schematic diagram of the display panel's working state at a second moment;

[0097] Figure 23 This is a schematic diagram of another working state of the display panel at a given moment;

[0098] Figure 24 This is a schematic diagram of another working state of the display panel at a second moment;

[0099] Figure 25This is a schematic diagram of one embodiment of the display device of this application. Detailed Implementation

[0100] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0101] It should be noted that the terms "first" and "second" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0102] To address the shortcomings of the "7T1C" pixel circuit, the industry invented the "8T1C" pixel circuit, which adds a transistor to perform high-frequency resets of the source or drain of the driving transistor, thereby improving low-frequency flicker. However, in the "8T1C" pixel circuit, the transistor performing high-frequency resets of the source or drain of the driving transistor and the transistor resetting the OLED anode are controlled by the same signal. This results in an excessively high frequency of OLED anode initialization, causing differences in the degree of OLED anode initialization at different times, leading to a split-screen problem on the display panel. The specific reasons are analyzed below:

[0103] Taking a maximum refresh rate of 120Hz for the display screen and an anode initialization control signal frequency of 360Hz as an example. Figure 1 This is a schematic diagram provided in related technologies showing that the pulse of the anode initialization control signal does not enter the Vblank region. Figure 2 This is a schematic diagram provided in related technologies showing the pulse of an anode initialization control signal entering the Vblank region. (See reference) Figure 1 and Figure 2The VActive area is the actual display area with sub-pixels, equivalent to the display area of ​​the display panel, while the Vblank area is a virtual area corresponding to the number of pixel rows that pulse a in the vertical blanking stage (or first blanking stage) control signal SP1 can scan in a frame; it is an area that does not actually exist. At this time, within a frame (within a screen refresh cycle), the control signal SP1 for controlling anode reset corresponding to the same pixel circuit has three pulses after the data writing stage of that pixel circuit. Figure 1 In the first time period, all three pulses of the control signal SP1, which controls anode reset, are in the VActive region. This means that at the same time, the initialization voltage needs to charge the anodes of three sub-pixels in the column direction of the display panel, each position corresponding to one or more rows of sub-pixels. As the three pulses scan (equivalent to moving downwards) in the display panel, Figure 2 In the second time period, pulse a enters the Vblank area (a hypothetical area without pixels for ease of understanding), while the two pulses (pulse b and pulse c) in the control signal SP1 controlling anode reset are in the VActive area. This means that at the same moment, the initialization voltage needs to charge and reset the anodes of two sub-pixels in the column direction of the display panel. Therefore, starting from when pulse a appears in the Vblank area, the load decreases, from three sub-pixels to two, thus reducing the load by 1 / 3. The two sub-pixels corresponding to the two pulses in the VActive area are initialized. Due to the reduced load, the anode charging speed of the light-emitting device increases; since the charging time remains constant, the charging is sufficient, resulting in a lower anode potential of the light-emitting device and a dimmer brightness for the sub-pixels. A black line appears at the positions corresponding to the two pulses (pulse b and pulse c), resulting in two black lines. Since the Vblank area has a certain width, the area swept by the two black lines forms two Mura areas, dividing the display panel into three segments. Figure 1 and Figure 2 The screen is divided into two zones: Z1 (normal display zone) and Z2 (darkened display zone). If N pulses are applied, N screens will be formed.

[0104] Further research is needed. (See also) Figure 3 By compensating for the voltage input to the initialization signal line during the second time period, the brightness difference between the first zone Z1 and the second zone Z2 can be improved. However, there is a phenomenon at the boundary between the first zone Z1 and the second zone Z2 where the brightness is more prominent than that of the first zone Z1 and the second zone Z2.

[0105] In view of this, this application provides a driving method for a display panel. Figure 4This is a schematic diagram of a display panel according to an embodiment of the present application. The display panel 10 includes a plurality of pixel circuits 100 arranged in an array, a plurality of first scan lines SP1, and a first voltage line Vref. The first scan lines SP1 are electrically connected to the pixel circuits 100 in the corresponding rows. The first voltage line Vref is electrically connected to the pixel circuits 100. The pixel circuits 100 are used to write the voltage on the first voltage line Vref into the pixel circuits 100 in response to the pulse signal of the first scan signal on the first scan line SP1.

[0106] See Figure 5 The driving method provided in this application includes:

[0107] Step S100: The first voltage V1 output to the first voltage line Vref in the first time period T1 is different from the second voltage V2 output to the first voltage line Vref in the second time period T2; a screen refresh cycle includes a refresh frame; a refresh frame includes an active phase AP and a first blank phase BP1, the first time period T1 is located in the active phase AP, at least a portion of the second time period T2 is located in the first blank phase BP1, the voltage output to the first voltage line Vref gradually changes from the first voltage V1 to the second voltage V2 at the first moment T11, the first moment T11 is located between the first time period T1 and the second time period T2, the first moment T11 is before the first blank phase BP1, and / or, the voltage output to the first voltage line Vref gradually changes from the second voltage V2 to the first voltage V1 at the second moment T21, the second moment T21 is located after the second time period T2, the second moment T21 is after the first blank phase BP1.

[0108] Specifically, due to Figure 1 and Figure 2 In these two cases, the number of rows of pixel circuit 100 written by the voltage on the first voltage line Vref is different, which is equivalent to the different load size of the first voltage line Vref in the first time period and the second time period. Therefore, if the voltage output to the first voltage line Vref is the same in the above two cases, it will inevitably cause display differences. Therefore, in the first time period T1 (for example, corresponding to...), the voltage can be adjusted accordingly. Figure 1 (Operating state) The power module or driver chip inputs the first voltage V1 to the first voltage line Vref, and in the second time period T2 (e.g., corresponding to the working state) Figure 2 (During operation) The power module or driver chip inputs a second voltage V2 to the first voltage line Vref. The first voltage V1 and the second voltage V2 are different to improve the display differences caused by the above two situations and improve the multi-screen phenomenon. The specific voltage value can be adjusted according to the display effect. The first scan signal is output to the first scan line SP1 through the scanning circuit. Part or all of the second time period T2 is located in the first blank stage BP1. The pulse signal of the first scan signal can be a conduction pulse. In the same refresh frame, the second time period is after the first time period.

[0109] Furthermore, in one embodiment, at a first moment T11, before the first time period T1 and between the second time period T2, and before the first blank phase BP1, the first voltage V1 begins to gradually change to the second voltage V2. This is equivalent to adjusting the voltage on the first voltage line Vref before the pulse signal a fully enters the Vblank region, which is equivalent to compensating for the voltage on the first voltage line Vref in advance. This reduces the impact of the sudden change in the first voltage line Vref from the first voltage V1 to the second voltage V2 on the brightness, thereby improving the problem of the prominent split-screen boundary and making the brightness transition between the first region Z1 and the second region Z2 smoother. In another embodiment, at a second time point T21 after the second time period T2 and after the first blanking phase BP1, the second voltage V2 begins to gradually change towards the first voltage V1. This is equivalent to restoring the voltage on the first voltage line Vref to its pre-compensation level only after pulse signal a completely leaves the Vblank region and pulse signals b and c leave their respective second regions Z2. This reduces the impact of the abrupt change from the second voltage V2 to the first voltage V1 on brightness, thereby improving the resulting problem of prominent screen boundaries and making the brightness transition between the first region Z1 and the second region Z2 smoother. In yet another embodiment, it can be a combination of the above two embodiments, which is equivalent to increasing the duration of the voltage output to the first voltage line Vref being the second voltage V2. The duration of the voltage output to the first voltage line Vref being the second voltage V2 is greater than the first blanking phase BP1, which is within the range of the duration of the voltage output to the first voltage line Vref being the second voltage V2. The effect of this is not described in detail here.

[0110] For a clearer explanation, please refer to [link / reference]. Figures 6 to 8 Three different implementation methods are provided respectively. Figure 6 The first time T11 is before the start time of the first blank phase BP1, and the second time T21 is the same as or before the end time of the first blank phase BP1. Figure 7 The first moment T11 is the same as the start time of the first blank phase BP1, or it is after the start time of the first blank phase BP1. The second moment T21 is after the end time of the first blank phase BP1. Figure 8 The first time point T11 is before the start of the first blank phase BP1, and the second time point T21 is after the end of the second time period T2. Of course, this application is not limited to the specific embodiment described above, and the first time point T11 and the second time point T21 can be selected according to the actual situation.

[0111] See Figure 9 and Figure 10,in, Figure 9 and Figure 1 correspond, Figure 10 and Figure 2 correspond, Figure 9 and Figure 10 All are improved display panels. Figure 9 All three pulses are in region Z1 of the first region. Figure 9 Corresponding to the first time period, Figure 10 One pulse enters the Vblank region, and two other pulses are in the second region Z2 of the Vactive region. Figure 10 Corresponding to the second time period, by making the voltage of the first voltage line Vref gradually change from the first voltage V1 to the second voltage V2 before the start time of the first blank stage BP1 in the above embodiments, and / or making the voltage of the first voltage line Vref gradually change from the second voltage V2 to the first voltage V1 after the end time of the first blank stage BP1, the problem of the prominent boundary between the first region Z1 and the second region Z2 can be improved.

[0112] The first blanking phase can be the time period between the end of the last row of pixel circuit data writing phase of the display panel in the previous refresh frame and the beginning of the first row of pixel circuit data writing phase in the next refresh frame, when the display panel is at its maximum refresh frequency (at which time a screen refresh cycle only includes refresh frames and not hold frames).

[0113] See Figure 11 and Figure 12 A screen refresh cycle also includes a hold frame. When the current refresh rate of the display panel is less than the maximum refresh rate, a screen refresh cycle includes a refresh frame and a hold frame. A screen refresh cycle includes an active phase (AP) and a blank phase. The blank phase (or vertical blanking phase) may include a first blank phase (BP1) and a hold frame, where the hold frame corresponds to BP2 in the figure. The active phase may be located within the refresh frame. The blank phase may be the time period between the end of the last row of pixel circuit data writing stage of the display panel in the previous refresh frame and the beginning of the first row of pixel circuit data writing stage in the next refresh frame when the refresh rate of the display panel is less than the maximum refresh rate (in which case only the refresh frame and hold frame are included). The driving method of this application also includes:

[0114] S200: Within a hold frame, the voltage output to the first voltage line Vref in the third time period T3 is different from the voltage output to the first voltage line Vref in the first time period T1.

[0115] Specifically, unlike the refresh frame, the hold frame does not write data voltage to the pixel circuit 100. During the third time period T3, the voltage output by the power supply module or driver chip to the first voltage line Vref can be... Figure 12The third voltage V3 is different from the voltage output to the first voltage line Vref in the first time period T1, in order to further improve the problem of multiple screens. The absolute value of the third voltage V3 can be less than the absolute value of the first voltage V1.

[0116] In one embodiment, within a holding frame, the voltage output to the first voltage line Vref includes one or more third pulses. The number of third pulses can be one, two, or three, etc., and can be set according to actual conditions; this application does not impose any limitations.

[0117] In one embodiment, combined with Figure 10 and Figure 12 The display area AA of the display panel 10 includes N first areas Z1 and M second areas Z2 arranged alternately along the first direction X. For example, the figure shows 3 first areas Z1 and 2 second areas Z2, where N is greater than M and N and M are positive integers. Within a holding frame, in the third time period T3, a first scan signal is output to the pixel circuit 100 of the second area Z2, so that the pixel circuit 100 of the second area Z2 responds to the pulse signal of the first scan signal and writes the voltage on the first voltage line Vref into the pixel circuit 100. The first direction X intersects, for example, perpendicularly to, the extension direction of the first scan line SP1 (parallel to the direction Y).

[0118] Specifically, the first direction X is the column direction of the pixel circuit 100. N first regions Z1 and M second regions Z2 are alternately arranged along the first direction X. During the third time period T3 in the hold frame, the voltage output to the first voltage line Vref by the power module or driver chip differs from the voltage output to the first voltage line Vref during the first time period T1 in the refresh frame. Dynamic compensation of the first voltage line Vref voltage during the hold frame can thus improve the multi-screen phenomenon. The second region Z2 can be the brightness compensation area, equivalent to the mura area. Therefore, when the first voltage line Vref voltage is written into the pixel circuit of the second region Z2 in the hold frame, further compensation can be performed on the voltage output to the first voltage line Vref to further improve the multi-screen problem.

[0119] In one embodiment, see Figure 12 The driving method of this application further includes: during a holding frame, in the fourth time period T4, outputting a first scan signal to the pixel circuit 100 of the first region Z1, so that the pixel circuit 100 of the first region Z1 responds to the pulse signal of the first scan signal and writes the voltage on the first voltage line Vref into the pixel circuit 100.

[0120] Optionally, the voltage output to the first voltage line Vref in the fourth time period T4 is different from the voltage output to the first voltage line Vref in the third time period T3.

[0121] Optionally, the voltage output to the first voltage line Vref in the fourth time period T4 is the same as the voltage output to the first voltage line Vref in the first time period T1. The first region Z1 can be a non-mura region, so when the pixel circuit of the first region Z1 of the holding frame writes the voltage to the first voltage line Vref, it is not necessary to compensate the voltage output to the first voltage line Vref.

[0122] Of course, the voltages output to the first voltage line Vref at different times can be other than those mentioned above, and this application does not impose any mandatory restrictions.

[0123] In one embodiment, the absolute value of the voltage output to the first voltage line Vref during the third time period T3 is less than the absolute value of the voltage output to the first voltage line Vref during the first time period T1.

[0124] Specifically, there are two scenarios. First, if the voltage output to the first voltage line Vref in the first time period T1 is negative, then the voltage output to the first voltage line Vref in the third time period T3 will be a negative voltage with a smaller absolute value. Second, if the voltage output to the first voltage line Vref in the first time period T1 is positive, then the voltage output to the first voltage line Vref in the third time period T3 will be a positive voltage with a smaller absolute value.

[0125] In one embodiment, within a hold frame, the first scan signal corresponding to the same pixel circuit 100 includes a plurality of second pulses. Specifically, the number of second pulses can be 2, 3, or 4, etc.

[0126] In one embodiment, see Figure 9 and Figure 10 The display panel 10 of this application includes a display area AA comprising N first areas Z1 and M second areas Z2 arranged alternately along a first direction X, where N is greater than M and N and M are positive integers; the driving method of this application includes:

[0127] During the first time period T1, a first scan signal is simultaneously output to the pixel circuits 100 of the N first regions Z1 at intervals, so that the pixel circuits 100 of the first regions Z1 respond to the pulse signal of the first scan signal and write the voltage on the first voltage line Vref into the pixel circuits 100.

[0128] During the second time period T2, a first scan signal is simultaneously output to the pixel circuits 100 of the M intervals of the second region Z2, so that the pixel circuits 100 of the second region Z2 respond to the pulse signal of the first scan signal and write the voltage on the first voltage line Vref into the pixel circuits 100.

[0129] During the first time period T1, the first scan signal activation pulse is not output to the pixel circuit 100 of the second region Z2. During the second time period T2, the first scan signal activation pulse is not output to the pixel circuit 100 of the first region Z1.

[0130] Specifically, the N first regions Z1 have more rows of pixel circuits than the M second regions Z2. Under the control of the pulse signal of the first scan signal in the first time period and the second time period, the number of rows of the pixel circuit 100 written with the voltage on the first voltage line Vref differs. Therefore, if the voltage output to the first voltage line Vref by the power module or driver chip is a constant value, it will cause a difference in brightness between the first regions Z1 and the second regions Z2, equivalent to a split-screen phenomenon. By outputting different voltages to the first voltage line Vref in the first time period T1 and the second time period T2 respectively, the brightness difference between the first regions Z1 and the second regions Z2 can be reduced, improving the split-screen phenomenon. In one embodiment, the absolute value of the first voltage V1 is greater than the absolute value of the second voltage V2.

[0131] Specifically, when the first voltage V1 is positive, the absolute value of the second voltage V2 is a smaller positive value; when the first voltage V1 is negative, the absolute value of the second voltage V2 is a smaller negative value.

[0132] In one embodiment, the absolute value of the first voltage V1 output to the first voltage line Vref in the first time period T1 is greater than the absolute value of the second voltage V2 output to the first voltage line Vref in the second time period T2. This is equivalent to the first time period T1 simultaneously scanning N first regions Z1, resulting in a larger load and requiring a larger absolute value of the voltage output to the first voltage line Vref; and the second time period T2 simultaneously scanning M second regions Z2, resulting in a smaller load and requiring a smaller absolute value of the voltage output to the first voltage line Vref, thus ensuring that the voltage values ​​written to the pixel circuits of the first regions Z1 and Z2 are the same or similar.

[0133] In one embodiment, see Figure 13 The first voltage line Vref is the first initialization signal line Vref1. In response to the pulse signal of the first scan signal, the pixel circuit 100 writes the voltage on the first voltage line Vref into the first electrode 110A of the light-emitting device 110 of the pixel circuit 100.

[0134] Specifically, the voltage on the first initialization signal line Vref1 is used to initialize the first electrode 110A of the light-emitting device 110. For example, the first electrode 110A can be the anode of the light-emitting device 110. When the first voltage line Vref is the first initialization signal line Vref1, the phenomenon of multiple screens caused by the different initialization degree of the first electrode 110A of the light-emitting device 110 in the pixel circuit 100 of the first region Z1 and the second region Z2 can be improved.

[0135] Optionally, at a first moment T11, before the first time period T1 and between the second time period T2, and before the first blanking phase BP1, the first voltage V1 is gradually transitioned to the second voltage V2, thereby improving the problem of the prominent boundary on one side of the second region Z2 (e.g., the side away from the Vblank region). Optionally, at a second moment T21, after the second time period T2 and after the first blanking phase BP1, the second voltage V2 is gradually transitioned to the first voltage V1, thereby improving the problem of the prominent split-screen boundary on the other side of the second region Z2 (e.g., the side closer to the Vblank region).

[0136] In one embodiment, the first voltage V1 is less than the second voltage V2. That is, when both the first voltage V1 and the second voltage V2 are negative, the first voltage V1 is less than the second voltage V2.

[0137] In one embodiment, the first voltage V1 output to the first voltage line Vref in the first time period T1 is less than the second voltage V2 output to the first voltage line Vref in the second time period T2.

[0138] In one embodiment, the first time T11 is before the start time of the first blank stage BP1, and the time interval D1 between the first time T11 and the start time of the first blank stage BP1 is greater than or equal to 1h and less than or equal to 100h, where 1h is the line scan time of the first scan signal; and / or, the second time T21 is after the end time of the first blank stage BP1, and the time interval D2 between the second time T21 and the end time of the first blank stage BP1 is greater than or equal to 1h and less than or equal to 100h, where 1h is the line scan time of the first scan signal.

[0139] Optionally, the first time point T11 is before the start of the first blank phase BP1, and the time interval D1 between the first time point T11 and the start of the first blank phase BP1 is greater than or equal to k3*h and less than or equal to 100h. And / or, the second time point T21 is after the end of the first blank phase BP1, and the time interval D2 between the second time point T21 and the end of the first blank phase BP1 is greater than or equal to k4*h and less than or equal to 100h. Optionally, k3 can be 1, 10, 20, 30, 40, or 50. Optionally, k4 can be 1, 10, 20, 30, 40, or 50.

[0140] Specifically, the first time T11 is before the start of the first blank phase BP1, and the time interval D1 between the first time T11 and the start of the first blank phase BP1 can be 1h, 20h, 50h or 100h, etc.; the second time T21 is after the end of the first blank phase BP1, and the time interval D2 between the second time T21 and the end of the first blank phase BP1 can be 1h, 20h, 50h or 100h, etc.

[0141] The row scan time of 1h for the first scan signal can be the time required to scan one row of pixel circuits. The row scan time of 1h for the first scan signal can also be the minimum time interval between the start times of the conduction pulses of the first scan signals corresponding to two adjacent rows of pixel circuits. The first scan circuit can be used to output the first scan signal. The row scan time of the first scan signal can be the minimum time interval between the start times of the conduction pulses of the first scan signals output by two adjacent shift registers in the first scan circuit.

[0142] In one embodiment, within a refresh frame, the first scan signal corresponding to the same pixel circuit 100 includes multiple first pulses. Specifically, the number of first pulses can be 2, 3, or 4, etc.

[0143] In one embodiment, see Figure 14 The pulse width D of the first pulse is greater than or equal to 4h, where 1h is the row scanning time of the first scan signal. SP1-x and SP1-x+1 can be the first scan signals corresponding to two adjacent rows of pixel circuits (which can be located in the first region Z1). SP1-x+y can be the first scan signal corresponding to one row of pixel circuits (which can be located in the first region Z1). y can be greater than the ratio of the first blank stage BP1 to the row scanning time 1h of the first scan signal. By setting a first pulse with a larger pulse width, the pulse width can be greater than the time it takes for the voltage output to the first voltage line Vref to gradually change from the first voltage to the second voltage, and the pulse width can be greater than the time it takes for the voltage on the first voltage line Vref to gradually change from the second voltage to the first voltage, so as to reduce the influence of voltage fluctuations output to the first voltage line Vref on the voltage written to the first voltage line Vref by the pixel circuit.

[0144] Please see Figure 15 and Figure 16 In one embodiment, the pixel circuit 100 includes a first initialization module 310. The control terminal of the first initialization module 310 is connected to the first scan line SP1, the first terminal of the first initialization module 310 is connected to the first initialization signal line Vref1, and the second terminal of the first initialization module 310 is connected to the first electrode 110A of the light-emitting device 110. The first initialization module 310 is used to initialize the first electrode 110A of the light-emitting device 110. The pulse signal of the first scan signal can be the turn-on pulse of the first initialization module 310.

[0145] In one embodiment, the pixel circuit 100 further includes a driving module 320 and a second initialization module 330. The driving module 320 is connected between the first power signal line ELVDD and the first electrode 110A of the light-emitting device 110. The control terminal of the second initialization module 330 is connected to the first scan line SP1, the first terminal of the second initialization module 330 is connected to the second initialization signal line Vref2, and the second terminal of the second initialization module 330 is connected to either the first or second terminal of the driving module 320. The driving module 320 is used to provide the current for driving the light-emitting device 110 to emit light, and the second initialization module 330 is used to initialize the first terminal of the driving module 320 (see reference). Figure 16 ) or the second end (see reference) Figure 15 Initialization is performed. Optionally, the first voltage line Vref is the second initialization signal line Vref2. In response to the pulse signal of the first scan signal, the pixel circuit 100 writes the voltage on the first voltage line Vref into the first or second terminal of the driving module 320 of the pixel circuit 100.

[0146] In one embodiment, the pixel circuit 100 further includes a data writing module 340. The control terminal of the data writing module 340 is connected to the second scan line SP2, the first terminal of the data writing module 340 is connected to the data signal line Data, and the second terminal of the data writing module 340 is connected to the first terminal of the driving module 320. The data writing module 340 is used to provide data voltage to the driving module 320.

[0147] In one embodiment, the pixel circuit 100 further includes a storage module 350. A first terminal of the storage module 350 is connected to a first power signal line ELVDD, and a second terminal of the storage module 350 is connected to the control terminal of the drive module 320. The storage module 350 is used to store the voltage at the control terminal of the drive module 320.

[0148] In one embodiment, the pixel circuit 100 further includes a threshold compensation module 360. The control terminal of the threshold compensation module 360 ​​is connected to the third scan line SP3, and the first terminal of the threshold compensation module 360 ​​is connected to the second terminal of the driving module 320. The second terminal of the threshold compensation module 360 ​​is also connected to the control terminal of the driving module 320. The threshold compensation module 360 ​​is used to perform threshold compensation on the driving module 320.

[0149] In one embodiment, the pixel circuit 100 further includes a third initialization module 370. The control terminal of the third initialization module 370 is connected to the fourth scan line SP4, the first terminal of the third initialization module 370 is connected to the third initialization signal line Vref3, and the second terminal of the third initialization module 370 is connected to the first terminal of the threshold compensation module 360. The third initialization module 370 is used to initialize the control terminal of the driving module 320.

[0150] In one embodiment, the pixel circuit 100 further includes a first light-emitting control module 380 and / or a second light-emitting control module 390. The control terminal of the first light-emitting control module 380 is connected to the light-emitting control signal line EM, the first end of the first light-emitting control module 380 is connected to the first power signal line ELVDD, and the second end of the first light-emitting control module 380 is connected to the first end of the driving module 320. The control terminal of the second light-emitting control module 390 is connected to the light-emitting control signal line EM, the first end of the second light-emitting control module 390 is connected to the second end of the driving module 320, and the second end of the second light-emitting control module 390 is connected to the first electrode 110A of the light-emitting device 110. The first light-emitting control module 380 and the second light-emitting control module 390 are used to connect the first power signal line ELVDD to the light-emitting device 110, and to control the light emission of the light-emitting device 110.

[0151] Specifically, the first initialization module 310, the driving module 320, the second initialization module 330, the data writing module 340, the threshold compensation module 360, the third initialization module 370, the first light-emitting control module 380, and the second light-emitting control module 390 are modules that may include transistors, which may be P-type transistors or N-type transistors, for example. Figure 15 or Figure 16 As shown, the first initialization module 310 includes a first transistor T1, the driving module 320 includes a second transistor T2, the second initialization module 330 includes a third transistor T3, the data writing module 340 includes a fourth transistor T4, the threshold compensation module 360 ​​includes a fifth transistor T5, the third initialization module 370 includes a sixth transistor T6, the first light-emitting control module 380 includes a seventh transistor T7, and the second light-emitting control module 390 includes an eighth transistor T8. The storage module 350 includes a capacitor Cst for storing the voltage at the control terminal of the driving module 320, and the second terminal of the light-emitting device 110 is also connected to the second power signal line ELVSS. For example, the fifth transistor T5 and the sixth transistor T6 can be N-type transistors, and the remaining transistors can be P-type transistors.

[0152] In one embodiment, see Figure 17 and Figure 18 Within a refresh frame, after the data writing phase, the first scan signal corresponding to the same pixel circuit 100 includes multiple first pulses, such as N first pulses.

[0153] In one embodiment, the number of first pulses of the first scan signal corresponding to the same pixel circuit 100 after the data writing stage is greater than or equal to 2. Specifically, the number of first pulses can be 2, 3, or 5, etc. Figure 17 and Figure 18An exemplary drawing shows that, after the data writing phase, the first scan signal corresponding to the same pixel circuit 100 includes three first pulses.

[0154] Optionally, N equals the number of the first pulses.

[0155] Optional, M = N-1.

[0156] Combination Figures 15 to 18 The refresh frame includes a gate initialization phase for the second transistor T2 (not shown), a data writing phase w1, followed by a first initialization phase h1, a second initialization phase h2, a third initialization phase h3 for the first electrode of the light-emitting device, and a light-emitting phase. For example, combined with... Figure 9 and Figure 18 In the first period Figure 9 The first region Z1 at the top can be equated to the third initialization phase h3, the first region Z1 in the middle can be equated to the second initialization phase h2, and the first region Z1 at the bottom can be equated to the first initialization phase h1. (Combined...) Figure 10 and Figure 17 In the second period, Figure 10 The upper second region Z2 in the diagram can be considered equivalent to the third initialization stage h3, and the lower second region Z2 can be considered equivalent to the second initialization stage h2. Specifically, in the third initialization stage h3 of the pixel circuit in the second region Z2, the voltage output to the first voltage line Vref by the power supply module or driver chip is the second voltage V2. Furthermore, the holding frame includes multiple initialization stages and light-emitting stages for the first electrode of the light-emitting device. The holding frame does not include the second transistor T2 gate initialization stage (not shown) and the data writing stage. See also... Figure 17 During the refresh frame, in the partial initialization phase of the first electrode of the light-emitting device in the second region Z2, the voltage output by the power supply module or driver chip to the first voltage line Vref is the second voltage V2; during the partial initialization phase of the first electrode of the light-emitting device in the second region Z2, the voltage output by the power supply module or driver chip to the first voltage line Vref is the first voltage V1; during the hold frame, in each initialization phase of the first electrode of the light-emitting device in the second region Z2, the voltage output by the power supply module or driver chip to the first voltage line Vref is the third voltage V3. (See also...) Figure 18 During the refresh frame and hold frame, at each initialization stage of the first electrode of the light-emitting device in the first region Z1, the voltage output to the first voltage line Vref by the power module or driver chip is the first voltage V1.

[0157] The widths of the M second regions Z2 along the first direction X can be equal. The width of the second region Z2 along the first direction X can be equal to the width of the Vblank region along the first direction X. The number of rows of pixel circuits in the second region Z2 can be equal to the ratio of the first blanking stage BP1 to the line scan time (1h) of the first scan signal. The number of rows of pixel circuits in the first region Z1 can be equal to the ratio of the time interval between corresponding pulse signals of the first scan signal to the line scan time (1h) of the first scan signal, minus the number of rows of pixel circuits in the second region Z2. For example, Figure 10 The number of rows of pixel circuits in the bottommost region Z1 can be equal to the ratio of the time interval between the pulse signal corresponding to the second initialization stage h2 and the pulse signal corresponding to the third initialization stage h3 to the row scanning time (1h) of the first scan signal, minus the number of rows of pixel circuits in the second region Z2. The positions of the first region Z1 and the second region Z2 can be determined based on the pulse signal waveform of the first scan signal.

[0158] Please see Figure 19 and Figure 20 This application provides another driving method for a display panel 10. Based on the above embodiments, the display area AA of the display panel 10 includes N first areas Z1 and M second areas Z2 arranged alternately along the first direction X, where N is greater than M and N and M are positive integers. A first area Z1 (which may be each first area Z1) includes a first boundary area B1, a first intermediate area M1 and a second boundary area B2 arranged sequentially along the first direction X. Optionally, a second area Z2 (which may be each second area Z2) includes a third boundary area B3, a second intermediate area M2 and a fourth boundary area B4 arranged sequentially along the first direction X. In adjacent first areas Z1 and second areas Z2, the second boundary area B2 and the third boundary area B3 are adjacent, or the first boundary area B1 and the fourth boundary area B4 are adjacent. A screen refresh cycle includes a refresh frame.

[0159] The driving method provided in this application includes:

[0160] See Figure 19 Within a refresh frame, during the first time period T1, a first scan signal is simultaneously output to the first intermediate area M1 of the N intervals of the first area Z1, so that the pixel circuit 100 of the first intermediate area M1 of the first area Z1 responds to the pulse signal of the first scan signal and writes the voltage on the first voltage line Vref into the pixel circuit 100.

[0161] See Figure 20 In a second time period T2, which is different from the first time period T1, a first scan signal is simultaneously output to the second intermediate area M2 of the M intervals of the second area Z2, so that the pixel circuit 100 of the second intermediate area M2 of the second area Z2 responds to the pulse signal of the first scan signal and writes the voltage on the first voltage line Vref into the pixel circuit 100.

[0162] During the first time period T1, the first scan signal activation pulse is not output to the pixel circuit 100 of the second region Z2. During the second time period T2, the first scan signal activation pulse is not output to the pixel circuit 100 of the first region Z1.

[0163] Please combine Figures 21 to 22 The driving method of this application also includes:

[0164] See Figure 21 At a first time T11 between the first time period T1 and the second time period T2, at least N first scan signals are simultaneously output to the second boundary regions B2 of the first region Z1, so that the pixel circuits 100 of the second boundary regions B2 of the first region Z1 respond to the pulse signal of the first scan signal and write the voltage on the first voltage line Vref into the pixel circuits 100; the voltage output to the first voltage line Vref gradually changes from the first voltage V1 to the second voltage V2 at the first time T11, and / or, please refer to Figure 22 At the second time T21 after the second time period T2, a first scan signal is simultaneously output to at least part of the first boundary region B1 and / or the first intermediate region M1 of the first region Z1, so that the pixel circuit 100 of the first boundary region B1 and / or the first intermediate region M1 of the first region Z1 responds to the pulse signal of the first scan signal and writes the voltage on the first voltage line Vref into the pixel circuit 100; the voltage output to the first voltage line Vref gradually changes from the second voltage V2 to the first voltage V1 at the second time T21.

[0165] See Figure 21 The first moment T11 corresponds to the moment before the pulse signals b and c of the first scan signal fully enter the second region Z2, the moment before the pulse signal a of the first scan signal fully enters the Vblank region, and the moment when the pulse signals b and c of the first scan signal at least partially scan to the second boundary region B2 of the first region Z1. Before the pulse signal a fully enters the Vblank region, the voltage of the voltage line Vref is compensated in advance to improve the problem of the brightness difference between the third boundary region B3 of the second region Z2 and the second intermediate region M. At the first moment T11, the conduction pulse of the first scan signal may not be output to the pixel circuit 100 of the second region Z2.

[0166] See Figure 22The second time T21 corresponds to the time after the pulse signals b and c of the first scan signal completely leave the second region Z2, and the time before the pulse signal a of the first scan signal completely leaves the Vblank region. It also corresponds to the time when the pulse signals b and c of the first scan signal at least partially scan to the first boundary region B1 and / or the first intermediate region M1 of the second region Z2. After the pulse signals b and c completely leave the second region Z2, and after the pulse signal a completely leaves the Vblank region, the voltage of the voltage line Vref is restored to the pre-compensation voltage level to improve the brightness difference between the fourth boundary region B4 and the second intermediate region M of the second region Z2. At the second time T21, the conduction pulse of the first scan signal may not be output to the pixel circuit 100 of the second region Z2.

[0167] Optional, see below Figure 23 At the first moment T11 between the first time period T1 and the second time period T2, a first scan signal is simultaneously output to the third boundary regions B3 of M second regions Z2 and the second boundary regions B2 of N first regions Z1, so that the pixel circuits 100 of the third boundary regions B3 of the second regions Z2 and the second boundary regions B2 of the first regions Z1 respond to the pulse signal of the first scan signal and write the voltage on the first voltage line Vref into the pixel circuits 100; the voltage output to the first voltage line Vref gradually changes from the first voltage V1 to the second voltage V2 at the first moment T11.

[0168] Optional, please refer to Figure 24 At the second time T21 after the second time period T2, a first scan signal is simultaneously output to at least part of the first intermediate region M1 of the first region Z1, so that the pixel circuit 100 of the first intermediate region M1 of the first region Z1 responds to the pulse signal of the first scan signal and writes the voltage on the first voltage line Vref into the pixel circuit 100; the voltage output to the first voltage line Vref gradually changes from the second voltage V2 to the first voltage V1 at the second time T21.

[0169] See Figure 23 The first moment T11 corresponds to the moment before the pulse signals b and c of the first scan signal fully enter the second region Z2, and the moment before the pulse signal a of the first scan signal fully enters the Vblank region. It also corresponds to the moment when the pulse signals b and c of the first scan signal reach the second boundary region B2 of the first region Z1 and the third boundary region B3 of the second region Z2. Before pulse signal a fully enters the Vblank region, the voltage of the voltage line Vref is compensated in advance to improve the brightness difference between the third boundary region B3 of the second region Z2 and the second intermediate region M.

[0170] See Figure 24The second time T21 corresponds to the time after the pulse signals b and c of the first scan signal completely leave the second region Z2, and the time before the pulse signal a of the first scan signal completely leaves the Vblank region. It also corresponds to the time when the pulse signals b and c of the first scan signal scan at least part of the first intermediate region M1 of the first region Z1. After the pulse signals b and c completely leave the second region Z2, and after the pulse signal a completely leaves the Vblank region, the voltage of the voltage line Vref is restored to the pre-compensation voltage level to improve the brightness difference between the fourth boundary region B4 of the second region Z2 and the second intermediate region M. At the second time T21, the conduction pulse of the first scan signal may not be output to the pixel circuit 100 of the second region Z2 and the first boundary region B1.

[0171] Please see Figure 12 The screen refresh cycle also includes a holding frame; the driving method of this application further includes: within a holding frame, in the third time period T3, outputting a first scan signal to the second region Z2, so that the pixel circuit 100 of the second region Z2 responds to the pulse signal of the first scan signal and writes the voltage on the first voltage line Vref into the pixel circuit 100; the voltage output to the first voltage line Vref in the third time period T3 is different from the voltage output to the first voltage line Vref in the first time period T1.

[0172] Specifically, unlike the refresh frame, the hold frame does not write data voltage to the pixel circuit 100. During the third time period T3, the voltage output by the power supply module or driver chip to the first voltage line Vref can be... Figure 12 The third voltage V3 in the frame differs from the voltage output to the first voltage line Vref during the first time period T1, to further improve the multi-screen problem. The absolute value of the third voltage V3 can be less than the absolute value of the first voltage V1. The second region Z2 can be the brightness compensation area, equivalent to the mura area. Therefore, when the voltage of the first voltage line Vref is written into the pixel circuit of the second region Z2 of the holding frame, the voltage output to the first voltage line Vref can be further compensated to further improve the multi-screen problem.

[0173] Further reading Figure 12 The driving method of this application further includes: during a holding frame, in the fourth time period T4, outputting a first scan signal to the first region Z1, so that the pixel circuit 100 of the first region Z1 responds to the pulse signal of the first scan signal and writes the voltage on the first voltage line Vref into the pixel circuit 100.

[0174] Optionally, the voltage output to the first voltage line Vref in the fourth time period T4 is different from the voltage output to the first voltage line Vref in the third time period T3.

[0175] Optionally, the voltage output to the first voltage line Vref in the fourth time period T4 is the same as the voltage output to the first voltage line Vref in the first time period T1. The first region Z1 can be a non-mura region, so when the pixel circuit of the first region Z1 of the holding frame writes the voltage to the first voltage line Vref, it is not necessary to compensate the voltage output to the first voltage line Vref.

[0176] In one embodiment, the absolute value of the voltage output to the first voltage line Vref during the third time period T3 is less than the absolute value of the voltage output to the first voltage line Vref during the first time period T1.

[0177] Specifically, there are two scenarios. First, if the voltage output to the first voltage line Vref in the first time period T1 is negative, then the voltage output to the first voltage line Vref in the third time period T3 will be a negative voltage with a smaller absolute value. Second, if the voltage output to the first voltage line Vref in the first time period T1 is positive, then the voltage output to the first voltage line Vref in the third time period T3 will be a positive voltage with a smaller absolute value.

[0178] In one embodiment, within a hold frame, the first scan signal corresponding to the same pixel circuit 100 includes a plurality of second pulses. Specifically, the number of second pulses can be 2, 3, or 4, etc.

[0179] Furthermore, the first voltage V1 is different from the second voltage V2. The voltage output to the first voltage line Vref during the first and second time periods is different, which can improve the brightness difference between the first zone Z1 and the second zone Z2 and improve the multi-screen phenomenon.

[0180] Optionally, the first voltage V1 output to the first voltage line Vref in the first time period T1 is different from the second voltage V2 output to the first voltage line Vref in the second time period T2.

[0181] In one embodiment, the absolute value of the first voltage V1 is greater than the absolute value of the second voltage V2.

[0182] Specifically, when the first voltage V1 is positive, the absolute value of the second voltage V2 is a smaller positive value; when the first voltage V1 is negative, the absolute value of the second voltage V2 is a smaller negative value.

[0183] In one embodiment, the absolute value of the first voltage V1 output to the first voltage line Vref in the first time period T1 is greater than the absolute value of the second voltage V2 output to the first voltage line Vref in the second time period T2. This is equivalent to scanning N first regions Z1 simultaneously in the first time period T1, resulting in a larger load and requiring a larger absolute value of the voltage output to the first voltage line Vref; and scanning M second regions Z2 simultaneously in the second time period T2, resulting in a smaller load and requiring a smaller absolute value of the voltage output to the first voltage line Vref, thus ensuring that the voltage values ​​written to the pixel circuits of the first regions Z1 and the second regions Z2 are the same or similar.

[0184] In one embodiment, see Figure 13 The first voltage line Vref is the first initialization signal line Vref1. In response to the pulse signal of the first scan signal, the pixel circuit 100 writes the voltage on the first voltage line Vref into the first electrode 110A of the light-emitting device 110 of the pixel circuit 100.

[0185] Specifically, the voltage on the first initialization signal line Vref1 is used to initialize the first electrode 110A of the light-emitting device 110. For example, the first electrode 110A can be the anode of the light-emitting device 110. When the first voltage line Vref is the first initialization signal line Vref1, the phenomenon of multiple screens caused by the different initialization degree of the first electrode 110A of the light-emitting device 110 in the pixel circuit 100 of the first region Z1 and the second region Z2 can be improved, so as to ensure that the initialization degree of the first electrode 110A of the light-emitting device 110 in the pixel circuit 100 of the first region Z1 and the second region Z2 is the same or similar.

[0186] In one embodiment, the first voltage V1 is less than the second voltage V2. That is, when both the first voltage V1 and the second voltage V2 are negative, the first voltage V1 is less than the second voltage V2.

[0187] In one embodiment, the first voltage V1 output to the first voltage line Vref in the first time period T1 is less than the second voltage V2 output to the first voltage line Vref in the second time period T2.

[0188] In one embodiment, see Figure 2 A refresh frame includes an active phase AP and a first blank phase BP1. A first time period T1 is located in the active phase AP. At least a portion of the second time period T2 is located in the first blank phase BP1. A first time point T11 is before the first blank phase BP1, and / or a second time point T21 is after the first blank phase BP1, and the second time point T21 is after the second time period T2.

[0189] Specifically, due to Figure 1 and Figure 2In these two cases, the number of rows of pixel circuit 100 written by the voltage on the first voltage line Vref is different, which is equivalent to the different load size of the first voltage line Vref in the first time period and the second time period. Therefore, if the voltage on the first voltage line Vref is the same in the above two cases, it will inevitably cause display differences. Therefore, in the first time period T1 of the effective phase AP (e.g., corresponding to...), Figure 19 (Operating state) Input the first voltage V1, during the second time period T2 of the first blank phase BP1 (e.g., corresponding to the working state) Figure 20 (In the working state) Input a second voltage V2. The first voltage V1 is different from the second voltage V2 to improve the display difference caused by the above two situations and improve the multi-screen phenomenon. The specific voltage value can be adjusted according to the display effect.

[0190] In one embodiment, the second boundary region B2 is provided with more than or equal to 1 row of pixel circuits and less than or equal to 100 rows of pixel circuits; and / or, the first boundary region B1 is provided with more than or equal to 1 row of pixel circuits and less than or equal to 100 rows of pixel circuits; the first direction X is perpendicular to the row direction.

[0191] For example, the second boundary region B2 has more than or equal to k1 rows of pixel circuits and less than or equal to 100 rows of pixel circuits; and / or, the first boundary region B1 has more than or equal to k2 rows of pixel circuits and less than or equal to 100 rows of pixel circuits; the first direction X is perpendicular to the row direction. Optionally, k1 can be 1, 10, 20, 30, 40, or 50. Optionally, k2 can be 1, 10, 20, 30, 40, or 50.

[0192] Specifically, the row pixel circuits included in the second boundary region B2 can be 1, 20, 50 or 100, etc.; the row pixel circuits included in the first boundary region B1 can be 1, 20, 50 or 100, etc.

[0193] For example, at the first moment, in the pixel circuits of the first region Z1 that receive the conduction pulse of the first scan signal, the distance between the row of pixel circuits farthest from the first boundary line L1 and the first boundary line L1 is greater than or equal to k5 rows of pixel circuits and less than or equal to 100 rows of pixel circuits. The first boundary line L1 may be the boundary line between the second boundary region B2 of the first region Z1 and its adjacent third boundary region B3. For example, at the second moment, in the pixel circuits of the first region Z1 that receive the conduction pulse of the first scan signal, the distance between the row of pixel circuits closest to the second boundary line L2 and the second boundary line L2 is greater than or equal to k6 rows of pixel circuits and less than or equal to 100 rows of pixel circuits. The second boundary line L2 may be the boundary line between the first boundary region B1 of the first region Z1 and its adjacent fourth boundary region B4. Optionally, k5 may be 1, 10, 20, 30, 40, or 50. Optionally, k6 may be 1, 10, 20, 30, 40, or 50.

[0194] In one embodiment, the first time T11 is before the start time of the first blank stage BP1, and the time interval D1 between the first time T11 and the start time of the first blank stage BP1 is greater than or equal to 1h and less than or equal to 100h, where 1h is the line scan time of the first scan signal; and / or, the second time T21 is after the end time of the first blank stage BP1, and the time interval D2 between the second time T21 and the end time of the first blank stage BP1 is greater than or equal to 1h and less than or equal to 100h, where 1h is the line scan time of the first scan signal.

[0195] Optionally, the first time point T11 is before the start of the first blank phase BP1, and the time interval D1 between the first time point T11 and the start of the first blank phase BP1 is greater than or equal to k3*h and less than or equal to 100h. And / or, the second time point T21 is after the end of the first blank phase BP1, and the time interval D2 between the second time point T21 and the end of the first blank phase BP1 is greater than or equal to k4*h and less than or equal to 100h. Optionally, k3 can be 1, 10, 20, 30, 40, or 50. Optionally, k4 can be 1, 10, 20, 30, 40, or 50.

[0196] Specifically, the first time T11 is before the start of the first blank phase BP1, and the time interval D1 between the first time T11 and the start of the first blank phase BP1 can be 1h, 20h, 50h or 100h, etc.; the second time T21 is after the end of the first blank phase BP1, and the time interval D2 between the second time T21 and the end of the first blank phase BP1 can be 1h, 20h, 50h or 100h, etc.

[0197] In one embodiment, see Figure 17 and Figure 18 Within a single refresh frame, the first scan signal corresponding to the same pixel circuit 100 includes multiple first pulses. Specifically, the number of first pulses can be 2, 3, or 4, etc.

[0198] In one embodiment, see Figure 14The pulse width D of the first pulse is greater than or equal to 4h, where 1h is the row scanning time of the first scan signal. SP1-x and SP1-x+1 can be the first scan signals corresponding to two adjacent rows of pixel circuits (which can be located in the first region Z1). SP1-x+y can be the first scan signal corresponding to one row of pixel circuits (which can be located in the first region Z1). By setting a first pulse with a larger pulse width, the pulse width can be greater than the time it takes for the voltage output to the first voltage line Vref to gradually change from the first voltage to the second voltage, and the pulse width can be greater than the time it takes for the voltage on the first voltage line Vref to gradually change from the second voltage to the first voltage, so as to reduce the influence of voltage fluctuations output to the first voltage line Vref on the voltage written to the first voltage line Vref by the pixel circuit.

[0199] In one embodiment, see Figure 17 and Figure 18 Within a refresh frame, after the data writing phase, the first scan signal corresponding to the same pixel circuit 100 includes multiple first pulses.

[0200] In one embodiment, see Figure 17 and Figure 18 For the first scan signal corresponding to the same pixel circuit 100, the number of the first pulses after the data writing stage is greater than or equal to 2. Specifically, the number of the first pulses can be 2, 3, or 5, etc.

[0201] Optionally, N equals the number of the first pulses. Optionally, M = N-1.

[0202] Please see Figure 9 , Figure 10 , Figure 12 , Figure 19 and Figure 20 This application provides another driving method for a display panel 10. Based on the above embodiments, the display area AA of the display panel 10 includes N first areas Z1 and M second areas Z2 arranged alternately along the first direction X, where N is greater than M and N and M are positive integers; a screen refresh cycle includes a refresh frame.

[0203] The driving method provided in this application includes:

[0204] See Figure 9 and Figure 19 Within a refresh frame, during the first time period T1, a first scan signal is simultaneously output to the first intermediate area M1 of the N intervals of the first area Z1, so that the pixel circuit 100 of the first intermediate area M1 of the first area Z1 responds to the pulse signal of the first scan signal and writes the voltage on the first voltage line Vref into the pixel circuit 100.

[0205] See Figure 10 and Figure 20In a second time period T2, which is different from the first time period T1, a first scan signal is simultaneously output to the second intermediate area M2 of the M intervals of the second area Z2, so that the pixel circuit 100 of the second intermediate area M2 of the second area Z2 responds to the pulse signal of the first scan signal and writes the voltage on the first voltage line Vref into the pixel circuit 100.

[0206] During the holding frame, in the third time period T3, the first scan signal is output to the second region Z2 so that the pixel circuit 100 of the second region Z2 responds to the pulse signal of the first scan signal and writes the voltage on the first voltage line Vref into the pixel circuit 100.

[0207] See Figure 12 The voltage output to the first voltage line Vref in the second time period T2 is different from the voltage output to the first voltage line Vref in the first time period T1.

[0208] The voltage output to the first voltage line Vref in the third time period T3 is different from the voltage output to the first voltage line Vref in the first time period T1. The second region Z2 can be the brightness compensation area, equivalent to the mura region. Therefore, when the pixel circuit in the second region Z2 of the hold frame writes the voltage to the first voltage line Vref, further compensation can be performed on the voltage output to the first voltage line Vref to further improve the multi-screen problem. Specifically, in the refresh frame, the voltage output to the first voltage line Vref in the second time period T2 is different from the voltage output to the first voltage line Vref in the first time period T1; in the hold frame, unlike the refresh frame, the hold frame no longer writes data voltage to the pixel circuit 100. The voltage output to the first voltage line Vref in the third time period T3 can be... Figure 12 The third voltage V3 in the equation can, of course, be any other voltage.

[0209] During the first time period T1, the first scan signal activation pulse is not output to the pixel circuit 100 of the second region Z2. During the second time period T2, the first scan signal activation pulse is not output to the pixel circuit 100 of the first region Z1.

[0210] Optionally, within a hold frame, in the fourth time period T4, a first scan signal is output to the pixel circuit 100 of the first region Z1, so that the pixel circuit 100 of the first region Z1 responds to the pulse signal of the first scan signal and writes the voltage on the first voltage line Vref into the pixel circuit 100.

[0211] Optionally, the voltage output to the first voltage line Vref in the fourth time period T4 is different from the voltage output to the first voltage line Vref in the third time period T3.

[0212] Optionally, the voltage output to the first voltage line Vref in the fourth time period T4 is the same as the voltage output to the first voltage line Vref in the first time period T1. The first region Z1 can be a non-mura region; therefore, when the pixel circuit of the first region Z1 of the holding frame writes the voltage to the first voltage line Vref, compensation for the voltage output to the first voltage line Vref is not required. In one embodiment, a refresh frame includes an active phase AP and a first blank phase BP1, the first time period T1 is located in the active phase AP, and at least a portion of the second time period T2 is located in the first blank phase BP1.

[0213] In one embodiment, within a refresh frame, after the data writing phase, the first scan signal corresponding to the same pixel circuit 100 includes multiple first pulses.

[0214] In one embodiment, the number of first pulses of the first scan signal corresponding to the same pixel circuit 100 after the data writing stage is greater than or equal to 2. Specifically, the number of first pulses can be 2, 3, or 5, etc.

[0215] Furthermore, N equals the number of the first pulses.

[0216] In one embodiment, within a refresh frame, the first scan signal corresponding to the same pixel circuit 100 includes multiple first pulses. Specifically, the number of first pulses can be 2, 3, or 4, etc.

[0217] In one embodiment, within a hold frame, the first scan signal corresponding to the same pixel circuit 100 includes a plurality of second pulses. Specifically, the number of second pulses can be 2, 3, or 4, etc.

[0218] The display panel and pixel circuit involved in the driving method of the display panel 10 in the above embodiments have the same or similar structures and functions, which will not be described again here.

[0219] See Figure 25 This application also provides a display device 1000, which includes a display panel 10 and a display driving module 20. The display driving module 20 is used to execute the driving method of the display panel 10 as described in any of the above embodiments. The detailed steps can be found in the above embodiments and will not be repeated here.

[0220] The display device 1000 may include devices such as computers, mobile phones, smartwatches, and tablets, and the display driver module 20 may be a chip with logic processing capabilities, etc., without limitation.

[0221] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

[0222] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A driving method for a display panel, characterized in that, The display panel includes: Multiple pixel circuits arranged in an array; Multiple first scan lines, each first scan line being electrically connected to the pixel circuit of the corresponding row; A first voltage line is electrically connected to the pixel circuit. The pixel circuit is used to write the voltage on the first voltage line into the pixel circuit in response to the pulse signal of the first scan signal on the first scan line. The first voltage line is a first initialization signal line. The pixel circuit writes the voltage on the first voltage line into the first electrode of the light-emitting device of the pixel circuit in response to the pulse signal of the first scan signal. The driving method includes: The first voltage output to the first voltage line in the first time period is different from the second voltage output to the first voltage line in the second time period; A screen refresh cycle includes a refresh frame; a refresh frame includes an active phase and a first blank phase, the first time period is located in the active phase, at least a portion of the second time period is located in the first blank phase, the voltage output to the first voltage line gradually changes from a first voltage to a second voltage at a first moment, the first moment is located between the first time period and the second time period, the first moment is before the first blank phase, and / or, the voltage output to the first voltage line gradually changes from a second voltage to a first voltage at a second moment, the second moment is located after the second time period, the second moment is after the first blank phase; Wherein, the time interval between the first moment and the start moment of the first blank phase is greater than or equal to 1 hour and less than or equal to 100 hours, where 1 hour is the line scan time of the first scan signal; and / or, the time interval between the second moment and the end moment of the first blank phase is greater than or equal to 1 hour and less than or equal to 100 hours, where 1 hour is the line scan time of the first scan signal.

2. The driving method for the display panel according to claim 1, characterized in that, A screen refresh cycle also includes holding frames; The driving method further includes: Within one of the holding frames, the voltage output to the first voltage line in the third time period is different from the voltage output to the first voltage line in the first time period.

3. The driving method for the display panel according to claim 2, characterized in that, Within one of the holding frames, the voltage output to the first voltage line includes one or more third pulses.

4. The driving method for the display panel according to claim 2, characterized in that, The display panel includes N first areas and M second areas arranged alternately along a first direction, where N is greater than M and N and M are positive integers. Within one of the holding frames, during a third time period, a first scan signal is output to the pixel circuit of the second region, causing the pixel circuit of the second region to respond to the pulse signal of the first scan signal and write the voltage on the first voltage line into the pixel circuit. The driving method further includes: Within one of the holding frames, in the fourth time period, a first scan signal is output to the pixel circuit of the first region, so that the pixel circuit of the first region responds to the pulse signal of the first scan signal and writes the voltage on the first voltage line into the pixel circuit. The voltage output to the first voltage line in the fourth time period is different from the voltage output to the first voltage line in the third time period; The voltage output to the first voltage line in the fourth time period is the same as the voltage output to the first voltage line in the first time period.

5. The driving method for a display panel according to claim 2, characterized in that, The absolute value of the voltage output to the first voltage line in the third time period is less than the absolute value of the voltage output to the first voltage line in the first time period.

6. The driving method for a display panel according to claim 2, characterized in that, Within a holding frame, the first scan signal corresponding to the same pixel circuit includes multiple second pulses.

7. The driving method for a display panel according to claim 1, characterized in that, The display panel includes N first areas and M second areas arranged alternately along a first direction, where N is greater than M, and N and M are positive integers; the driving method includes: In the first time period, a first scan signal is simultaneously output to the pixel circuits of N first regions at intervals, so that the pixel circuits of the first regions respond to the pulse signal of the first scan signal and write the voltage on the first voltage line into the pixel circuit. During the second time period, a first scan signal is simultaneously output to the pixel circuits of the M second zones at intervals, so that the pixel circuits of the second zones respond to the pulse signal of the first scan signal and write the voltage on the first voltage line into the pixel circuit.

8. The driving method for a display panel according to claim 7, characterized in that, The absolute value of the first voltage output to the first voltage line in the first time period is greater than the absolute value of the second voltage output to the first voltage line in the second time period.

9. The driving method for a display panel according to claim 7, characterized in that, The row scanning time 1h of the first scanning signal is the minimum time interval between the start times of the conduction pulses of the first scanning signal corresponding to two adjacent row pixel circuits, and / or, the row scanning time of the first scanning signal is the minimum time interval between the start times of the conduction pulses of the first scanning signal output by two adjacent shift registers in the first scanning circuit. The first moment is before the start of the first blank phase, and the time interval between the first moment and the start of the first blank phase is greater than or equal to k3. h, less than or equal to 100h, and / or, the second time is after the end time of the first blank phase, and the time interval between the second time and the end time of the first blank phase is greater than or equal to k4. h is less than or equal to 100h, k3 is 10, 20, 30, 40 or 50, and k4 is 10, 20, 30, 40 or 50.

10. The driving method for a display panel according to claim 7, characterized in that, The first voltage output to the first voltage line in the first time period is less than the second voltage output to the first voltage line in the second time period.

11. The driving method for a display panel according to claim 7, characterized in that, Within a refresh frame, the first scan signal corresponding to the same pixel circuit includes multiple first pulses; the pulse width of the first pulse is greater than or equal to 4h, where 1h is the row scan time of the first scan signal.

12. The driving method for a display panel according to claim 11, characterized in that, Within a refresh frame, after the data writing phase, the first scan signal corresponding to the same pixel circuit includes multiple first pulses; the number of first pulses corresponding to the same pixel circuit after the data writing phase is greater than or equal to 2.

13. The driving method for a display panel according to claim 12, characterized in that, N equals the number of the first pulses; M = N-1.

14. The driving method for a display panel according to claim 1, characterized in that, When the first blank phase is the maximum refresh rate of the display panel, it is the time period from the last row of pixel circuit data writing stage of the display panel in the previous refresh frame to the first row of pixel circuit data writing stage of the display panel in the next refresh frame.

15. The driving method for a display panel according to claim 1, characterized in that, The pixel circuit includes a first initialization module, the control terminal of the first initialization module is connected to the first scan line, the first terminal of the first initialization module is connected to the first initialization signal line, and the second terminal of the first initialization module is connected to the first electrode of the light-emitting device. The pixel circuit further includes a driving module and a second initialization module. The driving module is connected between the first power signal line and the first electrode of the light-emitting device. The control terminal of the second initialization module is connected to the first scan line. The first terminal of the second initialization module is connected to the second initialization signal line. The second terminal of the second initialization module is connected to the first or second terminal of the driving module. The pixel circuit also includes a data writing module, the control terminal of which is connected to the second scan line, the first terminal of which is connected to the data signal line, and the second terminal of which is connected to the first terminal of the driving module. The pixel circuit also includes a storage module, a first end of which is connected to the first power signal line, and a second end of which is connected to the control end of the drive module. The pixel circuit also includes a threshold compensation module. The control terminal of the threshold compensation module is connected to the third scan line, the first terminal of the threshold compensation module is connected to the second terminal of the driving module, and the second terminal of the threshold compensation module is connected to the control terminal of the driving module. The pixel circuit further includes a third initialization module, the control terminal of which is connected to the fourth scan line, the first terminal of which is connected to the third initialization signal line, and the second terminal of which is connected to the first terminal of the threshold compensation module. The pixel circuit further includes a first light-emitting control module and / or a second light-emitting control module. The control terminal of the first light-emitting control module is connected to the light-emitting control signal line, the first end of the first light-emitting control module is connected to the first power signal line, the second end of the first light-emitting control module is connected to the first end of the driving module, the control terminal of the second light-emitting control module is connected to the light-emitting control signal line, the first end of the second light-emitting control module is connected to the second end of the driving module, and the second end of the second light-emitting control module is connected to the first electrode of the light-emitting device.

16. A driving method for a display panel, characterized in that, The display panel includes N first areas and M second areas arranged alternately along a first direction, where N is greater than M and N and M are positive integers; each first area includes a first boundary area, a first intermediate area, and a second boundary area arranged sequentially along the first direction; a screen refresh cycle includes a refresh frame; the display panel further includes: a plurality of pixel circuits arranged in an array; a plurality of first scan lines electrically connected to the pixel circuits in corresponding rows; a first voltage line electrically connected to the pixel circuits; the pixel circuits are used to write the voltage on the first voltage line into the pixel circuits in response to a pulse signal of a first scan signal on the first scan line; the first voltage line is a first initialization signal line; the pixel circuits, in response to a pulse signal of the first scan signal, write the voltage on the first voltage line into the first electrode of the light-emitting device of the pixel circuits; the driving method includes: Within a refresh frame, during a first time period, a first scan signal is simultaneously output to the first intermediate area of ​​N spaced-apart first areas, so that the pixel circuit of the first intermediate area of ​​the first area responds to the pulse signal of the first scan signal and writes the voltage on the first voltage line into the pixel circuit. In a second time period different from the first time period, a first scan signal is simultaneously output to the second intermediate area of ​​the M intervals of the second area, so that the pixel circuit of the second intermediate area of ​​the second area responds to the pulse signal of the first scan signal and writes the voltage on the first voltage line into the pixel circuit. The driving method further includes: At a first moment between the first time period and the second time period, at least N second boundary regions of the first region are simultaneously output with a first scan signal, so that the pixel circuits of the N second boundary regions of the first region respond to the pulse signal of the first scan signal and write the voltage on the first voltage line into the pixel circuit; the voltage output to the first voltage line gradually changes from a first voltage to a second voltage at the first moment. And / or, at a second moment after the second time period, simultaneously output a first scan signal to at least a portion of the first boundary region and / or the first intermediate region of the first region, so that the pixel circuit of the first boundary region and / or the first intermediate region of the first region responds to the pulse signal of the first scan signal and writes the voltage on the first voltage line into the pixel circuit; the voltage output to the first voltage line gradually changes from the second voltage to the first voltage at the second moment; The refresh frame includes an active phase and a first blank phase, wherein the first time period is located in the active phase, at least a portion of the second time period is located in the first blank phase, the first moment is before the first blank phase, and / or the second moment is after the first blank phase, and the second moment is located after the second time period; wherein the time interval between the first moment and the start moment of the first blank phase is greater than or equal to 1 hour and less than or equal to 100 hours, where 1 hour is the line scan time of the first scan signal; and / or the time interval between the second moment and the end moment of the first blank phase is greater than or equal to 1 hour and less than or equal to 100 hours, where 1 hour is the line scan time of the first scan signal.

17. The driving method for a display panel according to claim 16, characterized in that, A screen refresh cycle also includes holding frames; The driving method further includes: Within one of the holding frames, during the third time period, a first scan signal is output to the second region, so that the pixel circuit of the second region responds to the pulse signal of the first scan signal and writes the voltage on the first voltage line into the pixel circuit; The voltage output to the first voltage line in the third time period is different from the voltage output to the first voltage line in the first time period.

18. The driving method for a display panel according to claim 17, characterized in that, The driving method further includes: Within one of the holding frames, in the fourth time period, a first scan signal is output to the first region so that the pixel circuit of the first region responds to the pulse signal of the first scan signal and writes the voltage on the first voltage line into the pixel circuit. The voltage output to the first voltage line in the fourth time period is different from the voltage output to the first voltage line in the third time period; The voltage output to the first voltage line in the fourth time period is the same as the voltage output to the first voltage line in the first time period.

19. The driving method for a display panel according to claim 16, characterized in that, The absolute value of the voltage output to the first voltage line in the third time period is less than the absolute value of the voltage output to the first voltage line in the first time period.

20. The driving method for a display panel according to claim 17, characterized in that, Within a holding frame, the first scan signal corresponding to the same pixel circuit includes multiple second pulses.

21. The driving method for a display panel according to claim 16, characterized in that, The second region includes a third boundary region, a second intermediate region, and a fourth boundary region arranged sequentially along the first direction. In adjacent first and second regions, the second boundary region and the third boundary region are adjacent, or the first boundary region and the fourth boundary region are adjacent. At the first moment between the first time period and the second time period, a first scan signal is simultaneously output to the third boundary regions of M second regions and the second boundary regions of N first regions, so that the pixel circuits of the third boundary regions of the second regions and the second boundary regions of the first regions respond to the pulse signal of the first scan signal and write the voltage on the first voltage line into the pixel circuit. The voltage output to the first voltage line gradually changes from the first voltage to the second voltage at the first moment.

22. The driving method for a display panel according to claim 21, characterized in that, The absolute value of the first voltage is greater than the absolute value of the second voltage.

23. The driving method for a display panel according to claim 22, characterized in that, The absolute value of the first voltage output to the first voltage line in the first time period is greater than the absolute value of the second voltage output to the first voltage line in the second time period.

24. The driving method for a display panel according to claim 23, characterized in that, The first voltage output to the first voltage line in the first time period is less than the second voltage output to the first voltage line in the second time period.

25. The driving method for a display panel according to claim 21, characterized in that, The second boundary region is provided with more than or equal to 1 row of pixel circuits and less than or equal to 100 rows of pixel circuits; And / or, the first boundary region is provided with more than or equal to 1 row of pixel circuits and less than or equal to 100 row of pixel circuits; the first direction is perpendicular to the row direction.

26. The driving method for a display panel according to claim 21, characterized in that, Within a refresh frame, the first scan signal corresponding to the same pixel circuit includes multiple first pulses; the pulse width of the first pulse is greater than or equal to 4h, where 1h is the row scan time of the first scan signal.

27. The driving method for a display panel according to claim 21, characterized in that, Within a refresh frame, after the data writing phase, the first scan signal corresponding to the same pixel circuit includes multiple first pulses; the number of first pulses corresponding to the same pixel circuit after the data writing phase is greater than or equal to 2.

28. The driving method for a display panel according to claim 27, characterized in that, N equals the number of the first pulses; M = N-1.

29. The driving method for a display panel according to claim 21, characterized in that, The pixel circuit includes a first initialization module, the control terminal of the first initialization module is connected to the first scan line, the first terminal of the first initialization module is connected to the first initialization signal line, and the second terminal of the first initialization module is connected to the first pole of the display device. The pixel circuit further includes a driving module and a second initialization module. The driving module is connected between the first power signal line and the first electrode of the light-emitting device. The control terminal of the second initialization module is connected to the first scan line. The first terminal of the second initialization module is connected to the second initialization signal line. The second terminal of the second initialization module is connected to the first or second terminal of the driving module. The pixel circuit also includes a data writing module, the control terminal of which is connected to the second scan line, the first terminal of which is connected to the data signal line, and the second terminal of which is connected to the first terminal of the driving module. The pixel circuit also includes a storage module, a first end of which is connected to the first power signal line, and a second end of which is connected to the control end of the drive module. The pixel circuit also includes a threshold compensation module. The control terminal of the threshold compensation module is connected to the third scan line, the first terminal of the threshold compensation module is connected to the second terminal of the driving module, and the second terminal of the threshold compensation module is connected to the control terminal of the driving module. The pixel circuit further includes a third initialization module, the control terminal of which is connected to the fourth scan line, the first terminal of which is connected to the third initialization signal line, and the second terminal of which is connected to the first terminal of the threshold compensation module. The pixel circuit further includes a first light-emitting control module and / or a second light-emitting control module. The control terminal of the first light-emitting control module is connected to the light-emitting control signal line, the first end of the first light-emitting control module is connected to the first power signal line, the second end of the first light-emitting control module is connected to the first end of the driving module, the control terminal of the second light-emitting control module is connected to the light-emitting control signal line, the first end of the second light-emitting control module is connected to the second end of the driving module, and the second end of the second light-emitting control module is connected to the first electrode of the light-emitting device.

30. The driving method for a display panel according to claim 16, characterized in that, When the first blank phase is the maximum refresh rate of the display panel, it is the time period from the last row of pixel circuit data writing stage of the display panel in the previous refresh frame to the first row of pixel circuit data writing stage of the display panel in the next refresh frame.

31. A driving method for a display panel, characterized in that, The display panel includes N first areas and M second areas arranged alternately along a first direction, where N is greater than M and N and M are positive integers; a screen refresh cycle includes a refresh frame and a hold frame; the display panel further includes: a plurality of pixel circuits arranged in an array; a plurality of first scan lines electrically connected to the pixel circuits in corresponding rows; a first voltage line electrically connected to the pixel circuits, wherein the pixel circuits are used to write the voltage on the first voltage line into the pixel circuits in response to a pulse signal of a first scan signal on the first scan line, the first voltage line being a first initialization signal line, and the pixel circuits, in response to a pulse signal of the first scan signal, write the voltage on the first voltage line into the first electrode of the light-emitting device of the pixel circuits; the driving method includes: Within the refresh frame, during a first time period, first scan signals are simultaneously output to N spaced first zones, causing the pixel circuits of the first zones to respond to the pulse signals of the first scan signals and write the voltage on the first voltage line into the pixel circuits. The display panel includes multiple pixel circuits and multiple first scan lines. The multiple pixel circuits are arranged in an array. The first scan lines are electrically connected to the pixel circuits in corresponding rows. The first voltage lines are electrically connected to the pixel circuits. The pixel circuits are used to respond to the pulse signals of the first scan signals on the first scan lines and write the voltage on the first voltage line into the pixel circuits. The first voltage line is a first initialization signal line. The pixel circuits respond to the pulse signals of the first scan signals and write the voltage on the first voltage line into the first electrode of the light-emitting device of the pixel circuit. In a second time period different from the first time period, a first scan signal is simultaneously output to M second zones at intervals, so that the pixel circuit of the second zone responds to the pulse signal of the first scan signal and writes the voltage on the first voltage line into the pixel circuit. During the holding frame, in the third time period, a first scan signal is output to the second region so that the pixel circuit of the second region responds to the pulse signal of the first scan signal and writes the voltage on the first voltage line into the pixel circuit. The voltage output to the first voltage line in the second time period is different from the voltage output to the first voltage line in the first time period. The voltage output to the first voltage line in the third time period is different from the voltage output to the first voltage line in the first time period; The refresh frame includes an active phase and a first blank phase, wherein the first time period is located in the active phase, at least a portion of the second time period is located in the first blank phase, the voltage output to the first voltage line gradually changes from a first voltage to a second voltage at a first moment, the first moment being located between the first time period and the second time period, the first moment being before the first blank phase, and / or, the voltage output to the first voltage line gradually changes from a second voltage to a first voltage at a second moment, the second moment being located after the second time period, the second moment being after the first blank phase; wherein, the time interval between the first moment and the start moment of the first blank phase is greater than or equal to 1 hour and less than or equal to 100 hours, where 1 hour is the line scan time of the first scan signal; and / or, the time interval between the second moment and the end moment of the first blank phase is greater than or equal to 1 hour and less than or equal to 100 hours, where 1 hour is the line scan time of the first scan signal.

32. The driving method for a display panel according to claim 31, characterized in that, The absolute value of the first voltage output to the first voltage line in the first time period is greater than the absolute value of the second voltage output to the first voltage line in the second time period.

33. The driving method for a display panel according to claim 32, characterized in that, The absolute value of the voltage output to the first voltage line in the third time period is less than the absolute value of the voltage output to the first voltage line in the first time period.

34. The driving method for a display panel according to claim 32, characterized in that, Within a refresh frame, after the data writing phase, the first scan signal corresponding to the same pixel circuit includes multiple first pulses; the number of first pulses corresponding to the same pixel circuit after the data writing phase is greater than or equal to 2.

35. The driving method for a display panel according to claim 34, characterized in that, N equals the number of the first pulses; M = N-1.

36. The driving method for a display panel according to claim 32, characterized in that, Within a holding frame, the first scan signal corresponding to the same pixel circuit includes multiple second pulses.

37. The driving method for a display panel according to claim 31, characterized in that, When the first blank phase is the maximum refresh rate of the display panel, it is the time period from the last row of pixel circuit data writing stage of the display panel in the previous refresh frame to the first row of pixel circuit data writing stage of the display panel in the next refresh frame.

38. A display device, characterized in that, It includes a display panel and a display driver module, wherein the display driver module is used to execute the driving method of the display panel as described in any one of claims 1-37.

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