Chip failure positioning method, electronic device and storage medium

Abstract

This application provides a chip failure location method, electronic device, and storage medium. The method includes: determining a top surface failure location on the top surface of a bare chip based on a substrate failure location; determining a first etching line and a second etching line on the top surface of the chip based on the top surface failure location; obtaining a chip substrate image obtained by etching the bare chip using the first and second etching lines; determining a failure location difference based on the substrate failure location and the top surface failure location; and when the failure location difference exceeds a preset location difference threshold, re-determining the first etching line and / or the second etching line to adjust the top surface failure location until the failure location difference does not exceed the preset location difference threshold, and then cutting the bare chip cross-section. This solution can locate the chip failure location based on a high-magnification chip failure image, improving the accuracy of chip failure location location and preventing positioning failure and incorrect cross-section cutting due to large measurement errors in the equipment.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a chip failure location method, an electronic device, and a storage medium. Background Technology

[0002] Chip failure analysis includes Electrical Failure Analysis (EFA) and Physical Failure Analysis (PFA). In failure analysis, EFA is used to locate the failure location, while PFA is used to cut cross-sections of the failure location to observe the cause of the failure.

[0003] Currently, an Emission Microscope (EMMI) is often used to capture chip failure images and measure the distance from the failure location in the image to the chip boundary. Then, a Focused Ion Beam (FIB) device is used to locate the failure location on the actual chip based on the distance from the failure location to the chip boundary, so as to perform cross-sectional cutting.

[0004] However, in order to observe the chip boundary, only low-magnification chip failure maps can be acquired. But low-magnification chip failure maps are not applicable to FIB, so the failure location cannot be located. Furthermore, the measurement error between the EMMI device and the FIB device is large, which can easily lead to failure in locating the chip failure location. Summary of the Invention

[0005] In view of this, this application provides a chip failure location method, electronic device and storage medium, which can locate the failure location of the chip based on a high-magnification chip failure map, improve the accuracy of chip failure location location, and prevent the location failure and incorrect cutting of the cross section due to large measurement errors of the equipment.

[0006] In a first aspect, embodiments of this application provide a method for locating the location of a chip failure, including:

[0007] Obtain a chip failure diagram of a packaged chip, the chip failure diagram including: the chip substrate of the packaged chip, and the failure location of the substrate of the packaged chip when powered on, wherein the failure location of the substrate is the projection location of the failure location inside the chip in the packaged chip on the chip substrate of the packaged chip;

[0008] Based on the substrate failure location, the top surface failure location on the top surface of the bare chip is determined, wherein the bare chip is the chip after the encapsulating adhesive has been removed from the packaged chip;

[0009] Based on the failure location on the top surface, a first etching line and a second etching line are determined on the top surface of the chip, and the intersection of the extensions of the first etching line and the second etching line is the failure location on the top surface.

[0010] Obtain a chip substrate image after etching the bare chip using the first etching line and the second etching line. The chip substrate image includes: the chip substrate of the bare chip, the etching positions corresponding to the first etching line and the second etching line, and the etching depth of the first etching line and the second etching line is from the top surface of the bare chip to the chip substrate of the bare chip.

[0011] The failure location difference is determined based on the substrate failure location in the chip failure diagram and the top surface failure location in the chip substrate diagram;

[0012] When the failure location difference exceeds a preset location difference threshold, the first etching line and / or the second etching line are redefined to adjust the failure location on the top surface until the failure location difference does not exceed the preset location difference threshold, so as to perform cross-sectional cutting on the bare chip.

[0013] In an optional implementation, determining the top surface failure location on the top surface of the bare chip based on the substrate failure location includes:

[0014] Obtain the distance between the substrate failure location in the chip failure diagram and the substrate boundary of the chip substrate;

[0015] Based on the distance and the target top surface boundary corresponding to the substrate boundary on the top surface of the chip, the top surface failure location is determined on the top surface of the chip.

[0016] In an optional implementation, before determining the top surface failure location on the top surface of the chip based on the distance and the target top surface boundary corresponding to the substrate boundary on the top surface of the chip, the method further includes:

[0017] The chip failure diagram is mirrored to obtain a mirrored chip failure diagram;

[0018] Determine the mirror substrate boundary corresponding to the substrate boundary in the mirror chip failure diagram;

[0019] The top surface boundary corresponding to the boundary of the mirror substrate is determined as the target top surface boundary in the top surface of the chip.

[0020] In an optional implementation, determining the first etching line and the second etching line on the top surface of the chip based on the top surface failure location includes:

[0021] The first etching line and the second etching line are determined in the area outside the preset distance of the failure location on the top surface of the chip.

[0022] In an optional implementation, obtaining the distance between the substrate failure location in the chip failure map and the substrate boundary of the chip substrate includes:

[0023] The distance between the substrate failure location and the substrate boundary is measured using a preset optical microscope.

[0024] In an optional implementation, the chip failure map is obtained using a preset microscopic microscope in the following manner:

[0025] From the chip substrate of the packaged chip, a substrate scan and a failure location scan are performed on the packaged chip to obtain a packaged chip substrate map and a failure location map. The packaged chip substrate map and the failure location map are then combined to generate the chip failure map.

[0026] The chip substrate pattern was obtained using the preset micro-microscope in the following manner:

[0027] The bare chip is subjected to substrate scanning from its chip substrate to obtain the chip substrate pattern.

[0028] In an optional embodiment, before performing substrate scanning and failure location scanning on the packaged chip from the chip substrate to obtain a packaged chip substrate map and a failure location map, the method further includes:

[0029] The chip substrate of the packaged chip is laser-etched, and the chip substrate of the packaged chip is etched with a preset etching liquid to expose the crystal back of the packaged chip.

[0030] In an optional implementation, before scanning the bare chip from its chip substrate to obtain the chip substrate pattern, the method further includes:

[0031] The encapsulating adhesive in the packaged chip is etched using a pre-set etching liquid to obtain the bare chip.

[0032] Secondly, embodiments of this application also provide an electronic device, including: a processor, a memory, and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the memory via the bus, and the processor executes the machine-readable instructions to perform the method described in any of the first aspects.

[0033] Thirdly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the method described in any of the first aspects.

[0034] This application provides a chip failure location method, electronic device, and storage medium. The method includes: determining a top surface failure location on the top surface of a bare chip based on a substrate failure location; determining a first etching line and a second etching line on the top surface of the chip based on the top surface failure location; obtaining a chip substrate map obtained by etching the bare chip using the first and second etching lines; determining a failure location difference based on the substrate failure location in the chip failure map and the top surface failure location in the substrate failure map; and when the failure location difference exceeds a preset location difference threshold, re-determining the first etching line and / or the second etching line to adjust the top surface failure location until the failure location difference does not exceed the preset location difference threshold, and then cutting the bare chip cross-section. This solution can locate the chip failure location based on a high-magnification chip failure map, improving the accuracy of chip failure location location and preventing positioning failure and incorrect cross-section cutting due to large measurement errors in the equipment. Attached Figure Description

[0035] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 A flowchart illustrating the chip failure location method provided in this application embodiment. Figure 1 ;

[0037] Figure 2 A flowchart illustrating the chip failure location method provided in this application embodiment. Figure 2 ;

[0038] Figure 3 A flowchart illustrating the chip failure location method provided in this application embodiment. Figure 3 ;

[0039] Figure 4 A flowchart illustrating the chip failure location method provided in this application embodiment. Figure 4 ;

[0040] Figure 5 A flowchart illustrating the chip failure location method provided in this application embodiment. Figure 5 ;

[0041] Figure 6This is a schematic diagram of the chip failure location device provided in the embodiments of this application;

[0042] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0044] Chip failure analysis includes Electrical Failure Analysis (EFA) and Physical Failure Analysis (PFA). Typically, EFA involves opening the chip's front cover and using an Emission Microscope (EMMI) to photograph the failure location. Then, the photographed failure location is used to locate the chip's top surface pattern under the EMMI, followed by targeted dicing using a Focused Ion Beam (FIB) device. However, with technological advancements, chips have increasingly more and denser metal layers, making it difficult for failure signals to accurately penetrate the chip. In most cases, the transmitted signal is affected by wiring, causing it to deviate from the actual failure location, thus preventing FIB from accurately locating the true failure point.

[0045] The chip back cover opening technique was developed to address this issue, as it avoids the displacement of failure points caused by metal obstruction. Chip back cover opening refers to opening the chip from the back (the pure monocrystalline silicon side). After opening, the monocrystalline silicon back of the chip is exposed, and it is then placed on an EMMI (Electronic Image Processing) device for positioning. Since the EMMI device can see through the sample, the information of the chip substrate can be observed, including the location of the failure point, which can be displayed in the substrate pattern. After saving the overlay image information of the substrate and the failure point location (i.e., the chip failure map), since the top surface of the chip is a wiring layer and the substrate is not visible, the approximate location of the failure point can only be selected on the top surface of the chip based on the chip failure map and the chip's size ratio. Then, a FIB (Film Injection Block) device is used to cut the chip from the front side to the failure point.

[0046] However, in order to observe the chip boundary, only a low magnification chip failure map can be acquired. But the area of ​​the low magnification chip failure map is too large for the FIB, and the FIB cannot cut such a large area, so it is not suitable for the FIB. Therefore, it is impossible to locate the failure location. In addition, the measurement error between the EMMI device and the FIB device is large, which can easily lead to failure in locating the chip failure location. It is worth noting that even a small error in such a large size range may completely deviate from the actual failure location.

[0047] Based on this, this application determines the failure location on the top surface of the chip by repeating experiments, thereby enabling the chip failure location to be located based on a high-magnification chip failure map. In other words, it can locate the chip failure location based on the magnified chip failure map, which improves the accuracy of chip failure location and prevents the location failure and incorrect cutting of the cross section due to large measurement errors of the equipment.

[0048] Figure 1 A flowchart illustrating the chip failure location method provided in this application embodiment. Figure 1 In this embodiment, the executing entity can be an electronic device, such as a mobile phone, desktop computer, or tablet computer.

[0049] like Figure 1 As shown, the method may include:

[0050] S101. Obtain the chip failure diagram of the packaged chip.

[0051] The chip failure diagram includes: the chip substrate of the packaged chip, and the failure location of the packaged chip substrate when powered on. The substrate failure location is the projection location of the failure location inside the chip in the packaged chip onto the chip substrate of the packaged chip.

[0052] Among them, the chip failure map is a failure map obtained by scanning the substrate and failure location of the packaged chip from the chip substrate when the packaged chip is powered on.

[0053] It is understandable that a packaged chip can be any chip that needs to be located for failure. The packaged chip consists of a chip substrate, a chip top surface, and the chip interior. The chip substrate is located at the bottom, the chip top surface is located at the top, and the chip interior is located between the chip substrate and the chip top surface. By scanning the failure location of the packaged chip, the failure location inside the chip can be projected onto the chip substrate, thereby obtaining a chip failure map.

[0054] In some embodiments, the packaged chip is placed on an EMMI device and power is applied to the power pins of the packaged chip to enable the packaged chip to operate. When scanning the failure location, the signal of the failure location will penetrate the back of the chip to the surface of the chip back. The chip substrate is composed of monocrystalline silicon, wherein the chip back is the back side of the monocrystalline silicon. The EMMI device can capture the chip substrate signal and the failure location signal, and then combine the chip substrate signal and the failure location signal to obtain the chip failure map.

[0055] It is worth noting that the EMMI device is equipped with a charging probe. Place the packaged chip on the probe stage, move the charging probe of the EMMI device to the power pin of the packaged chip, observe with the microscope eyepiece, use the fine adjustment knob to insert the charging probe into the power pin, and apply a certain current and voltage to the charging probe to put the packaged chip into the power-on working state.

[0056] S102. Determine the top surface failure location on the top surface of the bare chip based on the substrate failure location.

[0057] A bare chip is a chip after the encapsulating adhesive has been removed from a packaged chip. A bare chip consists of a chip substrate, a chip top surface, and the chip interior.

[0058] Based on the location and layout of the substrate failure location within the chip substrate of the packaged chip, the top surface failure location on the top surface of the bare chip can be determined. The top surface failure location is the projection location of the failure location inside the chip onto the top surface of the bare chip.

[0059] S103. Based on the failure location on the top surface, determine the first etching line and the second etching line on the top surface of the chip.

[0060] Based on the failure location on the top surface, a first etching line and a second etching point are determined on the top surface of the bare chip, wherein the intersection of the extensions of the first etching line and the second etching line is the failure location on the top surface.

[0061] S104. Obtain the chip substrate pattern obtained after etching the bare chip using the first etching line and the second etching line.

[0062] The bare chip is etched using a first etching line and a second etching line. The etching depth of the first etching line and the second etching line extends from the top surface of the bare chip to the chip substrate. In some embodiments, the bare chip can be placed in an FIB device and etched using the ion beam line scanning etching function. The bare chip is etched based on the first etching line and the second etching line, so that the intersection of the extensions of the first etching line and the second etching line is the top surface failure location on the top surface of the bare chip. The depth of the first etching line and the second etching line reaches the chip substrate. This allows the etching location to be identified during substrate scanning, making it easier to determine the top surface failure location.

[0063] After the bare chip is etched, a chip substrate image of the etched bare chip is acquired. The chip substrate image includes: the chip substrate of the bare chip, the etching positions corresponding to the first etching line and the second etching line. In some embodiments, the etched bare chip is placed on an EMMI device, and a substrate scan is performed on the etched bare chip from the chip substrate to obtain a chip substrate image. The infrared (IR) function of the EMMI device can be used to scan the chip substrate from the back side to see all the information of the chip substrate.

[0064] S105. Determine the failure location difference based on the substrate failure location in the chip failure diagram and the top surface failure location in the chip substrate diagram.

[0065] The intersection of the first and second etching lines used to etch the bare chip is the top surface failure location. The top surface failure location in the chip substrate map can be determined by the intersection of the extension lines of the two etching locations in the chip substrate map. The substrate failure location in the chip failure map is measured, and the substrate failure location in the chip failure map is compared with the top surface failure location in the chip substrate map to calculate the failure location difference between the substrate failure location and the top surface failure location.

[0066] In some embodiments, a preset optical microscope is used to measure the failure location difference between the substrate failure location and the top surface failure location based on a grid diagram.

[0067] S106. When the failure location difference exceeds the preset location difference threshold, the first etching line and / or the second etching line are redefined to adjust the failure location on the top surface until the failure location difference does not exceed the preset location difference threshold, so as to cut the bare chip cross-section.

[0068] When the failure location difference exceeds the preset location difference threshold, it indicates that the failure location on the top surface of the bare chip is not accurate enough, i.e. there is a certain measurement error. Then the first etching line and / or the second etching line can be re-determined. The intersection of the extensions of the two re-determined etching lines is the adjusted top surface failure location. In other words, by re-determining the first etching line and / or the second etching line, the top surface failure location on the top surface of the bare chip is adjusted.

[0069] Then, based on the substrate failure location and the adjusted top surface failure location, the failure location difference between the substrate failure location and the adjusted top surface failure location is determined. This process is repeated until the failure location difference does not exceed the preset location difference threshold. Finally, the bare chip is cut into sections using the finally determined top surface failure location.

[0070] It is worth noting that the position in this solution can be represented by the XY axis, where the X-axis represents the horizontal direction of the chip and the Y-axis represents the vertical direction of the chip.

[0071] In this embodiment, the top surface failure position is the projection position of the initially determined failure position on the top surface of the chip. The top surface failure position on the chip is adjusted by repeated experiments until the distance of the failure position does not exceed the preset position difference threshold. Thus, the failure position of the chip can be located based on the high-magnification chip failure map. That is, the chip failure position can be located based on the magnified chip failure map, which improves the accuracy of chip failure position location and prevents the positioning failure and incorrect section cutting caused by large measurement errors of the equipment.

[0072] Figure 2 A flowchart illustrating the chip failure location method provided in this application embodiment. Figure 2 ,like Figure 2 As shown, in an optional embodiment, step S102, determining the top surface failure location on the top surface of the bare chip based on the substrate failure location, may include:

[0073] S201. Obtain the distance between the substrate failure location and the substrate boundary of the chip substrate in the chip failure diagram.

[0074] The substrate boundary can include two adjacent boundaries of the chip substrate, which determine the distance between the substrate failure location and the substrate boundary in the chip failure diagram, for example, 1300μm and 600μm respectively.

[0075] In some embodiments, step S201, obtaining the distance between the substrate failure location in the chip failure map and the substrate boundary of the chip substrate, includes:

[0076] A pre-set optical microscope was used to measure the distance between the substrate failure location and the substrate boundary.

[0077] The chip failure map is placed under a preset optical microscope (OM), and the distance between the substrate failure location and the substrate boundary in the chip failure map is measured using the preset optical microscope.

[0078] S202. Determine the top surface failure location on the top surface of the chip based on the distance and the target top surface boundary corresponding to the substrate boundary on the top surface of the chip.

[0079] The target top surface boundary is the boundary on the top surface of the bare chip that corresponds to the substrate boundary in the chip failure diagram. Based on the distance between the substrate failure location and the substrate boundary, and the target top surface boundary, the top surface failure location is determined on the top surface of the chip. The distance between the target top surface boundary and the top surface failure location is consistent with the distance between the substrate failure location and the substrate boundary.

[0080] It is worth noting that the failure location on the top surface is a preliminary determination of the failure location on the top surface of the chip. In subsequent processing, the most accurate failure location on the top surface will be determined by repeatedly performing etching and observing.

[0081] In this embodiment, the distance between the substrate failure location and the substrate boundary is measured by an optical microscope, which facilitates the subsequent determination of the top surface failure location on the top surface of the bare chip. This allows for the location of the chip failure location based on a high-magnification chip failure map, improving the accuracy of chip failure location positioning and preventing positioning failure and incorrect section cutting due to large measurement errors in the equipment.

[0082] Figure 3 A flowchart illustrating the chip failure location method provided in this application embodiment. Figure 3 ,like Figure 3 As shown, in an optional embodiment, before determining the top surface failure location on the top surface of the chip based on the distance and the target top surface boundary corresponding to the substrate boundary on the top surface of the chip, step S202 may further include:

[0083] S301. Mirror the chip failure diagram to obtain a mirrored chip failure diagram.

[0084] S302. Determine the mirror substrate boundary corresponding to the substrate boundary in the mirror chip failure diagram.

[0085] Since the chip failure map and the substrate failure map are mirror images, the chip failure map is mirrored to obtain a mirror chip failure map. The mirror substrate boundary corresponding to the substrate boundary of the chip failure map is then determined in the mirror chip failure map. The mirror substrate boundary is the substrate boundary in the mirror chip failure map that corresponds to the substrate boundary in the chip failure map.

[0086] S303. Determine the target top surface boundary as the top surface boundary of the chip that corresponds to the boundary of the mirror substrate.

[0087] The top surface boundary corresponding to the mirror substrate boundary in the top surface of the chip is determined as the target top surface boundary. The distance between the target top surface boundary and the top surface failure location is the same as the distance between the mirror substrate boundary and the substrate failure location.

[0088] In some embodiments, the EMMI device may have a mirroring function, which can perform mirroring processing on the acquired chip failure image to obtain a mirrored chip failure image.

[0089] In this embodiment, the chip failure map is mirrored to facilitate subsequent determination of the top surface failure location, thereby improving the accuracy of the top surface failure location.

[0090] Figure 4 A flowchart illustrating the chip failure location method provided in this application embodiment. Figure 4 ,like Figure 4 As shown, in an optional embodiment, step S103, determining the first etching line and the second etching line on the top surface of the chip based on the top surface failure location, may include:

[0091] S401. In the area outside the preset distance of the failure position on the top surface of the chip, determine the first etching line and the second etching line.

[0092] Once the failure location on the top surface is determined, the first etching line and the second etching line can be determined in an area outside the preset distance of the failure location on the chip's top surface. In other words, the distance between the first etching line and the second etching line and the failure location on the top surface both exceed the preset distance. That is, determining the first etching line and the second etching line in an area far away from the failure location on the top surface can avoid damaging the failure location on the top surface during etching and prevent the bare chip from being unable to be cut into sections based on the failure location on the top surface in the future.

[0093] Figure 5 A flowchart illustrating the chip failure location method provided in this application embodiment. Figure 5 ,like Figure 5 As shown, the chip failure diagram was obtained using a preset low-light microscope in the following manner:

[0094] S501. From the chip substrate of the packaged chip, perform substrate scanning and failure location scanning on the packaged chip to obtain the packaged chip substrate map and failure location map, and combine the packaged chip substrate map and failure location map to generate the chip failure map.

[0095] From the chip substrate of the packaged chip, a substrate scan is performed to obtain a packaged chip substrate map, and a failure location scan is performed to obtain a failure location map. The packaged chip substrate map includes substrate information of the packaged chip, and the failure location map includes the failure location inside the packaged chip. The packaged chip substrate map and the failure location map are combined to generate a chip failure map.

[0096] Before step S501, which involves scanning the packaged chip and its failure locations from the chip substrate to obtain a packaged chip substrate map and a failure location map, the following steps are also included:

[0097] The chip substrate of the packaged chip is laser-etched, and a preset etching liquid is used to etch the chip substrate of the packaged chip to expose the crystal back of the packaged chip.

[0098] The packaged chip is placed on a laser device, and the chip substrate of the packaged chip is laser-etched. The laser device can be, for example, an X-ray laser. The packaged chip can be photographed on the laser device to determine the chip area, and then laser-etched. The laser-etched area is larger than the chip area.

[0099] Then, a pre-set etching liquid, such as fuming nitric acid droplets, is used to etch the laser-etched chip substrate to expose the crystal back of the packaged chip.

[0100] The chip substrate image was obtained using a pre-defined microscopy method as follows:

[0101] S502. Scan the bare chip from the chip substrate to obtain a chip substrate image.

[0102] Step S502, before scanning the bare chip from its substrate to obtain a chip substrate pattern, further includes:

[0103] A pre-set etching liquid is used to etch the encapsulating adhesive in the packaged chip to obtain a bare chip.

[0104] The pre-set etching liquid can be, for example, fuming nitric acid drops. Pour the fuming nitric acid drops into a beaker and place it on a heating platform. The temperature can be 10-200 degrees Celsius, and the mixture is boiled for 1-6 minutes. The pre-set etching liquid is then used to etch the encapsulating adhesive in the packaged chip to obtain a bare chip. The specific heating temperature and boiling time can be determined according to the chip type and size.

[0105] In this embodiment, the back cover of the chip is opened by laser and etching, which facilitates subsequent scanning of the chip substrate to obtain chip failure maps, and the removal of the encapsulating adhesive facilitates subsequent acquisition of chip substrate maps.

[0106] Based on the above embodiments, the solution of this application will be described below with reference to a specific embodiment. The implementation process of a specific chip failure location method provided in this application includes the following steps:

[0107] Step 1: Perform crystal back cover opening on the packaged chip.

[0108] The chip substrate of the packaged chip is laser-etched, and a preset etching liquid is used to etch the chip substrate of the packaged chip to expose the crystal back of the packaged chip.

[0109] Step 2: EMMI scan.

[0110] (1) Place the packaged chip on the probe stage, move the voltage probe to the vicinity of the corresponding pin (pin corner), and then use the microscope eyepiece to observe and use the fine adjustment knob to insert the probe into the corresponding pin corner.

[0111] (2) Apply the corresponding current and voltage to the charging probe to put the packaged chip into working state. Then the EMMI device captures the failure location of the packaged chip and saves the captured chip failure image.

[0112] Step 3: Remove the encapsulating adhesive

[0113] Pour fuming nitric acid into a beaker and place it on a heating plate. The temperature can be 10-200 degrees Celsius. Boil for 1-6 minutes and use a preset etching liquid to etch the encapsulating adhesive in the packaged chip to obtain a bare chip (Die).

[0114] Step 4: Use OM to measure the distance between the substrate failure location and the two adjacent substrate boundaries in the chip failure diagram.

[0115] Step 5: First etching (mark).

[0116] Take a global image of the bare chip under an OM (Optical Marker) to preliminarily determine the top failure location of the chip based on the measured distance. Then, place the sample in an FIB (Film Injection Block). At positions along the X and Y axes that pass approximately to the failure location and are far from the top failure location (ensuring a safe distance for the failure point), use the ion beam line scan etching function to etch two lines. The intersection of the two lines is the top failure location, and the depth of the two lines reaches the substrate.

[0117] Step 7: First verification.

[0118] The etched bare chip is placed on an EMMI device, and an IR scan is performed from the back side to obtain a substrate failure map. The etched location is observed in the substrate failure map, and two lines are drawn at the etched location. The distance between the intersection of the two lines and the substrate failure location is observed.

[0119] Step 8: Second etching.

[0120] If the distance between the intersection of the two lines and the substrate failure location exceeds the preset position difference threshold, the two etching lines are redefined, and the top failure location is adjusted. The two lines are then etched using the ion beam line scanning etching function so that the intersection of the two lines is the adjusted top failure location, and the depth of the two lines reaches the substrate.

[0121] Step 9: Second verification.

[0122] The etched bare chip is placed on the EMMI device, and the substrate failure map is obtained by scanning the IR from the back side. The etched position is observed in the substrate failure map. Two lines are drawn at the etched position, and the distance between the intersection of the two etched lines and the substrate failure position is observed.

[0123] Step 10: Repeat steps 5-9 until the distance between the intersection of the two etching lines and the substrate failure location does not exceed the preset position difference threshold, and save the final substrate failure map. Based on the top failure location in the substrate failure map, cut the bare chip into sections.

[0124] The core of this approach lies in gradually pinpointing the failure location on the top surface through repeated experiments. It's worth noting that if there's only one sample of the failed chip, this sample typically undergoes extensive analysis from devices like mobile phones or computers before being disassembled for individual analysis. By the time electrical analysis and FIB analysis are completed, significant costs have already been incurred. Failure at this stage could mean a complete waste of those costs, making the success of the experiment crucial. Conventional front-side solutions suffer from signal displacement due to the influence of wiring layers. Differences in wiring thickness or the surrounding insulating layer can cause signal misalignment and lead to experimental failure. This approach, however, allows the signal to bypass the wiring layer and pass directly through the chip substrate. Since the substrate is composed of pure monocrystalline silicon, without different materials or wires, the success rate is significantly increased, thus locating the failure location while reducing costs. Furthermore, by repeatedly probing towards the failure location, the success rate can be controlled by the number of experiments. For example, if project A has 10 identical failed chips, two experiments can be used to locate the failure. If project B has only one failure location, the number of experiments can be increased, such as to five, to ensure accuracy.

[0125] Based on the same inventive concept, this application also provides a chip failure location device corresponding to the chip failure location method. Since the principle of the device in this application is similar to the chip failure location method described above in this application, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be described again.

[0126] Figure 6 This is a schematic diagram of the chip failure location device provided in an embodiment of this application. The device can be integrated into an electronic device.

[0127] like Figure 6 As shown, the device may include:

[0128] The acquisition module 601 is used to acquire the chip failure diagram of the packaged chip. The chip failure diagram includes: the chip substrate of the packaged chip, and the failure position of the substrate of the packaged chip when powered on. The failure position of the substrate is the projection position of the failure position inside the chip in the packaged chip onto the chip substrate of the packaged chip.

[0129] The determination module 602 is used to determine the top surface failure location on the top surface of the bare chip based on the substrate failure location. The bare chip is the chip after the encapsulating adhesive has been removed from the packaged chip.

[0130] The determination module 602 is also used to determine the first etching line and the second etching line on the top surface of the chip according to the top surface failure location, and the intersection of the extension lines of the first etching line and the second etching line is the top surface failure location;

[0131] The acquisition module 601 is further configured to acquire a chip substrate image obtained after etching the bare chip using the first etching line and the second etching line. The chip substrate image includes: the chip substrate of the bare chip, the etching positions corresponding to the first etching line and the second etching line, and the etching depth of the first etching line and the second etching line is from the top surface of the bare chip to the chip substrate of the bare chip.

[0132] The determining module 602 is also used to determine the failure location difference based on the substrate failure location in the chip failure diagram and the top surface failure location in the chip substrate diagram;

[0133] The determination module 602 is further configured to, when the failure location difference exceeds a preset location difference threshold, redetermine the first etching line and / or the second etching line to adjust the failure location on the top surface until the failure location difference does not exceed the preset location difference threshold, so as to perform cross-sectional cutting on the bare chip.

[0134] In an optional implementation, the determining module 602 is specifically used for:

[0135] Obtain the distance between the substrate failure location and the substrate boundary of the chip substrate in the chip failure diagram;

[0136] Based on the distance and the target top surface boundary corresponding to the substrate boundary on the top surface of the chip, the location of the top surface failure is determined on the top surface of the chip.

[0137] In an optional implementation, it further includes:

[0138] Processing module 603 is used to perform mirroring processing on the chip failure diagram to obtain a mirrored chip failure diagram;

[0139] The determination module 602 is also used to determine the mirror substrate boundary corresponding to the substrate boundary in the mirror chip failure diagram;

[0140] The determining module 602 is also used to determine the top surface boundary corresponding to the boundary of the mirror substrate in the top surface of the chip as the target top surface boundary.

[0141] In an optional implementation, the determining module 602 is further configured to:

[0142] Within a preset distance from the failure location on the top surface of the chip, a first etching line and a second etching line are determined.

[0143] In an optional implementation, the acquisition module 601 is specifically used for:

[0144] A pre-set optical microscope was used to measure the distance between the substrate failure location and the substrate boundary.

[0145] In an optional implementation, the chip failure map is obtained using a preset microscopy method as follows:

[0146] From the chip substrate of the packaged chip, perform substrate scanning and failure location scanning on the packaged chip to obtain the packaged chip substrate map and failure location map, and combine the packaged chip substrate map and failure location map to generate chip failure map;

[0147] The chip substrate image was obtained using a pre-defined microscopy method as follows:

[0148] The substrate of the bare chip is scanned to obtain a chip substrate image.

[0149] In an optional implementation, before performing substrate scanning and failure location scanning on the packaged chip from the chip substrate to obtain the packaged chip substrate map and failure location map, the method further includes:

[0150] The chip substrate of the packaged chip is laser-etched, and a preset etching liquid is used to etch the chip substrate of the packaged chip to expose the crystal back of the packaged chip.

[0151] In an optional implementation, before scanning the bare die from its chip substrate to obtain a chip substrate pattern, the method further includes:

[0152] A pre-set etching liquid is used to etch the encapsulating adhesive in the packaged chip to obtain a bare chip.

[0153] The processing flow of each module in the device and the interaction flow between each module can be referred to the relevant descriptions in the above method embodiments, and will not be detailed here.

[0154] Figure 7 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application, such as... Figure 7 As shown, the device may include a processor 701, a memory 702, and a bus 703. The memory 702 stores machine-readable instructions that can be executed by the processor 701. When the electronic device is running, the processor 701 communicates with the memory 702 through the bus 703, and the processor 701 executes the machine-readable instructions to perform the above-described method.

[0155] This application also provides a computer-readable storage medium storing a computer program, which is executed by a processor, and the processor performs the above-described method.

[0156] In this embodiment, the computer program, when run by the processor, can also execute other machine-readable instructions to perform other methods as described in the embodiments. For details on the specific execution steps and principles, please refer to the description of the embodiments, which will not be repeated here.

[0157] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0158] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0159] In addition, the functional units in the embodiments provided in this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0160] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0161] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0162] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The protection scope of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application. All should be covered within the protection scope of this application. Therefore, the protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A method of chip failure localization, the method comprising: include: Obtain a chip failure diagram of a packaged chip, the chip failure diagram including: the chip substrate of the packaged chip, and the failure location of the substrate of the packaged chip when powered on, wherein the failure location of the substrate is the projection location of the failure location inside the chip in the packaged chip on the chip substrate of the packaged chip; Based on the substrate failure location, the top surface failure location on the top surface of the bare chip is determined, wherein the bare chip is the chip after the encapsulating adhesive has been removed from the packaged chip; Based on the failure location on the top surface, a first etching line and a second etching line are determined on the top surface of the chip, and the intersection of the extensions of the first etching line and the second etching line is the failure location on the top surface. Obtain a chip substrate image after etching the bare chip using the first etching line and the second etching line. The chip substrate image includes: the chip substrate of the bare chip, the etching positions corresponding to the first etching line and the second etching line, and the etching depth of the first etching line and the second etching line is from the top surface of the bare chip to the chip substrate of the bare chip. The failure location difference is determined based on the substrate failure location in the chip failure diagram and the top surface failure location in the chip substrate diagram; When the failure location difference exceeds a preset location difference threshold, the first etching line and / or the second etching line are redefined to adjust the failure location on the top surface until the failure location difference does not exceed the preset location difference threshold, so as to perform cross-sectional cutting on the bare chip.

2. The method of claim 1, wherein, Determining the top surface failure location on the top surface of the bare chip based on the substrate failure location includes: Obtain the distance between the substrate failure location in the chip failure diagram and the substrate boundary of the chip substrate; Based on the distance and the target top surface boundary corresponding to the substrate boundary on the top surface of the chip, the top surface failure location is determined on the top surface of the chip.

3. The method according to claim 2, characterized in that, Before determining the top surface failure location on the top surface of the chip based on the distance and the target top surface boundary corresponding to the substrate boundary on the top surface of the chip, the method further includes: The chip failure diagram is mirrored to obtain a mirrored chip failure diagram; Determine the mirror substrate boundary corresponding to the substrate boundary in the mirror chip failure diagram; The top surface boundary corresponding to the boundary of the mirror substrate is determined as the target top surface boundary in the top surface of the chip.

4. The method according to claim 1, characterized in that, The step of determining a first etching line and a second etching line on the top surface of the chip based on the failure location on the top surface includes: The first etching line and the second etching line are determined in the area outside the preset distance of the failure location on the top surface of the chip.

5. The method according to claim 2, characterized in that, Obtaining the distance between the substrate failure location in the chip failure map and the substrate boundary of the chip substrate includes: The distance between the substrate failure location and the substrate boundary is measured using a preset optical microscope.

6. The method according to any one of claims 1-5, characterized in that, The chip failure diagram was obtained using a preset low-light microscope in the following manner: From the chip substrate of the packaged chip, a substrate scan and a failure location scan are performed on the packaged chip to obtain a packaged chip substrate map and a failure location map. The packaged chip substrate map and the failure location map are then combined to generate the chip failure map. The chip substrate pattern was obtained using the preset micro-microscope in the following manner: The bare chip is subjected to substrate scanning from its chip substrate to obtain the chip substrate pattern.

7. The method according to claim 6, characterized in that, Before performing substrate scanning and failure location scanning on the packaged chip from the chip substrate to obtain the packaged chip substrate map and failure location map, the method further includes: The chip substrate of the packaged chip is laser-etched, and the chip substrate of the packaged chip is etched with a preset etching liquid to expose the crystal back of the packaged chip.

8. The method according to claim 6, characterized in that, Before scanning the bare chip from its chip substrate to obtain the chip substrate pattern, the method further includes: The encapsulating adhesive in the packaged chip is etched using a pre-set etching liquid to obtain the bare chip.

9. An electronic device, characterized in that, include: The device includes a processor, a memory, and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is in operation, the processor communicates with the memory via the bus, and the processor executes the machine-readable instructions to perform the method of any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the method according to any one of claims 1 to 8.

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