A method and apparatus for testing the insulation resistance of a multilayer chip ceramic capacitor

Abstract

The present application relates to the technical field of multilayer chip ceramic capacitor, and particularly relates to a multilayer chip ceramic capacitor insulation resistance test method and device, which comprises gradually applying a test voltage to a multilayer chip ceramic capacitor to be tested in a gradual manner according to an optimal gradual voltage application rate for each test voltage, and performing an insulation test on the multilayer chip ceramic capacitor to be tested under the test voltage to obtain an insulation resistance value, comparing the insulation resistance value with a preset insulation threshold value, and determining whether the multilayer chip ceramic capacitor to be tested is a good product. The present application realizes insulation resistance testing of the multilayer chip ceramic capacitor by gradually applying a voltage, reduces the impact on good products, effectively avoids the problem of potential damage to good products caused by high-voltage testing during the testing process, ensures the quality and reliability of the products during the insulation resistance testing of the multilayer chip ceramic capacitor, reduces maintenance costs, and improves the overall efficiency of the entire machine device.

Description

Technical Field

[0001] This invention relates to the field of multilayer ceramic chip capacitor technology, and in particular to a method and apparatus for testing the insulation resistance of multilayer ceramic chip capacitors. Background Technology

[0002] Multilayer ceramic chip capacitors (MLCCs) are small electronic components that can store electrical charge and are widely used in consumer electronics, automotive, aerospace and other fields. To ensure their reliability during use, manufacturers use testing machines to conduct full inspection tests on the products before they leave the factory to eliminate defective products that do not meet the requirements for capacitance, loss and insulation resistance.

[0003] Currently, insulation resistance tests are typically performed by applying voltages several times or even tens of times higher than the rated voltage directly to products using testing machines. Under high voltage, defective products with poor insulation resistance will break down and short-circuit or exhibit significantly lower insulation resistance compared to good products, thus being screened out. However, high voltage can also cause potential damage (such as delamination, microcracks, etc.) to good products with normal insulation resistance. This potential damage is often difficult to detect. Once a product containing such potential damage is shipped to the customer, this potential defect gradually manifests during product use, causing premature product failure and ultimately leading to the inability of the entire equipment to operate normally. Therefore, it is crucial to avoid high voltage damage to products during testing. Summary of the Invention

[0004] This invention provides a method and apparatus for testing the insulation resistance of multilayer ceramic chip capacitors. The technical problem it solves is that traditional high-voltage testing methods for the insulation resistance of MLCCs can cause undetectable potential damage to good products with normal insulation resistance, affecting the normal use of the products.

[0005] To address the above technical problems, this invention provides a method and apparatus for testing the insulation resistance of multilayer ceramic chip capacitors.

[0006] In a first aspect, the present invention provides a method for testing the insulation resistance of a multilayer ceramic chip capacitor, the method comprising the following steps:

[0007] The electroplated multilayer ceramic chip capacitor is used as the multilayer ceramic chip capacitor under test, and the test voltage is gradually applied to the multilayer ceramic chip capacitor under test in a gradual voltage application manner according to the optimal gradual voltage application rate of each test voltage.

[0008] The insulation resistance value is obtained by performing an insulation test on the multilayer ceramic chip capacitor under the test voltage.

[0009] The insulation resistance value is compared with a preset insulation threshold to determine whether the multilayer ceramic chip capacitor under test is a good product.

[0010] In a further embodiment, the test voltage is between 5 and 10 times the rated voltage of the multilayer ceramic chip capacitor under test.

[0011] In a further embodiment, the progressive voltage increase method employs linear voltage increase and raises the test voltage at the optimal progressive voltage increase rate, which is between 1 and 20 V / ms.

[0012] In a further embodiment, the insulation threshold is calculated based on the capacitance of the multilayer ceramic chip capacitor under test, and the calculation formula for the insulation threshold is:

[0013]

[0014] In the formula, γ represents the insulation threshold; C represents the capacitance of the multilayer ceramic chip capacitor under test; and α represents the time constant setting value.

[0015] In a further embodiment, the time constant is set to 500 MΩ·μF.

[0016] In a further embodiment, the multilayer ceramic chip capacitor to be tested is a Class II ceramic multilayer ceramic chip capacitor with a ceramic dielectric thickness ranging from 1 to 5 μm.

[0017] The dimensions of the multilayer ceramic chip capacitor under test are between 0.603 and 1.210 in imperial units.

[0018] In a further embodiment, the process of determining the optimal gradual pressurization rate includes:

[0019] Several electroplated multilayer ceramic chip capacitors were pre-selected as non-destructive testing samples, and the test voltage for this test was determined.

[0020] Under different progressive pressurization rates, the test voltage for this test is progressively applied to the non-destructive testing sample in a progressive pressurization manner, and an insulation test is performed to obtain the non-destructive testing sample after the test.

[0021] By performing nondestructive testing on each of the tested samples using different nondestructive testing methods, the optimal progressive pressurization rate of the tested samples under the test voltage in this test was determined.

[0022] In a further embodiment, the non-destructive testing method includes a breakdown voltage testing method, an ultrasonic flaw detection method, and an initial fault detection method.

[0023] In a further embodiment, the step of performing non-destructive testing on each of the tested non-destructive testing samples using different non-destructive testing methods to determine the optimal progressive pressurization rate of the tested non-destructive testing sample under the test voltage of this test includes:

[0024] When using the breakdown voltage detection method, a breakdown voltage tester is used to test the breakdown voltage of a first preset number of the tested non-destructive testing samples, and the breakdown voltage failure rate is determined.

[0025] When using the ultrasonic flaw detection method, a second preset number of the tested non-destructive testing samples are inspected using an ultrasonic scanning microscope, and the proportion of ultrasonic flaws is determined.

[0026] When using the initial fault detection method, a third preset number of the tested non-destructive testing samples are placed in an oven at the rated upper limit temperature, and the two ends of the tested non-destructive testing samples are connected to a DC power supply and kept connected for a first preset time to obtain an initial fault detection product. The initial fault detection product is then placed in a constant temperature and humidity chamber at 85°C and 85%RH, and a DC power supply is connected and kept connected for a second preset time to determine the initial fault rate. The voltage output by the DC power supply is the rated voltage of the non-destructive testing sample.

[0027] Based on the breakdown voltage failure rate, the ultrasonic flaw detection failure rate, and the initial fault failure rate, the optimal progressive pressurization rate of the non-destructive testing sample under the test voltage in this test is determined.

[0028] Secondly, the present invention provides a testing device for the insulation resistance of a multilayer ceramic chip capacitor, the testing device comprising:

[0029] The progressive voltage module is used to take the electroplated multilayer ceramic chip capacitor as the multilayer ceramic chip capacitor under test, and progressively apply the test voltage to the multilayer ceramic chip capacitor under test in a progressive voltage application manner according to the optimal progressive voltage application rate for each test voltage.

[0030] An insulation test module is used to perform an insulation test on the multilayer ceramic chip capacitor under test under the test voltage and obtain the insulation resistance value.

[0031] The good product detection module is used to compare the insulation resistance value with a preset insulation threshold to determine whether the multilayer ceramic chip capacitor under test is a good product.

[0032] This invention provides a method and apparatus for testing the insulation resistance of multilayer ceramic chip capacitors. The method applies a test voltage to the multilayer ceramic chip capacitor under test in a progressive manner according to the optimal progressive voltage application rate for each test voltage, and performs an insulation test on the capacitor under the test voltage to obtain the insulation resistance value. The insulation resistance value is compared with a preset insulation threshold to determine whether the multilayer ceramic chip capacitor under test is a good product. Compared with the traditional method of directly applying voltage during testing, this method uses a progressive voltage application method to reduce the impact on good products, effectively avoiding the potential damage to good products caused by high-voltage testing during the testing process. This ensures the quality and reliability of the product during the insulation resistance testing of multilayer ceramic chip capacitors, reduces maintenance and repair costs, and improves the overall efficiency of the equipment. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the test method for the insulation resistance of a multilayer ceramic chip capacitor provided in an embodiment of the present invention;

[0034] Figure 2 This is a schematic diagram of the gradual application of voltage provided in an embodiment of the present invention;

[0035] Figure 3 This is a block diagram of a testing device for the insulation resistance of a multilayer ceramic chip capacitor provided in an embodiment of the present invention;

[0036] Figure 4 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0037] The embodiments of the present invention are described in detail below with reference to the accompanying drawings. The embodiments are given for illustrative purposes only and should not be construed as limiting the present invention. The accompanying drawings are for reference and illustration only and do not constitute a limitation on the scope of patent protection of the present invention, because many changes can be made to the present invention without departing from the spirit and scope of the present invention.

[0038] refer to Figure 1 This invention provides a method for testing the insulation resistance of a multilayer ceramic chip capacitor, such as... Figure 1 As shown, the testing method includes the following steps:

[0039] S1. The electroplated multilayer ceramic chip capacitor is used as the multilayer ceramic chip capacitor to be tested, and the test voltage is gradually applied to the multilayer ceramic chip capacitor to be tested in a gradual voltage application manner according to the optimal gradual voltage application rate of each test voltage.

[0040] S2. Perform an insulation test on the multilayer ceramic chip capacitor under the test voltage to obtain the insulation resistance value.

[0041] S3. Compare the insulation resistance value with a preset insulation threshold to determine whether the multilayer ceramic chip capacitor under test is a good product.

[0042] Traditional testing machines apply voltages several times or even tens of times higher than the rated voltage directly to multilayer ceramic chip capacitors (MLCCs) during insulation resistance testing. While this direct voltage application can filter out defective products with poor insulation resistance, it can also cause imperceptible delamination, microcracks, and other potential damage to good products with normal insulation resistance. These damages gradually appear during the use of the MLCCs, increasing the risk of failure and premature product degradation, thus reducing their lifespan. Therefore, this embodiment proposes a novel method for testing the insulation resistance of multilayer ceramic chip capacitors. By gradually applying voltage to the electroplated MLCCs to the test voltage, the potential damage caused by high-voltage testing during the test is avoided, significantly reducing the impact damage to good MLCCs. The specific implementation process of the insulation resistance testing method for multilayer ceramic chip capacitors proposed in this embodiment is as follows:

[0043] In this embodiment, several electroplated multilayer ceramic chip capacitors (MLCCs) are selected as the multilayer ceramic chip capacitors to be tested. These capacitors are then used in a testing machine for testing. Figure 2 As shown, when testing insulation resistance, the voltage across the multilayer ceramic chip capacitor (MLCC) under test is gradually increased from 0V to the set value of the test voltage by gradually applying the voltage. Then, the insulation resistance of the MLCC is tested to obtain the insulation resistance value. The insulation resistance value of the MLCC is compared with the preset insulation threshold. Products with insulation resistance values ​​higher than the insulation threshold are judged as good products, and products with insulation resistance values ​​lower than the insulation threshold are judged as defective products.

[0044] During the insulation test, the gradual voltage increase method used in this embodiment is linear voltage increase, and the voltage across the multilayer ceramic chip capacitor under test is gradually increased to the set value of the test voltage at the optimal gradual voltage increase rate. The optimal gradual voltage increase rate is between 1 and 20V / ms, and the set value of the test voltage is set between 5 and 10 times the rated voltage (U0) of the multilayer ceramic chip capacitor (MLCC) under test.

[0045] Multilayer ceramic chip capacitors (MLCCs) exist in various types. MLCCs can be divided into two types: Class I ceramic (low capacitance series, secondary charge) and Class II ceramic (high capacitance series, ferroelectric). In this embodiment, the multilayer ceramic chip capacitor selected for testing is a Class II ceramic multilayer ceramic chip capacitor with a ceramic dielectric thickness ranging from 1-5 μm. The dimensions of the multilayer ceramic chip capacitor under test are between 0603 and 1210 imperial units. To ensure the rationality of the good product judgment standard, this embodiment calculates the insulation resistance threshold of the MLCC based on its capacitance and time constant setting, obtaining the insulation threshold. The formula for calculating the insulation threshold is:

[0046]

[0047] In the formula, γ represents the insulation threshold; C represents the capacitance of the multilayer ceramic chip capacitor to be tested; α represents the time constant setting value, which is preferably set to 500 MΩ·μF in this embodiment.

[0048] This embodiment employs different non-destructive testing methods to inspect the tested good products (non-destructive testing samples), and determines the fastest pressurization rate of the non-destructive testing samples without defective products as the optimal progressive pressurization rate. The process of determining the optimal progressive pressurization rate includes:

[0049] Several electroplated multilayer ceramic chip capacitors are pre-selected as non-destructive testing samples. The non-destructive testing samples are of the same model as the multilayer ceramic chip capacitors to be tested. The test voltage for this test is determined. Under different progressive voltage application rates, the test voltage for this test is progressively applied to the non-destructive testing samples in a progressive voltage application manner, and insulation tests are performed to obtain the tested non-destructive testing samples. Then, each of the tested non-destructive testing samples is subjected to non-destructive testing using different non-destructive testing methods to determine the optimal progressive voltage application rate of the tested non-destructive testing samples under the test voltage of this test.

[0050] In this embodiment, the non-destructive testing method includes a breakdown voltage detection method, an ultrasonic flaw detection method, and an initial fault detection method. Therefore, the step of performing non-destructive testing on each of the tested samples using different methods to determine the optimal progressive pressurization rate of the tested sample at the test voltage in this test includes:

[0051] When using the breakdown voltage detection method, a breakdown voltage tester is used to test the breakdown voltage of a first preset number of the tested non-destructive testing samples, and the breakdown voltage failure rate is determined.

[0052] When using the ultrasonic flaw detection method, a second preset number of the tested non-destructive testing samples are inspected using an ultrasonic scanning microscope, and the proportion of ultrasonic flaws is determined.

[0053] When using the initial fault detection method, a third preset number of the tested non-destructive testing samples are placed in an oven at the rated upper limit temperature, and the two ends of the tested non-destructive testing samples are connected to a DC power supply and kept connected for a first preset time to obtain an initial fault detection product. The initial fault detection product is then placed in a constant temperature and humidity chamber at 85°C and 85%RH, and a DC power supply is connected and kept connected for a second preset time to determine the initial fault rate. The voltage output by the DC power supply is the rated voltage of the non-destructive testing sample.

[0054] Based on the breakdown voltage failure rate, the ultrasonic flaw detection failure rate, and the initial fault failure rate, the optimal progressive pressurization rate of the non-destructive testing sample under the test voltage in this test is determined.

[0055] To further verify the progressive voltage increase test method proposed in this embodiment and analyze the process of determining the optimal progressive voltage increase rate, this embodiment uses a multilayer ceramic chip capacitor (MLCC) with 0805 imperial dimensions, X5R temperature characteristics, 10V rated voltage, and 10μF capacitance as an example. Several electroplated MLCCs were tested using a testing machine, and insulation resistance tests were performed on the products at various test voltages using different progressive voltage increase rates. The tested MLCCs were then inspected using breakdown voltage testing, ultrasonic flaw detection, and initial fault detection methods. The specific processes of these three non-destructive testing methods are as follows:

[0056] Breakdown voltage: 100 non-destructive testing samples of MLCC were selected and the breakdown voltage was tested using a breakdown voltage tester. The breakdown voltage failure rate was recorded. The breakdown voltage was lower than the breakdown voltage threshold, which was set to 8*U0, where U0 is the rated voltage of the multilayer ceramic chip capacitor MLCC.

[0057] Ultrasonic testing: 2000 non-destructive testing samples of MLCCs were selected and tested using an ultrasonic scanning microscope. The proportion of defects in ultrasonic testing was recorded.

[0058] Initial Failure: Select 1000 non-destructive testing (NDT) samples of MLCCs and place them in an oven at the rated upper limit temperature. Maintain this temperature for 100 hours with the DC power supply (U0) connected. Then, place the NDT samples in an 85℃, 85%RH chamber and maintain this temperature for 24 hours with the DC power supply (U0) connected. Record the initial failure rate (after the initial failure, the MLCC insulation resistance < 1 × 10⁻⁶). 6 Ω) ratio.

[0059] In this embodiment, qualified MLCC products are divided into multiple products of different quantities. Non-destructive testing is performed on different quantities of products to analyze the defect rate of direct pressurization and gradual pressurization methods. Based on the defect rate of different non-destructive testing methods, the optimal gradual pressurization rate is determined. Table 1 shows the different non-destructive testing methods for MLCCs and the corresponding test results, as shown below:

[0060] Table 1

[0061]

[0062] In Comparative Examples 1 and 2, this embodiment uses the traditional direct high-voltage application method to test the insulation resistance of multilayer ceramic chip capacitors at 70V and 90V. As can be seen from Table 1, the defect rate of multilayer ceramic chip capacitors at 90V test voltage is significantly higher than that at 70V test voltage, which indicates that high voltage can cause potential damage to the product.

[0063] In Examples 1-4, this example uses different progressive voltage application rates to test the insulation resistance of multilayer ceramic chip capacitors at 70V. As shown in Table 1, the defect rate of multilayer ceramic chip capacitors tested using the progressive voltage application method is better than that of the traditional direct voltage application method. This indicates that the progressive voltage application method can effectively reduce the damage of high voltage to multilayer ceramic chip capacitors. In addition, no defective products were found in the multilayer ceramic chip capacitors at voltage application rates of 1-10V / ms. Therefore, it can be determined that the voltage application rate of 10V / ms is the optimal progressive voltage application rate under the 70V test voltage condition, and the optimal progressive voltage application rate of the chip under the test voltage in this test is obtained.

[0064] Meanwhile, in Examples 5-8, this example uses different progressive voltage application rates to test the insulation resistance of multilayer ceramic chip capacitors at 90V. As shown in Table 1, the defect rate of multilayer ceramic chip capacitors tested using the progressive voltage application method is better than that of the traditional direct voltage application method. Similar to the 70V test voltage condition, the defect rate of multilayer ceramic chip capacitors gradually increases with the increase of the progressive voltage application rate. Only at the voltage application rate of 1V / ms, there are no defective products of multilayer ceramic chip capacitors. Therefore, it can be determined that the voltage application rate of 1V / ms is the optimal progressive voltage application rate under the 90V test voltage condition. The optimal progressive voltage application rate of the chip under the test voltage in this test is obtained.

[0065] This invention provides a method for testing the insulation resistance of a multilayer ceramic chip capacitor. The method applies a test voltage to the multilayer ceramic chip capacitor under test in a progressive manner, based on an optimal progressive voltage application rate for each test voltage. An insulation test is then performed on the capacitor under the test voltage to obtain the insulation resistance value. This value is compared with a preset insulation threshold to determine whether the multilayer ceramic chip capacitor under test is a good product. Compared to the traditional method of directly applying high voltage during testing, the progressive voltage application method used in this embodiment reduces the impact damage to good multilayer ceramic chip capacitors under test. This not only improves testing accuracy but also effectively avoids potential damage to good products caused by high test voltage. Furthermore, it prevents good multilayer ceramic chip capacitors from being mistakenly identified as defective products due to potential damage, ensuring product reliability and avoiding malfunctions or failures caused by potential damage from high voltage during use. This reduces maintenance and repair costs and improves the overall efficiency of the equipment.

[0066] It should be noted that the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0067] In one embodiment, such as Figure 3 As shown, this embodiment of the invention provides a testing device for the insulation resistance of a multilayer ceramic chip capacitor, the testing device comprising:

[0068] The progressive voltage module 101 is used to take the electroplated multilayer ceramic chip capacitor as the multilayer ceramic chip capacitor under test, and progressively apply the test voltage to the multilayer ceramic chip capacitor under test in a progressive voltage application manner according to the optimal progressive voltage application rate of each test voltage.

[0069] Insulation test module 102 is used to perform insulation test on the multilayer ceramic chip capacitor under test under the test voltage and obtain the insulation resistance value;

[0070] The good product detection module 103 is used to compare the insulation resistance value with a preset insulation threshold to determine whether the multilayer ceramic chip capacitor under test is a good product.

[0071] Specific limitations regarding the testing apparatus for the insulation resistance of a multilayer ceramic chip capacitor can be found in the above-described limitations regarding the testing method for the insulation resistance of a multilayer ceramic chip capacitor, and will not be repeated here. Those skilled in the art will recognize that the various modules and steps described in conjunction with the embodiments disclosed in this application can be implemented in hardware, software, or a combination of both. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0072] This invention provides a testing device for the insulation resistance of a multilayer ceramic chip capacitor. The device uses a progressive voltage application module to gradually apply a test voltage to the multilayer ceramic chip capacitor under test. An insulation testing module performs an insulation test on the capacitor under the test voltage to obtain the insulation resistance value. A product quality inspection module compares the insulation resistance value with a preset insulation threshold to determine whether the capacitor is a good product. Compared with existing high-voltage testing techniques, this invention uses a progressive voltage application method to gradually increase the voltage across the multilayer ceramic chip capacitor from 0V to the test voltage. This not only allows for more accurate detection of the insulation resistance but also avoids potential damage caused by directly applying high voltage, improving product quality and reliability. This helps ensure the normal operation of the equipment and extends its service life, while also reducing maintenance and repair costs, thus improving the product's economic efficiency.

[0073] Figure 4 This invention provides a computer device including a memory, a processor, and a transceiver, which are connected to each other via a bus. The memory is used to store a set of computer program instructions and data, and can transmit the stored data to the processor. The processor can execute the program instructions stored in the memory to perform the steps of the above method.

[0074] The memory may include volatile memory or non-volatile memory, or both; the processor may be a central processing unit, a microprocessor, an application-specific integrated circuit, a programmable logic device, or a combination thereof. By way of example, but not limitation, the programmable logic device described above may be a complex programmable logic device, a field-programmable gate array, a general-purpose array logic, or any combination thereof.

[0075] In addition, memory can be a physically independent unit or integrated with the processor.

[0076] Those skilled in the art will understand that Figure 4The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have the same component arrangement.

[0077] In one embodiment, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-described method.

[0078] This invention provides a method and apparatus for testing the insulation resistance of a multilayer ceramic chip capacitor. The method applies the test voltage gradually at an optimal gradual voltage application rate, avoiding potential damage from high voltage that could lead to product malfunction or premature failure. This reduces the risk of failure during use, extends the lifespan of the multilayer ceramic chip capacitor, lowers maintenance costs, and improves the overall efficiency of the equipment. Furthermore, the traditional method of directly applying high voltage is prone to safety accidents. The gradual voltage application method proposed in this embodiment reduces the dangers associated with directly applying high voltage during operation, ensuring operational safety and preventing accidents.

[0079] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., SSD), etc.

[0080] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when the computer program is executed, it can include the processes of the embodiments of the above methods.

[0081] The embodiments described above are merely preferred embodiments of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various improvements and substitutions without departing from the technical principles of this invention, and these improvements and substitutions should also be considered within the scope of protection of this application. Therefore, the scope of protection of this patent application should be determined by the scope of the claims.

Claims

1. A method for testing the insulation resistance of a multilayer ceramic chip capacitor, characterized in that, Includes the following steps: The electroplated multilayer ceramic chip capacitor is used as the multilayer ceramic chip capacitor under test, and the test voltage is gradually applied to the multilayer ceramic chip capacitor under test in a gradual voltage application manner according to the optimal gradual voltage application rate of each test voltage. The insulation resistance value is obtained by performing an insulation test on the multilayer ceramic chip capacitor under the test voltage. The insulation resistance value is compared with a preset insulation threshold to determine whether the multilayer ceramic chip capacitor under test is a good product. The test voltage is between 5 and 10 times the rated voltage of the multilayer ceramic capacitor under test; the gradual voltage increase method employs linear voltage increase and raises the test voltage at the optimal gradual voltage increase rate; the process of determining the optimal gradual voltage increase rate includes: Several electroplated multilayer ceramic chip capacitors were pre-selected as non-destructive testing samples, and the test voltage for this test was determined. Under different progressive pressurization rates, the test voltage for this test is progressively applied to the non-destructive testing sample in a progressive pressurization manner, and an insulation test is performed to obtain the non-destructive testing sample after the test. By performing nondestructive testing on each of the tested samples using different nondestructive testing methods, the optimal progressive pressurization rate of the tested samples under the test voltage in this test was determined.

2. The method for testing the insulation resistance of a multilayer ceramic chip capacitor as described in claim 1, characterized in that: The optimal gradual pressurization rate is between 1 and 20 V / ms.

3. The method for testing the insulation resistance of a multilayer ceramic chip capacitor as described in claim 1, characterized in that, The insulation threshold is calculated based on the capacitance of the multilayer ceramic chip capacitor under test, and the formula for calculating the insulation threshold is: In the formula, Indicates the insulation threshold; This indicates the capacitance of the multilayer ceramic chip capacitor under test. This indicates the time constant setting value.

4. The method for testing the insulation resistance of a multilayer ceramic chip capacitor as described in claim 3, characterized in that: The time constant is set to 500 MΩ·μF.

5. The method for testing the insulation resistance of a multilayer ceramic chip capacitor as described in claim 1, characterized in that: The multilayer ceramic chip capacitor under test is a Class II ceramic multilayer ceramic chip capacitor with a ceramic dielectric thickness ranging from 1 to 5 mm. ; The dimensions of the multilayer ceramic chip capacitor under test are between 0.603 and 1.210 in imperial units.

6. The method for testing the insulation resistance of a multilayer ceramic chip capacitor as described in claim 1, characterized in that: The non-destructive testing methods include breakdown voltage testing methods, ultrasonic flaw detection methods, and initial fault detection methods.

7. The method for testing the insulation resistance of a multilayer ceramic chip capacitor as described in claim 6, characterized in that, The step of performing non-destructive testing on each of the tested non-destructive testing samples using different non-destructive testing methods, and determining the optimal progressive pressurization rate of the tested non-destructive testing sample under the test voltage of this test, includes: When using the breakdown voltage detection method, a breakdown voltage tester is used to test the breakdown voltage of a first preset number of the tested non-destructive testing samples, and the breakdown voltage failure rate is determined. When using the ultrasonic flaw detection method, a second preset number of the tested non-destructive testing samples are inspected by an ultrasonic scanning microscope, and the proportion of ultrasonic flaws is determined. When using the initial fault detection method, a third preset number of the tested non-destructive testing samples are placed in an oven at the rated upper limit temperature, and a DC power supply is connected to both ends of the tested non-destructive testing samples and maintained for a first preset time to obtain an initial fault detection product. The initial fault detection product is then placed in a constant temperature and humidity chamber at 85°C and 85%RH, and a DC power supply is connected and maintained for a second preset time to determine the initial fault rate. The voltage output by the DC power supply is the rated voltage of the non-destructive testing sample. Based on the breakdown voltage failure rate, the ultrasonic flaw detection failure rate, and the initial fault failure rate, the optimal progressive pressurization rate of the non-destructive testing sample under the test voltage in this test is determined.

8. A testing device for the insulation resistance of a multilayer ceramic chip capacitor, characterized in that, The testing apparatus includes: The progressive voltage module is used to take the electroplated multilayer ceramic chip capacitor as the multilayer ceramic chip capacitor under test, and progressively apply the test voltage to the multilayer ceramic chip capacitor under test in a progressive voltage application manner according to the optimal progressive voltage application rate for each test voltage. An insulation test module is used to perform an insulation test on the multilayer ceramic chip capacitor under test under the test voltage and obtain the insulation resistance value. The good product detection module is used to compare the insulation resistance value with a preset insulation threshold to determine whether the multilayer ceramic chip capacitor under test is a good product. The test voltage is between 5 and 10 times the rated voltage of the multilayer ceramic capacitor under test; the gradual voltage increase method employs linear voltage increase and raises the test voltage at the optimal gradual voltage increase rate; the process of determining the optimal gradual voltage increase rate includes: Several electroplated multilayer ceramic chip capacitors were pre-selected as non-destructive testing samples, and the test voltage for this test was determined. Under different progressive pressurization rates, the test voltage for this test is progressively applied to the non-destructive testing sample in a progressive pressurization manner, and an insulation test is performed to obtain the non-destructive testing sample after the test. By performing nondestructive testing on each of the tested samples using different nondestructive testing methods, the optimal progressive pressurization rate of the tested samples under the test voltage in this test was determined.

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