A small high-capacity multilayer chip ceramic capacitor test screening method and device

Abstract

The present application relates to the technical field of multilayer chip ceramic capacitor testing, and particularly relates to a small high-capacity multilayer chip ceramic capacitor testing and screening method and device, which comprises the following steps: in each testing round, the preselected multilayer chip ceramic capacitors to be tested are subjected to insulation testing through optimal testing voltage, the testing insulation resistance of the current testing is obtained, the testing insulation resistance and the insulation resistance threshold are compared, the good multilayer chip ceramic capacitors are screened out from the multilayer chip ceramic capacitors to be tested, the good multilayer chip ceramic capacitors are subjected to heat treatment, the multilayer chip ceramic capacitors to be tested of the next testing round are obtained, until the testing round is reached, and the good multilayer chip ceramic capacitors output by the last testing are obtained. The small high-capacity MLCC is tested and screened through heat treatment and multiple insulation resistance testing, the products with unqualified insulation resistance in the small high-capacity MLCC are effectively screened out, and the reliability of the products is improved.

Description

Technical Field

[0001] This invention relates to the field of multilayer ceramic chip capacitor testing technology, and in particular to a method and apparatus for testing and screening small, high-capacity multilayer ceramic chip capacitors. Background Technology

[0002] Multilayer ceramic chip capacitors (MLCCs) are important electronic components that store (charge) and release (discharge) charge. They serve as decouplers, filters, and smooth voltages in electronic devices and are widely used in the electronics industry. To ensure their performance and quality, manufacturers use specialized testing machines to comprehensively inspect MLCCs after production, eliminating products that fail to meet key indicators such as capacitance, loss, and insulation resistance, thus ensuring product reliability during consumer use.

[0003] Generally, when testing the insulation resistance of products, testing machines typically use voltages several times or tens of times higher than the rated voltage to ensure that defective products with unacceptable insulation resistance are effectively screened out while good products with acceptable insulation resistance are not affected. However, as MLCCs develop towards higher capacitance and smaller size, the test voltage becomes increasingly difficult to define. It is becoming increasingly difficult to simultaneously screen out defective products with unacceptable insulation resistance and good products with normal insulation resistance in a single test. Therefore, how to effectively test and screen small-sized, high-capacity MLCCs has become a technical challenge, and there is an urgent need to provide a testing and screening method suitable for small-sized, high-capacity multilayer ceramic chip capacitors. Summary of the Invention

[0004] This invention provides a testing and screening method and apparatus for small, high-capacity multilayer ceramic chip capacitors (MLCCs). The technical problem it solves is that traditional MLCC insulation resistance testing methods are difficult to adapt to the testing requirements of small-sized, high-capacity MLCCs.

[0005] To address the above technical problems, this invention provides a method and apparatus for testing and screening small, high-capacity multilayer ceramic chip capacitors.

[0006] In a first aspect, the present invention provides a method for testing and screening small, high-capacity multilayer ceramic chip capacitors, the method comprising the following steps:

[0007] Several electroplated multilayer ceramic chip capacitors were used as the multilayer ceramic chip capacitors to be tested, and the test rounds and the optimal test voltage corresponding to each test round were determined.

[0008] In each test round, the insulation test of the multilayer ceramic chip capacitor under test is performed using the optimal test voltage to obtain the test insulation resistance for that test. The test insulation resistance is then compared with a preset insulation resistance threshold to select good multilayer ceramic chip capacitors from the multilayer ceramic chip capacitors under test. The good multilayer ceramic chip capacitors are then heat-treated using the optimal heat treatment test conditions to obtain the multilayer ceramic chip capacitors to be tested for insulation testing in the next test round, until the test round is reached.

[0009] The good multilayer ceramic chip capacitors output from the last test were used as the test screening results.

[0010] In a further embodiment, the test rounds include at least two test rounds.

[0011] In a further implementation scheme, if the test is the first test, the optimal test voltage for the first test is 4 to 8 times the rated voltage of the multilayer ceramic chip capacitor under test.

[0012] In a further implementation scheme, if the current test is not the first round of testing, the optimal test voltage for the current test is 0.4 to 0.8 times the optimal test voltage in the previous test round.

[0013] In a further embodiment, the optimal test conditions for heat treatment include the optimal test temperature and the optimal test time for heat treatment.

[0014] The optimal test temperature for heat treatment is between 90 and 150°C, and the optimal test time for heat treatment is determined based on the optimal test temperature for heat treatment.

[0015] In a further implementation, the insulation resistance threshold is determined based on a preset time constant and the capacitance of the multilayer ceramic chip capacitor under test. The formula for calculating the insulation resistance threshold is as follows:

[0016]

[0017] In the formula, γ represents the insulation resistance threshold; C represents the capacitance of the multilayer ceramic chip capacitor under test; and α represents the preset time constant.

[0018] In a further embodiment, the multilayer ceramic chip capacitor under test is a Class II ceramic multilayer ceramic chip capacitor with a ceramic dielectric thickness between 0.5 and 2 μm.

[0019] In a further embodiment, the method further includes: performing reliability verification on the test screening results, and updating the optimal test voltage and optimal heat treatment test conditions for the batch of multilayer ceramic chip capacitors in different test rounds based on the reliability verification results.

[0020] In a further implementation, the step of performing reliability verification on the test screening results includes:

[0021] The test screening results are divided into multiple good product groups of different numbers; each good product group corresponds to a reliability verification method, which includes a breakdown voltage test method, an ultrasonic scanning flaw detection method, and an accelerated life test method.

[0022] Different reliability testing methods were used to conduct reliability tests on the good product group under different test conditions, and the corresponding defect rate was recorded to obtain the reliability verification results.

[0023] Based on all the aforementioned defect rates, the optimal test voltage and optimal heat treatment test conditions for this batch of multilayer ceramic chip capacitors in different test rounds were re-determined.

[0024] Secondly, the present invention provides a small, high-capacity multilayer ceramic chip capacitor testing and screening device, the device comprising:

[0025] The parameter determination module is used to select several electroplated multilayer ceramic chip capacitors as multilayer ceramic chip capacitors to be tested, and to determine the test rounds and the optimal test voltage corresponding to each test round.

[0026] The good product testing and screening module is used to perform insulation testing on the multilayer ceramic chip capacitor under test using the optimal test voltage in each test round, obtain the test insulation resistance of the current test, compare the test insulation resistance with the preset insulation resistance threshold, screen out good multilayer ceramic chip capacitors from the multilayer ceramic chip capacitors under test, perform heat treatment on the good multilayer ceramic chip capacitors using the optimal heat treatment test conditions, and obtain the multilayer ceramic chip capacitors to be tested for insulation testing in the next test round, until the test round is reached;

[0027] The screening result determination module is used to select the good multilayer ceramic chip capacitors output from the last test as the test screening result.

[0028] This invention provides a method and apparatus for testing and screening small, high-capacity multilayer ceramic chip capacitors (MLCCs). The method involves performing an insulation test on the MLCC under test at an optimal test voltage in each test round, obtaining the insulation resistance for that test, and comparing the measured insulation resistance with a preset insulation resistance threshold. Good MLCCs are then selected from the test samples. These good MLCCs are then subjected to optimal heat treatment conditions to obtain the MLCCs to be tested in the next test round. This process continues until the final test round, yielding the good MLCCs output from the last test. Compared to existing single-test screening techniques, this method, based on heat treatment and multiple-test screening, can more accurately measure the insulation resistance of MLCCs, more effectively screen out products with substandard insulation resistance from small, high-capacity MLCCs without affecting the normal insulation resistance of good products. This improves testing accuracy, reduces the defect rate among qualified products, enhances the safety and reliability of electronic equipment, and helps manufacturers save significant time and costs. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the testing and screening method for small, high-capacity multilayer ceramic chip capacitors provided in an embodiment of the present invention.

[0030] Figure 2 This is a block diagram of a small, high-capacity multilayer ceramic chip capacitor testing and screening device provided in an embodiment of the present invention;

[0031] Figure 3 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0032] The embodiments of the present invention are described in detail below with reference to the accompanying drawings. The embodiments are given for illustrative purposes only and should not be construed as limiting the present invention. The accompanying drawings are for reference and illustration only and do not constitute a limitation on the scope of patent protection of the present invention, because many changes can be made to the present invention without departing from the spirit and scope of the present invention.

[0033] refer to Figure 1 This invention provides a testing and screening method for small, high-capacity multilayer ceramic chip capacitors (MLCCs), applicable to all products tested, such as... Figure 1 As shown, the method includes the following steps:

[0034] S1. Select several electroplated multilayer ceramic chip capacitors as the multilayer ceramic chip capacitors to be tested, and determine the test rounds and the optimal test voltage corresponding to each test round.

[0035] Multilayer ceramic chip capacitors (MLCCs) exist in various types. MLCCs can be divided into two types: Class I ceramic (low capacitance series, electrostatic) and Class II ceramic (high capacitance series, ferroelectric). In this embodiment, the multilayer ceramic chip capacitor under test is a Class II ceramic multilayer ceramic chip capacitor, with dimensions between 0.1005 and 0.402 in imperial units and a ceramic dielectric thickness between 0.5 and 2 μm. To address the increasingly difficult problem of simultaneously eliminating defective products with unacceptable insulation resistance and good products that do not affect normal insulation resistance in a single test of small, high-capacity multilayer ceramic chip capacitors, this embodiment sets... The test cycle shall include at least two test cycles. The test cycle shall be used to determine whether the current test (this test cycle) is the first test cycle. If the current test is the first test cycle, the optimal test voltage for the first test cycle shall be 4 to 8 times the rated voltage of the multilayer ceramic chip capacitor under test. If the current test is not the first test cycle, the optimal test voltage for the current test cycle shall be 0.4 to 0.8 times the optimal test voltage of the previous test cycle. The test voltage can be preliminarily determined in advance using reliability testing methods (breakdown voltage, ultrasonic testing, and accelerated life testing). Those skilled in the art can set specific test voltage values ​​according to specific implementation conditions. This embodiment of the invention does not impose any limitations.

[0036] S2. In each test round, the insulation test is performed on the multilayer ceramic chip capacitor under test using the optimal test voltage to obtain the test insulation resistance for that test. The test insulation resistance is then compared with a preset insulation resistance threshold. Good multilayer ceramic chip capacitors are selected from the multilayer ceramic chip capacitors under test. The good multilayer ceramic chip capacitors are then heat-treated using the optimal heat treatment test conditions to obtain the multilayer ceramic chip capacitors to be tested for insulation testing in the next test round, until the test round is reached.

[0037] In each test, this embodiment performs an insulation resistance test on the multilayer ceramic chip capacitor under test at the optimal test voltage to obtain the insulation resistance. The insulation resistance is then compared with a preset insulation resistance threshold. If the insulation resistance is higher than the insulation resistance threshold, the multilayer ceramic chip capacitor under test is determined to be a good product; if the insulation resistance is lower than the insulation resistance threshold, the multilayer ceramic chip capacitor under test is determined to be a defective product. Then, the good multilayer ceramic chip capacitors after this round of insulation resistance testing are heat-treated at a certain temperature for a preset heat treatment time. After the heat-treated good multilayer ceramic chip capacitors are placed for a certain period of time, the testing machine is used to continue the next round of insulation resistance testing. It should be noted that in the last round of testing, it is only necessary to compare the tested insulation resistance with the insulation resistance threshold to select good multilayer ceramic chip capacitors from the multilayer ceramic chip capacitors under test, without needing to perform a heat treatment step on the good multilayer ceramic chip capacitors.

[0038] In this embodiment, when heat-treating the good multilayer ceramic chip capacitors, the optimal heat treatment test conditions are used to heat-treat the good products after this round of testing. The optimal heat treatment test conditions include the optimal heat treatment test temperature and the optimal heat treatment test time. In order to ensure the reliability of product testing, this embodiment sets the optimal heat treatment test temperature between 90 and 150°C, and the optimal heat treatment test time is determined according to the optimal heat treatment test temperature. The optimal heat treatment test time can be set to 30 minutes.

[0039] In this embodiment, the insulation resistance threshold is determined based on a preset time constant and the capacitance of the multilayer ceramic chip capacitor under test. The formula for calculating the insulation resistance threshold is as follows:

[0040]

[0041] In the formula, γ represents the insulation resistance threshold; C represents the capacitance of the multilayer ceramic chip capacitor to be tested; α represents the preset time constant, which is preferably set to 500MΩ·μF.

[0042] S3. The good multilayer ceramic chip capacitors output from the last test are used as the test screening results.

[0043] The method for testing and screening small, high-capacity multilayer ceramic chip capacitors proposed in this embodiment further includes: performing reliability verification on the test screening results, and updating the optimal test voltage and optimal heat treatment test conditions for the batch of multilayer ceramic chip capacitors in different test rounds based on the reliability verification results. The step of performing reliability verification on the test screening results includes:

[0044] The test screening results are divided into multiple good product groups of different numbers; each good product group corresponds to a reliability verification method, which includes a breakdown voltage test method, an ultrasonic scanning flaw detection method, and an accelerated life test method.

[0045] Different reliability testing methods were used to conduct reliability tests on the good product group under different test conditions, and the corresponding defect rate was recorded to obtain the reliability verification results.

[0046] Based on all the aforementioned defect rates, the optimal test voltage and optimal heat treatment test conditions for this batch of multilayer ceramic chip capacitors in different test rounds were re-determined.

[0047] To facilitate understanding of the testing and screening method for small, high-capacity multilayer ceramic chip capacitors proposed in this invention, the following example illustrates the method using two rounds of insulation testing. In this example, the multilayer ceramic chip capacitor uses an imperial 0201 size, X5R temperature characteristics, a 10V rated voltage (U0), and a 1μF capacitance. The testing and screening method for multilayer ceramic chip capacitors includes steps such as primary testing, heat treatment, secondary testing, and reliability verification. The specific process is as follows:

[0048] Several electroplated multilayer ceramic chip capacitors were selected as multilayer ceramic chip capacitors to be tested. An insulation resistance test was performed on the multilayer ceramic chip capacitors to be tested under the optimal test voltage of a single test to obtain the single test insulation resistance. The single test insulation resistance was then compared with a preset insulation resistance threshold to select good multilayer ceramic chip capacitors from the multilayer ceramic chip capacitors to be tested.

[0049] For the good multilayer ceramic chip capacitors after the first test, heat treatment is carried out at a certain temperature for 30 minutes. After the heat-treated good multilayer ceramic chip capacitors are placed for 24 hours, heat-treated ceramic capacitors are obtained. A second test is carried out using a testing machine. The insulation resistance of the heat-treated ceramic capacitors is tested at the optimal test voltage of the second test. The insulation resistance of the second test is obtained and compared with the preset insulation resistance threshold. Good multilayer ceramic chip capacitors that have passed the second test are selected from the heat-treated ceramic capacitors, and the final test selection results are obtained.

[0050] In this embodiment, after performing secondary testing on the multilayer ceramic chip capacitor under test, the reliability (breakdown voltage, ultrasonic testing, and accelerated life) of the good multilayer ceramic chip capacitors after the secondary testing is verified. Based on the lowest temperature and lowest voltage corresponding to the absence of defective products, the optimal test voltage and optimal heat treatment test conditions are determined. The breakdown voltage, ultrasonic testing, and accelerated life verification processes are as follows:

[0051] Breakdown voltage: In this embodiment, 100 good MLCCs after secondary testing were selected, and a breakdown voltage tester was used to test the breakdown voltage. The proportion of poor breakdown voltage (breakdown voltage < 8U0) was recorded.

[0052] Ultrasonic flaw detection: In this example, 1000 good MLCCs after secondary testing were selected and inspected using an ultrasonic scanning microscope, and the proportion of defective products was recorded.

[0053] Accelerated Life Testing: In this example, 1000 good MLCCs after secondary testing were selected and placed in an oven at the rated upper limit temperature. A DC power supply of 2 times U0 was applied for 168 hours. The products were then removed and allowed to stand at room temperature for 24 hours. The insulation resistance of the products was tested using an insulation resistance tester at the rated voltage, and the accelerated life test results were recorded (MLCC insulation resistance < 1 × 10⁻⁶). 6 (Ω) Failure rate, where U0 is the rated voltage of the multilayer ceramic chip capacitor under test. Table 1 shows the MLCC test process and reliability inspection results, as shown below:

[0054] Table 1

[0055]

[0056]

[0057] As shown in Table 1, in Comparative Example 1, this embodiment uses the traditional one-time testing process and uses a 50V test voltage to test the insulation resistance of the product. It can be seen that the good products selected by the traditional one-time testing process show different degrees of defects in different reliability testing methods. This indicates that there are still some products with poor reliability among the good products selected by only one test.

[0058] In Examples 1-9, this example employs the proposed multiple testing process and uses a 50V test voltage to perform insulation resistance testing on the product. It can be seen that as the heat treatment temperature increases, the defect rate of the product gradually decreases. Among the secondary insulation resistance test voltages, the defect rate is lowest at the moderate voltage. The optimal secondary test conditions are obtained at 150℃ and a secondary insulation resistance test voltage of 37.5V, and the product has no defects. Compared with the traditional single-round testing process, the multi-round testing process proposed in this example significantly improves the reliability of the product.

[0059] This invention provides a method for testing and screening small, high-capacity multilayer ceramic chip capacitors (MLCCs). In each test round, the method performs an insulation test on the MLCC under test using an optimal test voltage, obtains the insulation resistance for that test, and compares it with a preset insulation resistance threshold. Good MLCCs are then selected from the tested MLCCs. Based on the good MLCCs and a heat treatment method, the next test round's MLCCs for insulation testing are determined, until all test rounds are completed. The good MLCCs output from the final test are used as the screening result. Compared to traditional single-stage testing, this multilayer ceramic chip capacitor testing and screening method based on multi-round testing and heat treatment can more accurately identify defective products, avoid missed or false detections, and effectively eliminate defective products with unacceptable insulation resistance. This achieves rapid and accurate screening of defective products, reducing the defect rate among qualified products. This not only improves testing accuracy and production efficiency but also saves the cost and time of manual inspection, meeting the quality and performance requirements of modern electronic equipment for MLCCs.

[0060] It should be noted that the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0061] In one embodiment, such as Figure 2 As shown, this embodiment of the invention provides a small, high-capacity multilayer ceramic chip capacitor testing and screening device, the device comprising:

[0062] The parameter determination module 101 is used to take several electroplated multilayer ceramic chip capacitors as multilayer ceramic chip capacitors to be tested, and determine the test rounds and the optimal test voltage corresponding to each test round.

[0063] The good product testing and screening module 102 is used to perform insulation testing on the multilayer ceramic chip capacitor under test using the optimal test voltage in each test round, obtain the test insulation resistance of the current test, compare the test insulation resistance with the preset insulation resistance threshold, screen out good multilayer ceramic chip capacitors from the multilayer ceramic chip capacitors under test, perform heat treatment on the good multilayer ceramic chip capacitors using the optimal heat treatment test conditions, and obtain the multilayer ceramic chip capacitors under test for insulation testing in the next test round, until the test round is reached;

[0064] The screening result determination module 103 is used to take the good multilayer ceramic chip capacitors output in the last test as the test screening result.

[0065] Specific limitations regarding the testing and screening device for small, high-capacity multilayer ceramic chip capacitors can be found in the aforementioned limitations regarding the testing and screening method for small, high-capacity multilayer ceramic chip capacitors, and will not be repeated here. Those skilled in the art will recognize that the various modules and steps described in conjunction with the embodiments disclosed in this application can be implemented in hardware, software, or a combination of both. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0066] This invention provides a small, high-capacity multilayer ceramic chip capacitor testing and screening device. The device determines the test rounds and the optimal test voltage corresponding to each test round through a parameter determination module; performs multiple rounds of insulation testing and heat treatment on the multilayer ceramic chip capacitors under test through a good product testing and screening module; and uses a screening result determination module to take the good multilayer ceramic chip capacitors output from the last test as the screening result. Compared with traditional single-stage testing processes, the multilayer ceramic chip capacitor testing and screening method based on multi-round testing and heat treatment proposed in this application can quickly and accurately eliminate defective products with unqualified insulation resistance, improving testing accuracy, reducing the defect rate among qualified products, and improving the safety and reliability of subsequent electronic equipment. It has advantages such as high accuracy and high reliability.

[0067] Figure 3 This invention provides a computer device including a memory, a processor, and a transceiver, which are connected to each other via a bus. The memory is used to store a set of computer program instructions and data, and can transmit the stored data to the processor. The processor can execute the program instructions stored in the memory to perform the steps of the above method.

[0068] The memory may include volatile memory or non-volatile memory, or both; the processor may be a central processing unit, a microprocessor, an application-specific integrated circuit, a programmable logic device, or a combination thereof. By way of example, but not limitation, the programmable logic device described above may be a complex programmable logic device, a field-programmable gate array, a general-purpose array logic, or any combination thereof.

[0069] In addition, memory can be a physically independent unit or integrated with the processor.

[0070] Those skilled in the art will understand that Figure 3The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have the same component arrangement.

[0071] In one embodiment, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-described method.

[0072] This invention provides a method and apparatus for testing and screening small, high-capacity multilayer ceramic chip capacitors (MLCCs). This method, through heat treatment technology and multiple rounds of testing, can more accurately screen out defective MLCCs with substandard insulation resistance, improving testing accuracy and avoiding missed or false detections. It boasts advantages such as high precision, high reliability, and wide applicability, meeting the current quality and performance requirements of electronic devices for MLCCs.

[0073] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., SSD), etc.

[0074] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when the computer program is executed, it can include the processes of the embodiments of the above methods.

[0075] The embodiments described above are merely preferred embodiments of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various improvements and substitutions without departing from the technical principles of this invention, and these improvements and substitutions should also be considered within the scope of protection of this application. Therefore, the scope of protection of this patent application should be determined by the scope of the claims.

Claims

1. A method for testing and screening small, high-capacity multilayer ceramic chip capacitors, characterized in that, Includes the following steps: Several electroplated multilayer ceramic chip capacitors were used as the multilayer ceramic chip capacitors to be tested, and the test rounds and the optimal test voltage corresponding to each test round were determined. The test rounds included at least two test rounds. If the current test was the first test round, the optimal test voltage for the first test round was 4 to 8 times the rated voltage of the multilayer ceramic chip capacitor to be tested. If the current test was not the first test round, the optimal test voltage for the current test round was 0.4 to 0.8 times the optimal test voltage in the previous test round. In each test round, the insulation resistance of the multilayer ceramic chip capacitor under test is obtained by using the optimal test voltage. The test insulation resistance is then compared with a preset insulation resistance threshold. Good multilayer ceramic chip capacitors are selected from the test capacitors. These good capacitors are then subjected to heat treatment under optimal heat treatment conditions to obtain the multilayer ceramic chip capacitors to be tested in the next test round for insulation testing. This process continues until the next test round is reached. The optimal heat treatment conditions include an optimal heat treatment temperature and an optimal heat treatment time. The optimal heat treatment temperature is between 90 and 150°C. The good multilayer ceramic chip capacitors output from the last test were used as the test screening results.

2. The method for testing and screening small, high-capacity multilayer ceramic chip capacitors as described in claim 1, characterized in that: The optimal test time for heat treatment is determined based on the optimal test temperature for heat treatment.

3. The method for testing and screening small, high-capacity multilayer ceramic chip capacitors as described in claim 1, characterized in that, The insulation resistance threshold is determined based on a preset time constant and the capacitance of the multilayer ceramic chip capacitor under test. The calculation formula for the insulation resistance threshold is as follows: In the formula, Indicates the insulation resistance threshold; This indicates the capacitance of the multilayer ceramic chip capacitor under test. This indicates the preset time constant.

4. The method for testing and screening small, high-capacity multilayer ceramic chip capacitors as described in claim 1, characterized in that: The multilayer ceramic chip capacitor under test is a Class II ceramic multilayer ceramic chip capacitor with a ceramic dielectric thickness between 0.5 and 2 μm.

5. The method for testing and screening small, high-capacity multilayer ceramic chip capacitors as described in claim 1, characterized in that, The method further includes: performing reliability verification on the test screening results, and updating the optimal test voltage and optimal heat treatment test conditions for the batch of multilayer ceramic chip capacitors in different test rounds based on the reliability verification results.

6. The method for testing and screening small, high-capacity multilayer ceramic chip capacitors as described in claim 5, characterized in that, The step of verifying the reliability of the test screening results includes: The test screening results are divided into multiple good product groups of different numbers; each good product group corresponds to a reliability verification method, which includes a breakdown voltage test method, an ultrasonic scanning flaw detection method, and an accelerated life test method. Different reliability testing methods were used to conduct reliability tests on the good product group under different test conditions, and the corresponding defect rate was recorded to obtain the reliability verification results. Based on all the aforementioned defect rates, the optimal test voltage and optimal heat treatment test conditions for this batch of multilayer ceramic chip capacitors in different test rounds were re-determined.

7. A small, high-capacity multilayer ceramic chip capacitor testing and screening device, characterized in that, The device includes: The parameter determination module is used to select several electroplated multilayer ceramic chip capacitors as multilayer ceramic chip capacitors to be tested, and to determine the test rounds and the optimal test voltage corresponding to each test round; wherein, the test rounds include at least two test rounds; if the current test is the first test round, the optimal test voltage for the first test round is 4 to 8 times the rated voltage of the multilayer ceramic chip capacitor under test; if the current test is not the first test round, the optimal test voltage for the current test round is 0.4 to 0.8 times the optimal test voltage in the previous test round; The good product screening module is used to perform insulation testing on the multilayer ceramic chip capacitor under test using the optimal test voltage in each test round, obtain the test insulation resistance for that test, compare the test insulation resistance with a preset insulation resistance threshold, and screen out good multilayer ceramic chip capacitors from the test multilayer ceramic chip capacitors. The good multilayer ceramic chip capacitors are then heat-treated using optimal heat treatment test conditions to obtain the multilayer ceramic chip capacitors to be tested for insulation testing in the next test round, until the test round is reached. The optimal heat treatment test conditions include an optimal heat treatment test temperature and an optimal heat treatment test time; the optimal heat treatment test temperature is between 90 and 150°C. The screening result determination module is used to select the good multilayer ceramic chip capacitors output from the last test as the test screening result.

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