A selection switching heating circuit, a junction temperature testing circuit and a junction temperature testing method

Abstract

This application relates to the technical field of aging testing, and in particular to a selection and switching heating circuit, a junction temperature testing circuit, and a junction temperature testing method. It includes: a voltage source, comprising a positive terminal PWR+ and a negative terminal PWR-, for providing a heating voltage to the MOSFET under test; a heating current supply module for outputting a corresponding constant heating current based on a reference current; a MOSFET placement module for placing the MOSFET under test, connected to the voltage source; a power supply reversal switching module connected to the heating current supply module, used to switch the position of the positive terminal PWR+ of the voltage source according to the type of the MOSFET under test to change the direction of the reference current; and a signal reversal switching module for switching the signal corresponding to the constant heating current in either direction according to the type of the MOSFET under test on the MOSFET placement module. This application achieves compatible junction temperature testing for both NMOS and PMOS transistors.

Description

Technical Field

[0001] This application relates to the technical field of aging testing, and in particular to a selection and switching heating circuit, a junction temperature testing circuit, and a junction temperature testing method. Background Technology

[0002] Junction temperature testing is a commonly used aging test method used to measure the temperature of electronic components or circuit boards under certain heating conditions to evaluate the thermal performance and reliability of the equipment; common heating conditions are applying current, voltage or power to the equipment.

[0003] Currently, due to the lack of junction temperature testing circuits compatible with both PMOS and NMOS, junction temperature testing of different types of MOSFETs is generally performed using two separate devices. Currently, the usage rate of NMOS is relatively high, while the usage rate of PMOS is relatively low. Consequently, there are more orders for junction temperature testing of NMOS. However, since PMOS also has certain junction temperature requirements, testing often requires the simultaneous production or purchase of two devices corresponding to different types of MOSFETs. Therefore, performing junction temperature testing of different MOSFETs using two separate devices leads to higher costs. Summary of the Invention

[0004] The purpose of this application is to enable compatible junction temperature testing for NMOS and PMOS.

[0005] Firstly, this application provides a selection and switching heating circuit, which adopts the following technical solution: A selectable switching heating circuit includes: The voltage source, including the positive terminal PWR+ and the negative terminal PWR- of the power supply voltage, is used to provide heating voltage to the MOSFET under test. A heating current providing module includes an input terminal and an output terminal. The input terminal is connected to the voltage source to provide a reference current according to the voltage source, and the output terminal is used to output a corresponding constant heating current according to the reference current. A MOS transistor placement module is used to place the MOS transistor under test, which is connected to the voltage source. The MOS transistor under test includes PMOS or NMOS. A power reverse switching module is connected to the heating current supply module. The power reverse switching module is used to switch the position of the positive terminal PWR+ of the power supply voltage of the voltage source according to the type of the MOS transistor under test on the MOS transistor placement module in order to change the direction of the reference current. The signal inversion switching module is connected at one end to the power inversion switching module to receive a constant heating current, and at the other end to the MOS transistor placement module. The signal inversion switching module is used to switch the signal corresponding to the constant heating current in either direction according to the type of MOS transistor under test on the MOS transistor placement module.

[0006] In other embodiments, the MOS transistor placement module includes a first side and a second side, the first side corresponding to the gate of the MOS transistor under test, the second side corresponding to the drain and source of the MOS transistor under test, the first side being connected to the signal inversion switching module, and the second side being connected to the voltage source. When the MOSFET under test is an NMOS, the source of the MOSFET under test is connected to the negative terminal of the power supply voltage PWR-, and the drain of the MOSFET under test is connected to the positive terminal of the power supply voltage PWR+. When the MOSFET under test is a PMOS, the source of the MOSFET under test is connected to the positive terminal of the power supply voltage PWR+, and the drain of the MOSFET under test is connected to the negative terminal of the power supply voltage PWR-.

[0007] In other embodiments, the heating current providing module includes a sampling resistor RSH, a first differential amplifier U1, a first operational amplifier P1, a first resistor R1, and a first comparator Q1, wherein, One end of the sampling resistor RSH is connected to the positive terminal PWR+ of the power supply voltage, and the other end is connected to the negative terminal PWR- of the power supply voltage. The end connected to the positive terminal PWR+ of the power supply voltage is also connected to the positive input terminal of the first differential amplifier U1, and the end connected to the negative terminal PWR- of the power supply voltage is also connected to the negative input terminal of the first differential amplifier U1. The output terminal of the first differential amplifier U1 is connected to the non-inverting input terminal of the first operational amplifier P1, the inverting input terminal of the first operational amplifier P1 is grounded, and the output terminal of the first operational amplifier P1 is connected to the inverting input terminal of the first comparator Q1. The non-inverting input of the first comparator Q1 is used to obtain the reference voltage, and the output of the first comparator Q1 is connected to the signal inverting switching module. The first resistor R1 is connected between the inverting input terminal and the output terminal of the first operational amplifier P1.

[0008] In other embodiments, the power reverse switching module includes a first relay switch K1, one end of which is grounded and connected to the first differential amplifier U1, and the other end is in a floating state to selectively engage with either the positive terminal PWR+ or the negative terminal PWR- of the power supply voltage based on the type of the MOSFET under test on the MOSFET placement module.

[0009] In other embodiments, the signal inversion switching module includes a second operational amplifier P2, a second resistor R2, and a second relay switch K2. The non-inverting input of the second operational amplifier P2 is grounded, and the inverting input is connected to the output of the first comparator Q1. The second resistor R2 is connected between the inverting input terminal and the output terminal of the second operational amplifier P2; One end of the second relay switch K2 is connected to the gate of the corresponding MOS transistor under test in the MOS transistor placement module, and the other end is in a floating state to be connected to the P-path or N-path according to the type of MOS transistor under test in the MOS transistor placement module. The N-path is connected to the output terminal of the first amplifier Q1, and the P-path is connected to the output terminal of the second operational amplifier P2.

[0010] Secondly, the junction temperature testing circuit provided in this application adopts the following technical solution: A junction temperature testing circuit, including the above-mentioned selection and switching heating circuit, further includes: A temperature detection module, connected to the MOS transistor placement module, is used to detect the voltage value of the parasitic diode corresponding to the MOS transistor under test, and calculate the temperature of the MOS transistor under test based on the voltage value and the temperature sensitivity coefficient k corresponding to the parasitic diode. A test current supply module is connected to the MOS transistor placement module to provide a detection current, which is used to keep the temperature sensitivity coefficient k corresponding to the parasitic diode constant. A junction temperature control module is connected to the MOS transistor placement module and the voltage source, and is used to control the voltage source and the MOS transistor under test on the MOS transistor placement module to disconnect according to the junction temperature test requirements.

[0011] In other embodiments, the temperature detection module includes a second differential amplifier U2, a third resistor R3, and a first Zener diode D1. The positive and negative input terminals of the second differential amplifier U2 are both connected to the second side of the MOS transistor placement module, and the output terminal is connected to the third resistor R3. The other end of the third resistor R3 is connected to the positive terminal of the first Zener diode D1, and the negative terminal of the first Zener diode D1 is connected to the common terminal of the second differential amplifier U2.

[0012] In other embodiments, the junction temperature control module includes a first switch control circuit. The first switch control circuit includes a first optocoupler OC1 and a switching transistor M1. The input terminal of the first optocoupler OC1 is used to receive a switch command and control the switching transistor M1 to turn off or on according to the switch command. The output terminal of the first optocoupler OC1 is connected to the gate of the switching transistor M1. The drain of the switching transistor M1 is connected to the negative terminal of the power supply voltage PWR-, and the source of the switching transistor M1 is connected to the positive terminal of the power supply voltage PWR+.

[0013] In other embodiments, the junction temperature control module further includes a second switch control circuit and a third switch control circuit connected in parallel, wherein, The second switch control circuit includes a second optocoupler OC2. The output terminal of the second optocoupler OC2 is connected to the first side of the MOS transistor placement module and ground, respectively. The second optocoupler OC2 is used to control whether the gate of the MOS transistor under test is grounded when the MOS transistor under test on the MOS transistor placement module is an NMOS, so as to realize the switching control of the MOS transistor under test. The third switch control circuit includes a third optocoupler OC3. The output terminal of the third optocoupler OC3 is connected to the first side of the MOS transistor placement module and the positive power supply voltage PWR+, respectively. The third optocoupler (OC3) is used to control whether the gate of the MOS transistor under test is connected to the positive power supply voltage PWR+ when the MOS transistor under test on the MOS transistor placement module is a PMOS, so as to realize the switching control of the MOS transistor under test.

[0014] Thirdly, the junction temperature testing method provided in this application adopts the following technical solution: A junction temperature testing method is implemented based on the junction temperature testing circuit described above.

[0015] In summary, this application includes at least one of the following beneficial technical effects: 1. Compatible with heating circuits for both NMOS and PMOS types, allowing for different heating schemes for different MOSFETs under test through a switching switch, saving costs; 2. By using a test current, the parasitic diode corresponding to the MOSFET under test is made to have a fixed preset temperature sensitivity coefficient k. The temperature is calculated by detecting the voltage across the parasitic diode and combining it with the temperature sensitivity coefficient k to achieve junction temperature measurement. 3. By using several switches to control the on / off state of the MOSFET under test at regular intervals, the maximum and minimum junction temperatures can be precisely controlled. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the overall circuit when the heating circuit is selected and switched to correspond to NMOS in this application; Figure 2This is a schematic diagram of the circuit connection for placing PMOS and NMOS transistors in the MOS transistor placement module of this application; Figure 3 This is a schematic diagram of the overall circuit when the heating circuit is selected and switched to correspond to the PMOS in this application; Figure 4 This is a schematic diagram of the overall circuit of the junction temperature test circuit in this application; Figure 5 This is a circuit connection diagram of the temperature detection module in this application; Figure 6 This is a circuit connection diagram of the test current supply module in this application; Figure 7 This is a circuit connection diagram of the junction temperature control module in this application.

[0017] In the diagram, 1 is the voltage source; 2 is the heating current supply module; 3 is the MOSFET placement module; 31 is the first side; 32 is the second side; 4 is the power supply reverse switching module; 5 is the signal reverse switching module; 6 is the selection switching heating circuit; 7 is the temperature detection module; 8 is the test current supply module; 9 is the junction temperature control module; 91 is the first switch control circuit; 92 is the second switch control circuit; and 93 is the third switch control circuit. Detailed Implementation

[0018] The following is in conjunction with the appendix Figure 1 - Appendix Figure 7 This application will be described in further detail below.

[0019] like Figure 1 As shown, a selectable switching heating circuit includes: Voltage source 1 includes a positive terminal PWR+ and a negative terminal PWR-. Voltage source 1 is used to provide heating voltage to the MOSFET under test. The voltage of voltage source 1 is adjustable.

[0020] The heating current providing module 2 includes an input terminal and an output terminal. The input terminal is connected to the voltage source 1 to provide a reference current according to the voltage source 1, and the output terminal is used to output a corresponding constant heating current according to the reference current.

[0021] The heating current supply module 2 is a constant current source circuit, which can output a constant current source. The constant current source circuit can automatically adjust the current output to adapt to load changes. It generates a corresponding reference current according to the load change, and after amplifying, comparing and other processing of the reference current, it generates a constant heating current for heating the MOSFET under test.

[0022] A constant heating current combined with the heating voltage corresponding to voltage source 1 can generate the corresponding power to heat the MOSFET under test. The power can be changed by adjusting the heating voltage corresponding to voltage source 1 and the corresponding constant heating current, thereby meeting the heating requirements of different MOSFETs under test.

[0023] MOSFET placement module 3 is used to place the MOSFET under test and is connected to voltage source 1.

[0024] The MOSFETs under test include PMOS and NMOS. The MOSFET placement module is a small clamping board that is compatible with both PMOS and NMOS, enabling the clamping of both types of MOSFETs. Through the MOSFET placement module 3, different MOSFETs can be connected to the selection switching heating circuit 6, and the corresponding selection switching and heating steps can be performed according to the type of MOSFET under test.

[0025] The power supply reverse switching module 4 is connected to the heating current supply module 2. It is used to switch the position of the positive terminal PWR+ of the power supply voltage of the voltage source 1 according to the type of MOSFET under test on the MOSFET placement module 3, thereby changing the direction of the reference current.

[0026] The signal inversion switching module 5 is connected at one end to the power inversion switching module 4 to receive a constant heating current, and at the other end to the MOSFET placement module 3. The signal inversion switching module 5 is used to switch the signal corresponding to the constant heating current in either direction according to the type of MOSFET under test on the MOSFET placement module 3.

[0027] Because heating PMOS and NMOS transistors for junction temperature testing requires both PMOS and NMOS transistors to be turned on, and since the turn-on conditions for NMOS and PMOS are different, the gate voltage values ​​of PMOS and NMOS transistors need to be different. First, based on the type of the MOSFET under test, the power supply reverse switching module 4 switches to select the appropriate range so that the direction of the reference current is adjusted between forward and reverse. The positive and reverse directions of the reference current correspond to the positive and negative voltage drops; the forward current direction corresponds to the forward voltage drop, and the reverse current direction corresponds to the negative voltage drop.

[0028] Within the constant current source circuit, when the positive and negative voltage drops are compared with the reference voltage, a corresponding high-level signal is generated. This high-level signal corresponds to a positive high voltage for the constant heating current. To turn on an NMOS, the voltage at the gate must be greater than the voltage at the source. Therefore, when the signal corresponding to the constant heating current is a high-level signal, the NMOS is turned on. Conversely, to turn on a PMOS, the voltage at the gate must be less than the voltage at the source. This requires inverting the high-level signal to make it negative, thus turning on the PMOS.

[0029] Through the above settings, heating compatibility for NMOS and PMOS is achieved. When different MOSFETs under test are installed, the power supply reverse switching module 4 and signal reverse switching module 5 can be switched to the corresponding positions to meet the conduction conditions of different MOSFETs. When different types of MOSFETs are turned on, heating of different MOSFETs under test under different junction temperature test requirements can be achieved by changing the heating voltage and the magnitude of the constant heating current.

[0030] like Figure 2 As shown, in some other embodiments, the MOS transistor placement module 3 includes a first side 31 and a second side 32, the first side 31 corresponding to the gate of the MOS transistor under test, and the second side 32 corresponding to the drain and source of the MOS transistor under test.

[0031] like Figure 1-3 As shown, the first side 31 is connected to the signal forward switching module, and the second side 32 is connected to the voltage source 1.

[0032] When different types of MOSFETs under test are mounted on the MOSFET placement module 3, the gate of the MOSFET under test is connected to the first side 31, while in the second side 32, the source and drain positions of NMOS and PMOS are reversed.

[0033] Specifically, when the MOSFET under test is an NMOS, the source of the MOSFET under test is connected to the negative terminal of the power supply voltage PWR-, and the drain of the MOSFET under test is connected to the positive terminal of the power supply voltage PWR+.

[0034] When the MOSFET under test is a PMOS, the source of the MOSFET under test is connected to the positive terminal of the power supply voltage PWR+, and the drain of the MOSFET under test is connected to the negative terminal of the power supply voltage PWR-.

[0035] In other embodiments, the heating current providing module 2 includes a sampling resistor RSH, a first differential amplifier U1, a first operational amplifier P1, a first resistor R1, and a first comparator Q1.

[0036] One end of the sampling resistor RSH is connected to the positive terminal PWR+ of the power supply voltage, and the other end is connected to the negative terminal PWR- of the power supply voltage. The end connected to the positive terminal PWR+ is also connected to the positive input terminal of the first differential amplifier U1, and the end connected to the negative terminal PWR- is also connected to the negative input terminal of the first differential amplifier U1.

[0037] In this application, the sampling resistor RSH is a current feedback resistor, which is connected to the voltage source 1 to generate a small current, which serves as a reference current. Different resistance values ​​of the sampling resistor RSH correspond to generating different magnitudes of reference current, and the magnitude of the reference current affects the magnitude of the subsequent constant heating current.

[0038] In this application, the first differential amplifier U1 is a common-mode voltage differential amplifier of model INA148. It consists of two input terminals and one output terminal. The two input terminals are a positive input terminal and a negative input terminal, and each input terminal is cascaded with an identical amplifier. By cascading the two amplifiers together, differential-mode amplification of the input signal can be achieved, thereby amplifying the difference between the output signal and the input signal by more than double.

[0039] The first differential amplifier U1 also includes a common terminal, which is connected to REF A and REF B and grounded.

[0040] The first differential amplifier U1 performs the initial amplification of the reference current.

[0041] The output of the first differential amplifier U1 is connected to the non-inverting input of the first operational amplifier P1, the inverting input of the first operational amplifier P1 is grounded, and the output of the first operational amplifier P1 is connected to the inverting input of the first comparator Q1.

[0042] The first operational amplifier P1 is used to amplify the reference current again.

[0043] Specifically, a fourth resistor R4 is connected between the output terminal of the first differential amplifier U1 and the non-inverting input terminal of the first operational amplifier P1, and a fifth resistor R5 is connected between the inverting input terminal of the first operational amplifier P1 and ground.

[0044] The first resistor R1 is connected between the inverting input and output terminals of the first operational amplifier P1.

[0045] The non-inverting input of the first comparator Q1 is used to obtain the reference voltage, and the output of the first comparator Q1 is connected to the signal inversion switching module 5.

[0046] When the reference current is amplified, it will cause the voltage at the inverting input of the first comparator Q1 to increase. If the voltage at the inverting input of the first comparator Q1 is greater than the reference voltage at the non-inverting input after amplification, the output of the first comparator Q1 will output a negative signal. If the voltage at the inverting input of the first comparator Q1 is less than the reference voltage at the non-inverting input after amplification, the output of the first comparator Q1 will output a positive signal.

[0047] A sixth resistor R6 is also connected between the inverting input of the first comparator Q1 and the output of the first operational amplifier P1.

[0048] A first capacitor C1 is also connected between the output terminal and the inverting input terminal of the first comparator Q1.

[0049] The constant current principle of the heating current providing module 2 as a constant current source circuit is as follows: when the load current flowing through the MOSFET under test increases, the voltage on the sampling resistor RSH increases, which in turn increases the voltage at the inverting input terminal of the first comparator Q1. This leads to a decrease in the voltage difference between the reference voltage at the non-inverting input terminal and the voltage at the inverting input terminal, which in turn leads to a decrease in the output voltage of the first amplifier Q1 (i.e., the driving voltage of the MOSFET under test). This results in an increase in the equivalent resistance of the MOSFET under test (the MOSFET under test is equivalent to a variable resistor), which in turn leads to a decrease in the output current, thus forming negative feedback.

[0050] The first capacitor C1 serves to establish a transient negative feedback path when the first amplifier Q1 is powered on, making the op-amp more stable.

[0051] In other embodiments, the power reverse switching module 4 includes a first relay switch K1, one end of which is grounded and a first differential amplifier P1, and the other end is in a floating state to be selectively pulled to the positive terminal PWR+ or the negative terminal PWR- of the power supply voltage based on the type of the MOS transistor under test on the MOS transistor placement module 3.

[0052] One end of the first relay switch K1 is grounded with the first differential amplifier P1, and the other end can be controlled by the relay to select a specific engagement position based on user selection. There are two engagement positions, corresponding to the positive terminal PWR+ and the negative terminal PWR- of the power supply voltage, respectively.

[0053] When the first relay switch K1 is energized at the negative terminal PWR- of the power supply, the negative terminal PWR- is grounded, and the current direction remains unchanged, flowing from the positive terminal PWR+ of voltage source 1 to the negative terminal PWR-. Therefore, both the current and voltage are positive. When the first relay switch K1 is energized at the positive terminal PWR+ of the power supply, the negative terminal PWR- of voltage source 1 remains unchanged, but the higher-order terminal becomes the positive terminal PWR+ of the power supply on the side of the first relay switch K1. The current direction changes to flow from the first differential amplifier P1 to the sampling resistor RSH, so both the current and voltage are negative at this time.

[0054] In other embodiments, the signal inversion switching module 5 includes a second operational amplifier P2, a second resistor R2, and a second relay switch K2.

[0055] The non-inverting input of the second operational amplifier P2 is grounded, and the inverting input is connected to the output of the first comparator Q1.

[0056] The second resistor R2 is connected between the inverting input and output terminals of the second operational amplifier P2.

[0057] It also includes a seventh resistor R7, one end of which is connected to the inverting input of the second operational amplifier P2, and the other end is connected to the output of the first comparator Q1.

[0058] The second operational amplifier acts as an inverting amplifier, which can invert the signal received at the input terminal. If it receives a positive signal, it outputs a negative signal, and if it receives a negative signal, it outputs a positive signal.

[0059] One end of the second relay switch K2 is connected to the gate of the corresponding MOSFET under test in the MOSFET placement module 3, and the other end is in a floating state to select the P-path or N-path according to the type of MOSFET under test in the MOSFET placement module 3.

[0060] The N-path is connected to the output of the first amplifier Q1, and the P-path is connected to the output of the second operational amplifier P2.

[0061] The implementation principle of this application embodiment is as follows: If the MOSFET under test is an NMOS, first connect the first relay switch K1 to the negative terminal PWR- of the power supply voltage, and the second relay switch K2 to the N- channel. The sampling resistor RSH generates a reference current and the corresponding voltage drop. After being amplified by the first differential amplifier U1 and the first operational amplifier P1, it is compared with the reference voltage at the non-inverting input of the first comparator Q1. When the voltage at the inverting input is less than the reference voltage, the first comparator Q1 outputs a high-level signal, which turns on the NMOS transistor in the MOSFET placement module 3. The remaining voltage after subtracting the voltage from the sampling resistor RSH from the reference voltage source 1 is used as the heating voltage, which is combined with a constant heating current to generate power for heating.

[0062] If the MOSFET under test is a PMOS, first connect the first relay switch K1 to the positive terminal of the power supply voltage PWR+, and the second relay switch K2 to the P- channel. At this time, the high-order position of the voltage changes, the current direction reverses, and the reference current and corresponding voltage drop on the sampling resistor RSH are negative. After amplification, it is compared with the reference voltage. Since the voltage on the inverting input terminal is negative at this time, the reference voltage is still higher than the voltage on the inverting input terminal. The first comparator Q1 outputs a high-level signal. This high-level signal flows to the second operational amplifier P2, which is used to invert the signal, and outputs a negative signal, thereby turning on the PMOS on the MOSFET placement module 3. The remaining voltage after subtracting the voltage from the sampling resistor RSH from the reference voltage source 1 is used as the heating voltage, which is combined with a constant heating current to form power for heating.

[0063] like Figure 4 As shown, this application also discloses a junction temperature testing circuit, which includes the above-mentioned selection switching heating circuit 6, and further includes: Temperature detection module 7 is connected to MOSFET placement module 3. It is used to detect the voltage value of the parasitic diode corresponding to the MOSFET under test, and calculate the temperature of the MOSFET under test based on the voltage value and the temperature sensitivity coefficient k of the parasitic diode.

[0064] The current sensing module is connected to the MOSFET placement module 3 to provide a current sensing current, which is used to keep the temperature sensitivity coefficient k of the parasitic diode constant.

[0065] Junction temperature control module 9 is connected to MOSFET placement module 3 and voltage source 1, and is used to control the voltage source 1 and the MOSFET under test on MOSFET placement module 3 to disconnect according to junction temperature test requirements.

[0066] Each conventional MOSFET has a corresponding parasitic diode. In an NMOS transistor, the anode of the parasitic diode is connected to the source, and the cathode is connected to the drain. In a PMOS transistor, the anode is connected to the drain, and the cathode is connected to the source. Different materials of parasitic diodes correspond to different temperature sensitivity coefficients k, which are also called temperature sensitivity factors. They represent the proportion of a physical quantity (resistance, capacitance, expansion, etc.) to the change in temperature when the temperature of an object changes.

[0067] For diodes, the commonly used temperature sensitivity coefficient k represents the proportion of voltage change with temperature. For example, a silicon diode corresponds to an increase or decrease of 2mV for every degree of temperature. Furthermore, the voltage and temperature of a diode exhibit a linear relationship; for instance, at 0 degrees Celsius, the diode's voltage drop is 0.65V, while with a temperature sensitivity coefficient k of 2mV per degree Celsius, the diode's voltage drop at 100 degrees Celsius is 0.45V.

[0068] When the temperature sensitivity coefficient k of a parasitic diode is fixed, the current temperature of the parasitic diode can be calculated by detecting the voltage value of the parasitic diode.

[0069] The temperature sensitivity coefficient k only exists when the corresponding component has a small current, and the specific value of the temperature sensitivity coefficient k is different under different currents. Therefore, in order to keep the temperature sensitivity coefficient k of the parasitic diode constant and improve the subsequent temperature detection accuracy, it is necessary to provide a constant test current for the parasitic diode.

[0070] Meanwhile, during junction temperature testing, the MOSFET under test needs to be repeatedly heated and cooled to determine the highest and lowest junction temperatures. Therefore, it is necessary to heat the MOSFET under test at appropriate times and stop heating it at appropriate times according to the test requirements. This step is achieved by the junction temperature control module 9.

[0071] like Figure 4and Figure 5 As shown, in some other embodiments, the temperature detection module 7 includes a second differential amplifier U2, a third resistor R3, and a first Zener diode D1.

[0072] The positive and negative input terminals of the second differential amplifier U2 are both connected to the second side 32 of the MOSFET placement module 3. When the MOSFET under test on the MOSFET placement module 3 is an NMOS, the positive input terminal is connected to the drain of the NMOS, and the negative input terminal is connected to the source of the NMOS. Conversely, when the MOSFET under test on the MOSFET placement module 3 is a PMOS, the positive input terminal is connected to the source of the PMOS, and the negative input terminal is connected to the drain of the PMOS. The output terminal is connected to the third resistor R3, the other end of the third resistor R3 is connected to the negative terminal of the first Zener diode D1, and the positive terminal of the first Zener diode D1 is connected to the common terminal of the second differential amplifier U2.

[0073] The second differential amplifier U2 can detect and amplify the voltage drop across the parasitic diode to obtain the corresponding voltage value on the parasitic diode, and calculate the current temperature of the parasitic diode based on the temperature sensitivity coefficient k. The temperature of the parasitic diode can then represent the temperature of the MOSFET under test.

[0074] like Figure 6 As shown, in some other embodiments, the test current providing module 8 is the same constant current source circuit as the heating current providing module 2 described above. This constant current source circuit can provide a constant test current to the parasitic diode so that the temperature sensitivity coefficient k of the parasitic diode remains constant. In this embodiment, the magnitude of the test current is 10mA.

[0075] The specific circuit configuration of the test current supply module 8 is as follows: Figure 6 As shown.

[0076] like Figure 4 and Figure 7 As shown in some other embodiments, the junction temperature control module 9 includes a first switch control circuit 91.

[0077] The first switch control circuit 91 includes a first optocoupler OC1 and a switching transistor M1. The input terminal of the first optocoupler OC1 is used to receive a switch command to control the switching transistor M1 to turn off or on according to the switch command. The output terminal of the first optocoupler OC1 is connected to the gate of the switching transistor M1. The drain of the switching transistor M1 is connected to the negative terminal of the power supply voltage PWR-, and the source of the switching transistor M1 is connected to the positive terminal of the power supply voltage PWR+.

[0078] The first optocoupler OC1 acts as a control switch and has four ports. The first port is connected to a 5V power supply through the eighth resistor R8, the second port is connected to the driver U3 of model 74LS07, the third port is connected to -p12V, and the fourth port is connected to the gate of the switching transistor M1.

[0079] A ninth resistor R9 and a second diode D2 are also connected between the fourth port of the first optocoupler OC1 and the gate of the switching transistor M1. One end of the ninth resistor R9 is connected to the gate of the switching transistor M1, and the other end is connected to the positive terminal of the second diode D2. The negative terminal of the second diode D2 is connected to the fourth port of the first optocoupler OC1.

[0080] In this application, the switching transistor M1 is a PMOS.

[0081] The driver U3 drives the first optocoupler OC1 to turn on or off according to the acquired logic control instructions. When the first optocoupler OC1 is on, it causes the switching transistor M1 to turn on; when the first optocoupler OC1 is off, it causes the switching transistor M1 to turn off. When the switching transistor M1 is off, the voltage source 1 circuit is open, and there is no heating voltage on the MOSFET under test. When the switching transistor M1 is on, the voltage source 1 circuit is on, and there is a heating voltage on the MOSFET under test.

[0082] In other embodiments, the junction temperature control module 9 further includes a second switch control circuit 92 and a third switch control circuit 93 connected in parallel.

[0083] The second switch control circuit 92 includes a second optocoupler OC2. The output terminal of the second optocoupler OC2 is connected to the first side 31 of the MOS transistor placement module 3 and ground, respectively. The second optocoupler OC2 is used to control whether the gate of the MOS transistor under test is grounded when the MOS transistor under test on the MOS transistor placement module 3 is an NMOS, so as to realize the switching control of the MOS transistor under test.

[0084] The second optocoupler OC2 is a switching device with four ports. The first port is connected to a 5V power supply via the tenth resistor R10. The second port receives logic control commands. The third port is connected to ground. The fourth port is connected to the first side 31 of the MOSFET placement module 3. The first and second ports are input ports, and the third and fourth ports are output ports. A third diode D3 is connected to the fourth port. The anode of the third diode D3 is connected to the first side 31 of the MOSFET placement module 3, and the cathode is connected to the fourth port.

[0085] The second optocoupler OC2 is turned on or off by logic control instructions. When the second optocoupler OC2 is turned on, the gate of the NMOS is grounded through the third port of the second optocoupler OC2, and the NMOS is turned off. When the second optocoupler OC2 is turned off, the second switch control circuit 92 is open, and there is still a certain voltage on the gate of the NMOS.

[0086] The third switch control circuit 93 includes a third optocoupler OC3. The output terminal of the third optocoupler OC3 is connected to the first side 31 of the MOS transistor placement module 3 and the positive power supply voltage PWR+, respectively. The third optocoupler OC3 is used to control whether the gate of the MOS transistor under test is connected to the positive power supply voltage PWR+ when the MOS transistor under test on the MOS transistor placement module 3 is a PMOS, so as to realize the switching control of the MOS transistor under test.

[0087] The third optocoupler OC3 is a switching device with four ports. The first port is connected to a 5V power supply via the eleventh resistor R11. The second port is connected to the driver U4. The third port is connected to the first side 31 of the MOSFET placement module 3. The fourth port is connected to the positive terminal of the power supply, PWR+. The first and second ports are input ports, and the third and fourth ports are output ports. A fourth diode D4 is connected to the third port; the anode of the fourth diode D4 is connected to the third port, and the cathode of the fourth diode D4 is connected to the first side 31 of the MOSFET placement module 3.

[0088] Driver U4 is used to receive logic control commands and drive the conduction state of the third optocoupler OC3 according to the logic control commands. When the third optocoupler OC3 is on, the gate of the PMOS under test is connected to the positive terminal PWR+ of the power supply voltage through the fourth port of the third optocoupler OC3 to obtain a high voltage, which causes its gate voltage to be greater than the source voltage, thus causing the PMOS to be turned off. Conversely, when the third optocoupler OC3 is off, there is still a certain voltage on the gate of the PMOS under test.

[0089] The second switch control circuit 92 and the third switch control circuit 93 are set up to detect the minimum junction temperature during the junction temperature measurement process. This minimum junction temperature is determined by stopping heating the MOSFET under test (MTB) and allowing it to cool naturally to the lowest temperature within a preset time. To prevent further heating of the TMB, it needs to be turned off. Although the first switch control circuit 91 disconnects the voltage source loop 1, if the gate of the TMB is not disconnected, a small voltage may still exist on it. Due to the characteristics of MOSFETs, they conduct even with a small gate voltage. If the TMB remains on, the subsequent junction temperature measurement cannot be accurately detected. Therefore, appropriate switch control circuits are needed to control the turn-off of the TMB depending on its type.

[0090] The implementation method is as follows: First, switch M1 is turned on, while the second optocoupler OC2 and the third optocoupler OC3 are both turned off. The MOSFET under test is heated by a certain power. The test current supply module 8 provides a constant small current to the parasitic diode corresponding to the MOSFET under test, so that the temperature sensitivity coefficient k on the parasitic diode is kept constant at a preset value. After heating for a preset time, a logic control instruction is generated to turn off switch M1 and the second optocoupler OC2 (NMOS) or the third optocoupler OC3 (PMOS). The temperature detection module 7 quickly detects the current voltage value corresponding to the parasitic diode and calculates the current temperature value of the MOSFET under test in combination with the temperature sensitivity coefficient k. This temperature corresponds to the highest junction temperature of the MOSFET under test. Because the MOSFET under test is cut off, it will undergo natural cooling. After the natural cooling time is maintained for a preset time, the temperature detection module 7 quickly detects the voltage value corresponding to the parasitic diode and calculates the current temperature value of the MOSFET under test in combination with the temperature sensitivity coefficient k. This temperature corresponds to the lowest junction temperature of the MOSFET under test. The switching transistor M1 is put back into the conducting state via a logic control instruction, and the second optocoupler OC2 (NMOS) or the third optocoupler OC3 (PMOS) is turned off, causing the MOSFET under test to be reheated to repeat the junction temperature process described above. The number of repetitions of the junction temperature process and the preset heating and cooling times can be adaptively adjusted according to different junction temperature requirements.

[0091] This application also discloses a junction temperature testing method, which is implemented based on the junction temperature testing circuit described above.

[0092] The embodiments described in this specific implementation are preferred embodiments of this application and are not intended to limit the scope of protection of this application. Identical components are represented by the same reference numerals. Therefore, all equivalent changes made to the structure and principles of this application should be included within the scope of protection of this application.

Claims

1. A selection switching heating circuit, characterized by, include: The voltage source (1) includes a positive terminal (PWR+) and a negative terminal (PWR-) of the power supply voltage, which is used to provide heating voltage to the MOSFET under test; The heating current providing module (2) includes an input terminal and an output terminal. The input terminal is connected to the voltage source (1) to provide a reference current according to the voltage source (1), and the output terminal is used to output a corresponding constant heating current according to the reference current. MOS transistor placement module (3) is used to place the MOS transistor under test, which is connected to the voltage source (1). The MOS transistor under test includes PMOS or NMOS. The power reverse switching module (4) is connected to the heating current supply module (2). The power reverse switching module (4) is used to switch the positive terminal (PWR+) of the power supply voltage of the voltage source (1) according to the type of the MOS transistor under test on the MOS transistor placement module (3) to change the direction of the reference current. The signal inversion switching module (5) is connected at one end to the power inversion switching module (4) to receive a constant heating current, and at the other end to the MOS transistor placement module (3). The signal inversion switching module (5) is used to switch the signal corresponding to the constant heating current in the positive or negative direction according to the type of MOS transistor under test on the MOS transistor placement module (3). The heating current providing module (2) includes a sampling resistor (RSH), a first differential amplifier (U1), a first operational amplifier (P1), a first resistor (R1), and a first comparator (Q1), wherein, One end of the sampling resistor (RSH) is connected to the positive terminal of the power supply voltage (PWR+), and the other end is connected to the negative terminal of the power supply voltage (PWR-). The end connected to the positive terminal of the power supply voltage (PWR+) is also connected to the positive input terminal of the first differential amplifier (U1), and the end connected to the negative terminal of the power supply voltage (PWR-) is also connected to the negative input terminal of the first differential amplifier (U1). The output of the first differential amplifier (U1) is connected to the non-inverting input of the first operational amplifier (P1), the inverting input of the first operational amplifier (P1) is grounded, and the output of the first operational amplifier (P1) is connected to the inverting input of the first comparator (Q1). The non-inverting input of the first comparator (Q1) is used to obtain the reference voltage, and the output of the first comparator (Q1) is connected to the signal inversion switching module (5). The first resistor (R1) is connected between the inverting input terminal and the output terminal of the first operational amplifier (P1); The power reverse switching module (4) includes a first relay switch (K1), one end of which is grounded and connected to the first differential amplifier (U1), and the other end is in a floating state to be selectively pulled to the positive terminal (PWR+) or negative terminal (PWR-) of the power supply voltage based on the type of the MOS transistor under test on the MOS transistor placement module (3). The signal inversion switching module (5) includes a second operational amplifier (P2), a second resistor (R2), and a second relay switch (K2). The non-inverting input of the second operational amplifier (P2) is grounded, and the inverting input is connected to the output of the first comparator (Q1). The second resistor (R2) is connected between the inverting input and output of the second operational amplifier (P2); One end of the second relay switch (K2) is connected to the gate of the corresponding MOS transistor under test in the MOS transistor placement module (3), and the other end is in a floating state to be connected to the P-path or N-path according to the type of MOS transistor under test in the MOS transistor placement module (3). The N-path is connected to the output terminal of the first comparator (Q1), and the P-path is connected to the output terminal of the second operational amplifier (P2).

2. The selection and switching heating circuit according to claim 1, characterized in that, The MOS transistor placement module (3) includes a first side (31) and a second side (32). The first side (31) corresponds to the gate of the MOS transistor under test, and the second side (32) corresponds to the drain and source of the MOS transistor under test. The first side (31) is connected to the signal inversion switching module (5), and the second side (32) is connected to the voltage source (1). When the MOSFET under test is an NMOS, the source of the MOSFET under test is connected to the negative terminal of the power supply voltage (PWR-), and the drain of the MOSFET under test is connected to the positive terminal of the power supply voltage (PWR+). When the MOSFET under test is a PMOS, the source of the MOSFET under test is connected to the positive terminal of the power supply voltage (PWR+), and the drain of the MOSFET under test is connected to the negative terminal of the power supply voltage (PWR-).

3. A junction temperature testing circuit, characterized in that, Including the selection switching heating circuit (6) as described in any one of claims 1-2, it further includes: The temperature detection module (7) is connected to the MOS tube placement module (3) and is used to detect the voltage value of the parasitic diode corresponding to the MOS tube under test, and calculate the temperature of the MOS tube under test according to the voltage value and the temperature sensitivity coefficient k corresponding to the parasitic diode. A test current supply module (8) is connected to the MOS transistor placement module (3) to provide a detection current, which is used to keep the temperature sensitivity coefficient k corresponding to the parasitic diode constant. Junction temperature control module (9) is connected to the MOS transistor placement module (3) and the voltage source (1) and is used to control the voltage source (1) and the MOS transistor under test on the MOS transistor placement module (3) to disconnect according to the junction temperature test requirements.

4. The junction temperature testing circuit according to claim 3, characterized in that, The temperature detection module (7) includes a second differential amplifier (U2), a third resistor (R3), and a first Zener diode (D1). The positive and negative input terminals of the second differential amplifier (U2) are both connected to the second side (32) of the MOS transistor placement module (3), and the output terminal is connected to the third resistor (R3). The other end of the third resistor (R3) is connected to the positive terminal of the first Zener diode (D1), and the negative terminal of the first Zener diode (D1) is connected to the common terminal of the second differential amplifier (U2).

5. The junction temperature testing circuit according to claim 3, characterized in that, The junction temperature control module (9) includes a first switch control circuit (91). The first switch control circuit (91) includes a first optocoupler (OC1) and a switch transistor (M1). The input terminal of the first optocoupler (OC1) is used to receive a switch command and control the switch transistor (M1) to turn off or on according to the switch command. The output terminal of the first optocoupler (OC1) is connected to the gate of the switch transistor (M1). The drain of the switch transistor (M1) is connected to the negative terminal of the power supply voltage (PWR-), and the source of the switch transistor (M1) is connected to the positive terminal of the power supply voltage (PWR+).

6. The junction temperature testing circuit according to claim 5, characterized in that, The junction temperature control module (9) also includes a second switch control circuit (92) and a third switch control circuit (93) connected in parallel, wherein, The second switch control circuit (92) includes a second optocoupler (OC2). The output terminal of the second optocoupler (OC2) is connected to the first side (31) of the MOS transistor placement module (3) and ground respectively. The second optocoupler (OC2) is used to control whether the gate of the MOS transistor under test is grounded when the MOS transistor under test on the MOS transistor placement module (3) is an NMOS, so as to realize the switching control of the MOS transistor under test. The third switch control circuit (93) includes a third optocoupler (OC3). The output terminal of the third optocoupler (OC3) is connected to the first side (31) of the MOS transistor placement module (3) and the positive power supply voltage (PWR+). The third optocoupler (OC3) is used to control whether the gate of the MOS transistor under test is connected to the positive power supply voltage (PWR+) when the MOS transistor under test on the MOS transistor placement module (3) is a PMOS, so as to realize the switching control of the MOS transistor under test.

7. A method for testing junction temperature, characterized in that, It is implemented based on the junction temperature test circuit as described in any one of claims 3-6.

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