Read data alignment

Abstract

Systems, devices, and methods related to controller architecture for read data alignment are described. An example method can include sending a first notification from a physical layer to each of a number of memory controllers, where the first notification indicates that the physical layer and / or a memory device coupled to the physical layer is busy, and blocking commands on each of the number of memory controllers in response to receiving the first notification to cause read data alignment. The method can also include sending a second notification from the physical layer to each of the number of memory controllers, where the second notification indicates that the physical layer and / or the memory device coupled to the physical layer is no longer busy, and resuming processing commands on each of the number of memory controllers in response to receiving the second notification.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor memories and methods, and more particularly to apparatus, systems and methods for reading data alignment. Background Technology

[0002] Memory devices are typically provided as internal semiconductor integrated circuit systems in computers or other electronic systems. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory requires power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), etc. Non-volatile memory provides persistent data by retaining the stored data when no power is applied and includes NAND flash memory, NOR flash memory, ferroelectric random access memory (FeRAM), and resistive variable memory (e.g., phase-change random access memory (PCRAM)), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), etc.

[0003] A memory device may be coupled to a host computer (e.g., a host computing device) to store data, commands, and / or instructions for use by the host computer or electronic system during operation. For example, during the operation of a computing or other electronic system, data, commands, and / or instructions may be transferred between the host computer and the memory device. A controller may be used to manage the transfer of data, commands, and / or instructions between the host computer and the memory device. Summary of the Invention

[0004] One aspect of this disclosure relates to a method comprising: sending a first notification from a physical layer to each of a plurality of memory controllers, wherein the first notification indicates that the physical layer and / or memory devices coupled to the physical layer are busy; blocking a command to induce a read data alignment on each of the plurality of memory controllers in response to receiving the first notification; sending a second notification from the physical layer to each of the plurality of memory controllers, wherein the second notification indicates that the physical layer and / or the memory devices coupled to the physical layer are no longer busy; and resuming a processing command on each of the plurality of memory controllers in response to receiving the second notification.

[0005] Another aspect of this disclosure relates to a method comprising: sending a command from a central controller to each of a plurality of memory controllers on a command bus; sending the command from each of the plurality of memory controllers to each of a plurality of memory devices; receiving data associated with the command at each of the plurality of memory controllers from each of the plurality of memory devices; and receiving the data associated with the command at the central controller via a data bus from each of the plurality of memory controllers.

[0006] Another aspect of this disclosure relates to an apparatus comprising: a central controller; a plurality of memory controllers coupled to the central controller via a data bus and a command bus, each of the plurality of memory controllers comprising one of a plurality of physical layers; and a plurality of memory devices, wherein each particular memory device of the plurality of memory devices is coupled to the particular memory controller of the plurality of memory controllers, wherein the apparatus is configured to: send a first notification from one of the physical layers to each of the plurality of memory controllers, wherein the first notification indicates that the physical layer and / or the memory devices coupled to the physical layer are busy; block commands on each of the plurality of memory controllers in response to receiving the first notification; send a second notification from the physical layer to each of the plurality of memory controllers, wherein the second notification indicates that the physical layer and / or the memory devices coupled to the physical layer are no longer busy; and resume processing commands on each of the plurality of memory controllers in response to receiving the second notification. Attached Figure Description

[0007] Figure 1 This is a block diagram of a computing system including a memory controller according to several embodiments of the present disclosure.

[0008] Figure 2 This is a block diagram of a controller having several channels coupled to several memory devices according to several embodiments of the present disclosure.

[0009] Figure 3 This is a block diagram of a controller configured to read data alignment according to several embodiments of the present disclosure.

[0010] Figure 4 This is a block diagram of a method for operating a controller configured to read data alignment according to several embodiments of the present disclosure. Detailed Implementation

[0011] This document describes systems, apparatus, and methods related to controller architectures for reading data alignment. The controller may be located within a memory system, which may be a memory module, a storage device, or a hybrid of both. The memory controller may be coupled to several memory devices via several memory channels that can be organized into several channel groups.

[0012] Several memory channels can operate independently or work together as a whole. When the memory channels work together, the read data must reach the central controller before any further processing can be performed. Therefore, if the read data is not returned at the same time or in a different order, the central controller will not be able to process the read data further, which can increase the latency of the memory system. This latency can be introduced by physical layer-triggered training on the PHY memory interface, the central controller issuing different commands to the memory controller on several memory channels, the memory controller registers being programmed at different times and / or the memory controller operating at different clock times, and other latency factors.

[0013] In several embodiments of this disclosure, a central controller may be coupled to a plurality of memory controllers via a command bus. The command bus couples the central controller to each of the memory controllers. When the central controller issues a command, the command is sent on the command bus to each of the plurality of memory controllers. The central controller sends commands on the command bus such that each of the plurality of memory controllers receives the command; therefore, sending commands from the central controller to the plurality of memory controllers on the command bus reduces and / or eliminates latency in the memory system caused by receiving different commands among the plurality of memory controllers.

[0014] In several embodiments of this disclosure, a central controller may be coupled to a plurality of memory controllers via a data bus. The data bus may couple the central controller to each of the plurality of memory controllers. When the plurality of memory controllers send data to the central controller (in response to a command received from the central controller via a command bus, read data is sent on the data bus from each of the plurality of memory controllers to a data buffer on the central controller), the plurality of memory controllers may send read data on the data bus such that the central controller receives read data corresponding to a command sent from the central controller to the memory controller via the command bus. Therefore, sending read data from the plurality of memory controllers to the central controller on the data bus that couples the central controller to each of the plurality of memory controllers can reduce and / or eliminate latency in the memory system caused by receiving different commands among the plurality of memory controllers.

[0015] In several embodiments of this disclosure, multiple memory controllers may be coupled to a physical layer on multiple PHY memory interfaces via a sideband bus. The sideband bus may include logic gates such that any signal sent from one of the physical layers on the sideband bus will be sent to each of the multiple memory controllers. When one of the physical layers is busy (e.g., busy requesting training), a notification (e.g., a signal) of the physical layer being busy can be sent on the sideband bus to the logic gates. The notification may be received by the logic gates and transmitted from the logic gates to each of the multiple memory controllers on the sideband bus. When each of the multiple memory controllers receives the notification, the multiple memory controllers may prevent command execution. In response to receiving the notification, the multiple memory controllers may prevent command execution when one or more of the physical layers are busy; therefore, sending the notification on the sideband bus to each of the multiple memory controllers may reduce and / or eliminate any latency in the memory system caused by one of the memory channels being unable to execute a command.

[0016] When one of the physical layers is no longer busy (e.g., training operation completes), another notification (e.g., a signal) indicating that the physical layer is no longer busy can be sent to a logic gate on the sideband bus. This notification can be received by the logic gate and transmitted from the logic gate to each of the plurality of memory controllers on the sideband bus. When each of the plurality of memory controllers receives the notification, the plurality of memory controllers can resume command execution. In response to receiving a notification indicating that one or more of the physical layers are no longer busy, the plurality of memory controllers can resume command execution; therefore, sending the notification to each of the plurality of memory controllers on the sideband bus can reduce and / or eliminate any latency in the memory system caused by one of the memory channels being busy and unable to execute commands.

[0017] As used herein, the singular forms “a” and “the” include both singular and plural indicators unless the content expressly indicates otherwise. Furthermore, the word “may” is used throughout this application in a permissive sense (i.e., possible, able) rather than a mandatory sense (i.e., required). The term “comprising” and its derivatives mean “including (but not limited to)”. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without intermediate components), whether wired or wireless, including connections such as electrical, optical, magnetic, and similar. The terms “data” and “data value” are used interchangeably herein and can have the same meaning, depending on the context.

[0018] The diagrams in this document follow a numbering convention, where the first one or a few numbers correspond to the diagram number, and the remaining numbers identify the elements or components within the diagram. Similar elements or components across different diagrams can be identified using similar numbers. For example, element 122 in... Figure 1 The symbol "22" can be used to represent element "22", and similar elements are used in... Figure 2 The symbol 222 may be used as a reference. Similar elements within the figures may be referenced using hyphens and additional numbers or letters. It will be understood that elements shown in the various embodiments herein may be added, interchanged, and / or eliminated to provide several additional embodiments of this disclosure. Furthermore, it should be understood that the scale and relative dimensions of the elements provided in the figures are intended to illustrate certain embodiments of the invention and should not be construed as limiting.

[0019] Figure 1 This is a block diagram of a computing system 101 including a memory controller 100 according to several embodiments of the present disclosure. The memory controller 100 includes a front-end portion 104, a central controller portion 110, and a back-end portion 119. The computing system 101 includes a host 103 and memory devices 126-1, ..., 126-N coupled to the memory controller 100. The computing system 101 may be, for example, a high-performance computing (HPC) data center and various other types of computing systems (e.g., servers, desktop computers, laptop computers, mobile devices, etc.).

[0020] although Figure 1 Not shown, but the front-end portion 104 may include a physical (PHY) layer and a front-end controller for interfacing with the host 103 via several buses 102-1, 102-2, ..., 102-M, which may include several input / output (I / O) paths. The several buses 102-1, 102-2, ..., 102-M may include various combinations of data, address, and control buses, which may be individual buses or one or more combined buses. In at least one embodiment, the interface between the memory controller 100 and the host 103 may be a Peripheral Component Interconnect Fast (PCIe) physical and electrical interface operating according to the Compute Fast Link (CXL) protocol. As a non-limiting example, the several buses 102-1, 102-2, ..., 102-M may be a PCIe 5.0 interface operating according to the CXL 2.0 specification or a PCIe 6.0 interface operating according to the CXL 3.0 specification.

[0021] CXL is a high-speed central processing unit (CPU) to device and CPU to memory interconnect designed to accelerate the performance of next-generation data centers. CXL technology maintains memory coherence between the CPU's memory space and the memory on attached devices (such as accelerators, memory buffers, and intelligent I / O devices), allowing resource sharing for higher performance, reduced software stack complexity, and lower overall system cost. CXL is designed as an industry-open standard interface for high-speed communication, as accelerators are increasingly used to complement CPUs to support emerging applications such as artificial intelligence and machine learning. Built on the PCIe infrastructure, CXL technology leverages PCIe physical and electrical interfaces to provide high-level protocols in areas such as input / output (I / O) protocols, memory protocols (e.g., initially allowing hosts and accelerators to share memory), and coherence interfaces. CXL provides protocols with PCIe-like I / O semantics (e.g., CXL.io), cache protocol semantics (e.g., CXL.cache), and memory access semantics (CXL.mem).

[0022] The central controller section 110 is responsible for controlling and executing various operations associated with memory access requests (e.g., read commands and write commands) from the host 103. For example, as further described below, the central controller section 110 may include various error circuitry systems (e.g., error detection and / or correction circuitry systems) capable of generating error detection and / or error correction information to provide data reliability associated with writing data to and / or reading data from the memory device 126. As further described herein, for example, this error detection and / or correction circuitry system may include an error correction code (ECC) circuitry system, a low-power chip kill (LPCK) circuitry system, and / or a "chip kill" circuitry system.

[0023] Back-end portion 119 may include several memory channel controllers (e.g., media controllers) and a physical (PHY) layer coupling memory controller 100 to memory device 126. As used herein, the term "PHY layer" generally refers to the physical layer in the Open Systems Interconnection (OSI) model of a computing system. The PHY layer may be the first (e.g., lowest) layer of the OSI model and may be used to transmit data via a physical data transmission medium. In various embodiments, the physical data transmission medium includes memory channels 125-1, ..., 125-N. Memory channels 125-1, ..., 125-N may be, for example, 16-bit channels to two 8-bit (x8) devices, although embodiments are not limited to a particular back-end interface. As another example, memory channels 125-1, ..., 125-N may each also include a two-pin data mask inversion (DMI) bus and other possible bus configurations. The back-end portion 119 can exchange data (e.g., user data and error detection and / or correction data) with memory devices 126-1, ..., 126-N via physical pins corresponding to the respective memory channels 125-1, ..., 125-N. As further described herein, in several embodiments, the memory channels 125 can be organized into several channel groups, wherein the memory channels of each group are accessed together in association with performing various memory access operations and / or error detection and / or correction operations.

[0024] Memory devices 126-1, ..., 126-N may be, for example, dynamic random access memory (DRAM) devices operating according to a protocol such as Low Power Double Data Rate (LPDDRx), which may be referred to herein as LPDDRx DRAM devices, LPDDRx memory, etc. The "x" in LPDDRx refers to any of several generations of protocols (e.g., LPDDR5). However, embodiments are not limited to a specific type of memory device 126-1, ..., 126-N. For example, memory devices 126-1, ..., 126-N may be FeRAM devices.

[0025] In some embodiments, the memory controller 100 may include a management unit 105 for initializing, configuring, and / or monitoring the characteristics of the memory controller 100. The management unit 105 may include an I / O bus for managing out-of-band data and / or commands, a management unit controller for executing instructions associated with initializing, configuring, and / or monitoring the characteristics of the memory controller, and a management unit memory for storing data associated with initializing, configuring, and / or monitoring the characteristics of the memory controller 100. As used herein, the term "out-of-band" generally refers to a transmission medium different from the primary transmission medium of the network. For example, out-of-band data and / or commands may be data and / or commands transmitted to the network using a different transmission medium than that used to transmit data within the network.

[0026] Figure 2 This is a block diagram of a controller having several channels coupled to several memory devices, according to several embodiments of the present disclosure. (See also...) Figure 2 As shown, controller 200 may include a front-end section 204, a central controller section 210, and a back-end section 219. Controller 200 may be a controller, such as... Figure 1 The controller 100 is described in the document.

[0027] Front-end portion 204 includes a front-end PHY 205 for interfacing with a host via a communication link 202, which may be, for example, a CXL link. Front-end 204 includes a front-end controller 206 for managing the interface and communicating with the central controller portion 210. In embodiments where link 202 is a CXL link, the front-end controller 206 is configured to receive memory access requests for memory devices 226-1, ..., 226-X according to the CXL protocol (e.g., from the host).

[0028] As in Figure 2 As shown, the central controller section 210 may include a media management layer (MML) 212, which can be used to translate memory access requests according to a specific protocol (e.g., CXL-compatible requests) into protocols conforming to a specific memory controller 200 and / or a specific type of memory media (e.g., memory devices 226-1, ..., 226-X). The central controller section 210 may also include a cache 211, which may include an associated cache controller. For example, the cache 211 can be used for temporary storage of data frequently accessed (e.g., by the host).

[0029] The central controller portion 210 further includes a security component 214 for encrypting / decrypting data (e.g., UDBs corresponding to write commands). Data received from cache 211 in plaintext form (e.g., data corresponding to cache lines) can be input (e.g., transmitted) to the security component 214 and can be converted to ciphertext as a result of encryption at the security component 214. As used herein, a UDB in ciphertext form may alternatively be referred to as an "encrypted UDB," which may alternatively be referred to as an "encrypted version of a UDB." Although embodiments are not so limited, the security component 214 may operate using AES encryption / decryption (e.g., an algorithm).

[0030] As in Figure 2As shown, the memory controller 200 may include a back-end portion 219 coupled to the central controller portion 210. The back-end portion 219 may include memory controllers 221-1, ..., 221-X, respectively coupled to PHY memory interfaces 224-1, ..., 224-X. The PHY memory interfaces 224-1, ..., 224-X are coupled to memory devices 226-1, ..., 226-X via memory channels 225-1, ..., 225-X, respectively.

[0031] Memory controllers 221-1, ..., 221-X can be used substantially simultaneously to drive channels 225-1, ..., 225-X. In at least one embodiment, each of the memory controllers 221-1, ..., 221-X can receive the same command and address, and substantially simultaneously drive channels 225-1, ..., 225-X. By using the same command and address, each of the memory controllers 221-1, ..., 221-X can perform the same memory operation on the same memory cell (e.g., perform memory operation on a memory cell sharing a common address) using channels 225-1, ..., 225-X.

[0032] As used herein, the term "substantially" means that the characteristics do not need to be absolute, but are close enough to achieve the advantages of the characteristics. For example, "substantially simultaneous" is not limited to operations that are executed absolutely simultaneously, but can include timing that is expected to be simultaneous but may not be precisely simultaneous due to manufacturing limitations. For example, due to the read / write latency that various interfaces (e.g., LPDDR5 and PCIe) may exhibit, the media controllers utilized "substantially simultaneously" may not start or end at exactly the same time. For example, memory controllers can be used such that they write data to memory devices at the same time, regardless of whether one of the media controllers starts or terminates before the other.

[0033] PHY memory interfaces 224-1, ..., 224-X may be LPDDRx memory interfaces. In some embodiments, each of the PHY memory interfaces 224-1, ..., 224-X may include data and DMI pins. For example, each PHY memory interface 224 may include four data pins (DQ pins) and one DMI pin. Media controllers 221-1, ..., 221-X may be configured to exchange data (e.g., UDB and / or auxiliary data) with a corresponding number of memory devices 226-1, ..., 226-X via the data pins. The DMI pin can perform multiple functions, such as data masking, data bus inversion, and parity checking for read operations, by setting a mode register. The DMI bus uses bidirectional signals. In some examples, each transmitted byte of data has a corresponding signal sent via the DMI pin for selecting the data. In some embodiments, the DMI and DQ pins of the same memory chip may be used simultaneously, allowing data to be transferred and / or exchanged from and / or exchanged from the memory die simultaneously via the DMI and DQ pins.

[0034] Memory channels 225-1, ..., 225-X can operate independently or as a whole. When memory channels 225-1, ..., 225-X are working together, read data from each of the memory channels 225-1, ..., 225-X must reach the central controller 210 before any further processing of the read data. Therefore, if the memory controllers 225-1, ..., 225-X do not return read data simultaneously or return read data in a different order (e.g., executing commands on the memory device in an order different from the order in which commands were received), then the central controller 210 will not be able to process the read data further, which can increase the latency of the memory system. This latency can be introduced by physical layer triggered training on the PHY memory interface 224, the central controller 210 issuing different commands to the memory controller 221 on several memory channels, the memory controller registers being programmed at different times and / or the memory controller 221 operating at different clock times, and other latency causes.

[0035] In several embodiments, the central controller 210 may be coupled to memory controllers 221-1, ..., 221-X via a command bus 230. The command bus 230 may couple the central controller 210 to each of the memory controllers 221-1, ..., 221-X. When the central controller 210 issues a command, the command is sent on the command bus 230 to each of the memory controllers 221-1, ..., 221-X. The central controller 210 sends commands on the command bus 230 such that each of the memory controllers 221-1, ..., 221-X receives the command. Therefore, sending commands from the central controller 210 to each of the memory controllers 221-1, ..., 221-X on the command bus 230 ensures that each memory controller 221-1, ..., 221-X receives the same command from the central controller 210, thereby reducing and / or eliminating latency in the memory system caused by receiving different commands among the memory controllers 221-1, ..., 221-X. Central controller 210 can send commands on command bus 230 to each of memory controllers 221-1, ..., 221-X to program the registers on memory controllers 221-1, ..., 221-X. In response to receiving a command from central controller 210 on command bus 230, the registers on memory controllers 221-1, ..., 221-X can be programmed. Sending commands on command bus 230 to each of memory controllers 221-1, ..., 221-X causes memory controllers 221-1, ..., 221-X to be programmed substantially at the same time and in substantially the same manner.

[0036] In several embodiments, the central controller 210 may be coupled to memory controllers 221-1, ..., 221-X via a data bus 232. The data bus 232 may couple the central controller 210 to each of the memory controllers 221-1, ..., 221-X. When memory controllers 221-1, ..., 221-X are sending data to the central controller 210 (in response to a command received from the central controller 210 via the command bus 230), read data is sent on the data bus 232 from one of the memory devices 226-1, ..., 226-X, the PHY memory interface 224-1, ..., 224-X, and the memory controllers 221-1, ..., 221-X to a data buffer 228 on the central controller 210. Memory controllers 221-1, ..., 221-X can send read data on data bus 232, causing central controller 210 to receive read data corresponding to commands sent to memory controllers 221-1, ..., 221-X via command bus 230. Therefore, sending read data from memory controllers 221-1, ..., 221-X to central controller 210 on data bus 232, which couples central controller 210 to the plurality of memory controllers 221-1, ..., 221-X, causes central controller 210 to receive read data at approximately the same time, thereby allowing central controller 210 to continue processing read data and reducing and / or eliminating latency in the memory system caused by receiving different commands and / or sending different read data from memory controllers 221-1, ..., 221-X to central controller 210.

[0037] Figure 3 This is a block diagram of a controller configured to read data alignment according to several embodiments of the present disclosure. Figure 3 Includes the backend part (similar to) Figure 1 The backend part 119 and Figure 2 The back-end section 219). The memory controllers 321-1, ..., 321-X and the PHY memory interfaces 324-1, ..., 324-X can be similar to Figure 2 The memory controllers 221-1, ..., 221-X and the PHY memory interfaces 224-1, ..., 224-X described herein.

[0038] exist Figure 3In this configuration, memory controllers 321-1, ..., 321-X are coupled to the physical layer on the PHY memory interfaces 324-1, ..., 324-X via several first portions 344-1, ..., 344-X of the sideband bus. The sideband bus may contain logic gate 336 such that any signal sent on the sideband bus from one of the physical layers will be sent to each of the memory controllers 321-1, ..., 321-X via a second portion 338 of the sideband bus. The second portion 338 of the sideband bus couples logic gate 336 to each of the memory controllers 321-1, ..., 321-X. Logic gate 336 can receive signals from any of the physical layers on the PHY memory interfaces 324-1, ..., 324-X via the several first portions 344-1, ..., 344-X of the sideband bus. In response to receiving a signal from one or more of the physical layers on the PHY memory interfaces 324-1, ..., 324-X, logic gate 336 may transmit the signal received via the sideband bus through the second part 338 of the sideband bus to each of the memory controllers 321-1, ..., and 321-X.

[0039] When one of the physical layers on the PHY memory interfaces 324-1, ..., 324-X is busy (e.g., busy requesting and / or performing training), a notification of physical layer busy can be sent to logic gate 336 on one of the plurality of first portions 344-1, ..., 344-X of the sideband bus. The notification can be received by logic gate 336 and transmitted from logic gate 336 to one of the plurality of memory controllers on the second portion 338 of the sideband bus. When each of the memory controllers 321-1, ..., 321-X receives the notification, the memory controllers 321-1, ..., 321-X can prevent command execution. When one or more of the physical layers on the PHY memory interfaces 324-1, ..., 324-X are busy, the memory controllers 321-1, ..., 321-X can prevent command execution in response to receiving a notification. Therefore, sending a notification on the sideband bus to each of the memory controllers 321-1, ..., 321-X can reduce and / or eliminate any delay in the memory system caused by one of the memory channels being unable to execute a command.

[0040] Memory controllers 321-1, ..., 321-X can be coupled to PHY memory interfaces 324-1, ..., 324-X via buses 340-1, ..., 340-X. A memory controller located on the same channel as a busy physical layer can send an acknowledgment (e.g., a signal) to the busy physical layer via buses 340-1, ..., 340-X to indicate that the memory controller has received notification that the physical layer is busy. For example, when the physical layer on PHY memory interface 324-1 sends a notification that the physical layer is busy to each of the memory controllers 321-1, ..., 321-X via the first portion 344-1, ..., 344-X of the sideband, logic gate 336, and the second portion 338, the memory controller 321-1 located on the same channel as the physical layer on PHY memory interface 324-1 can send an acknowledgment on bus 340-1 that it has received the notification that the physical layer is busy.

[0041] When one of the physical layers on the PHY memory interfaces 324-1, ..., 324-X is no longer busy (e.g., training operation complete), another notification (e.g., a second signal) indicating that the physical layer is no longer busy can be sent on several first portions 344-1, ..., 344-X of the sideband bus. This notification can be received by logic gate 336 and transmitted from logic gate 336 to each of the memory controllers 321-1, ..., 321-X via a second portion 338 of the sideband bus. The memory controllers 321-1, ..., 321-X can resume command execution in response to receiving the notification. Since the memory controllers 321-1, ..., 321-X can resume command execution in response to receiving a notification indicating that one or more of the physical layers are no longer busy, sending a notification on the sideband bus to each of the plurality of memory controllers can reduce and / or eliminate any latency in the memory system caused by one of the memory channels being busy and unable to execute commands.

[0042] Memory controllers 321-1, ..., 321-X can be coupled to PHY memory interfaces 324-1, ..., 324-X via buses 340-1, ..., 340-X. A memory controller located on the same channel as a no-busy physical layer can send an acknowledgment (e.g., a signal) to the no-busy physical layer via buses 340-1, ..., 340-X to indicate that the memory controller has received notification that the physical layer is no longer busy. For example, when a physical layer on PHY memory interface 324-1 sends a notification that the physical layer is no longer busy to each of the memory controllers 321-1, ..., 321-X via the first portion 344-1, ..., 344-X of the sideband, logic gate 336, and the second portion 338, memory controller 321-1 located on the same channel as the physical layer on PHY memory interface 324-1 can send an acknowledgment on bus 340-1 that it has received the notification that the physical layer is no longer busy.

[0043] Figure 4 This is a block diagram of a method for operating a controller configured to read data alignment according to several embodiments of the present disclosure. The methods described herein can be performed by processing logic, which may include hardware (e.g., processing means, circuitry, special-purpose logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing means), or a combination thereof. Although shown in a particular sequence or order, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0044] At 450, the method may include sending a first notification from the physical layer to each of a plurality of memory controllers, wherein the first notification indicates that the physical layer and / or memory devices coupled to the physical layer are busy.

[0045] The physical layer may be busy due to the initiation of training operations. Training operations may be initiated based on temperature changes in the physical layer and / or the memory devices coupled to the physical layer.

[0046] At 452, the method may include blocking a command on each of a plurality of memory controllers in response to receiving a first notification to induce a read data alignment.

[0047] When one or more physical layers are busy and unable to execute commands, the memory controller can prevent command execution to cause read data alignment, such that when the memory controller sends a command to a physical layer, each of the physical layers can execute the command and the read data returned (e.g., from the memory device on each of the channels) to the central controller is aligned.

[0048] At 454, the method may include sending a second notification from the physical layer to each of the plurality of memory controllers, wherein the second notification indicates that the physical layer and / or memory devices coupled to the physical layer are no longer busy.

[0049] At 456, the method may include resuming command processing on each of the plurality of memory controllers in response to receiving a second notification. Once one or more physical layers are no longer busy and unable to execute commands, the memory controller may resume command execution in response to receiving the second notification to ensure that each of the physical layers is able to execute commands when the memory controller resumes sending commands to the physical layers.

[0050] Although specific embodiments have been described and illustrated herein, those skilled in the art will understand that arrangements calculated to achieve the same results may be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of this disclosure. It should be understood that the foregoing description has been carried out in an illustrative rather than restrictive manner. Those skilled in the art will understand, upon reviewing the foregoing description, combinations of the foregoing embodiments and other embodiments not explicitly described herein. The scope of one or more embodiments of this disclosure includes other applications using the above-described structures and processes. Therefore, the scope of one or more embodiments of this disclosure should be determined with reference to the appended claims and the full scope of their equivalents.

[0051] In the foregoing detailed embodiments, for the purpose of simplifying this disclosure, some features are grouped in a single embodiment. This approach of the disclosure should not be construed as reflecting an intention that the disclosed embodiments of the disclosure must use more features than expressly recited in each claim. Rather, as reflected in the appended claims, the subject matter of the invention exists in fewer than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed embodiments, wherein each claim is an independent, separate embodiment.

Claims

1. A method for reading data alignment, comprising: A first notification is sent from the physical layer on the PHY memory interface to each of several memory controllers, wherein the first notification indicates that the physical layer and / or the memory device coupled to the physical layer is busy, and wherein the first notification is sent to a logic gate on a sideband bus, the logic gate transmitting the first notification from the logic gate to each of the several memory controllers. In response to receiving the first notification, a blocking command is executed on each of the plurality of memory controllers to induce a read data alignment; A second notification is sent from the physical layer on the PHY memory interface to each of the plurality of memory controllers, wherein the second notification indicates that the physical layer and / or the memory device coupled to the physical layer is no longer busy and wherein the second notification is sent to the logic gate on the sideband bus, the logic gate transmitting the second notification from the logic gate to each of the plurality of memory controllers; as well as In response to receiving the second notification, the processing command is resumed on each of the plurality of memory controllers.

2. The method of claim 1, further comprising sending the first notification and the second notification on the sideband bus.

3. The method of claim 1, further comprising sending the first notification and the second notification from the physical layer to each of the plurality of memory controllers via the logic gate.

4. The method of claim 1, further comprising sending an acknowledgment from one of the plurality of memory controllers to the physical layer in response to receiving the first notification.

5. The method of claim 1, further comprising sending an acknowledgment from one of the plurality of memory controllers to the physical layer in response to receiving the second notification.

6. The method of claim 1, further comprising blocking the command on each of the plurality of memory controllers in response to the physical layer performing a training operation.

7. The method of claim 1, further comprising sending the first notification from the physical layer to one of the plurality of memory controllers via a bus on the same channel.

8. The method of claim 6, wherein the physical layer is one of a plurality of physical layers.

9. An apparatus for reading data alignment, comprising: Central controller; A plurality of memory controllers, coupled to the central controller via a data bus and a command bus, wherein each of the plurality of memory controllers is coupled to one of a plurality of physical layers on a plurality of PHY memory interfaces; and A plurality of memory devices, wherein each particular memory device is coupled to a particular memory controller among the plurality of memory controllers, wherein the device is configured to: A first notification is sent from one of the physical layers to each of the plurality of memory controllers, wherein the first notification indicates that the physical layer and / or the memory devices coupled to the physical layer are busy, and wherein the first notification is sent to a logic gate on a sideband bus, the logic gate transmitting the first notification from the logic gate to each of the plurality of memory controllers. In response to receiving the first notification, a blocking command is executed on each of the plurality of memory controllers; A second notification is sent from the physical layer to each of the plurality of memory controllers, wherein the second notification indicates that the physical layer and / or the memory device coupled to the physical layer is no longer busy, and wherein the second notification is sent to the logic gate on the sideband bus, the logic gate transmitting the second notification from the logic gate to each of the plurality of memory controllers; as well as In response to receiving the second notification, the processing command is resumed on each of the plurality of memory controllers.

10. The device of claim 9, wherein the first notification is sent from the physical layer to each of the plurality of memory controllers on the sideband bus.

11. The device of claim 9, wherein the first notification is sent from the physical layer to the logic gate and from the logic gate to each of the plurality of memory controllers.

12. The device of claim 9, wherein the command is blocked on the plurality of memory controllers in response to the physical layer performing a training operation.

13. The device of claim 9, wherein commands are transmitted from the central controller to each of the plurality of memory controllers on a command bus.

14. The device of claim 9, wherein the command is sent from each of the plurality of memory controllers to a corresponding memory device in the plurality of memory devices.

15. The device of claim 9, wherein data associated with the command is transmitted from each of the plurality of memory devices to the central controller.

16. The device of claim 9, wherein a programming operation is performed on the registers of each of the plurality of memory controllers.

17. The device of claim 9, wherein a command to program the registers on each of the plurality of memory controllers is transmitted on a command bus.

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