A solid state disk error correction method, device, equipment and medium

Abstract

This application discloses a method, apparatus, device, and medium for error correction in solid-state drives (SSDs), relating to the field of computer technology. Applied to SSD controllers, the method includes: counting the number of erase / write cycles of the flash memory physical blocks in the current SSD and determining the preset lifespan of the current SSD; determining a data redundancy strategy for the current SSD based on the preset lifespan and constructing corresponding stripes; obtaining the parity bit position of the current stripe in the dynamic random access memory (DRAM) based on the target flash memory structure; determining the parity bit position after adaptive rotation through a flash conversion layer, wherein the adaptive rotation dynamically adjusts the parity bit position according to the actual write speed of the current SSD; and when the host encounters an unrecoverable error event while reading data from the SSD, data recovery is performed using the normal data bits and parity bits in the current stripe. This technical solution can improve the performance and reliability of the SSD throughout its lifespan.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a method, apparatus, device, and medium for error correction of solid-state drives. Background Technology

[0002] Solid State Drives (SSDs) typically incorporate error correction mechanisms to ensure data storage reliability. These mechanisms usually include three steps: ECC (Error Checking and Correcting) correction, rereading, and RAID (Redundant Arrays of Independent Disks).

[0003] Existing solid-state drive (SSD) RAID error correction methods employ fixed redundancy data levels and fixed parity bit storage on a specific NAND flash memory chip. For example, RAID 5 uses 15 data bits + 1 parity bit for data redundancy; RAID 6 uses 62 data bits + 2 parity bits for data redundancy, and the parity bit is fixedly stored on a specific NAND flash memory chip. However, this approach does not precisely consider the different data reliability characteristics of NAND flash memory at different lifecycle stages, thus reducing the read / write performance of the SSD in its early lifespan and the data reliability in its later lifespan.

[0004] Therefore, how to provide a solution to the above-mentioned technical problems is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] In view of this, the purpose of this invention is to provide a method, apparatus, device, and medium for error correction of solid-state drives (SSDs), which can improve the performance and reliability of SSDs throughout their lifespan. The specific solution is as follows:

[0006] In a first aspect, this application discloses a solid-state drive (SSD) error correction method, applied to an SSD controller, comprising:

[0007] The number of erase / write cycles for each physical flash memory block in the current solid-state drive is counted, and the preset lifespan of the current solid-state drive is determined based on the number of erase / write cycles.

[0008] The data redundancy strategy of the current solid-state drive is determined according to the preset lifespan period, and the corresponding stripe construction is performed based on the data redundancy strategy to determine the target flash memory structure.

[0009] Based on the target flash memory structure, the parity bit position of the current stripe in which all data is stored in the dynamic random access memory is obtained; wherein, the parity bit position is determined by adaptive rotation of the flash conversion layer, and the adaptive rotation dynamically adjusts the parity bit position according to the actual write speed of the current solid-state drive;

[0010] When the host encounters an error event that cannot be recovered by error checking and correction while reading data from the current solid-state drive, it uses the normal data bits in the current stripe and the check bit at the check bit position to recover the data from the error event.

[0011] Optionally, before counting the number of erase / write operations for each physical flash memory block in the current solid-state drive, the method further includes:

[0012] The flash memory conversion layer constructs an erase / write count table in the dynamic random access memory to record the erase / write count corresponding to each physical block of flash memory;

[0013] When a physical block erase command is received from the flash memory conversion layer and sent to the flash memory controller in the solid-state drive controller, the count of the corresponding flash memory physical block is incremented by one.

[0014] Optionally, the step of counting the number of erase / write operations for each flash memory physical block in the current solid-state drive and determining the preset lifespan of the current solid-state drive based on the number of erase / write operations includes:

[0015] The erase / write count of each flash memory physical block in the current solid-state drive is periodically calculated from the erase / write count table based on a preset time interval.

[0016] Calculate the average number of erase / write cycles for all the flash memory physical blocks in the current solid-state drive based on the number of erase / write cycles for each flash memory physical block;

[0017] The preset lifespan of the current solid-state drive is determined based on the average number of erase / write cycles.

[0018] Optionally, after calculating the average number of erase / write cycles for all flash memory physical blocks in the current solid-state drive based on the number of erase / write cycles for each flash memory physical block, the method further includes:

[0019] The error bit rate corresponding to the current solid-state drive is determined based on the average number of erase and write cycles, so as to filter bad blocks in the flash memory physical blocks based on the error bit rate;

[0020] The bad blocks are marked by the flash memory conversion layer, and the valid data on the bad blocks is transferred to other free physical blocks in the flash memory physical blocks.

[0021] Optionally, the preset lifespan period includes early lifespan, mid lifespan, and late lifespan; the step of determining the data redundancy strategy of the current solid-state drive based on the preset lifespan period, and performing corresponding stripe construction based on the data redundancy strategy to determine the target flash memory structure, specifically includes:

[0022] If the current solid-state drive is in the early part of its lifespan, the number of data bits corresponding to the current independent disk redundant array error correction method is 63, the number of parity bits is 1, and the target flash memory structure is determined by constructing corresponding stripes during data writing according to the current independent disk redundant array error correction method.

[0023] If the current solid-state drive is in the middle of its lifespan, the number of data bits corresponding to the current independent disk redundant array error correction method is 31, the number of parity bits is 1, and the target flash memory structure is determined by performing corresponding stripe construction during data writing according to the current independent disk redundant array error correction method.

[0024] If the preset lifespan period corresponding to the current solid-state drive is in the late stage of its lifespan, then the number of data bits corresponding to the current independent disk redundant array error correction method is 15, the number of parity bits is 1, and stripe construction is performed during data writing according to the current independent disk redundant array error correction method to determine the target flash memory structure.

[0025] Optionally, the target flash memory structure is a physical page-level flash memory structure, which includes a target number of dies corresponding to the data redundancy strategy. Each die includes multiple facets, each facet includes multiple blocks, and each block includes multiple pages. After determining the target flash memory structure by performing corresponding stripe construction based on the data redundancy strategy, the process further includes:

[0026] The host inputs the current data. When the number of pages containing the current data reaches the number of faces included in a single die, the current data is stored as the first data bit of the current stripe in the data bit area of ​​the buffer of the dynamic random access memory, and the first data bit is copied to the parity bit area of ​​the buffer.

[0027] Repeat the step of obtaining the current data input by the host, and use the current data bits to perform XOR processing on the check bit of the check bit area to update the check bit;

[0028] When all the data bits of the current stripe are stored in the data bit area and all the parity bits are stored in the parity bit area, the data of the current stripe is determined and the data of the current stripe is transferred to the flash memory through the flash conversion layer. Then, the step of obtaining the current data input by the host is triggered again to determine the data of the next stripe.

[0029] Optionally, obtaining the parity bit position of the current stripe with complete data storage in the dynamic random access memory based on the target flash memory structure includes:

[0030] Obtain the current maximum write bandwidth and initial parity bit position of the solid-state drive;

[0031] Determine whether this is the first time data is written to the current solid-state drive;

[0032] If data is being written to the current solid-state drive for the first time, the initial parity bit position is used as the parity bit position of the current stripe.

[0033] If this is not the first time data is written to the current solid-state drive, the actual write rate of the current solid-state drive at the current moment is statistically analyzed through the flash conversion layer, and the ratio between the actual write rate and the maximum write bandwidth is determined.

[0034] Determine whether the ratio is not less than a preset threshold;

[0035] If the ratio is not less than the preset threshold, then the current check bit position is determined and the current check bit position is shifted one position to the right as the check bit position of the current stripe;

[0036] If the ratio is less than the preset threshold, the current check bit position remains unchanged and is used as the check bit position of the current stripe.

[0037] Optionally, when the host encounters an unrecoverable error event while reading data from the current solid-state drive, data recovery is performed using the normal data bits in the current stripe and the check bit at the check bit position to address the error event, including:

[0038] When the host encounters an error event that cannot be recovered by error checking and correction while reading data from the current solid-state drive, the abnormal data bit corresponding to the error event is determined;

[0039] Data recovery is performed by XORing the normal data bits in the current strip with the check bit at the check bit position.

[0040] Optionally, the solid-state drive error correction method further includes:

[0041] The flash translation layer maps the data bits and parity bits in the current stripe to the physical page address in the flash memory, so that the host can read the data in the current solid-state drive according to the physical page address.

[0042] Secondly, this application discloses a solid-state drive error correction device, applied to a solid-state drive controller, comprising:

[0043] The lifespan determination module is used to count the number of erase / write operations for each flash memory physical block in the current solid-state drive, and determine the preset lifespan period corresponding to the current solid-state drive based on the number of erase / write operations.

[0044] The flash memory structure determination module is used to determine the data redundancy strategy of the current solid-state drive according to the preset lifespan period, and to perform corresponding stripe construction based on the data redundancy strategy to determine the target flash memory structure.

[0045] The parity bit position acquisition module is used to acquire the parity bit position of the current stripe in which all data is stored in the dynamic random access memory based on the target flash memory structure; wherein, the parity bit position is determined by adaptive rotation change through the flash conversion layer, and the adaptive rotation dynamically adjusts the parity bit position according to the actual write speed of the current solid-state drive;

[0046] The data recovery module is used to recover data from an error event that cannot be recovered when the host encounters an error during data reading from the current solid-state drive, by using the normal data bits in the current stripe and the check bit at the check bit position.

[0047] Thirdly, this application discloses an electronic device including a processor and a memory; wherein the memory is used to store a computer program, which is loaded and executed by the processor to implement the solid-state drive error correction method as described above.

[0048] Fourthly, this application discloses a computer-readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the solid-state drive error correction method as described above.

[0049] This application provides a solid-state drive (SSD) error correction method applied to an SSD controller, comprising: counting the number of erase / write operations for each flash physical block in the current SSD, and determining a preset lifespan period corresponding to the current SSD based on the number of erase / write operations; determining a data redundancy strategy for the current SSD based on the preset lifespan period, and constructing corresponding stripes based on the data redundancy strategy to determine a target flash memory structure; obtaining the parity bit position of the current stripe with complete data storage in the dynamic random access memory (DRAM) based on the target flash memory structure; wherein the parity bit position is determined by adaptive rotation through a flash conversion layer, and the adaptive rotation dynamically adjusts the parity bit position according to the actual write rate of the current SSD; when the host encounters an error event that cannot be recovered by error checking and correction while reading data in the current SSD, data recovery is performed on the error event using the normal data bits in the current stripe and the parity bit at the parity bit position.

[0050] The beneficial technical effects of this application are as follows: On the one hand, the technical solution of this application determines the lifespan of the solid-state drive (SSD) based on the number of erase / write cycles of the flash memory in the SSD, and further adopts different data redundancy strategies according to different lifespan periods. In this way, the characteristics of flash memory at different lifespan periods of the hard drive are fully considered, ensuring the reliability of hard drive data storage. On the other hand, when allocating the parity bit positions of the stripes in the flash conversion layer, the parity bit positions are dynamically adjusted according to the actual write rate of the current SSD through adaptive rotation. This can effectively improve the read concurrency of the SSD, ensure the sequential read and random read performance of the hard drive, achieve a dynamic balance between read and write performance of the SSD, and improve the read performance of the SSD.

[0051] In addition, the solid-state drive error correction device, equipment and storage medium provided in this application correspond to the above-mentioned solid-state drive error correction method and have the same effect. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0053] Figure 1 This is a flowchart of a solid-state drive error correction method disclosed in this application;

[0054] Figure 2 This is a schematic diagram of a solid-state drive structure disclosed in this application;

[0055] Figure 3 This is a schematic diagram of a grain-level flash memory structure disclosed in this application;

[0056] Figure 4 This is a schematic diagram of a physical page-level flash memory structure disclosed in this application;

[0057] Figure 5 This is a schematic diagram of 15+1 data redundancy with a fixed check bit position disclosed in this application;

[0058] Figure 6 This is a schematic diagram of an adaptive check bit position rotation process disclosed in this application;

[0059] Figure 7 This is a schematic diagram of the structure of a solid-state drive error correction device disclosed in this application;

[0060] Figure 8 This is a structural diagram of an electronic device disclosed in this application. Detailed Implementation

[0061] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0062] Solid-state drives (SSDs) based on NAND flash memory are increasingly becoming the industry's preferred storage medium due to their larger capacity and higher random read / write performance. However, in pursuit of ever-smaller manufacturing processes, the current 3D vertically stacked NAND flash memory is encountering data storage reliability issues. The lifespan of SSDs (the number of erase / write cycles of flash memory cells) is gradually shortening, and they are more susceptible to read / write interference, causing the data read from the SSD by the host to differ from the data written to it.

[0063] Currently, solid-state drives (SSDs) typically incorporate error correction schemes to ensure data storage reliability. These schemes generally include three steps: ECC correction, rereading, and RAID. First, ECC correction is achieved by adding a redundancy checksum to each data block. If data cannot be corrected by ECC, the SSD moves the flash memory cell voltage axis for rereading and performs ECC correction again. Finally, if multiple rereads fail to retrieve the correct data, RAID is used to perform redundancy checks on multiple data entries. Existing SSD RAID methods use fixed redundancy data levels and fixed parity bits on fixed NAND flash chips. For example, RAID 5 uses 15 data bits + 1 parity bit for data redundancy, and RAID 6 uses 62 data bits + 2 parity bits, with the parity bit fixed on a specific NAND flash chip. This approach does not precisely consider the different data reliability characteristics of flash memory at different lifecycles, thus reducing the read / write performance of the SSD in its early lifespan and the data reliability in its later lifespan.

[0064] As can be seen, existing solid-state drive (SSD) RAID schemes employ fixed data redundancy strategies and fixed parity bit positions, which fail to consider the flash memory characteristics at different stages of the SSD's lifespan. Therefore, this application provides an SSD error correction scheme that optimizes the SSD RAID scheme, thereby improving the SSD's performance and reliability throughout its lifespan.

[0065] This invention discloses a solid-state drive error correction method, see [link to relevant documentation]. Figure 1 As shown, applied to a solid-state drive controller, the method includes:

[0066] S101: Count the number of erase / write operations for each flash memory physical block in the current solid-state drive, and determine the preset lifespan period corresponding to the current solid-state drive based on the number of erase / write operations.

[0067] In this embodiment of the application, it is applied to a solid-state drive controller. For example... Figure 2 The diagram shows the basic structure of a solid-state drive (SSD). A NAND flash-based SSD mainly consists of three parts: an SSD controller, Dynamic Random Access Memory (DRAM), and multiple NAND flash memory chips. The central processing unit (CPU) in the SSD controller is responsible for executing the FTL (Flash Translation Layer) function, receiving read / write requests from the host through the host interface, and sending read / write / erase operation commands to the NAND flash memory via the flash controller.

[0068] Understandably, in the early stages of the lifespan of NAND flash memory-based solid-state drives (SSDs), the number of write cycles to the flash memory physical blocks is very small, and the drive only has bad blocks due to manufacturing processes, resulting in high overall reliability. However, as the lifespan of the SSD increases, the number of write cycles to the flash memory physical blocks increases, the reliability of the storage medium gradually decreases, and the number of errors that ECC cannot correct also increases. Therefore, this application employs lifespan-graded data redundancy. By statistically analyzing the number of write cycles to each flash memory physical block in the current SSD, the corresponding lifespan period of the current SSD is determined. Then, different levels of data redundancy strategies are adopted according to different lifespan periods to improve the read and write performance of the drive.

[0069] Specifically, before counting the number of erase / write operations for each physical flash memory block in the current solid-state drive, the method further includes: constructing an erase / write count table in the dynamic random access memory through the flash conversion layer to record the number of erase / write operations for each physical flash memory block; when a physical block erase command is received from the flash conversion layer to the flash controller in the solid-state drive controller, the count of the corresponding physical flash memory block is incremented by one.

[0070] As can be seen, the FTL maintains an erase / write count table in the DRAM, which records the number of erase / write operations for each flash memory physical block. This table allows for the statistical analysis of the erase / write count for each physical block. Each time the FTL sends a physical block erase command to the flash memory controller, the erase / write count for the corresponding physical block is incremented by one.

[0071] In this embodiment, the average number of erase / write cycles for all flash memory physical blocks is periodically calculated based on an erase / write cycle table, and the lifespan of the current solid-state drive (SSD) is estimated based on this average value. Specifically, the erase / write cycles for each flash memory physical block in the current SSD are periodically counted from the erase / write cycle table at preset time intervals; the average number of erase / write cycles for all flash memory physical blocks in the current SSD is calculated based on the erase / write cycles for each flash memory physical block; and the preset lifespan of the current SSD is determined based on the average number of erase / write cycles.

[0072] Additionally, the average error bit rate of the current SSD can be estimated, and the corresponding preset lifespan of the SSD can be determined based on this error bit rate. It's understandable that the flash memory error bit rate is typically lower in the early stages of an SSD's lifespan and higher in the later stages. Therefore, a comparison threshold can be set for the error bit rate, and the lifespan of the SSD can be determined by comparing the error bit rate with the preset threshold.

[0073] S102: Determine the data redundancy strategy of the current solid-state drive according to the preset lifespan period, and perform corresponding stripe construction based on the data redundancy strategy to determine the target flash memory structure.

[0074] In this embodiment, the RAID mode is determined based on the estimated lifespan, dividing the lifespan of the solid-state drive (SSD) into early, mid, and late lifespans, and employing different data redundancy strategies for each lifespan stage. For example, in the early lifespan of the SSD, the flash memory has a low write / erase cycle count. To improve read / write performance, a lower-level data redundancy strategy can be adopted, allocating more space on the SSD to data to enhance read / write performance. However, as the lifespan of the SSD increases, in the late lifespan, the reliability of the storage medium gradually decreases, and ECC-uncorrectable errors increase. At this point, a higher-level data redundancy strategy can be adopted, storing more redundant data to ensure the reliability of data storage.

[0075] It should be noted that different data redundancy strategies correspond to different RAID methods. Different RAID methods correspond to different combinations of data bits and parity bits. Depending on the RAID method, different stripe construction methods can be performed during data writing based on different combinations of data bits and parity bits. Once all stripes are constructed, the target flash memory structure is obtained.

[0076] S103: Obtain the parity bit position of the current stripe in which all data is stored in the dynamic random access memory based on the target flash memory structure; wherein, the parity bit position is determined by adaptive rotation change through the flash conversion layer, and the adaptive rotation dynamically adjusts the parity bit position according to the actual write speed of the current solid-state drive.

[0077] In this embodiment, the SSD transfers data input from the host via DMA (Direct Memory Access) through the bus to the DRAM buffer of the DRAM and stores it in the buffer. The buffer is divided into a data bit area and a parity bit area. The size of the data bit area and the parity bit area depends on the size of the stripe.

[0078] Since parity bits are used to correct data bits during solid-state drive error correction, the parity bit position of the current stripe in the DRAM buffer is determined based on the current target flash memory structure. Because the FTL can transfer the data of a stripe to flash memory once all the data in that stripe is stored, and then proceed with storing and transferring data for the next stripe, the current stripe is a stripe with all the data stored.

[0079] Furthermore, because current methods typically use a fixed parity bit allocation, the parity bit is only read during RAID error recovery, and since the parity bit occupies one die, the read concurrency of the solid-state drive (SSD) is reduced, leading to a decrease in both sequential and random read performance. Therefore, in this embodiment, the parity bit position is determined through adaptive rotation by the flash memory conversion layer. The parity bit position is dynamically adjusted based on the actual write speed of the SSD, ensuring that the parity bit position of the stripe remains unchanged when the actual write speed is low, and changes the parity bit position when the actual write speed reaches the required level. This ensures parallelism during data reading and improves the read performance of the SSD.

[0080] S104: When the host encounters an error event that cannot be recovered by error checking and correction while reading data in the current solid-state drive, data recovery is performed on the error event using the normal data bits in the current stripe and the check bit at the check bit position.

[0081] In this embodiment, when the host reads data, if an error occurs that cannot be recovered by ECC, it can be recovered by XORing other data in the same stripe. Specifically, when the host encounters an error event that cannot be recovered by error checking and correction while reading data in the current solid-state drive, the abnormal data bit corresponding to the error event is determined; the normal data bit in the current stripe is XORed with the parity bit at the parity bit position to recover the data in the abnormal data bit.

[0082] For example, if data bit 0_0 in stripe 0, which uses a rotating parity bit position, is corrupted, the data in data bit 0_0 can be recovered by XORing data bits 0_1 to 0_14 with the parity bit. It should be noted that if the parity bit is corrupted, no error recovery is needed; however, if more than one error occurs, the correct data cannot be recovered using RAID 5, and RAID 6 level redundancy should be considered.

[0083] This application provides a solid-state drive (SSD) error correction method applied to an SSD controller, comprising: counting the number of erase / write operations for each flash physical block in the current SSD, and determining a preset lifespan period corresponding to the current SSD based on the number of erase / write operations; determining a data redundancy strategy for the current SSD based on the preset lifespan period, and constructing corresponding stripes based on the data redundancy strategy to determine a target flash memory structure; obtaining the parity bit position of the current stripe with complete data storage in the dynamic random access memory (DRAM) based on the target flash memory structure; wherein the parity bit position is determined by adaptive rotation through a flash conversion layer, and the adaptive rotation dynamically adjusts the parity bit position according to the actual write rate of the current SSD; when the host encounters an error event that cannot be recovered by error checking and correction while reading data in the current SSD, data recovery is performed on the error event using the normal data bits in the current stripe and the parity bit at the parity bit position.

[0084] The beneficial technical effects of this application are as follows: On the one hand, the technical solution of this application determines the lifespan of the solid-state drive (SSD) based on the number of erase / write cycles of the flash memory in the SSD, and further adopts different data redundancy strategies according to different lifespan periods. In this way, the characteristics of flash memory at different lifespan periods of the hard drive are fully considered, ensuring the reliability of hard drive data storage. On the other hand, when allocating the parity bit positions of the stripes in the flash conversion layer, the parity bit positions are dynamically adjusted according to the actual write rate of the current SSD through adaptive rotation. This can effectively improve the read concurrency of the SSD, ensure the sequential read and random read performance of the hard drive, achieve a dynamic balance between read and write performance of the SSD, and improve the read performance of the SSD.

[0085] Based on the above embodiments, this embodiment will specifically describe S102 in the above embodiments. Specifically, in order to determine which combination of data bits and parity bits corresponds to different RAID methods, the process of determining the data redundancy strategy of the current solid-state drive based on the preset lifespan, and constructing corresponding stripes based on the data redundancy strategy to determine the target flash memory structure may include the following steps:

[0086] Step 11: If the preset lifespan period corresponding to the current solid-state drive is in the early stage of the lifespan, then the number of data bits corresponding to the current independent disk redundant array error correction method is 63, the number of parity bits is 1, and the corresponding stripe construction is performed during data writing according to the current independent disk redundant array error correction method to determine the target flash memory structure.

[0087] Step 12: If the preset lifespan period corresponding to the current solid-state drive is in the middle of the lifespan, then the number of data bits corresponding to the current independent disk redundant array error correction method is 31, the number of parity bits is 1, and the corresponding stripe construction is performed during data writing according to the current independent disk redundant array error correction method to determine the target flash memory structure.

[0088] Step 13: If the preset lifespan period corresponding to the current solid-state drive is in the late stage of its lifespan, then the number of data bits corresponding to the current independent disk redundant array error correction method is 15, the number of parity bits is 1, and stripe construction is performed during data writing according to the current independent disk redundant array error correction method to determine the target flash memory structure.

[0089] For ease of description, the above steps will be combined for explanation.

[0090] In this embodiment, the RAID mode is determined based on the estimated lifespan, dividing the solid-state drive's lifespan into early, mid, and late stages. The early lifespan corresponds to a 63+1 (data bits + parity bits) RAID mode; the mid-lifespan corresponds to a 31+1 (data bits + parity bits) RAID mode; and the late lifespan corresponds to a 15+1 (data bits + parity bits) RAID mode. Depending on the RAID mode, different striping methods are used during data writing. It should be noted that when the solid-state drive supports RAID 6 level data redundancy, RAID modes such as 62+2 or 126+2 can be added.

[0091] As can be seen, by grading the lifespan of solid-state drives (SSDs), different data redundancy strategies can be set for the drives according to different stages of their lifespan. In the early stages of their lifespan, the flash memory has a low bit error rate, so a lower level of data redundancy strategy is adopted, allocating more space on the drive to data and improving read and write performance. In the later stages of their lifespan, the flash memory has a high bit error rate, so a higher level of data redundancy strategy is adopted, storing more redundant data to ensure the reliability of data storage.

[0092] Based on the above embodiments, in a feasible implementation, to ensure that the written data can be correctly read, this embodiment uses page mapping for FTL, mapping the data bits and parity bits in the stripe to physical page addresses in the flash memory one-to-one. Specifically, it may also include the following steps:

[0093] The flash translation layer maps the data bits and parity bits in the current stripe to the physical page address in the flash memory, so that the host can read the data in the current solid-state drive according to the physical page address.

[0094] In this embodiment, a stripe in different flash memory structures corresponds to a different number of physical pages of data in the flash memory. Based on the aforementioned embodiments, a stripe corresponds to 64 / 32 / 16 physical pages of data in the flash memory. The FTL uses a page mapping method to map the data bits and parity bits in the stripe to the physical page addresses in the flash memory one-to-one. When the data of a stripe in the DRAM buffer is complete, the FTL allocates the addresses of 64 / 32 / 16 physical pages to that stripe.

[0095] Furthermore, the written data is read correctly based on the allocated physical page address. It should be noted that when allocating physical addresses, the FTL needs to skip bad blocks in the flash memory. Bad blocks refer to flash memory physical blocks with a high error bit rate due to manufacturing defects or later use; therefore, it cannot be guaranteed that the written data can be read correctly from these bad blocks. In this case, the FTL marks the bad blocks and stops writing to them, while simultaneously moving the valid data from the bad blocks to other free physical blocks.

[0096] Specifically, the error bit rate corresponding to the current solid-state drive is determined based on the average number of erase / write cycles, so as to filter bad blocks in the flash memory physical block based on the error bit rate; the bad blocks are marked by the flash memory conversion layer, and the valid data on the bad blocks is transferred to other free physical blocks in the flash memory physical block.

[0097] Furthermore, this embodiment will specifically describe how to construct the data in the stripes. After constructing the stripes based on the data redundancy strategy to determine the target flash memory structure, the following steps are also included:

[0098] Step 21: Obtain the current data input by the host. When the number of pages containing the current data reaches the number of faces included in a single die, store the current data as the first data bit of the current stripe in the data bit area of ​​the buffer of the dynamic random access memory, and copy the first data bit to the parity bit area in the buffer.

[0099] Step 22: Repeat the step of obtaining the current data input by the host, and use the current data bits to perform XOR processing on the check bits in the check bit area to update the check bits;

[0100] Step 23: When all the data bits of the current stripe are stored in the data bit area and all the parity bits are stored in the parity bit area, determine the data of the current stripe and transfer the data of the current stripe to the flash memory through the flash conversion layer. Then, re-trigger the step of obtaining the current data input by the host to determine the data of the next stripe.

[0101] First, we will explain the composition of NAND FLASH in detail.

[0102] NAND chips are organized into multiple independently accessible channels. Each chip is further composed of 3D dies. Each die includes multiple planes (faces in flash memory), each plane includes hundreds of blocks (blocks in flash memory), and each block contains thousands of pages (pages in flash memory). The die is the smallest basic management unit for flash memory communication, the page is the smallest unit for read and write operations, and the block is the smallest unit for erase operations.

[0103] Flash memory read / write parallelism includes channel-level parallelism, chip-level parallelism, die-level parallelism, and plane-level parallelism. Most SSDs use a multi-plane approach for read / write operations, enabling simultaneous read / write operations across multiple planes to improve performance. Figure 3 The chip-level flash memory structure is shown, assuming that the SSD has 4 channels, 2 chips on each channel, and 2 chips on each chip; Figure 4 The physical page-level flash memory structure is shown. Due to page size limitations, not all blocks and pages are depicted, and the number of planes in the flash memory is assumed to be 4. In this embodiment, the target flash memory structure determined by stripe construction based on a data redundancy strategy is a physical page-level flash memory structure.

[0104] For example, such as Figure 5 The diagram illustrates a 15+1 data redundancy strategy. The physical page-level flash memory structure includes the target number of dies corresponding to the data redundancy strategy. Data transmitted from the host is stored in the data area. After four physical pages (for multi-plane write operations) of data are collected, this data is stored as the first data bit of the stripe in the data area. Simultaneously, this first data bit is copied to the parity area. Thereafter, each time a data bit is collected, it is stored in the data area and simultaneously XORed with the parity bit of the corresponding stripe in the parity area, updating the parity bit value, until all data bits of the stripe are collected and stored in the data area. The XOR value of all data bits, representing the parity bit, is stored in the parity area.

[0105] It should be noted that once a stripe is accumulated in the DRAM buffer and address mapping and parity bit allocation are completed, the FTL can transfer the data of that stripe to the flash memory, writing one stripe of data at a time. Only after one flash memory transfer is completed will the transfer of the next stripe begin.

[0106] Based on the above embodiments, this embodiment will specifically describe S103 in the above embodiments. Specifically, the process of dynamically adjusting the parity bit position according to the actual write rate, and obtaining the parity bit position of the current stripe with complete data storage in the dynamic random access memory based on the target flash memory structure, may include the following steps:

[0107] Step 31: Obtain the current maximum write bandwidth and initial parity bit position of the solid-state drive;

[0108] Step 32: Determine whether this is the first time data is being written to the current solid-state drive;

[0109] Step 33: If this is the first time data is written to the current solid-state drive, then the initial parity bit position is used as the parity bit position of the current stripe;

[0110] Step 34: If this is not the first time data is written to the current solid-state drive, the actual write rate of the current solid-state drive at the current moment is calculated by the flash conversion layer, and the ratio between the actual write rate and the maximum write bandwidth is determined.

[0111] Step 35: Determine whether the ratio is not less than a preset threshold;

[0112] Step 36: If the ratio is not less than the preset threshold, determine the current check bit position and shift the current check bit position one position to the right as the check bit position of the current stripe;

[0113] Step 37: If the ratio is less than the preset threshold, the current check bit position remains unchanged and is used as the check bit position of the current stripe.

[0114] It's understandable that the addresses allocated by the FTL to each stripe are distributed across different dies, and the die allocation varies depending on the location of the parity bit assigned by the FTL. When the parity bit is fixedly allocated to a specific die, it's called a fixed parity bit allocation method. For example... Figure 5 The diagram shows a 15+1 data redundancy method with fixed check bit positions.

[0115] In this configuration, data bit 0_0 represents data bit 0 of stripe 0, data bit 0_1 ​​represents data bit 1 of stripe 0, data bit 1_0 represents data bit 0 of stripe 1, parity bit 0_ represents the parity bit of stripe 0, and so on. When performing a write operation on stripe 0, data bit 0 of stripe 0 is allocated to die 0 / block 0 / face 0-3 / page 0; data bit 1 is allocated to die 1 / block 0 / face 0-3 / page 0; data bit 2 is allocated to die 2 / block 0 / face 0-3 / page 0; data bit 3 is allocated to die 3 / block 0 / face 0-3 / page 0; data bit 14 is allocated to die 14 / block 0 / face 0-3 / page 0; and the parity bit is allocated to die 15 / block 0 / face 0-3 / page 0.

[0116] When the next stripe is written, the writing continues in the next empty page. Therefore, with the fixed parity bit address mapping method, the parity bit will always appear on die 15, while the target data bits are allocated in dies 0-14. The read parallelism at the die level is reduced to the normal 14 / 15, and the parity bit data is only read during RAID error recovery. Consequently, normal data reads only access the data bits of each stripe. Because the parity bit occupies one die, the read concurrency of the SSD is reduced, leading to a decrease in both sequential and random read performance.

[0117] Therefore, by varying the parity bit position in each stripe, distributing the parity bits across multiple dies, the read concurrency of the solid-state drive (SSD) can be effectively improved. However, due to the physical characteristics of flash memory, frequent changes in the parity bit position can lead to a certain degree of decrease in the flash memory write speed. In this embodiment, the parity bit position is adaptively rotated. When allocating the stripe parity bit position during the FTL (Flash Thread Layer) process, the parity bit position is dynamically adjusted based on the ratio between the flash memory write speed statistically obtained by the FTL and the optimal write speed. The specific process is as follows: Figure 6 As shown.

[0118] First, we need prior data on the optimal write performance of the SSD and the initial parity bit position. Let's assume the current SSD's maximum write bandwidth is x, and the initial parity bit position is m. Second, we need to determine if this is the first time data is written to the current SSD. If yes, the initial parity bit position is the parity bit position of the current stripe. If not, we calculate the write rate within the FTL (Flash Thread Tilt), which is the amount of data written to the flash memory per unit time. Based on this write rate, we adjust the parity bit position. Let's assume the actual write rate at the current moment, calculated from the FTL, is y.

[0119] Next, the parity bit position is rotated based on the ratio of y to x. Assuming a write rate decrease threshold of 0.9, in one specific implementation, when y / x ≥ 0.9, the write rate is considered sufficient, and the parity bit position of the current stripe is changed. Assuming the parity bit position of the previous stripe after the change is n (n = 0, 1, ..., m), and the current data redundancy strategy is m+1 (m = 15, 31, 63), then the parity bit position of the current stripe is set to (n+1)%(m+1), that is, the current parity bit position is shifted one position to the right. Here, "%" represents the modulo operator. It should be noted that if the current parity bit position is greater than the stripe position limit, it is reassigned to the first position in the stripe.

[0120] In another specific implementation, when y / x < 0.9, the actual write speed of the solid-state drive is affected by the position of the parity bit, resulting in a significant performance degradation. Therefore, the write of the current stripe will no longer modify the parity bit position, and the parity bit position of the current stripe will remain at n.

[0121] As can be seen, the adaptive parity bit position rotation method can dynamically balance the read and write performance of solid-state drives, so that the decline in hard drive write performance is only within a controlled range, and ensures a slight decrease in write performance while improving read parallelism.

[0122] Accordingly, this application also discloses a solid-state drive error correction device, see [link to relevant documentation]. Figure 7 As shown, this device is applied to a solid-state drive controller and includes:

[0123] The lifespan determination module 11 is used to count the number of erase / write operations of each flash physical block in the current solid-state drive, and determine the preset lifespan period corresponding to the current solid-state drive based on the number of erase / write operations.

[0124] The flash memory structure determination module 12 is used to determine the data redundancy strategy of the current solid-state drive according to the preset lifespan period, and to perform corresponding stripe construction based on the data redundancy strategy to determine the target flash memory structure.

[0125] The parity bit position acquisition module 13 is used to acquire the parity bit position of the current stripe in which all data is stored in the dynamic random access memory based on the target flash memory structure; wherein, the parity bit position is determined by adaptive rotation change through the flash conversion layer, and the adaptive rotation dynamically adjusts the parity bit position according to the actual write speed of the current solid-state drive;

[0126] Data recovery module 14 is used to recover data from the error event when the host encounters an error that cannot be recovered after error checking and correction while reading data in the current solid-state drive, by using the normal data bits in the current stripe and the check bit at the check bit position.

[0127] For more detailed information on the working process of each of the above modules, please refer to the relevant content disclosed in the foregoing embodiments, which will not be repeated here.

[0128] Therefore, the above-described solution in this embodiment, applied to a solid-state drive (SSD) controller, includes: counting the number of erase / write operations for each flash memory physical block in the current SSD, and determining a preset lifespan period corresponding to the current SSD based on the number of erase / write operations; determining a data redundancy strategy for the current SSD based on the preset lifespan period, and constructing corresponding stripes based on the data redundancy strategy to determine a target flash memory structure; obtaining the parity bit position of the current stripe with complete data storage in the dynamic random access memory (DRAM) based on the target flash memory structure; wherein, the parity bit position is determined after adaptive rotation by the flash conversion layer, and the adaptive rotation dynamically adjusts the parity bit position according to the actual write rate of the current SSD; when the host encounters an error event that cannot be recovered by error checking and correction while reading data in the current SSD, data recovery is performed on the error event using the normal data bits in the current stripe and the parity bit at the parity bit position.

[0129] The beneficial technical effects of this application are as follows: On the one hand, the technical solution of this application determines the lifespan of the solid-state drive (SSD) based on the number of erase / write cycles of the flash memory in the SSD, and further adopts different data redundancy strategies according to different lifespan periods. In this way, the characteristics of flash memory at different lifespan periods of the hard drive are fully considered, ensuring the reliability of hard drive data storage. On the other hand, when allocating the parity bit positions of the stripes in the flash conversion layer, the parity bit positions are dynamically adjusted according to the actual write rate of the current SSD through adaptive rotation. This can effectively improve the read concurrency of the SSD, ensure the sequential read and random read performance of the hard drive, achieve a dynamic balance between read and write performance of the SSD, and improve the read performance of the SSD.

[0130] In one specific embodiment, the solid-state drive error correction device further includes:

[0131] The erase / write count table construction module is used to construct an erase / write count table in the dynamic random access memory through the flash memory conversion layer to record the erase / write count corresponding to each physical block of flash memory;

[0132] The erase / write count recording module is used to increment the count of the corresponding physical block by one when a physical block erase command is received from the flash memory conversion layer to the flash memory controller in the solid-state drive controller.

[0133] In one specific implementation, the lifespan determination module 11 is specifically used for:

[0134] The erase / write count of each flash memory physical block in the current solid-state drive is periodically calculated from the erase / write count table based on a preset time interval.

[0135] Calculate the average number of erase / write cycles for all the flash memory physical blocks in the current solid-state drive based on the number of erase / write cycles for each flash memory physical block;

[0136] The preset lifespan of the current solid-state drive is determined based on the average number of erase / write cycles.

[0137] In one specific embodiment, the solid-state drive error correction device further includes:

[0138] An error bit rate calculation module is used to determine the error bit rate corresponding to the current solid-state drive based on the average number of erase / write cycles, so as to filter bad blocks in the flash memory physical blocks based on the error bit rate;

[0139] The effective data transfer module is used to mark the bad blocks through the flash memory conversion layer and transfer the effective data on the bad blocks to other free physical blocks in the flash memory physical blocks.

[0140] In one specific implementation, the preset lifetime period includes early lifetime, mid-life, and late lifetime; the flash memory structure determination module 12 includes:

[0141] The early error correction module is used to determine the target flash memory structure by setting the number of data bits to 63 and the number of parity bits to 1 if the preset lifespan period corresponding to the current solid-state drive is in the early lifespan.

[0142] The mid-term error correction module is used to determine the target flash memory structure by setting the number of data bits and the number of parity bits corresponding to the current independent disk redundant array error correction method if the preset lifespan period corresponding to the current solid-state drive is in the middle of the lifespan.

[0143] The late error correction module is used to determine the target flash memory structure by setting the number of data bits to 15 and the number of parity bits to 1 if the preset lifespan period corresponding to the current solid-state drive is in the late lifespan. It also performs corresponding stripe construction during data writing based on the current independent disk redundant array error correction method.

[0144] In one specific embodiment, the target flash memory structure is a physical page-level flash memory structure, which includes a target number of dies corresponding to the data redundancy strategy. Each die includes multiple faces, each face includes multiple blocks, and each block includes multiple pages. The solid-state drive error correction device further includes:

[0145] The stripe filling module is used to obtain the current data input by the host. When the number of pages containing the current data reaches the number of faces included in a single die, the current data is stored as the first data bit of the current stripe in the data bit area of ​​the buffer of the dynamic random access memory, and the first data bit is copied to the parity bit area in the buffer.

[0146] The check bit update module is used to repeatedly execute the step of obtaining the current data input by the host, and to perform XOR processing on the check bit of the check bit area using the current data bit to update the check bit;

[0147] The data transmission module is used to determine the data of the current stripe when all the data bits of the current stripe are stored in the data bit area and all the check bits are stored in the check bit area, and then transmit the data of the current stripe to the flash memory through the flash conversion layer, and then re-trigger the step of obtaining the current data input by the host to determine the data of the next stripe.

[0148] In one specific implementation, the check bit position acquisition module 13 is specifically used for:

[0149] Obtain the current maximum write bandwidth and initial parity bit position of the solid-state drive;

[0150] Determine whether this is the first time data is written to the current solid-state drive;

[0151] If data is being written to the current solid-state drive for the first time, the initial parity bit position is used as the parity bit position of the current stripe.

[0152] If this is not the first time data is written to the current solid-state drive, the actual write rate of the current solid-state drive at the current moment is statistically analyzed through the flash conversion layer, and the ratio between the actual write rate and the maximum write bandwidth is determined.

[0153] Determine whether the ratio is not less than a preset threshold;

[0154] If the ratio is not less than the preset threshold, then the current check bit position is determined and the current check bit position is shifted one position to the right as the check bit position of the current stripe;

[0155] If the ratio is less than the preset threshold, the current check bit position remains unchanged and is used as the check bit position of the current stripe.

[0156] In one specific implementation, the data recovery module 14 is specifically used for:

[0157] When the host encounters an error event that cannot be recovered by error checking and correction while reading data from the current solid-state drive, the abnormal data bit corresponding to the error event is determined;

[0158] Data recovery is performed by XORing the normal data bits in the current strip with the check bit at the check bit position.

[0159] In one specific embodiment, the solid-state drive error correction device further includes:

[0160] The address mapping module is used to map the data bits and parity bits in the current stripe to the physical page address in the flash memory through the flash translation layer, so that the host can read the data in the current solid-state drive according to the physical page address.

[0161] Furthermore, embodiments of this application also disclose an electronic device, Figure 8 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of this application.

[0162] Figure 8 This is a schematic diagram of the structure of an electronic device 20 provided in an embodiment of this application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the solid-state drive error correction method disclosed in any of the foregoing embodiments.

[0163] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0164] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk, or optical disk, etc. The resources stored on it can include an operating system 221, computer programs 222, and data 223, etc. The data 223 can include various types of data. The storage method can be temporary storage or permanent storage.

[0165] The operating system 221 is used to manage and control the various hardware devices on the electronic device 20 and the computer program 222, which may be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of performing the solid-state drive error correction method executed by the electronic device 20 as disclosed in any of the foregoing embodiments, the computer program 222 may further include a computer program capable of performing other specific tasks.

[0166] Furthermore, this application also discloses a computer-readable storage medium, which includes random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, magnetic disks, optical disks, or any other form of storage medium known in the art. The computer program, when executed by a processor, implements the aforementioned solid-state drive error correction method. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.

[0167] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0168] The steps of the solid-state drive error correction method or algorithm described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0169] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0170] The present invention provides a detailed description of a solid-state drive error correction method, apparatus, device, and medium. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, those skilled in the art will recognize that there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A solid state drive error correction method, characterized in that, Applications in solid-state drive controllers include: The number of erase / write cycles for each physical flash memory block in the current solid-state drive is counted, and the preset lifespan of the current solid-state drive is determined based on the number of erase / write cycles. The data redundancy strategy of the current solid-state drive is determined according to the preset lifespan period, and the corresponding stripe construction is performed based on the data redundancy strategy to determine the target flash memory structure. Based on the target flash memory structure, the parity bit position of the current stripe in which all data is stored in the dynamic random access memory is obtained; wherein, the parity bit position is determined by adaptive rotation of the flash conversion layer, and the adaptive rotation dynamically adjusts the parity bit position according to the actual write speed of the current solid-state drive; When the host encounters an error event that cannot be recovered by error checking and correction while reading data in the current solid-state drive, it uses the normal data bits in the current stripe and the check bit at the check bit position to recover data for the error event; The preset lifespan period includes early lifespan, mid lifespan, and late lifespan; the step of determining the data redundancy strategy for the current solid-state drive based on the preset lifespan period, and performing corresponding stripe construction based on the data redundancy strategy to determine the target flash memory structure, specifically involves: If the current solid-state drive is in the early part of its lifespan, the number of data bits corresponding to the current independent disk redundant array error correction method is 63, the number of parity bits is 1, and the target flash memory structure is determined by constructing corresponding stripes during data writing according to the current independent disk redundant array error correction method. If the current solid-state drive is in the middle of its lifespan, the number of data bits corresponding to the current independent disk redundant array error correction method is 31, the number of parity bits is 1, and the target flash memory structure is determined by performing corresponding stripe construction during data writing according to the current independent disk redundant array error correction method. If the current solid-state drive is in the late stage of its lifespan, the number of data bits corresponding to the current independent disk redundant array error correction method is 15, the number of parity bits is 1, and the corresponding stripe construction is performed during data writing according to the current independent disk redundant array error correction method to determine the target flash memory structure. The step of obtaining the parity bit position of the current stripe with complete data storage in the dynamic random access memory based on the target flash memory structure includes: Obtain the current maximum write bandwidth and initial parity bit position of the solid-state drive; Determine whether this is the first time data is written to the current solid-state drive; If data is being written to the current solid-state drive for the first time, the initial parity bit position is used as the parity bit position of the current stripe. If this is not the first time data is written to the current solid-state drive, the actual write rate of the current solid-state drive at the current moment is statistically analyzed through the flash conversion layer, and the ratio between the actual write rate and the maximum write bandwidth is determined. Determine whether the ratio is not less than a preset threshold; If the ratio is not less than the preset threshold, then the current check bit position is determined and the current check bit position is shifted one position to the right as the check bit position of the current stripe; If the ratio is less than the preset threshold, the current check bit position remains unchanged and is used as the check bit position of the current stripe.

2. The solid state drive error correction method of claim 1, wherein, Before calculating the number of erase / write cycles for each physical flash memory block in the current solid-state drive, the method also includes: The flash memory conversion layer constructs an erase / write count table in the dynamic random access memory to record the erase / write count corresponding to each physical block of flash memory; When a physical block erase command is received from the flash memory conversion layer and sent to the flash memory controller in the solid-state drive controller, the count of the corresponding physical block of the flash memory is incremented by one.

3. The solid state drive error correction method of claim 2, wherein, The step of counting the number of erase / write operations for each flash memory physical block in the current solid-state drive (SSD) and determining the preset lifespan of the current SSD based on the number of erase / write operations includes: The erase / write count of each flash memory physical block in the current solid-state drive is periodically calculated from the erase / write count table based on a preset time interval. Calculate the average number of erase / write cycles for all the flash memory physical blocks in the current solid-state drive based on the number of erase / write cycles for each flash memory physical block; The preset lifespan of the current solid-state drive is determined based on the average number of erase / write cycles.

4. The solid state drive error correction method of claim 3, wherein, After calculating the average number of erase / write cycles for all flash memory physical blocks in the current solid-state drive based on the number of erase / write cycles for each flash memory physical block, the method further includes: The error bit rate corresponding to the current solid-state drive is determined based on the average number of erase and write cycles, so as to filter bad blocks in the flash memory physical blocks based on the error bit rate; The bad blocks are marked by the flash memory conversion layer, and the valid data on the bad blocks is transferred to other free physical blocks in the flash memory physical blocks.

5. The method of claim 1, wherein, The target flash memory structure is a physical page-level flash memory structure, which includes a target number of dies corresponding to the data redundancy strategy. Each die includes multiple facets, each facet includes multiple blocks, and each block includes multiple pages. After determining the target flash memory structure by performing corresponding stripe construction based on the data redundancy strategy, the process further includes: The host inputs the current data. When the number of pages containing the current data reaches the number of faces included in a single die, the current data is stored as the first data bit of the current stripe in the data bit area of ​​the buffer of the dynamic random access memory, and the first data bit is copied to the parity bit area of ​​the buffer. Repeat the step of obtaining the current data input by the host, and use the current data bits to perform XOR processing on the check bit of the check bit area to update the check bit; When all the data bits of the current stripe are stored in the data bit area and all the parity bits are stored in the parity bit area, the data of the current stripe is determined and the data of the current stripe is transferred to the flash memory through the flash conversion layer. Then, the step of obtaining the current data input by the host is triggered again to determine the data of the next stripe.

6. The solid state drive error correction method of claim 1, wherein, When the host encounters an unrecoverable error event while reading data from the current solid-state drive, data recovery is performed using the normal data bits in the current stripe and the check bit at the check bit position to address the error event, including: When the host encounters an error event that cannot be recovered by error checking and correction while reading data from the current solid-state drive, the abnormal data bit corresponding to the error event is determined; Data recovery is performed by XORing the normal data bits in the current strip with the check bit at the check bit position.

7. The method of claim 1 to 6, wherein, Also includes: The flash translation layer maps the data bits and parity bits in the current stripe to the physical page address in the flash memory, so that the host can read the data in the current solid-state drive according to the physical page address.

8. A solid state drive error correction apparatus, comprising: Applications in solid-state drive controllers include: The lifespan determination module is used to count the number of erase / write operations for each flash memory physical block in the current solid-state drive, and determine the preset lifespan period corresponding to the current solid-state drive based on the number of erase / write operations. The flash memory structure determination module is used to determine the data redundancy strategy of the current solid-state drive according to the preset lifespan period, and to perform corresponding stripe construction based on the data redundancy strategy to determine the target flash memory structure. The parity bit position acquisition module is used to acquire the parity bit position of the current stripe in which all data is stored in the dynamic random access memory based on the target flash memory structure; wherein, the parity bit position is determined by adaptive rotation change through the flash conversion layer, and the adaptive rotation dynamically adjusts the parity bit position according to the actual write speed of the current solid-state drive; The data recovery module is used to recover data from the error event when the host encounters an unrecoverable error event while reading data from the current solid-state drive, by using the normal data bits in the current stripe and the check bit at the check bit position. The preset lifespan period includes early lifespan, mid lifespan, and late lifespan; the flash memory structure determination module is specifically used for: If the current solid-state drive is in the early part of its lifespan, the number of data bits corresponding to the current independent disk redundant array error correction method is 63, the number of parity bits is 1, and the target flash memory structure is determined by constructing corresponding stripes during data writing according to the current independent disk redundant array error correction method. If the current solid-state drive is in the middle of its lifespan, the number of data bits corresponding to the current independent disk redundant array error correction method is 31, the number of parity bits is 1, and the target flash memory structure is determined by performing corresponding stripe construction during data writing according to the current independent disk redundant array error correction method. If the current solid-state drive is in the late stage of its lifespan, the number of data bits corresponding to the current independent disk redundant array error correction method is 15, the number of parity bits is 1, and the corresponding stripe construction is performed during data writing according to the current independent disk redundant array error correction method to determine the target flash memory structure. The check bit position acquisition module is specifically used for: Obtain the current maximum write bandwidth and initial parity bit position of the solid-state drive; Determine whether this is the first time data is written to the current solid-state drive; If data is being written to the current solid-state drive for the first time, the initial parity bit position is used as the parity bit position of the current stripe. If this is not the first time data is written to the current solid-state drive, the actual write rate of the current solid-state drive at the current moment is statistically analyzed through the flash conversion layer, and the ratio between the actual write rate and the maximum write bandwidth is determined. Determine whether the ratio is not less than a preset threshold; If the ratio is not less than the preset threshold, then the current check bit position is determined and the current check bit position is shifted one position to the right as the check bit position of the current stripe; If the ratio is less than the preset threshold, the current check bit position remains unchanged and is used as the check bit position of the current stripe.

9. An electronic device, comprising: The electronic device includes a processor and a memory; wherein the memory is used to store a computer program, which is loaded and executed by the processor to implement the solid-state drive error correction method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, Used to store computer programs; wherein the computer programs, when executed by a processor, implement the solid-state drive error correction method as described in any one of claims 1 to 7.

Images