A method, apparatus, and storage medium for implementing a DMA request.

Abstract

This application discloses a method, apparatus, and storage medium for implementing DMA requests. The DMA request implementation method includes: recording the state machine and timeout for each queue; if no queue update event occurs, polling the queue in a round-robin manner. If a queue update event occurs, using the queue's ID as the address index of the queue information memory, reading the previously recorded state information and timeout, sending them to the state machine for processing, and writing the result back to the memory at the address index after processing. This application also provides an apparatus and storage medium for implementing DMA requests.

Description

Technical Field

[0001] This application relates to the field of data communication, and more particularly to a method, apparatus and storage medium for implementing DMA requests. Background Technology

[0002] DMA (Direct Memory Access) is a hardware-based data transfer technology that allows direct access to main memory for reading and writing data without CPU intervention. Its greatest advantage lies in its high-efficiency data transfer capabilities, enabling data transfer without consuming CPU resources. Packet per second (PPS) refers to the maximum number of network packets a server can process per second. PPS is a crucial indicator of cloud server network performance; a higher PPS indicates better server performance. PPS performance testing typically uses 64-byte packets, meaning each 64-byte packet transfer requires one PCIe (Peripheral Component Interconnect Express IO) and one MSIX (Message Signaled Interrupts) request. Using conventional PCIe-DMA would undoubtedly pose significant challenges to PCIe data recovery and CPU interrupt response. Summary of the Invention

[0003] To address the aforementioned technical problems, embodiments of this application provide a method, apparatus, and storage medium for implementing DMA requests.

[0004] In a first aspect, embodiments of this application provide a method for implementing a DMA request, comprising:

[0005] Record the state machine and timeout for each queue;

[0006] If no queue update event occurs, the queue is polled in a round-robin manner. If a queue update event occurs, the queue number ID is used as the address index of the queue information memory. The previously recorded status information and timeout time are read and sent to the state machine for processing. After processing, the result is written back to the memory at the address index.

[0007] Preferably, the processing of the state machine includes:

[0008] Initiate an update request for the descriptor table entry number DCB idx to the state machine;

[0009] The DCB idx update request is processed by the state machine.

[0010] Preferably, processing the DCB idx update request through the state machine includes:

[0011] Start the timer, and the state machine enters the idle state;

[0012] Upon receiving a DCB idx update request, it enters a busy state, sets the timeout for the next timer based on the current time, and directly outputs the update request.

[0013] If another DCB idx update request is received and the state machine is in a busy state, first check if the current time has exceeded the timeout period. If it has, output the DCB idx update request and the state machine jumps back to the idle state; if it has not timed out, suppress the current DCB idx update request and the state machine jumps to the waiting state.

[0014] If another DCB idx update request is received and the state is in a waiting state, suppress this DCB idx update request until the timeout period is reached, release the last received DCB idx update request, and the state machine jumps to the idle state.

[0015] Preferably, polling the queue in a round-robin manner includes:

[0016] The queue is polled in a way that increments every clock cycle.

[0017] Secondly, embodiments of this application also provide an apparatus for implementing a DMA request, comprising:

[0018] The queue management module includes multiple queues and is configured to record the state machine and timeout of each queue. If no queue update event occurs, the queue is polled in a round-robin manner. If a queue update event occurs, the queue number ID is used as the address index of the queue information memory. The previously recorded state information and timeout are read, sent to the state machine for processing, and the result is written back to the memory at the address index after processing.

[0019] The state machine module is configured to handle the descriptor table entry number DCB idx update request of the queue management module.

[0020] Thirdly, embodiments of this application also provide an apparatus for implementing a DMA request, including: a memory, a processor, and a user interface;

[0021] The memory is used to store computer programs;

[0022] The user interface is used to interact with the user;

[0023] The processor is used to read a computer program from the memory, and when the processor executes the computer program, it implements the DMA request implementation method provided by the present invention.

[0024] Fourthly, embodiments of this application also provide a processor-readable storage medium storing a computer program, wherein when the processor executes the computer program, it implements the DMA request implementation method provided by the present invention.

[0025] The DMA request implementation method of this invention records the state machine and timeout for each queue separately, supports the merging of IDX update write requests under single queue and multi-queue conditions, is applicable to virtualization and non-virtualization scenarios, and can merge data requests of arbitrary length; it reduces the number of write requests, reduces the consumption of PCIe bandwidth, and improves overall performance; it also reduces the number of msix interrupt requests and the number of CPU response times. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of buffer data update provided in an embodiment of this application;

[0028] Figure 2 A schematic diagram of a queue state machine provided in an embodiment of this application;

[0029] Figure 3 A schematic flowchart illustrating the implementation method of a DMA request provided in an embodiment of this application;

[0030] Figure 4 This is a schematic diagram of queue management provided in an embodiment of this application;

[0031] Figure 5 A schematic diagram of an apparatus for implementing a DMA request provided in an embodiment of this application;

[0032] Figure 6 This is a schematic diagram of another DMA request implementation device provided in an embodiment of this application. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0034] The following are explanations of some of the words that appear in the text:

[0035] 1. In the embodiments of this invention, the term "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship.

[0036] 2. In the embodiments of this application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0037] 3. DMA: Direct Memory Access.

[0038] 4. DCB: Descriptor Table Entries.

[0039] 6. Idx: Number.

[0040] 7. Addr: Address.

[0041] 8. FIFO, or First In First Out, is a data buffer that operates on a first-in, first-out basis (data can only be written and read sequentially).

[0042] To address the problems in the existing technology, this invention discloses a method for implementing DMA requests. Based on the existing standard DMA transfer mechanism, it improves the utilization rate of PCIe bandwidth for DMA requests by optimizing the DCB idx update mechanism, while reducing the number of MSIX interrupt requests.

[0043] The method of this invention uses a front-end and back-end communication model, running the PCIe device driver on the host and achieving data interaction by updating the contents of the DCB. The DCB can be considered as a circular buffer, including information such as idx, flag, addr, and length, with each DCB pointing to a data storage space.

[0044] During data transmission, the backend logic informs the driver that the buffer pointed to by the DCB has been updated by updating the DCB and idx. Figure 1As shown. The idx field above the DCB is used to index the next available DCB entry. If the historical idx value recorded by the software is less than the idx value updated by the backend logic, it means that the buffer already contains data to be processed. At this time, the software can retrieve the data from the buffer and release the buffer. When multiple data packets need to be transmitted, the DCB idx needs to be updated multiple times. Each DCB idx update operation will trigger a PCIe write request and also initiate an msix interrupt request.

[0045] As a preferred example, the interaction flow between the driver and the backend logic is as follows:

[0046] S1. Obtain the physical base address of the storage space where the backend DCB table entry is located (multiple queues correspond to multiple DCB table entries);

[0047] S2. Waiting for the uplink channel enable signal to become valid;

[0048] S3. Initiate a memory read to obtain DCB content and check the flag status bit;

[0049] S4. Schedule based on the FIFO status of user data;

[0050] S5. Data is split and framed, and a memory write is initiated to write the data.

[0051] S6. After all data has been written, update the DCB table entries and update idx;

[0052] S7. Initiate an msix interrupt to notify the driver side that the data transfer is complete;

[0053] S8. After copying the data, update the DCB table entries.

[0054] Frequent IDX write requests consume a lot of PCIe credits, causing a decrease in bandwidth utilization. In addition, frequent MSIX interrupts also increase CPU response time and put a burden on the CPU.

[0055] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0056] It should be noted that the order in which the embodiments of this application are presented only represents the chronological order of the embodiments and does not represent the superiority or inferiority of the technical solutions provided by the embodiments.

[0057] See Figure 3 The present application provides a schematic diagram of a method for implementing a DMA request, as shown in the embodiment. Figure 1 As shown, the method includes steps S301 to S302:

[0058] S301. Record the state machine and timeout for each queue;

[0059] S302. If no queue update event occurs, the queue is polled in a round-robin manner. If a queue update event occurs, the queue number ID is used as the address index of the queue information memory. The previously recorded status information and timeout time are read and sent to the state machine for processing. After processing, the result is written back to the memory at the address index.

[0060] In this invention, each queue maintains a state machine and a timeout period. The timeout period refers to the time at which the queue can output a timeout. For example, if the initial time is 0 and the merging time is 1us, then the timeout period is 1us, and the next timeout period is 2us.

[0061] The state maintained by each queue is as follows: Figure 2 As shown, the operation and state transition process of the state machine are as follows: steps A1 to A4:

[0062] A1. Start the timer, then enter idle state;

[0063] A2, queue a initiates, directly outputs the update request, the state machine jumps from idle to busy, and sets the next timeout time based on the current time;

[0064] A3. When queue a initiates a DCB idx update request again, it first checks whether the current time has exceeded the timeout period. If it has, it outputs the DCB idx update request and the state machine jumps back to the idle state. If it has not timed out, it suppresses the current DCB idx update request and the state machine jumps to the waiting state.

[0065] A4. Suppress all received DCB idx update requests until the timeout period is reached, then release the last received DCB idx update request and the state machine jumps to the idle state.

[0066] As an optional example, the processing fed into the state machine includes:

[0067] Initiate an update request for the descriptor table entry number DCB idx to the state machine;

[0068] The DCB idx update request is processed by the state machine.

[0069] As an optional example, such as Figure 2The state machine shown above processes the DCB idx update request in the following ways:

[0070] Start the timer, and the state machine enters the idle state;

[0071] Upon receiving a DCB idx update request, it enters a busy state, sets the timeout for the next timer based on the current time, and directly outputs the update request.

[0072] If another DCB idx update request is received and the state machine is in a busy state, first check if the current time has exceeded the timeout period. If it has, output the DCB idx update request and the state machine jumps back to the idle state; if it has not timed out, suppress the current DCB idx update request and the state machine jumps to the waiting state.

[0073] If another DCB idx update request is received and the state is in a waiting state, suppress this DCB idx update request until the timeout period is reached, release the last received DCB idx update request, and the state machine jumps to the idle state.

[0074] Preferably, polling the queue in a round-robin manner includes:

[0075] The queue is polled in a way that increments every clock cycle.

[0076] As an alternative example, in the case of multiple queues, such as Figure 4 As shown, the state machine and timeout for each queue need to be recorded. The state changes of different queues are modified through queue update events and polling. When a queue update event occurs, the queue ID is used directly as the address index of the queue info RAM to read the previously recorded state information and timeout, and then sent to the appropriate database. Figure 2 The state machine process is shown. After processing, the result is written back to the RAM at the same address. If no queue update event occurs, the queue is polled incrementally every clock cycle to complete the reading of the polled queue's historical state, state machine processing, and writing back the new state.

[0077] The DMA request implementation method of this invention can be applied to smart network cards and also to network cards based on PCIe DMA hardware acceleration. The scope encompasses both software and hardware; the software includes DMA multi-queue management, and the hardware includes circuit design for implementing DCB idx merging in chip digital circuit design.

[0078] In this invention, in a multi-queue scenario, the state machine and timeout time of each queue are recorded. The state changes of different queues are modified through queue update events and polling. Each queue runs independently using a separate state machine, thereby improving the utilization of PCIe bandwidth for DMA requests and reducing the number of MSIX interrupt requests. This method supports merging IDX update write requests in both single-queue and multi-queue scenarios, is applicable to both virtualized and non-virtualized environments, and can merge data requests of arbitrary length. It reduces the number of write requests, lowers PCIe bandwidth consumption, and improves overall performance. It also reduces the number of MSIX interrupt requests and CPU response times. Furthermore, the timeout merging time in this invention can be controlled in real-time through the management plane to meet the needs of different scenarios.

[0079] Based on the same inventive concept, such as Figure 5 As shown, embodiments of the present invention also provide an apparatus for implementing DMA requests, such as... Figure 5 As shown, the device includes:

[0080] The queue management module 501 includes multiple queues and is configured to record the state machine and timeout of each queue. If no queue update event occurs, the queue is polled in a round-robin manner. If a queue update event occurs, the queue number ID is used as the address index of the queue information memory. The previously recorded state information and timeout are read, sent to the state machine for processing, and the result is written back to the memory at the address index after processing.

[0081] State machine module 502 is configured to handle descriptor table entry number DCB idx update requests from the queue management module.

[0082] As an optional example, the process of feeding the state machine includes:

[0083] Initiate an update request for the descriptor table entry number DCB idx to the state machine;

[0084] The DCB idx update request is processed by the state machine.

[0085] As an optional example, state machine module 502 is configured to handle descriptor table entry number (DCB) idx update requests from the queue management module, including:

[0086] Start the timer, and the state machine enters the idle state;

[0087] Upon receiving a DCB idx update request, it enters a busy state, sets the timeout for the next timer based on the current time, and directly outputs the update request.

[0088] If another DCB idx update request is received and the state machine is in a busy state, first check if the current time has exceeded the timeout period. If it has, output the DCB idx update request and the state machine jumps back to the idle state; if it has not timed out, suppress the current DCB idx update request and the state machine jumps to the waiting state.

[0089] If another DCB idx update request is received and the state is in a waiting state, suppress this DCB idx update request until the timeout period is reached, release the last received DCB idx update request, and the state machine jumps to the idle state.

[0090] As an optional example, polling the queue in a round-robin manner includes:

[0091] The queue is polled in a way that increments every clock cycle.

[0092] It should be noted that the device provided in this embodiment and the method provided in the above method embodiment belong to the same inventive concept, solve the same technical problem, and achieve the same technical effect. The similarities will not be repeated.

[0093] Based on the same inventive concept, embodiments of the present invention also provide an apparatus for implementing DMA requests, such as... Figure 6 As shown, the device includes:

[0094] It includes a memory 602, a processor 601, and a user interface 603;

[0095] The memory 602 is used to store computer programs;

[0096] The user interface 603 is used to interact with the user.

[0097] The processor 601 is configured to read a computer program from the memory 602, and when the processor 601 executes the computer program, it performs the following:

[0098] Record the state machine and timeout for each queue;

[0099] If no queue update event occurs, the queue is polled in a round-robin manner. If a queue update event occurs, the queue number ID is used as the address index of the queue information memory. The previously recorded status information and timeout time are read and sent to the state machine for processing. After processing, the result is written back to the memory at the address index.

[0100] Among them, Figure 6In this context, the bus architecture can include any number of interconnected buses and bridges, specifically linking various circuits together, represented by one or more processors (processor 601) and memory (memory 602). The bus architecture can also link various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. A bus interface provides the interface. Processor 601 is responsible for managing the bus architecture and general processing, and memory 602 can store data used by processor 601 during operation.

[0101] The processor 601 can be a CPU, ASIC, FPGA or CPLD, and the processor 601 can also adopt a multi-core architecture.

[0102] When processor 601 executes a computer program stored in memory 602, it implements any of the DMA request implementation methods in Embodiment 1.

[0103] It should be noted that the device provided in Embodiment 3 and the method provided in Embodiment 1 belong to the same inventive concept, solve the same technical problem, and achieve the same technical effect. The device provided in Embodiment 3 can implement all the methods in Embodiment 1, and the similarities will not be repeated.

[0104] This application also proposes a processor-readable storage medium. This processor-readable storage medium stores a computer program, which, when executed by a processor, implements a method for implementing any DMA request in Embodiment 1.

[0105] It should be noted that the division of units in the embodiments of this application is illustrative and only represents one logical functional division. In actual implementation, other division methods may be used. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated units described above can be implemented in hardware or as software functional units.

[0106] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage and optical storage) containing computer-usable program code.

[0107] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0108] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0109] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for implementing a DMA request, characterized in that, include: Record the state machine and timeout for each queue; If no queue update event occurs, the queue will be polled in a round-robin fashion. When a queue update event occurs, the queue number ID is used as the address index of the queue information memory. The previously recorded state information and timeout time are read and sent to the state machine for processing. After processing, the result is written back to the memory at the address index. The states of the state machine include idle state, busy state, and waiting state; The process of sending data into the state machine includes: Initiate an update request for the descriptor table entry number DCB idx to the state machine; The DCB idx update request is processed by the state machine. The process of handling the DCB idx update request through the state machine includes: Start the timer, and the state machine enters the idle state; Upon receiving a DCB idx update request, it enters a busy state, sets the timeout for the next timer based on the current time, and directly outputs the update request. If another DCB idx update request is received and the state machine is in a busy state, first check if the current time has exceeded the timeout period. If it has, output the DCB idx update request and the state machine jumps back to the idle state; if it has not timed out, suppress the current DCB idx update request and the state machine jumps to the waiting state. If another DCB idx update request is received and the state is in a waiting state, suppress this DCB idx update request until the timeout period is reached, release the last received DCB idx update request, and the state machine jumps to the idle state.

2. The method according to claim 1, characterized in that, The method of polling the queue includes: The queue is polled in a way that increments every clock cycle.

3. An apparatus for implementing a DMA request, characterized in that, include: The queue management module includes multiple queues and is configured to record the state machine and timeout of each queue. If no queue update event occurs, the queue is polled in a round-robin manner. If a queue update event occurs, the queue number ID is used as the address index of the queue information memory. The previously recorded state information and timeout are read, sent to the state machine for processing, and the result is written back to the memory at the address index after processing. The state machine module is configured to handle the descriptor table entry number DCB idx update request of the queue management module; The states of the state machine include idle state, busy state, and waiting state; The process of sending data into the state machine includes: Initiate an update request for the descriptor table entry number DCB idx to the state machine; The DCB idx update request is processed by the state machine. The state machine module is configured to handle descriptor table entry number (DCB) idx update requests from the queue management module, including: Start the timer, and the state machine enters the idle state; Upon receiving a DCB idx update request, it enters a busy state, sets the timeout for the next timer based on the current time, and directly outputs the update request. If another DCB idx update request is received and the state machine is in a busy state, first check if the current time has exceeded the timeout period. If it has, output the DCB idx update request and the state machine jumps back to the idle state; if it has not timed out, suppress the current DCB idx update request and the state machine jumps to the waiting state. If another DCB idx update request is received and the state is in a waiting state, suppress this DCB idx update request until the timeout period is reached, release the last received DCB idx update request, and the state machine jumps to the idle state.

4. The apparatus according to claim 3, characterized in that, The method of polling the queue includes: The queue is polled in a way that increments every clock cycle.

5. An apparatus for implementing a DMA request, characterized in that, This includes memory, processor, and user interface; The memory is used to store computer programs; The user interface is used to interact with the user; The processor is configured to read a computer program from the memory, and when the processor executes the computer program, it implements the DMA request implementation method as described in any one of claims 1 to 2.

6. A processor-readable storage medium, characterized in that, The processor-readable storage medium stores a computer program, and when the processor executes the computer program, it implements the method for implementing a DMA request as described in any one of claims 1 to 2.

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