A power probability density statistical processing system, method, apparatus, processor, and storage medium for real-time spectrum analysis of ultra-wide bandwidth.

Abstract

This invention relates to a power probability density statistical processing system suitable for real-time spectrum analysis with ultra-wide bandwidth, comprising a digital down-conversion module, a parallel data interface FFT processing module, a numerical conversion and logarithmic operation module, a parallel data interface power occurrence probability statistics module, and a data dumping module, connected sequentially. This invention also relates to a method, apparatus, processor, and storage medium for power probability density statistical processing in real-time spectrum analysis with ultra-wide bandwidth. By employing the power probability density statistical processing system, method, apparatus, processor, and storage medium of this invention, the power occurrence probability statistics function of real-time spectrum analysis equipment with ultra-wide bandwidth is realized, processing large signal bandwidths with high real-time performance. This invention utilizes multiple parallel processing methods to reduce the pressure on software data processing, improve the thermal afterglow map rendering update rate, and enhance the UI display effect.

Description

Technical Field

[0001] This invention relates to the field of digital signal processing technology, and particularly to the fields of real-time spectrum analysis, power density probability statistics, and persistence display. Specifically, it refers to a power probability density statistical processing system, method, device, processor, and storage medium suitable for real-time spectrum analysis with ultra-wide bandwidth. Background Technology

[0002] With the evolution of wireless communication technology and the large-scale deployment of 5G communication systems, the electromagnetic operating environment of wireless communication devices has become increasingly complex. The simultaneous existence of numerous TDD communication standards and frequency hopping systems has increased the difficulty of wireless signal monitoring. Traditional spectrum analysis or monitoring equipment often employs frequency sweeping methods based on RBW filters or windowed FFT, which cannot capture real-time signals and has blind spots in the judgment of burst signals. Real-time spectrum analysis equipment, on the other hand, uses uninterrupted FFT and overlap data processing methods to ensure real-time signal acquisition and processing analysis under certain POI (Point of Interest) specifications. Currently, the maximum bandwidth of most real-time spectrum analysis equipment is below 160MHz, which is no longer sufficient for real-time signal analysis in multi-carrier aggregation and spread spectrum communication systems. Developing real-time spectrum analysis equipment with bandwidths of 500MHz and above is extremely urgent to improve POI specifications. While FPGA manufacturing processes have improved year by year, the operating clock of the device itself does not match the operating clock required for processing ultra-wide bandwidth signals in a single-phase manner. The maximum stable operating clock of the device itself is much smaller than the sampling clock of ultra-wide bandwidth signals. Therefore, ultra-wideband signal digital processing in FPGAs often adopts a multi-phase parallel approach.

[0003] Real-time spectrum analysis equipment relies on the continuous FFT processing within its logic devices to achieve real-time spectrum data acquisition. FPGAs generate massive amounts of spectrum data, typically on the order of 10GB / s. This data cannot be transmitted to a host computer in real time, and software cannot render the spectrum data in real time. Furthermore, the human eye's refresh rate is only 60Hz / s, making megahertz-level video refresh rates meaningless. To present the spectral changes of instantaneous or sudden signals, real-time spectrum analysis equipment often uses afterglow heatmaps for information display. In this heatmap, colors represent the probability of signal power occurrence; generally, warm colors indicate a high probability, and cool colors indicate a low probability. Gradual afterglow patterns represent the historical information of the signal's existence.

[0004] Determining the probability of power occurrence within a certain timeframe is a core operation of real-time spectrum analysis and the afterglow heatmap display function. As the bandwidth of wireless communication systems increases, we need to achieve high-speed data processing capabilities to adapt to this increase. However, due to the physical limitations of FPGA chips, their processing speed is difficult to meet current demands. This necessitates multi-phase parallel processing of data to enable high-speed data processing even under low-speed clock conditions. For example... Figure 1 As shown, the original high-speed data is converted into eight parallel data streams for parallel FFT processing and probability statistics. This reduces the FPGA's internal processing speed to one-eighth of the sampling clock, meeting the device's operating requirements. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a power probability density statistical processing system, method, device, processor, and storage medium that meets the requirements of large signal bandwidth, high real-time performance, and wide applicability for real-time spectrum analysis with ultra-large bandwidth.

[0006] To achieve the above objectives, the present invention provides a power probability density statistical processing system, method, apparatus, processor, and storage medium suitable for real-time spectrum analysis with ultra-wide bandwidth, as follows:

[0007] The power probability density statistical processing system applicable to real-time spectrum analysis of ultra-wide bandwidth is characterized by the following: the system includes a digital down-conversion module, a parallel data interface FFT processing module, a numerical conversion and logarithmic operation module, a parallel data interface power occurrence probability statistics module, and a data dump module, which are connected in sequence.

[0008] The digital downconversion module is used to perform parallel data conversion by setting the width ratio of the data interface; the parallel data interface FFT processing module is used to process the time domain data of the parallel interface, use the FFT algorithm and output parallel frequency domain data; the numerical conversion and logarithmic operation module is used to convert the level spectrum data into power spectrum data; the parallel data interface power occurrence probability statistics module takes parallel power spectrum data as input, uses the proportionalized numerical data as the write address value and read address value of the dual-port RAM, and uses feedback technology to refresh the power statistics value by incrementing the historical accumulated data in the next cycle; the data dump module is used to store the power statistics value for a certain period of time in the DDR memory and display the thermal afterglow map.

[0009] Preferably, the digital downconversion module consists of a FIFO data buffer with different read / write interface widths.

[0010] Preferably, the digital downconverter module includes a multiplication unit, a half-band filter unit, and a DDS unit, wherein the DDS unit is connected to two multiplication units, and the two multiplication units are connected to the half-band filter unit.

[0011] Preferably, the numerical conversion and logarithmic operation module includes an integer-to-floating-point unit, a logarithmic calculation unit, and a floating-point-to-integer unit, which are connected in sequence. The input terminal of the integer-to-floating-point unit is connected to the parallel data interface FFT processing module, and the floating-point-to-integer unit is connected to the parallel data interface power occurrence probability statistics module.

[0012] Preferably, the parallel data interface power occurrence probability statistics module includes a control state machine and a dual-port RAM, wherein the control state machine is connected to the dual-port RAM.

[0013] Preferably, the FFT algorithm uses a pipeline-based approach and employs a Delay Feedback pattern.

[0014] The power probability density statistical processing method for real-time spectrum analysis of ultra-wide bandwidth using the above system is characterized by the following steps:

[0015] (1) Use complex multiplication to obtain I / Q data, and use a half-band filter to perform a 2x decimation to reduce the data clock speed;

[0016] (2) Input the 4 parallel time-domain complex data into the parallel data interface FFT processing module for time-frequency conversion to obtain 4 parallel frequency domain data. The parallel data interface FFT processing module outputs the level spectrum data.

[0017] (3) Convert the level spectrum data output by the parallel data interface FFT processing module from integer to floating point and input it to the numerical conversion and logarithmic operation module;

[0018] (4) When the probability statistics begin, the parallel data interface power occurrence probability statistics module confirms the counting duration, stores the current counting frequency information, and passes the spliced ​​complete address value to the dual-port RAM as the write address and read address.

[0019] Preferably, step (4) specifically includes the following steps:

[0020] (4.1) When the probability statistics begin, the parallel data interface power generation probability statistics module confirms the counting duration, i.e. the number of FFT frames, as a comparison parameter for the internal running counter.

[0021] (4.2) When the count value of the running counter is less than the number of FFT frames, the module is in running state, and the register stores the current counting frequency information;

[0022] (4.3) The parallel data interface power generation probability statistics module transmits the concatenated complete address value to the dual-port RAM as the write address and read address. The read data value is incremented by 1 and rewritten to the address in the next clk, realizing the value update operation of a specific address space.

[0023] Preferably, the result input to the numerical conversion and logarithmic operation module in step (3) is a floating-point number, and step (3) also includes a process of converting the floating-point number into an integer number.

[0024] The power probability density statistical processing device for real-time spectrum analysis of ultra-wide bandwidth is characterized in that the device comprises:

[0025] A processor is configured to execute computer-executable instructions;

[0026] The memory stores one or more computer-executable instructions, which, when executed by the processor, implement the steps of the power probability density statistical processing method described above for real-time spectrum analysis of ultra-wide bandwidth.

[0027] The processor used to implement power probability density statistical processing for real-time spectrum analysis of ultra-wide bandwidth is characterized in that the processor is configured to execute computer-executable instructions, which, when executed by the processor, implement the various steps of the above-described method for implementing power probability density statistical processing for real-time spectrum analysis of ultra-wide bandwidth.

[0028] The computer-readable storage medium is characterized in that it stores a computer program that can be executed by a processor to implement the various steps of the power probability density statistical processing method for real-time spectrum analysis of ultra-wide bandwidth described above.

[0029] This invention employs a power probability density statistical processing system, method, apparatus, processor, and storage medium suitable for real-time spectrum analysis with ultra-wide bandwidth. It realizes the power occurrence probability statistical function of real-time spectrum analysis equipment with ultra-wide bandwidth, processing large signal bandwidth and achieving high real-time performance. This invention utilizes multiple parallel processing methods to achieve real-time processing of large bandwidth, high-speed data within an FPGA, reducing the pressure on software data processing, improving the thermal afterglow map rendering update rate, and enhancing the UI display effect. Attached Figure Description

[0030] Figure 1This is a basic structural block diagram of the power probability density statistical processing system for real-time spectrum analysis of ultra-wide bandwidth according to the present invention.

[0031] Figure 2 This is a schematic diagram of the basic structure of the digital downconversion module of the power probability density statistical processing system for real-time spectrum analysis of ultra-wide bandwidth according to the present invention.

[0032] Figure 3 This is a schematic diagram of the basic structure of the parallel data interface FFT processing module of the power probability density statistical processing system for real-time spectrum analysis of ultra-large bandwidth according to the present invention.

[0033] Figure 4 This is a schematic diagram of the basic structure of the numerical conversion and logarithmic operation module of the power probability density statistical processing system applicable to real-time spectrum analysis of ultra-wide bandwidth according to the present invention.

[0034] Figure 5 This is a schematic diagram of the basic structure of the parallel data interface power occurrence probability statistics module of the power probability density statistical processing system for real-time spectrum analysis of ultra-large bandwidth according to the present invention.

[0035] Figure 6 This is a schematic diagram of the time axis of specific frequency power probability of N FFT frames in the power probability density statistical processing system applicable to real-time spectrum analysis of ultra-wide bandwidth according to the present invention.

[0036] Figure 7 This diagram illustrates the storage location of statistical values ​​for the number of occurrences of different power values ​​at different frequencies in the power probability density statistical processing system applicable to real-time spectrum analysis of ultra-wide bandwidth according to the present invention. Detailed Implementation

[0037] To more clearly describe the technical content of the present invention, the following description is provided in conjunction with specific embodiments.

[0038] The present invention provides a power probability density statistical processing system for real-time spectrum analysis of ultra-wide bandwidth, comprising a digital downconversion module, a parallel data interface FFT processing module, a numerical conversion and logarithmic operation module, a parallel data interface power occurrence probability statistics module, and a data dumping module, wherein the digital downconversion module, the parallel data interface FFT processing module, the numerical conversion and logarithmic operation module, the parallel data interface power occurrence probability statistics module, and the data dumping module are connected in sequence.

[0039] The digital downconversion module is used to perform parallel data conversion by setting the width ratio of the data interface; the parallel data interface FFT processing module is used to process the time domain data of the parallel interface, use the FFT algorithm and output parallel frequency domain data; the numerical conversion and logarithmic operation module is used to convert the level spectrum data into power spectrum data; the parallel data interface power occurrence probability statistics module takes parallel power spectrum data as input, uses the proportionalized numerical data as the write address value and read address value of the dual-port RAM, and uses feedback technology to refresh the power statistics value by incrementing the historical accumulated data in the next cycle; the data dump module is used to store the power statistics value for a certain period of time in the DDR memory and display the thermal afterglow map.

[0040] In a preferred embodiment of the present invention, the digital downconversion module is composed of a FIFO data buffer with different read / write interface widths.

[0041] In a preferred embodiment of the present invention, the digital downconversion module includes a multiplication unit, a half-band filter unit, and a DDS unit. The DDS unit is connected to two multiplication units, and the two multiplication units are connected to the half-band filter unit.

[0042] In a preferred embodiment of the present invention, the numerical conversion and logarithmic operation module includes an integer-to-floating-point unit, a logarithmic calculation unit, and a floating-point-to-integer unit, which are connected in sequence. The input terminal of the integer-to-floating-point unit is connected to the parallel data interface FFT processing module, and the floating-point-to-integer unit is connected to the parallel data interface power occurrence probability statistics module.

[0043] In a preferred embodiment of the present invention, the parallel data interface power generation probability statistics module includes a control state machine and a dual-port RAM, wherein the control state machine is connected to the dual-port RAM.

[0044] In a preferred embodiment of the present invention, the FFT algorithm is pipeline-based and employs a DelayFeedback pattern.

[0045] The present invention provides a power probability density statistical processing method for real-time spectrum analysis of ultra-wide bandwidth using the aforementioned system, wherein the method includes the following steps:

[0046] (1) Use complex multiplication to obtain I / Q data, and use a half-band filter to perform a 2x decimation to reduce the data clock speed;

[0047] (2) Input the 4 parallel time-domain complex data into the parallel data interface FFT processing module for time-frequency conversion to obtain 4 parallel frequency domain data. The parallel data interface FFT processing module outputs the level spectrum data.

[0048] (3) Convert the level spectrum data output by the parallel data interface FFT processing module from integer to floating point and input it to the numerical conversion and logarithmic operation module;

[0049] (4) When the probability statistics begin, the parallel data interface power occurrence probability statistics module confirms the counting duration, stores the current counting frequency information, and passes the spliced ​​complete address value to the dual-port RAM as the write address and read address.

[0050] In a preferred embodiment of the present invention, step (4) specifically includes the following steps:

[0051] (4.1) When the probability statistics begin, the parallel data interface power generation probability statistics module confirms the counting duration, i.e. the number of FFT frames, as a comparison parameter for the internal running counter.

[0052] (4.2) When the count value of the running counter is less than the number of FFT frames, the module is in running state, and the register stores the current counting frequency information;

[0053] (4.3) The parallel data interface power generation probability statistics module transmits the concatenated complete address value to the dual-port RAM as the write address and read address. The read data value is incremented by 1 and rewritten to the address in the next clk, realizing the value update operation of a specific address space.

[0054] In a preferred embodiment of the present invention, the result input to the numerical conversion and logarithmic operation module in step (3) is a floating-point number, and step (3) also includes a process of converting the floating-point number into an integer number.

[0055] The present invention provides a power probability density statistical processing apparatus for performing real-time spectrum analysis of ultra-wide bandwidth, wherein the apparatus comprises:

[0056] A processor is configured to execute computer-executable instructions;

[0057] The memory stores one or more computer-executable instructions, which, when executed by the processor, implement the steps of the power probability density statistical processing method described above for real-time spectrum analysis of ultra-wide bandwidth.

[0058] The present invention provides a processor for implementing power probability density statistical processing for real-time spectrum analysis of ultra-wide bandwidth, wherein the processor is configured to execute computer-executable instructions, which, when executed by the processor, implement the various steps of the above-described method for implementing power probability density statistical processing for real-time spectrum analysis of ultra-wide bandwidth.

[0059] The computer-readable storage medium of the present invention stores a computer program that can be executed by a processor to implement the various steps of the power probability density statistical processing method for real-time spectrum analysis of ultra-wide bandwidth described above.

[0060] In a specific embodiment of the present invention, an FFT processing module with a parallel data interface is implemented to achieve ultra-high bandwidth processing capabilities. High-speed data processing is implemented based on an FPGA, employing power probability statistics technology with a parallel data interface based on a dual-port random access memory.

[0061] Figure 1 The basic structural block diagram of this invention consists of a digital downconversion module (DDC), a parallel data interface FFT processing module (FFT), a numerical conversion and logarithmic operation module (LOG), a parallel data interface power generation probability statistics module (HISTOGRAM), and a data dump module (DDR4), ultimately realizing the function of ultra-wide bandwidth power generation frequency statistics.

[0062] Figure 2 The basic structure of the digital downconverter module consists of a multiplication unit and a half-band filter unit. Figure 3 The basic structure of the parallel data interface FFT processing module (using a 16-point FFT example) is implemented using an FFT algorithm with a Multiple-Path DelayFeedback pattern. Figure 4 The basic structure of the numerical conversion and logarithmic operation module consists of units such as integer to floating-point conversion, logarithmic calculation, and floating-point to integer conversion, realizing the conversion of level spectrum data to power spectrum data. Figure 5 The basic structure of the parallel data interface power occurrence probability statistics module consists of a read / write state machine and a dual-port RAM, which realizes the statistics of the number of power occurrences within a certain period of time. Figure 6 The schematic diagram of the power probability timeline for a specific frequency across N FFT frames clearly shows the order of continuous FFT spectral data on the timeline. Figure 7 The diagram illustrates the storage location of statistical values ​​for the number of occurrences of different power values ​​at different frequencies, clearly showing the format and location of the statistical values ​​required for the two-dimensional dot matrix.

[0063] This invention provides a real-time spectrum analysis device for multi-channel parallel data FFT processing, based on a dual-port memory statistical power occurrence probability technique. Its structure is as follows: Figure 2 As shown, it mainly consists of five parts: a digital downconversion module, a parallel data interface FFT processing module, a numerical conversion and logarithmic operation module, a parallel data interface power generation probability statistics module, and a data dumping module.

[0064] The digital downconversion module consists of a FIFO with different read and write interface widths. By setting the ratio of the data interface width, parallel data conversion is achieved to reduce the data clock speed and meet the clock conditions for stable FPGA operation.

[0065] The parallel data interface FFT processing module operates at low clock speeds, processes time-domain data from the parallel interface, and uses a pipelined FFT algorithm with a delay feedback mode to output parallel frequency-domain data.

[0066] The numerical conversion and logarithmic operation module converts the level spectrum data into power spectrum data.

[0067] The core component of this invention is a parallel data interface power occurrence probability statistics module. This component takes in parallel power spectrum data, scales the numerical data and uses it as the write address value and read address value of the dual-port RAM. Using feedback technology, the power statistics value is refreshed in the next cycle by incrementing the historical cumulative data.

[0068] The data dumping module stores power statistics over a certain period of time in a DDR memory, which is easily accessible to the host computer software to display the thermal afterglow map.

[0069] This invention provides a statistical method for the probability of spectral power occurrence, enabling parallel processing of ultra-wide bandwidth, high-speed data. First, the high-speed data stream is digitally down-converted and decimated to reduce the data processing rate, ensuring feasibility on an FPGA. The description in this invention assumes operating conditions of a single-channel ADC sampling clock of 1.2288 GHz, a JESD204B data interface clock of 307.2 MHz, a sampling data bit width of 16 bits, and an interface data bit width of 64 bits, i.e., single-clock, four-channel parallel sampling data output.

[0070] First, I / Q data is obtained using complex multiplication, and then decimation is performed by 2x using a half-band filter, reducing the data clock from 307.2MHz to 153.6MHz. This helps reduce FPGA timing violations and lowers operating power consumption.

[0071] Subsequently, four parallel time-domain complex data streams at a rate of 153.6MHz are input to the parallel data interface FFT processing module for time-frequency conversion, resulting in four parallel frequency-domain data streams. The parallel data interface FFT processing module employs a multipath delay feedback (MDF) and pipelined design to meet the requirements for real-time parallel data processing.

[0072] The parallel data interface FFT processing module outputs level spectrum data in fixed-point format. In real-time spectrum analysis equipment, the thermal afterglow map is a two-dimensional grid map. The horizontal axis of each grid point represents frequency, the vertical axis represents power, and the color information represents the probability of that point's occurrence. The grid map uses linear division, with the vertical axis unit being power, and has a logarithmic relationship with the signal level. The calculation formula is:

[0073] P = 20 * log 10 (V)-offset;

[0074] Where P is the signal power, measured in dBm; and V is the signal level, measured in volts.

[0075] The level spectrum data output by the parallel data interface FFT processing module is converted from an integer to a floating-point number, and then input to the logarithmic calculation unit. The result is a floating-point number, and finally the floating-point number is converted back to an integer number, assuming it is expressed as an unsigned 16-bit number.

[0076] Assume we count N FFT frames. The FFT length is predefined as 1024(2πf / ... 10 The number of power quantizations is 256 (2). 9 The dot matrix is ​​1024×256 pixels, with a total of 262,144 positions. The probability value of occurrence at each position is stored in a dual-port RAM, addressed linearly. The power value is multiplied by a scaling factor A to ensure a reasonable dynamic range, and the data is truncated to an unsigned 9-bit word length, which is used as the low-order address value. The dual-port RAM is 262,144 pixels in size, with a data interface width of 32 bits and a storage space of 1 MB. The high 10 bits of the address are used for frequency point addressing. For example, the address range 0b0000000000_000000000 to 0b0000000000_111111111 stores the number of times different power occurs at frequency point F[0]; the address range 0b0000000001_000000000 to 0b0000000001_111111111 stores the number of times different power occurs at frequency point F[1].

[0077] When a probability statistics operation begins, the histogram module first determines the counting duration, i.e., the number of FFT frames (FFT_FRAME_NUM), which serves as a comparison parameter for the internal run counter (RUN_COUNTER). When the run counter value is less than FFT_FRAME_NUM, the module is in running state. An internal register named FREQ_INDEX stores the current counting frequency (e.g., F[k]), and this value is used as the high 10 bits of the address. The histogram state machine passes the concatenated address value to the dual-port RAM as the write and read addresses. The read data value is incremented by 1 and rewritten to that address in the next clock cycle, thus implementing value updates for a specific address space. The core of the algorithm lies in the organization of the addressing mode and the feedback-based data update operation. Using dual-port RAM for probability statistics avoids the use of a massive number of comparators, making it an efficient and resource-saving implementation.

[0078] The counter value of the dual-port RAM is updated to the DDR in real time, and the software reads the statistical value synchronously to realize the rendering of the thermal afterglow map.

[0079] Figure 1 The basic structural block diagram of this invention consists of a digital downconversion module (DDC), a parallel data interface FFT processing module (FFT), a numerical conversion and logarithmic operation module (LOG), a parallel data interface power generation probability statistics module (HISTOGRAM), and a data dump module (DDR4), ultimately realizing the function of ultra-wide bandwidth power generation frequency statistics. Figure 2 The basic structure of the digital downconverter module consists of a multiplication unit and a half-band filter unit. Figure 3 The basic structure of the parallel data interface FFT processing module (using a 16-point FFT example) is implemented using an FFT algorithm with a Multiple-Path Delay Feedback pattern. Figure 4 The basic structure of the numerical conversion and logarithmic operation module consists of units such as integer to floating-point conversion, logarithmic calculation, and floating-point to integer conversion, realizing the conversion of level spectrum data to power spectrum data. Figure 5 The basic structure of the parallel data interface power occurrence probability statistics module consists of a read / write state machine and a dual-port RAM, which realizes the statistics of the number of power occurrences within a certain period of time. Figure 6 The schematic diagram of the power probability timeline for a specific frequency across N FFT frames clearly shows the order of continuous FFT spectral data on the timeline. Figure 7 The diagram illustrates the storage location of statistical values ​​for the number of occurrences of different power values ​​at different frequencies, clearly showing the format and location of the statistical values ​​required for the two-dimensional dot matrix. Figure 7The number represents the probability, expressed in different thermal chromaticities. The higher the value, the warmer the chromaticity, and the lower the value, the colder the chromaticity.

[0080] For the specific implementation scheme of this embodiment, please refer to the relevant descriptions in the above embodiments, which will not be repeated here.

[0081] It is understood that the same or similar parts in the above embodiments can be referred to each other, and the contents not described in detail in some embodiments can be referred to the same or similar contents in other embodiments.

[0082] It should be noted that in the description of this invention, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means at least two.

[0083] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of the invention pertain.

[0084] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution device. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0085] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The corresponding program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0086] Furthermore, the functional units in the various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0087] The storage media mentioned above can be read-only memory, disk, or optical disk, etc.

[0088] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0089] This invention employs a power probability density statistical processing system, method, apparatus, processor, and storage medium suitable for real-time spectrum analysis with ultra-wide bandwidth. It realizes the power occurrence probability statistical function of real-time spectrum analysis equipment with ultra-wide bandwidth, processing large signal bandwidth and achieving high real-time performance. This invention utilizes multiple parallel processing methods to achieve real-time processing of large bandwidth, high-speed data within an FPGA, reducing the pressure on software data processing, improving the thermal afterglow map rendering update rate, and enhancing the UI display effect.

[0090] In this specification, the invention has been described with reference to specific embodiments thereof. However, it will be apparent that various modifications and variations can be made without departing from the spirit and scope of the invention. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

Claims

1. A power probability density statistical processing system suitable for real-time spectrum analysis with ultra-wide bandwidth, characterized in that, The system includes a digital downconversion module, a parallel data interface FFT processing module, a numerical conversion and logarithmic operation module, a parallel data interface power generation probability statistics module, and a data dump module, which are connected in sequence. The digital downconversion module is used to perform parallel data conversion by setting the width ratio of the data interface; the parallel data interface FFT processing module is used to process the time domain data of the parallel interface, use the FFT algorithm and output parallel frequency domain data; the numerical conversion and logarithmic operation module is used to convert the level spectrum data into power spectrum data; the parallel data interface power occurrence probability statistics module takes parallel power spectrum data as input, uses the proportionalized numerical data as the write address value and read address value of the dual-port RAM, and uses feedback technology to refresh the power statistics value by incrementing the historical accumulated data in the next cycle; the data dump module is used to store the power statistics value for a certain period of time in the DDR memory and display the thermal afterglow map.

2. The power probability density statistical processing system for real-time spectrum analysis with ultra-wide bandwidth according to claim 1, characterized in that, The digital downconversion module consists of a FIFO data buffer with different read / write interface widths.

3. The power probability density statistical processing system for real-time spectrum analysis with ultra-wide bandwidth according to claim 1, characterized in that, The digital downconverter module includes a multiplication unit, a half-band filter unit, and a DDS unit. The DDS unit is connected to two multiplication units, and the two multiplication units are connected to the half-band filter unit.

4. The power probability density statistical processing system for real-time spectrum analysis with ultra-wide bandwidth according to claim 1, characterized in that, The numerical conversion and logarithmic operation module includes an integer-to-floating-point unit, a logarithmic calculation unit, and a floating-point-to-integer unit, which are connected in sequence. The input terminal of the integer-to-floating-point unit is connected to the parallel data interface FFT processing module, and the floating-point-to-integer unit is connected to the parallel data interface power occurrence probability statistics module.

5. The power probability density statistical processing system for real-time spectrum analysis with ultra-wide bandwidth according to claim 1, characterized in that, The parallel data interface power generation probability statistics module includes a control state machine and a dual-port RAM, wherein the control state machine is connected to the dual-port RAM.

6. The power probability density statistical processing system for real-time spectrum analysis with ultra-wide bandwidth according to claim 1, characterized in that, The FFT algorithm described uses a pipeline-based approach and employs a Delay Feedback pattern.

7. A power probability density statistical processing method for real-time spectrum analysis of ultra-wide bandwidth based on the system described in claim 1, characterized in that, The method includes the following steps: (1) Use complex multiplication to obtain I / Q data, and use a half-band filter to perform a 2x decimation to reduce the data clock speed; (2) Input the 4 parallel time-domain complex data into the parallel data interface FFT processing module for time-frequency conversion to obtain 4 parallel frequency domain data. The parallel data interface FFT processing module outputs the level spectrum data. (3) Convert the level spectrum data output by the parallel data interface FFT processing module from integer to floating point and input it to the numerical conversion and logarithmic operation module; (4) When the probability statistics begin, the parallel data interface power occurrence probability statistics module confirms the counting duration, stores the current counting frequency information, and passes the spliced ​​complete address value to the dual-port RAM as the write address and read address.

8. The power probability density statistical processing method for real-time spectrum analysis of ultra-wide bandwidth according to claim 7, characterized in that, Step (4) specifically includes the following steps: (4.1) When the probability statistics begin, the parallel data interface power generation probability statistics module confirms the counting duration, i.e. the number of FFT frames, as a comparison parameter for the internal running counter. (4.2) When the count value of the running counter is less than the number of FFT frames, the module is in running state, and the register stores the current counting frequency information; (4.3) The parallel data interface power generation probability statistics module transmits the concatenated complete address value to the dual-port RAM as the write address and read address. The read data value is incremented by 1 and rewritten to the address in the next clk, realizing the value update operation of a specific address space.

9. The power probability density statistical processing method for real-time spectrum analysis of ultra-wide bandwidth according to claim 1, characterized in that, The result input to the numerical conversion and logarithmic operation module in step (3) is a floating-point number. Step (3) also includes the process of converting the floating-point number into an integer number.

10. A power probability density statistical processing device for implementing real-time spectrum analysis of ultra-wide bandwidth, characterized in that, The device includes: A processor is configured to execute computer-executable instructions; The memory stores one or more computer-executable instructions, which, when executed by the processor, implement the steps of the power probability density statistical processing method for real-time spectrum analysis of ultra-wide bandwidth as described in any one of claims 7 to 9.

11. A processor for implementing power probability density statistical processing for real-time spectrum analysis of ultra-wide bandwidth, characterized in that, The processor is configured to execute computer-executable instructions, which, when executed by the processor, implement the steps of the power probability density statistical processing method for real-time spectrum analysis of ultra-wide bandwidth as described in any one of claims 7 to 9.

12. A computer-readable storage medium, characterized in that, It stores a computer program that can be executed by a processor to implement the steps of the power probability density statistical processing method for real-time spectrum analysis of ultra-wide bandwidth as described in any one of claims 7 to 9.

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