Display device and driving method thereof

Abstract

The application discloses a display device and a driving method thereof. The display device comprises a display panel comprising a plurality of rows of pixel circuits, each pixel circuit comprising a light emitting control transistor and a driving transistor, the light emitting control transistor being configured to control a light emitting element to enter a light emitting stage, and the driving transistor being configured to provide a driving current for the light emitting element; a driving process of the display panel comprises a first stage and a display stage, and the first stage is at least one of before and after the display stage; in the first stage, at least one of the light emitting control transistor and the driving transistor in each row of pixel circuits is turned off; a time length of the first stage is t, a data refresh frequency of the pixel circuit in the display stage is f, and t<=1 / f. According to the embodiment of the application, the time required for power-on and / or power-off can be shortened, and the user experience can be improved.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display device and its driving method. Background Technology

[0002] With the continuous development of display technology, users have increasingly higher requirements for the performance of display devices in all aspects.

[0003] The use of display devices involves a power-on and power-off process, which currently takes a long time and affects the user experience. Summary of the Invention

[0004] This application provides a display device and its driving method, which can control the power-on and / or power-off process within one refresh frame, thereby shortening the time required for power-on and / or power-off and improving the user experience.

[0005] In a first aspect, embodiments of this application provide a display device, comprising: a display panel including multiple rows of pixel circuits, each pixel circuit including a light-emitting control transistor and a driving transistor, the light-emitting control transistor controlling a light-emitting element to enter a light-emitting stage, and the driving transistor providing a driving current to the light-emitting element; the driving process of the display panel includes a first stage and a display stage, with at least one of the two stages before and after the display stage; in the first stage, at least one of the light-emitting control transistors and driving transistors in each row of pixel circuits is turned off; the duration of the first stage is t, and the data refresh frequency of the pixel circuit in the display stage is f, where t≤1 / f.

[0006] Based on the same inventive concept, in a second aspect, embodiments of this application also provide a driving method for a display device. The display device includes: a display panel, including multiple rows of pixel circuits, the pixel circuits including light-emitting control transistors and driving transistors, the light-emitting control transistors being used to control light-emitting elements to enter a light-emitting stage, and the driving transistors being used to provide driving current to the light-emitting elements; the driving process of the display panel includes a first stage and a display stage, with at least one of the first stage before and after the display stage.

[0007] The driving methods include:

[0008] In the first stage, at least one of the light-emitting control transistor and the driving transistor in each row of pixel circuits is turned off;

[0009] The duration of the first stage is t, and the data refresh frequency of the pixel circuit during the display stage is f, where t≤1 / f.

[0010] In this embodiment, by controlling the duration of the power-on and power-off phases to within one refresh frame, the power-on and power-off time is shortened, enabling fast power-on and power-off and improving the user experience. Furthermore, with the light-emitting control transistors and driving transistors of each row of pixel circuits turned off in the first phase, a double safety net is provided to prevent the light-emitting elements from emitting light, thus helping to avoid screen flickering during the power-on and power-off phases. Attached Figure Description

[0011] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0012] Figure 1 This illustration shows a top view of a display device provided in an embodiment of this application.

[0013] Figure 2 This illustration shows a schematic diagram of a pixel circuit in a display panel provided in an embodiment of this application;

[0014] Figure 3 This illustration shows a schematic diagram of a circuit structure of a first transmission shift circuit in a display panel provided in an embodiment of this application;

[0015] Figure 4 This illustration shows a timing diagram of a display device provided in an embodiment of this application;

[0016] Figure 5 This diagram illustrates a connection structure of the first scanning shift circuit in a display panel provided in an embodiment of this application.

[0017] Figure 6 This illustration shows a schematic diagram of a circuit structure of the first A-scan shift circuit in a display panel provided in an embodiment of this application;

[0018] Figure 7 Show Figure 6 A timing diagram;

[0019] Figure 8 This diagram illustrates a connection structure of the second scanning shift circuit in a display panel provided in an embodiment of this application.

[0020] Figure 9 This illustration shows a schematic diagram of a second B-scan shift circuit in a display panel provided in an embodiment of this application.

[0021] Figure 10 This illustration shows another circuit structure diagram of the pixel circuit in the display panel provided in the embodiments of this application;

[0022] Figure 11 This invention provides another timing diagram of a display device according to an embodiment of the present application.

[0023] Figure 12 This illustration shows a schematic diagram of a connection structure of the third scanning shift circuit in a display panel provided in an embodiment of this application;

[0024] Figure 13 This invention provides a schematic diagram of a circuit structure for a third scanning shift circuit in a display panel according to an embodiment of the present application.

[0025] Figure 14 This illustration shows a schematic diagram of a pixel circuit in a display panel provided in an embodiment of this application;

[0026] Figure 15 This invention provides another timing diagram of a display device according to an embodiment of the present application.

[0027] Figure 16 This invention provides another timing diagram of a display device according to an embodiment of the present application.

[0028] Figure 17 This illustration shows a schematic diagram of a connection structure of the fourth scanning shift circuit in a display panel provided in an embodiment of this application;

[0029] Figure 18 This illustration shows a schematic diagram of a fourth scanning shift circuit in a display panel provided in an embodiment of this application.

[0030] Figure 19 This illustration shows a flowchart of a driving method for a display device provided in an embodiment of this application.

[0031] Explanation of some figure labels:

[0032] 100. Display panel; 200. Display driver chip;

[0033] 20. Pixel circuit; 30. Light-emitting element;

[0034] 40. Transmit shift circuit; 41. First transmit shift circuit;

[0035] EMIT, light emission control signal line;

[0036] STV_E, Transmit Start Signal Line;

[0037] RST_E, the first control signal line;

[0038] 50. Scanning shift circuit;

[0039] 51. First scan shift circuit; 51a. First A scan shift circuit;

[0040] SP*, First Scan Line; STV*, First Scan A Start Signal Line; RST*, Second Scan A Control Signal Line

[0041] 52. Second scan shift circuit; 52b. Second scan shift circuit;

[0042] S2N, second scan line; STV_S2N, second scan start signal line; RST_S2N, second scan control signal line;

[0043] 53. Third scan shift circuit; 53c. Third scan shift circuit (C);

[0044] S1N, third scan line; STV_S1N, third scan start signal line; RST_S1N, third scan control signal line;

[0045] 54. Fourth scan shift circuit; 54d. Fourth scan shift circuit;

[0046] SP, fourth scan line; STV_SP, fourth scan start signal line; RST_SP, fourth scan control signal line;

[0047] DVH, bias signal line; DATA, data line;

[0048] VREF1 is the reset signal line; VREF2 is the initialization signal line. Detailed Implementation

[0049] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0050] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0051] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0052] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0053] In the embodiments of this application, the term "electrical connection" can refer to a direct electrical connection between two components, or an electrical connection between two components via one or more other components. The term "drive" can refer to "control" or "operation." The term "part" can refer to "section." The term "pattern" can refer to "component." The term "end" can refer to "end segment" or "end edge." The display panel can be a display device or a module / part of a display device.

[0054] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0055] This application provides a display device and its driving method. The following description, in conjunction with the accompanying drawings, will illustrate various embodiments of the display device and its driving method.

[0056] like Figure 1 As shown, the display device includes a display panel 100, which includes multiple rows of pixel circuits 20 for driving light-emitting elements 30.

[0057] like Figure 1 As shown, multiple pixel circuits 20 can be arranged in an array along the first direction X and the second direction Y, and multiple light-emitting elements 30 can also be arranged in an array along the first direction X and the second direction Y. The first direction X and the second direction Y intersect. For example, the first direction X can be a row direction, and the second direction Y can be a column direction.

[0058] Pixel circuit 20 is electrically connected to light-emitting element 30, and pixel circuit 20 can be used to drive light-emitting element 30 to emit light. Light-emitting element 30 may include organic light-emitting diode (OLED). In addition, pixel circuit 20 is electrically connected to data line DATA.

[0059] As an example, such as Figure 2 As shown, the pixel circuit 20 may include a driving transistor M3 and light-emitting control transistors M1 and M6. The driving transistor M3 can be used to generate a driving current to drive the light-emitting element 30 to emit light, and the magnitude of the driving current affects the brightness of the light-emitting element 30. The light-emitting control transistors M1 and M6 can be used to control the light-emitting element 30 to enter the light-emitting stage. For example, when the light-emitting control transistors M1 and M6 are turned on, the driving current generated by the driving transistor M3 is transmitted to the light-emitting element 30, and the light-emitting element 30 emits light.

[0060] For example, the pixel circuit 20 may also include a data writing transistor M2, a threshold compensation transistor M5, a reset transistor M4, and an initialization transistor M7.

[0061] The gates of the light-emitting control transistors M1 and M6 are electrically connected to the light-emitting control signal line EMIT. At least some of the different transistors among the data writing transistor M2, threshold compensation transistor M5, reset transistor M4, and initialization transistor M7 have their gates connected to different scan lines.

[0062] The driving process of the display panel may include a first stage and a display stage, wherein the first stage is located before and / or after the display stage. The display stage may include at least one display frame. The first stage located before the display stage may be referred to as the power-on stage, and the first stage located after the display stage may be referred to as the power-off stage.

[0063] In the first stage, the light-emitting control transistors M1 and M6 in each row pixel circuit 20 are turned off, and / or, the driving transistor M3 in each row pixel circuit 20 is turned off. It is understood that when the light-emitting control transistors M1 and M6 in each row pixel circuit 20 are turned off, the light-emitting element 30 driven by each row pixel circuit 20 does not emit light; similarly, when the driving transistor M3 in each row pixel circuit 20 is turned off, the light-emitting element 30 driven by each row pixel circuit 20 also does not emit light.

[0064] The duration of the first stage is t, and the data refresh frequency of the pixel circuit 20 during the display stage is f, where t ≤ 1 / f. The data refresh frequency refers to the frequency at which the data signal is effectively written to the gate of the driving transistor. 1 / f can be the duration of one refresh frame, which can be understood as a display frame.

[0065] In this embodiment, by controlling the duration of the power-on and power-off phases to within one refresh frame, the power-on and power-off time is shortened, enabling fast power-on and power-off and improving the user experience. Furthermore, with the light-emitting control transistors and driving transistors of each row of pixel circuits turned off in the first phase, a double safety net is provided to prevent the light-emitting elements from emitting light, thus helping to avoid screen flickering during the power-on and power-off phases.

[0066] In some alternative implementations, the display device can display in segments with varying refresh rates, and the pixel circuitry has multiple data refresh rates during the display phase. For example, one display area may have a data refresh rate of 60 Hz, while another display area may have a data refresh rate of 90 Hz. f is the maximum value among the multiple data refresh rates. The larger f is, the smaller 1 / f becomes, thus reducing the duration t of the first phase and further shortening the time required for power-on and power-off.

[0067] In some alternative implementations, please refer to the references. Figure 1 and Figure 2 The display panel 100 also includes multiple cascaded emitter shifting circuits 40. Each emitter shifting circuit 40 is electrically connected to the gates of light-emitting control transistors M1 and M6 via an emitter control signal line EMIT. Each emitter shifting circuit 40 includes a first emitter shifting circuit 41, which is electrically connected to an emitter start signal line STV_E. The emitter start signal line STV_E is electrically connected to the display driver chip 200. The display driver chip 200 can provide a start signal to the emitter shifting circuit 40 via the emitter start signal line STV_E to trigger the emitter shifting circuit 40.

[0068] like Figure 3As shown, the first emitter shift circuit 41 includes a first input transistor T9, a first set transistor T7, and a first output transistor T2. The first input transistor T9 is electrically connected between the emitter start signal line STV_E and the gate of the first output transistor T2. The first terminal of the first output transistor T2 is electrically connected to the first potential signal line VGL, and the second terminal of the first output transistor T2 is electrically connected to the light emission control signal line EMIT. It can be understood that the second terminal of the first output transistor T2 is connected to the output terminal of the first emitter shift circuit 41.

[0069] The gate of the first set transistor T7 is electrically connected to the first control signal line RST_E, the first terminal of the first set transistor T7 is electrically connected to the second potential signal line VGH, and the second terminal of the first set transistor T7 is electrically connected to the gate of the first output transistor T2 (including direct and indirect electrical connections).

[0070] The first potential signal line VGL is used to provide the enable voltage for the light-emitting control transistors M1 and M6, and the second potential signal line VGH is used to provide the disable voltage for the light-emitting control transistors M1 and M6. For example, if the light-emitting control transistors M1 and M6 are P-type transistors, their enable voltage is a low voltage vgl, and their disable voltage is a high voltage vgh.

[0071] The circuit structure of each transmit shift circuit 40 can be as follows: Figure 3 As shown, the output signal of the previous stage transmit shift circuit 40 can be used as the start signal of the next stage transmit shift circuit 40. A trace can be connected between the output terminal of the previous stage transmit shift circuit 40 and the next stage transmit shift circuit 40. This trace serves as the transmit start signal line electrically connected to the first input transistor T9 in the next stage transmit shift circuit 40.

[0072] like Figure 4 As shown, in the first stage, the display driver chip 200 can provide the first output transistor T2 with an enable voltage (e.g., high voltage vgh) to the transmit start signal line STV_E to which it is connected, and provide the first set transistor T7 with an enable voltage (e.g., low voltage vgl) to the first control signal line RST_E.

[0073] In the first stage, since the first control signal line RST_E is the enable voltage, the first set transistor T7 is turned on, and the high voltage vgh on the second potential signal line VGH is transmitted to the gate of the first output transistor T2. In this way, the first output transistor T2 in each emitter shift circuit 40 is turned off, which avoids each emitter shift circuit 40 from outputting the low voltage vgl on the first potential signal line VGL, but instead outputting the high voltage vgh on the second potential signal line VGH, thereby controlling the light-emitting control transistors M1 and M6 to be turned off in the first stage.

[0074] For example, such as Figure 3 As shown, each transmit shift circuit 40 can also be connected to clock signal line CK_E and clock signal line XCK_E. Both clock signal lines CK_E and XCK_E can alternately provide high voltage vgh and low voltage vgl, and the signal transitions on clock signal lines CK_E and XCK_E are misaligned. The signal refresh periods on clock signal lines CK_E and XCK_E can be the same.

[0075] For example, within one signal refresh cycle of clock signal lines CK_E and XCK_E, all emitter shift circuits 40 can output a high voltage vgh on the second potential signal line VGH. For instance, when the signal on clock signal line XCK_E transitions from high to low, transistor T1 of part of the emitter shift circuit 40 is turned on, thus enabling part of the emitter shift circuit 40 to output a high voltage vgh on the second potential signal line VGH. When the signal on clock signal line CK transitions from high to low, transistor T1 of another part of the emitter shift circuit 40 is turned on, thus enabling the other part of the emitter shift circuit 40 to output a high voltage vgh on the second potential signal line VGH.

[0076] Within a data refresh frame, the signals on clock signal lines CK_E and XCK_E typically undergo multiple transitions, and the duration of one refresh cycle for clock signal lines CK_E and XCK_E is less than the duration of the data refresh frame.

[0077] For example, such as Figure 4 As shown, during the display phase, the transmit start signal line STV_E can be equipped with a normal pulse signal (including low voltage vgl and high voltage vgh), thereby controlling the light-emitting control transistors M1 and M6 to be normally turned on or off. During the display phase, the first control signal line RST_E can be kept at an enabled voltage (e.g., high voltage vgh), thereby controlling the first set transistor T7 to remain off during the display phase.

[0078] like Figure 2 As shown, the light-emitting control transistors M1 and M6 and the driving transistor M3 are electrically connected between the first power line PVDD and the first electrode of the light-emitting element 30.

[0079] In some optional embodiments, in the first stage, the gate of the driving transistor M3 in each row pixel circuit 20 is written with a first voltage V1, which is greater than or equal to the voltage of the first power line PVDD during the display stage. The voltage of the first power line PVDD during the display stage is a positive voltage.

[0080] The driving transistor M3 can be a P-type transistor. In the first stage, a large first voltage V1 is written to the gate of the driving transistor M3, which can turn off the driving transistor M3 and prevent the voltage on the driving transistor M3 from flowing to the light-emitting element 30, thereby preventing the light-emitting element 30 from emitting light in the first stage, so as to solve the problem of screen flickering in the power-on and power-off stages of the display device.

[0081] In some alternative implementations, the first voltage V1 is less than or equal to the black-state voltage VGMP. The higher the required write voltage, the greater the power consumption. Therefore, in the first stage, controlling the voltage at the gate of the write drive transistor to be less than or equal to the black-state voltage VGMP can prevent excessive power consumption.

[0082] In some alternative implementations, such as Figure 2 As shown, the pixel circuit 20 also includes a bias transistor M8 and a threshold compensation transistor M5. The first electrode of the bias transistor M8 is electrically connected to the bias signal line DVH, and the second electrode of the bias transistor M8 is electrically connected to the first electrode of the driving transistor M3. The first electrode of the threshold compensation transistor M5 is electrically connected to the second electrode of the driving transistor M3, and the second electrode of the threshold compensation transistor M5 is electrically connected to the gate of the driving transistor M3.

[0083] In the first stage, the bias transistor M8 and the threshold compensation transistor M5 in each row pixel circuit 10 are both turned on.

[0084] The bias signal line DVH is electrically connected to the display driver chip 200 of the display device. In the first stage, the display driver chip 200 provides a first voltage V1 to the bias signal line DVH.

[0085] In this embodiment, in the first stage, the bias transistor M8 and the threshold compensation transistor M5 are turned on, and the first voltage V1 on the bias signal line DVH can be transmitted to the first terminal of the driving transistor M3 through the bias transistor M8, and then transmitted to the gate of the driving transistor M3 through the threshold compensation transistor M5, thereby turning off the driving transistor M3 in the first stage.

[0086] For example, such as Figure 4 As shown, the voltage of the bias signal line DVH during the display stage can be lower than its voltage during the first stage.

[0087] For example, in the first stage, the first voltage V1 provided by the display driver chip 200 to the bias signal line DVH is equal to the black state voltage VGMP.

[0088] The following are some examples of how the bias transistors M8 in each row pixel circuit 10 can be turned on in the first stage.

[0089] In some alternative implementations, such as Figure 1As shown, the display panel 100 also includes multiple cascaded scan shift circuits 50, which can be connected to the pixel circuit 20 via the scan line SCAN. The first-stage scan shift circuit 50 is connected to the display driver chip 200 via the scan start signal line STV_S, and the scan shift circuit 50 can also be electrically connected to the clock signal line CK_S and the clock signal line XCK_S.

[0090] The signal output from the scan shift circuit 50 can be used to control the state of the switching transistors in the pixel circuit 20. For example, the switching transistors may include... Figure 2 The data is written to at least one of the following transistors: transistor M2, threshold compensation transistor M5, reset transistor M4, initialization transistor M7, and bias transistor M8.

[0091] As an example, such as Figure 5 As shown, the scan shift circuit 50 includes a first scan shift circuit 51, and multiple first scan shift circuits 51 are cascaded. The first scan shift circuit 51 is electrically connected to the gate of the bias transistor M8 through the first scan line SP*. The signal output by the first scan shift circuit 51 is used to control the state of the bias transistor M8 in the pixel circuit 20.

[0092] like Figure 5 As shown, the first scan shift circuit 51 includes a first A scan shift circuit 51a, which is electrically connected to a first A scan start signal line STV*. The first A scan start signal line STV* is electrically connected to the display driver chip 200. The display driver chip 200 can provide a start signal to the first scan shift circuit 51 via the first A scan start signal line STV* to trigger the first scan shift circuit 51.

[0093] like Figure 6 As shown, the first A-scan shift circuit 51a includes a second A-input transistor T9a and a second A-output transistor T2a. The second A-input transistor T9a is electrically connected between the first A-scan start signal line STV* and the gate of the second A-output transistor T2a. The first terminal of the second A-output transistor T2a is electrically connected to the first A-potential signal line VGLa, and the second terminal of the second A-output transistor T2a is electrically connected to the first scan line SP*. It can be understood that the second terminal of the second A-output transistor T2a is connected to the output terminal of the first A-scan shift circuit 51a.

[0094] The first potential signal line VGLa is used to provide the enable voltage for the bias transistor M8. For example, if the bias transistor M8 is a P-type transistor, the enable voltage provided by the first potential signal line VGLa is a low voltage vgl. The voltages provided by the first potential signal line VGLa and the first potential signal line VGL can be the same.

[0095] The circuit structure of each first scan shift circuit 51 can be as follows: Figure 6 As shown, the output signal of the previous stage first scan shift circuit 51 can be used as the start signal of the next stage first scan shift circuit 51. A trace can be connected between the output terminal of the previous stage first scan shift circuit 51 and the next stage first scan shift circuit 51. This trace serves as the first scan start signal line electrically connected to the second A input transistor T9a in the next stage first scan shift circuit 51.

[0096] like Figure 4 As shown, in the first stage, the display driver chip 200 can provide the enable voltage (such as low voltage vgl) of the second output transistor T2a to the first A scan start signal line STV* to which it is connected.

[0097] In this embodiment, in the first stage, since the first A scan start signal line STV* is an enable voltage, the second A output transistor T2a is turned on, thereby causing the first scan shift circuit 51 to output a low voltage vgl on the first A potential signal line VGLa, thereby controlling the bias transistor M8 to turn on in the first stage.

[0098] For example, such as Figure 6 As shown, each of the first scan shift circuits 51 can also be connected to clock signal line CK_S1 and clock signal line XCK_S1, and clock signal line CK_S1 and clock signal line XCK_S1 can alternately provide high voltage vgh and low voltage vgl.

[0099] When there is no signal input to the first scan shift circuit 51 (e.g., in the initial state), the internal potential of the first scan shift circuit 51 is defaulted to ground potential GND. Figure 7 As shown, in the first stage, when the voltage on the clock signal line CK_S1 first transitions to a low voltage, the second A input transistor T9a turns on, and the low voltage vgl on the first A scan start signal line STV* is input to the gate of the second A output transistor T2a, causing the second A output transistor T2a to turn on. The first scan shift circuit 51 only outputs a high voltage vgh when the voltage on the first A scan start signal line STV* is high. Within a data refresh frame, the signals on the clock signal lines CK_S1 and XCK_S1 typically undergo multiple transitions; therefore, the duration for which all first scan shift circuits 51 output a low voltage vgl is less than the duration of a data refresh frame.

[0100] For example, such as Figure 4 As shown, during the display phase, the first scan start signal line STV* can be a normal pulse signal (including low voltage vgl and high voltage vgh), thereby controlling the bias transistor M8 to perform normal conduction or cutoff.

[0101] In some alternative implementations, such as Figure 6 As shown, the first A scanning shift circuit 51a may further include a second A setting transistor T7a. The gate of the second A setting transistor T7a is electrically connected to the second A control signal line RST*, the first terminal of the second A setting transistor T7a is electrically connected to the second A potential signal line VGHa, and the second terminal of the second A setting transistor T7a is electrically connected to the gate of the second A output transistor T2a.

[0102] The second potential signal line VGHa is used to provide the disable voltage for the bias transistor M8. For example, if the bias transistor M8 is a P-type transistor, the disable voltage provided by the second potential signal line VGHa is a high voltage vgh. The voltages provided by the second potential signal line VGHa and the second potential signal line VGH can be the same.

[0103] like Figure 4 As shown, in the first stage, the display driver chip 200 provides an enable voltage for the second A set transistor T7a to the second A control signal line RST*. That is, in the first stage, the second A set transistor T7a remains off, thereby preventing a high level on the second A potential signal line VGHa from being transmitted to the gate of the second A output transistor T2a.

[0104] In this embodiment, by setting a second A-position transistor T7a, the state of the second A-position transistor T7a can be flexibly controlled according to requirements, thereby improving the flexibility of the circuit.

[0105] For example, such as Figure 4 As shown, during the display phase, a non-enabled voltage (e.g., a high voltage vgh) can be maintained on the second A control signal line RST*, thereby controlling the second A set transistor T7a to remain off during the display phase.

[0106] The above are some examples of how the bias transistor M8 in each row pixel circuit 10 can be turned on in the first stage. It should be noted that the examples of controlling the bias transistor M8 in each row pixel circuit 10 to be turned on in the first stage may include, but are not limited to, the examples above.

[0107] Next, we will introduce some examples of how the threshold compensation transistor M5 in each row pixel circuit 10 can be turned on in the first stage.

[0108] In some alternative implementations, such as Figure 8 As shown, the scan shift circuit 50 includes a second scan shift circuit 52, and multiple second scan shift circuits 52 are cascaded. The second scan shift circuit 52 is electrically connected to the gate of the threshold compensation transistor M5 through the second scan line S2N. The signal output by the second scan shift circuit 52 is used to control the state of the threshold compensation transistor M5 in the pixel circuit 20.

[0109] like Figure 8 As shown, the second scan shift circuit 52 includes a second scan shift circuit 52b, which is electrically connected to the second scan start signal line STV_S2N. The second scan start signal line STV_S2N is electrically connected to the display driver chip 200. The display driver chip 200 can provide a start signal to the second scan shift circuit 52 via the second scan start signal line STV_S2N to trigger the second scan shift circuit 52.

[0110] like Figure 9 As shown, the second B scan shift circuit 52b includes a second B input transistor T9b, a second B set transistor T7b, and a second B output transistor T2b. The second B input transistor T9b is electrically connected between the second B scan start signal line STV_S2N and the gate of the second B output transistor T2b. The first terminal of the second B output transistor T2b is electrically connected to the first B potential signal line VGLb, and the second terminal of the second B output transistor T2b is electrically connected to the second scan line S2N. It can be understood that the second terminal of the second B output transistor T2b is connected to the output terminal of the second B scan shift circuit 52b.

[0111] The gate of the second B set transistor T7b is electrically connected to the second B control signal line RST_S2N, the first terminal of the second B set transistor T7b is electrically connected to the second B potential signal line VGHb, and the second terminal of the second B set transistor T7b is electrically connected to the gate of the second B output transistor T2b.

[0112] The first potential signal line VGLb is used to provide the disable voltage for the threshold compensation transistor M5, and the second potential signal line VGHb is used to provide the enable voltage for the threshold compensation transistor M5. For example, for an N-type threshold compensation transistor M5, the disable voltage provided by the first potential signal line VGLb is a low voltage vgl, and the enable voltage provided by the second potential signal line VGHb is a high voltage vgh. The voltages provided by the first potential signal line VGLb and the first potential signal line VGL can be the same. The voltages provided by the second potential signal line VGHb and the second potential signal line VGH can also be the same.

[0113] The circuit structure of each second scan shift circuit 52 can be as follows: Figure 9 As shown, the output signal of the previous stage second scan shift circuit 52 can be used as the start signal of the next stage second scan shift circuit 52. A trace can be connected between the output terminal of the previous stage second scan shift circuit 52 and the next stage second scan shift circuit 52. This trace serves as the second scan start signal line electrically connected to the second input transistor T9b in the next stage second scan shift circuit 52.

[0114] like Figure 2 As shown, the threshold compensation transistor M5 is an N-type transistor. For an N-type transistor, it is turned on when its gate voltage is high (vgh) and turned off when its gate voltage is low (vgl).

[0115] For the N-type threshold compensation transistor M5, for example, such as Figure 4 As shown, in the first stage, the display driver chip provides the second B output transistor T2b with an enable voltage (e.g., high voltage vgh) to the second B scan start signal line STV_S2N, and provides the second B set transistor T7b with an enable voltage (e.g., low voltage vgl) to the second B control signal line RST_S2N.

[0116] In this embodiment, in the first stage, since the second B scan start signal line STV_S2N is a non-enabled voltage and the second B control signal line RST_S2N is an enabled voltage, the second B set transistor T7b is turned on and the second B output transistor T2b is turned off, thereby causing the second scan shift circuit 52 to output a high voltage vgh on the second B potential signal line VGHb, thereby controlling the N-type threshold compensation transistor M5 to turn on in the first stage.

[0117] For example, such as Figure 9 As shown, each of the second scan shift circuits 52 can also be connected to clock signal line CK_S2 and clock signal line XCK_S2, and clock signal line CK_S2 and clock signal line XCK_S2 can alternately provide high voltage vgh and low voltage vgl.

[0118] When no signal is input to the second scan shift circuit 52 (e.g., in the initial state), the internal potential of the second scan shift circuit 52 is defaulted to ground potential GND. In the first stage, when the voltage on the clock signal line XCK_S2 transitions to a low voltage, transistor T1b turns on, and the high voltage vgh on the second potential signal line VGHb is input to the second scan line S2N. Within a data refresh frame, the signals on the clock signal lines CK_S2 and XCK_S2 typically undergo multiple transitions; therefore, the duration for which all second scan shift circuits 52 output high voltage vgh is less than the duration of a data refresh frame.

[0119] For example, such as Figure 4 As shown, during the display phase, the second B scan start signal line STV_S2N can be equipped with a normal pulse signal (including low voltage vgl and high voltage vgh), thereby controlling the threshold compensation transistor M5 to perform normal on or off operation. During the display phase, the second B control signal line RST_S2N can be kept at an enabled voltage (e.g., high voltage vgh), thereby controlling the second B set transistor T7b to remain off during the display phase.

[0120] In other alternative implementations, such as Figure 10 As shown, the threshold compensation transistor M5 is a P-type transistor. For a P-type transistor, when its gate is at a high voltage vgh, the N-type transistor is turned off, and when its gate is at a low voltage vgl, the P-type transistor is turned on.

[0121] For the P-type threshold compensation transistor M5, it is still possible to utilize, as Figure 8 , Figure 9 The second scan shift circuit shown is used for control. It should be noted that for the P-type threshold compensation transistor M5, Figure 9 The transistor T7b shown does not need to be configured.

[0122] The differences in control timing compared to the N-type threshold compensation transistor M5 include: For the P-type threshold compensation transistor M5, for example, as... Figure 11 As shown, in the first stage, the display driver chip provides the enable voltage (e.g., low voltage Vgl) of the second output transistor T2b to the second scan start signal line STV_S2N.

[0123] In this embodiment, in the first stage, since the second scan start signal line STV_S2N is the enable voltage, the second scan output transistor T2b is turned on, thereby causing the second scan shift circuit 52 to output a low voltage vgl on the first scan potential signal line VGLa, thereby controlling the threshold compensation transistor M5 to turn on in the first stage.

[0124] It is understandable that the duration of the low voltage vgl output by all second scan shift circuits 52 is less than the duration of a data refresh frame, which is the same principle as the duration of the low voltage vgl output by all first scan shift circuits 51 in the above example being less than the duration of a data refresh frame. This will not be elaborated on here.

[0125] For example, for the P-type threshold compensation transistor M5, it is also possible to set Figure 9 The transistor T7b shown is exemplary, as follows: Figure 11 As shown, in the first stage, the display driver chip can also provide the second B set transistor T7b with an enable voltage (e.g., a high voltage Vgh) to the second B control signal line RST_S2N. That is, in the first stage, the second B set transistor T7b remains off, thereby preventing a high level on the second B potential signal line VGHb from being transmitted to the gate of the second B output transistor T2b.

[0126] The above are some examples of how the threshold compensation transistor M5 in each row pixel circuit 10 can be turned on in the first stage. It should be noted that the examples of controlling the threshold compensation transistor M5 in each row pixel circuit 10 to be turned on in the first stage may include, but are not limited to, the examples above.

[0127] In some alternative implementations, such as Figure 2 As shown, the pixel circuit 20 also includes a reset transistor M4, which is electrically connected between the gate of the driving transistor M3 and the reset signal line VREF1.

[0128] In the first stage, the bias transistors M8 of each row pixel circuit 10 are all turned on, the threshold compensation transistors M5 of each row pixel circuit 10 are all turned on, and the reset transistors M4 of each row pixel circuit 10 can be turned off.

[0129] In this embodiment, the reset transistor M4 is turned off, which prevents the reset signal on the reset signal line VREF1 from being written into the gate of the driving transistor M3, thereby avoiding affecting the turn-off state of the driving transistor M3 in the first stage.

[0130] In some alternative implementations, during the first stage, the display driver chip 200 may not provide a reset voltage to the reset signal line VREF1; however, during the display stage, the display driver chip 200 provides a reset voltage to the reset signal line VREF1. That is, the reset signal line VREF1 can be powered on at the beginning of the display stage and powered off at the end of the display stage.

[0131] Next, we will introduce some examples of how the reset transistor M4 in each row pixel circuit 10 can be turned off in the first stage.

[0132] In some alternative implementations, such as Figure 12 As shown, the scan shift circuit 50 includes a third scan shift circuit 53, and multiple third scan shift circuits 53 are cascaded. The third scan shift circuit 53 is electrically connected to the gate of the reset transistor M4 through the third scan line S1N. The signal output by the third scan shift circuit 53 is used to control the state of the reset transistor M4 in the pixel circuit 20.

[0133] like Figure 12 As shown, the third scan shift circuit 53 includes a third C scan shift circuit 53c, which is electrically connected to the third C scan start signal line STV_S1N. The third C scan start signal line STV_S1N is electrically connected to the display driver chip 200. The display driver chip 200 can provide a start signal to the third scan shift circuit 53 through the third C scan start signal line STV_S1N to trigger the third scan shift circuit 53.

[0134] like Figure 13As shown, the third C scan shift circuit 53c includes a third C input transistor T9c, a third C set transistor T7c, and a third C output transistor T2c. The third C input transistor T9c is electrically connected between the third C scan start signal line STV_S1N and the gate of the third C output transistor T2c. The first terminal of the third C output transistor T2c is electrically connected to the first C potential signal line VGLc, and the second terminal of the third C output transistor T2c is electrically connected to the third scan line S1N.

[0135] The gate of the third C-position transistor T7c is electrically connected to the third C-control signal line RST_S1N, the first terminal of the third C-position transistor T7c is electrically connected to the third C-potential signal line VGHc, and the second terminal of the third C-position transistor T7c is electrically connected to the gate of the third C-output transistor T2c.

[0136] The first C-potential signal line VGLc provides the disable voltage for the reset transistor M4, and the second C-potential signal line VGHc provides the enable voltage for the reset transistor M4. For example, for an N-type reset transistor M4, the disable voltage provided by the first C-potential signal line VGLc is a low voltage vgl, and the enable voltage provided by the second C-potential signal line VGHc is a high voltage vgh. The voltages provided by the first C-potential signal line VGLc and the first potential signal line VGL can be the same. The voltages provided by the second C-potential signal line VGHc and the second potential signal line VGH can also be the same.

[0137] The circuit structure of each third scan shift circuit 53 can be as follows: Figure 13 As shown, the output signal of the previous stage third scan shift circuit 53 serves as the start signal of the next stage third scan shift circuit 53. A trace can be connected between the output terminal of the previous stage third scan shift circuit 53 and the next stage third scan shift circuit 53. This trace serves as the second scan start signal line electrically connected to the third input transistor T9c in the next stage third scan shift circuit 53.

[0138] For the N-type reset transistor M4, for example, such as Figure 4 As shown, in the first stage, the display driver chip provides the enable voltage (e.g., low voltage vgl) of the third C output transistor T2c to the third C scan start signal line STV_S1N, and provides the disable voltage (e.g., high voltage vgh) of the third C set transistor T7c to the third C control signal line RST_S1N. In this way, the N-type reset transistor M4 in each row pixel circuit can be turned off.

[0139] For the P-type reset transistor M4, it is still possible to use, as Figure 12 , Figure 13 The third scan shift circuit shown is used for control.

[0140] The differences in the turn-off control timing compared to the N-type reset transistor M4 include: for the P-type reset transistor M4, for example, as Figure 11 As shown, in the first stage, the display driver chip provides the third C scan start signal line STV_S1N with the de-enable voltage (e.g., high voltage vgh) of the third C output transistor T2c, and the third C set transistor T7c with the enable voltage (e.g., low voltage vgl) of the third C control signal line. In this way, the P-type reset transistor M4 in each row pixel circuit can be turned off.

[0141] The above are some examples of how the reset transistor M4 in each row pixel circuit 10 can be turned off in the first stage. It should be noted that the examples of controlling the reset transistor M4 in each row pixel circuit 10 to be turned off in the first stage may include, but are not limited to, the examples above.

[0142] The example above describes how, in the first stage, the bias transistor M8 is turned on and the threshold compensation transistor M5 writes the first voltage V1 to the gate of the driving transistor M3. In other examples, in the first stage, the first voltage V1 can be written to the gate of the driving transistor M3 by the reset transistor M4.

[0143] In some alternative implementations, such as Figure 14 As shown, the reset transistor M4 is electrically connected between the gate of the drive transistor M3 and the reset signal line VREF1.

[0144] In the first stage, the reset transistors M4 in each row of pixel circuits 10 can all be turned on.

[0145] like Figure 15 As shown, in the first stage, the display driver chip 200 can provide a first voltage V1 to the reset signal line VREF1.

[0146] In this embodiment, in the first stage, the reset transistor M4 is turned on, and the reset signal line VREF1 provides a first voltage V1 which is transmitted to the gate of the driving transistor M3 through the reset transistor M4, thereby causing the driving transistor M3 to be turned off in the first stage.

[0147] For example, such as Figure 15 As shown, the voltage of the reset signal line VREF1 during the display phase can be lower than its voltage during the first phase. The voltage of the reset signal line VREF1 during the display phase is a negative voltage.

[0148] For example, in the first stage, the first voltage V1 provided by the display driver chip 200 to the reset signal line VREF1 is between the voltage Vdd and the black state voltage VGMP. The voltage of the first power line PVDD in the display stage is Vdd.

[0149] Next, we will introduce some examples of how the reset transistor M4 in each row pixel circuit 10 can be turned on in the first stage.

[0150] In some alternative implementations, methods such as Figure 12 and Figure 13 The third scan shift circuit 53 shown controls the state of the reset transistor M4. The specific circuit structure of the third scan shift circuit 53 will not be described here.

[0151] For the N-type reset transistor M4, such as Figure 15 As shown, in the first stage, the display driver chip provides the third C scan start signal line STV_S1N with the de-enable voltage (e.g., high voltage vgh) of the third C output transistor T2c, and provides the third C set transistor T7c with the enable voltage (e.g., low voltage vgl) of the third C control signal line RST_S1N.

[0152] In this embodiment, in the first stage, since the third C scan start signal line STV_S1N is a non-enabled voltage and the third C control signal line RST_S1N is an enabled voltage, the third C set transistor T7c is turned on and the third C output transistor T2c is turned off, thereby causing the third scan shift circuit 53 to output a high voltage vgh on the second C potential signal line VGHb, thereby controlling the N-type reset transistor M4 to turn on in the first stage.

[0153] For the P-type reset transistor M4, it is still possible to use, as Figure 12 , Figure 13 The third scan shift circuit shown is used for control.

[0154] The differences in the turn-on control timing between the P-type and N-type reset transistor M4 include: For example, as... Figure 16 As shown, in the first stage, the display driver chip provides the enable voltage (e.g., low voltage Vgl) of the third C scan start signal line STV_S1N to the third C output transistor T2c. In this way, the P-type reset transistor M4 in each row pixel circuit can be turned on.

[0155] For example, for a P-type reset transistor M4, such as... Figure 16 As shown, in the first stage, the display driver chip can also provide the third C set transistor T7c with an enable voltage (e.g., high voltage Vgh) to the third C control signal line RST_S1N.

[0156] For example, such as Figure 15 or Figure 16As shown, during the display phase, the third C scan start signal line STV_S1N can be a normal pulse signal (including low voltage vgl and high voltage vgh), thereby controlling the reset transistor M4 to normally turn on or off. During the display phase, the third C control signal line RST_S1N can be kept at an enabled voltage (e.g., high voltage vgh), thereby controlling the third C set transistor T7c to remain off during the display phase.

[0157] The above are some examples of how the reset transistor M4 in each row pixel circuit 10 can be turned on in the first stage. It should be noted that the examples of controlling the reset transistor M4 in each row pixel circuit 10 to be turned on in the first stage may include, but are not limited to, the examples above.

[0158] In the first stage, when the first voltage is written to the gate of the driving transistor M3 using the reset transistor M4, the threshold compensation transistors M5 of each row pixel circuit 10 can be turned on or off.

[0159] As an example, when the threshold compensation transistor M5 of each row pixel circuit 10 is turned on, the threshold compensation transistor M5 and the reset transistor M4 are in the same state in the first stage, and the threshold compensation transistor M5 and the reset transistor M4 can share the scan shift circuit.

[0160] As another example, in the first stage, the threshold compensation transistors M5 of each row pixel circuit 10 are all turned off.

[0161] Next, we will introduce some examples of how the threshold compensation transistors M5 in each row of pixel circuits 10 can be turned off in the first stage.

[0162] For example, it is still possible to utilize, such as Figure 8 , Figure 9 The second scan shift circuit shown controls the threshold compensation transistor M5 to turn off in the first stage.

[0163] For the N-type threshold compensation transistor M5, in the first stage, the display driver chip provides the enable voltage (e.g., low voltage vgl) of the second B output transistor T2b to the second B scan start signal line STV_S2N, and provides the de-enable voltage (e.g., high voltage vgh) of the second B set transistor T7b to the second B control signal line RST_S2N, thereby controlling the N-type threshold compensation transistor M5 to turn off in the first stage.

[0164] For the P-type threshold compensation transistor M5, for example, such as Figure 16 As shown, in the first stage, the display driver chip provides the second B output transistor T2b with an enable voltage (e.g., high voltage Vgh) to the second B scan start signal line STV_S2N, thereby controlling the N-type threshold compensation transistor M5 to turn off in the first stage.

[0165] For example, for the P-type threshold compensation transistor M5, it is also possible to set Figure 9 As shown, in the first stage, the display driver chip can also provide the enable voltage (e.g., low voltage vgl) of the second set transistor T7b to the second control signal line RST_S2N, thereby controlling the N-type threshold compensation transistor M5 to turn off in the first stage.

[0166] The above are some examples of how the threshold compensation transistor M5 in each row pixel circuit 10 can be turned off in the first stage. It should be noted that the examples of controlling the threshold compensation transistor M5 in each row pixel circuit 10 to be turned off in the first stage may include, but are not limited to, the examples above.

[0167] In some alternative implementations, such as Figure 2 , Figure 10 or Figure 14 As shown, the data writing transistor M2 is electrically connected between the first terminal of the driving transistor M3 and the data line DATA.

[0168] like Figure 17 As shown, the scan shift circuit 50 includes a fourth scan shift circuit 54, and multiple fourth scan shift circuits 54 are cascaded. The fourth scan shift circuit 54 is electrically connected to the gate of the data writing transistor M2 through the fourth scan line SP. The signal output by the fourth scan shift circuit 54 is used to control the state of the data writing transistor M2 in the pixel circuit 20.

[0169] like Figure 17 As shown, the fourth scan shift circuit 54 includes a fourth scan shift circuit 54d, which is electrically connected to the fourth scan start signal line STV_SP. The fourth scan start signal line STV_SP is electrically connected to the display driver chip 200. The display driver chip 200 can provide a start signal to the fourth scan shift circuit 54 via the fourth scan start signal line STV_SP to trigger the fourth scan shift circuit 54.

[0170] like Figure 18 As shown, the fourth scan shift circuit 54d includes a fourth input transistor T1d and a fourth output transistor T8d. The fourth input transistor T1d is electrically connected between the fourth scan start signal line STV_SP and the gate of the fourth output transistor T8d. The first terminal of the fourth output transistor T8d is electrically connected to the clock signal line XCK_S4, and the second terminal of the fourth output transistor T8d is electrically connected to the fourth scan line SP.

[0171] The clock signal line XCK_S4 is used to alternately provide the enable and disable voltages for the data write transistor M2. For example, for the P-type data write transistor M2, the enable voltage is a low voltage vgl, and the disable voltage is a high voltage vgh.

[0172] The circuit structure of each fourth scan shift circuit 54 can be as follows: Figure 18 As shown, the output signal of the previous stage fourth scan shift circuit 54 serves as the start signal of the next stage fourth scan shift circuit 54. A trace can be connected between the output terminal of the previous stage fourth scan shift circuit 54 and the next stage fourth scan shift circuit 54. This trace serves as the fourth scan start signal line electrically connected to the fourth input transistor T1d in the next stage fourth scan shift circuit 54.

[0173] like Figure 4 As shown, in the first stage, the display driver chip can provide the fourth output transistor T8d with an enable voltage (e.g., high voltage Vgh) to the fourth scan start signal line STV_SP.

[0174] In this embodiment, in the first stage, since the fourth scan start signal line STV_SP is kept at a high voltage, the fourth scan output transistor T8d is prevented from being turned off in the first stage, thereby enabling each fourth scan shift circuit 54 to output a high voltage in the first stage to control the data writing transistor M2 to be turned off in the first stage.

[0175] In some optional implementations, in the first stage, the display driver chip 200 can provide the data line DATA with its reference voltage VCI. Other voltages provided by the display driver chip are converted from the reference voltage VCI. Providing the reference voltage VCI directly to the data line in the first stage can reduce the conversion process and improve efficiency.

[0176] In some alternative implementations, to improve the flickering problem caused by leakage current in the data writing transistor during the first stage, the display driver chip 200 may provide a black state voltage VGMP to the data line DATA during the first stage.

[0177] In some alternative implementations, such as Figure 2 As shown, the light-emitting control transistors M1 / M6, the driving transistor M3, and the light-emitting element 30 are connected in series between the first power line PVDD and the second power line PVEE.

[0178] In the first stage, the display driver chip may not supply power voltage to the first power line PVDD and the second power line PVEE. During the display stage, the display driver chip supplies power voltage to both the first power line PVDD and the second power line PVEE. In the display stage, the display driver chip provides a positive voltage to the first power line PVDD and a negative voltage to the second power line PVEE.

[0179] And / or, such as Figure 2 As shown, the initialization transistor M7 is electrically connected between the initialization signal line VREF2 and the first terminal of the light-emitting element 30. In the first stage, the display driver chip does not provide an initialization voltage to the initialization signal line VREF2. In the display stage, the display driver chip provides an initialization voltage to the initialization signal line VREF2. During the display stage, the display driver chip provides a negative voltage to the initialization signal line VREF2.

[0180] The first power line PVDD, the second power line PVEE, and the initialization signal line VREF2 are at a low potential GND in the first stage. The first power line PVDD, the second power line PVEE, and the initialization signal line VREF2 begin to be powered normally in the display stage.

[0181] Understandably, Figure 4 The timing sequence shown includes the following: In the first stage, P-type light-emitting control transistors M1 and M6 are turned off, P-type bias transistor M8 is turned on, N-type threshold compensation transistor M5 is turned on, N-type reset transistor M4 is turned off, P-type data writing transistor M2 is turned off, and the bias signal line DVH provides the first voltage V1 to the driving transistor M3.

[0182] Figure 11 The timing sequence shown includes the following: In the first stage, P-type light-emitting control transistors M1 and M6 are turned off, P-type bias transistor M8 is turned on, P-type threshold compensation transistor M5 is turned on, P-type reset transistor M4 is turned off, P-type data writing transistor M2 is turned off, and the bias signal line DVH provides the first voltage V1 to the driving transistor M3.

[0183] Figure 15 The timing sequence shown includes the following: In the first stage, P-type light-emitting control transistors M1 and M6 are turned off, N-type threshold compensation transistor M5 is turned off, N-type reset transistor M4 is turned on, P-type data writing transistor M2 is turned off, and the reset signal line VREF1 provides the first voltage V1 to the driving transistor M3.

[0184] Figure 16 The timing sequence shown includes the following: In the first stage, P-type light-emitting control transistors M1 and M6 are turned off, P-type threshold compensation transistor M5 is turned off, P-type reset transistor M4 is turned on, P-type data writing transistor M2 is turned off, and the reset signal line VREF1 provides the first voltage V1 to the driving transistor M3.

[0185] Based on the same inventive concept, embodiments of this application also provide a driving method for a display device.

[0186] like Figure 1 As shown, the display device includes a display panel 100, which includes multiple rows of pixel circuits 20 for driving light-emitting elements 30.

[0187] The pixel circuit 20 may include a driving transistor M3 and light-emitting control transistors M1 and M6. The driving transistor M3 can be used to generate a driving current to drive the light-emitting element 30 to emit light, and the magnitude of the driving current affects the brightness of the light-emitting element 30. The light-emitting control transistors M1 and M6 can be used to control the light-emitting element 30 to enter the light-emitting stage. For example, when the light-emitting control transistors M1 and M6 are turned on, the driving current generated by the driving transistor M3 is transmitted to the light-emitting element 30, and the light-emitting element 30 emits light.

[0188] The driving process of the display panel includes a first stage and a display stage, with the first stage occurring at least once before or after the display stage.

[0189] like Figure 19 As shown, the driving method for the display device includes step 191.

[0190] Step 191: In the first stage, at least one of the light-emitting control transistors and driving transistors in each row of pixel circuits is turned off;

[0191] The duration of the first stage is t, and the data refresh frequency of the pixel circuit during the display stage is f, where t≤1 / f.

[0192] In this embodiment, by controlling the duration of the power-on and power-off phases to within one refresh frame, the power-on and power-off time is shortened, enabling fast power-on and power-off and improving the user experience. Furthermore, with the light-emitting control transistors and driving transistors of each row of pixel circuits turned off in the first phase, a double safety net is provided to prevent the light-emitting elements from emitting light, thus helping to avoid screen flickering during the power-on and power-off phases.

[0193] In some optional embodiments, the display panel further includes multiple cascaded emission shifting circuits, which are electrically connected to the gate of the light-emitting control transistor via a light-emitting control signal line. The emission shifting circuit includes a first emission shifting circuit, which is electrically connected to the emission start signal line.

[0194] The first emitter shifting circuit includes a first input transistor, a first set transistor, and a first output transistor. The first input transistor is electrically connected between the emitter start signal line and the gate of the first output transistor. The first terminal of the first output transistor is electrically connected to the first potential signal line, and the second terminal of the first output transistor is electrically connected to the light emission control signal line.

[0195] The gate of the first set transistor is electrically connected to the first control signal line, the first terminal of the first set transistor is electrically connected to the second potential signal line, and the second terminal of the first set transistor is electrically connected to the gate of the first output transistor.

[0196] The first potential signal line is used to provide the enable voltage of the light-emitting control transistor, and the second potential signal line is used to provide the disable voltage of the light-emitting control transistor.

[0197] The display device also includes a display driver chip;

[0198] The driving method includes: in a first stage, the display driver chip provides an enable voltage for the first output transistor to the transmit start signal line connected thereto, and provides an enable voltage for the first set transistor to the first control signal line.

[0199] In some alternative implementations, the light-emitting control transistor and the driving transistor are electrically connected between the first power supply line and the first electrode of the light-emitting element;

[0200] The driving method includes: in a first stage, the gate of the driving transistor in each row pixel circuit is written with a first voltage, the first voltage being greater than or equal to the voltage of the first power line in the display stage.

[0201] In some alternative implementations, the first voltage is less than or equal to the black-state voltage.

[0202] In some alternative implementations, the pixel circuit further includes a bias transistor and a threshold compensation transistor, wherein the first terminal of the bias transistor is electrically connected to a bias signal line, the second terminal of the bias transistor is electrically connected to the first terminal of the driving transistor, the first terminal of the threshold compensation transistor is electrically connected to the second terminal of the driving transistor, and the second terminal of the threshold compensation transistor is electrically connected to the gate of the driving transistor.

[0203] In the first stage, the bias transistors and threshold compensation transistors in each row of pixel circuits are turned on;

[0204] The display device also includes a display driver chip;

[0205] The driving method includes: in the first stage, the display driver chip provides a first voltage to the bias signal line.

[0206] In some optional embodiments, the display panel further includes a plurality of cascaded first scan shift circuits, the first scan shift circuits being electrically connected to the gates of bias transistors via first scan lines, the first scan shift circuits including a first A scan shift circuit, the first A scan shift circuit being electrically connected to a first A scan start signal line;

[0207] The first A-scan shift circuit includes a second A-input transistor and a second A-output transistor. The second A-input transistor is electrically connected between the gate of the first A-scan start signal line and the gate of the second A-output transistor. The first terminal of the second A-output transistor is electrically connected to the first A-potential signal line, and the second terminal of the second A-output transistor is electrically connected to the first scan line.

[0208] The first A potential signal line is used to provide the enable voltage for the bias transistor;

[0209] The display device also includes a display driver chip;

[0210] The driving method includes: in the first stage, the display driver chip provides the enable voltage of the second A output transistor to the first A scan start signal line.

[0211] In some optional embodiments, the first A scan shift circuit further includes a second A set transistor, the gate of the second A set transistor is electrically connected to the second A control signal line, the first terminal of the second A set transistor is electrically connected to the second A potential signal line, and the second terminal of the second A set transistor is electrically connected to the gate of the second A output transistor.

[0212] The second potential signal line is used to provide the disable voltage for the bias transistor;

[0213] The driving method includes: in the first stage, the display driver chip provides the second A set transistor with an enable voltage to the second A control signal line.

[0214] In some alternative implementations, the threshold compensation transistor is an N-type transistor;

[0215] The display panel also includes multiple cascaded second scan shift circuits. The second scan shift circuits are electrically connected to the gate of the threshold compensation transistor through the second scan line. The second scan shift circuit includes a second B scan shift circuit, which is electrically connected to the second B scan start signal line.

[0216] The second B scan shift circuit includes a second B input transistor, a second B set transistor, and a second B output transistor. The second B input transistor is electrically connected between the second B scan start signal line and the gate of the second B output transistor. The first terminal of the second B output transistor is electrically connected to the first B potential signal line, and the second terminal of the second B output transistor is electrically connected to the second scan line.

[0217] The gate of the second B set transistor is electrically connected to the second B control signal line, the first terminal of the second B set transistor is electrically connected to the second B potential signal line, and the second terminal of the second B set transistor is electrically connected to the gate of the second B output transistor.

[0218] The first potential signal line is used to provide the disabling voltage of the threshold compensation transistor, and the second potential signal line is used to provide the enabling voltage of the threshold compensation transistor.

[0219] The display device also includes a display driver chip;

[0220] The driving method includes: in a first stage, the display driver chip provides a de-enable voltage of the second B output transistor to the second B scan start signal line and an enable voltage of the second B set transistor to the second B control signal line.

[0221] In some alternative implementations, the threshold compensation transistor is a P-type transistor;

[0222] The display panel also includes multiple cascaded second scan shift circuits. The second scan shift circuits are electrically connected to the gate of the threshold compensation transistor through the second scan line. The second scan shift circuit includes a second B scan shift circuit, which is electrically connected to the second B scan start signal line.

[0223] The second B scan shift circuit includes a second B input transistor and a second B output transistor. The second B input transistor is electrically connected between the second B scan start signal line and the gate of the second B output transistor. The first terminal of the second B output transistor is electrically connected to the first B potential signal line, and the second terminal of the second B output transistor is electrically connected to the second scan line.

[0224] The first potential signal line is used to provide the enable voltage for the threshold compensation transistor;

[0225] The display device also includes a display driver chip;

[0226] The driving method includes: in the first stage, the display driver chip provides the enable voltage of the second output transistor to the second scan start signal line.

[0227] In some alternative implementations, the pixel circuit further includes a reset transistor electrically connected between the gate of the driving transistor and a reset signal line.

[0228] The driving method includes: in the first stage, the reset transistors controlling each row of pixel circuits are all turned off.

[0229] In some alternative implementations, the driving method includes:

[0230] In the first stage, the display driver chip does not provide a reset voltage to the reset signal line. In the display stage, the display driver chip provides a reset voltage to the reset signal line.

[0231] In some alternative implementations, the pixel circuit further includes a reset transistor electrically connected between the gate of the driving transistor and a reset signal line.

[0232] In the first stage, the reset transistors in each row of pixel circuits are turned on;

[0233] The display device also includes a display driver chip;

[0234] The driving method includes: in the first stage, the display driver chip provides a first voltage to the reset signal line.

[0235] In some alternative implementations, the reset transistor is an N-type transistor;

[0236] The display panel also includes multiple cascaded third scan shift circuits. The third scan shift circuits are electrically connected to the gate of the reset transistor through the third scan line. The third scan shift circuit includes a third C scan shift circuit, which is electrically connected to the third C scan start signal line.

[0237] The third C scan shift circuit includes a third C input transistor, a third C set transistor, and a third C output transistor. The third C input transistor is electrically connected between the third C scan start signal line and the gate of the third C output transistor. The first terminal of the third C output transistor is electrically connected to the first C potential signal line, and the second terminal of the third C output transistor is electrically connected to the third scan line.

[0238] The gate of the third C-position transistor is electrically connected to the third C-control signal line, the first terminal of the third C-position transistor is electrically connected to the second C-potential signal line, and the second terminal of the third C-position transistor is electrically connected to the gate of the third C-output transistor.

[0239] The first C-potential signal line is used to provide the de-enable voltage of the reset transistor, and the second C-potential signal line is used to provide the enable voltage of the reset transistor.

[0240] The display device also includes a display driver chip, and the driving method includes:

[0241] In the first stage, the display driver chip provides the third C output transistor's de-enable voltage to the third C scan start signal line and the third C set transistor's enable voltage to the third C control signal line.

[0242] In some alternative implementations, the reset transistor is a P-type transistor;

[0243] The display panel also includes multiple cascaded third scan shift circuits. The third scan shift circuits are electrically connected to the gate of the reset transistor through the third scan line. The third scan shift circuit includes a third C scan shift circuit, which is electrically connected to the third C scan start signal line.

[0244] The third C scan shift circuit includes a third C input transistor and a third C output transistor. The third C input transistor is electrically connected between the third C scan start signal line and the gate of the third C output transistor. The first terminal of the third C output transistor is electrically connected to the first C potential signal line, and the second terminal of the third C output transistor is electrically connected to the third scan line.

[0245] The first C potential signal line is used to provide the enable voltage for the reset transistor;

[0246] The display device also includes a display driver chip, and the driving method includes:

[0247] In the first stage, the display driver chip provides the enable voltage of the third C output transistor to the third C scan start signal line.

[0248] In some alternative implementations, the pixel circuit further includes a threshold compensation transistor, the first terminal of which is electrically connected to the second terminal of the driving transistor, and the second terminal of which is electrically connected to the gate of the driving transistor.

[0249] The gate of the threshold compensation transistor is electrically connected to the third scan shift circuit;

[0250] Alternatively, in the first stage, all threshold compensation transistors are turned off.

[0251] In some alternative implementations, the pixel circuit also includes a data writing transistor electrically connected between the first terminal of the driving transistor and the data line.

[0252] The display panel also includes multiple cascaded fourth scan shift circuits. The fourth scan shift circuits are electrically connected to the gate of the data writing transistor through the fourth scan line. The fourth scan shift circuit includes a fourth scan shift circuit and is electrically connected to the fourth scan start signal line.

[0253] The fourth scan shift circuit includes a fourth input transistor and a fourth output transistor. The fourth input transistor is electrically connected between the fourth scan start signal line and the gate of the fourth output transistor. The first terminal of the fourth output transistor is electrically connected to the clock signal line, and the second terminal of the fourth output transistor is electrically connected to the fourth scan line.

[0254] The clock signal line is used to alternately provide the enable and disable voltages for data writing transistors;

[0255] The display device also includes a display driver chip, and the driving method includes:

[0256] In the first stage, the display driver chip provides the fourth output transistor with the fourth scan start signal line as an enable voltage.

[0257] In some alternative implementations, the driving method includes:

[0258] In the first stage, the display driver chip provides the reference voltage of the display driver chip to the data line.

[0259] In some alternative implementations, the light-emitting control transistor, the driving transistor, and the light-emitting element are connected in series between the first power line and the second power line.

[0260] The display device also includes a display driver chip, and the driving method includes:

[0261] In the first stage, the display driver chip does not provide power voltage to the first power line and the second power line. In the display stage, the display driver chip provides power voltage to the first power line and the second power line.

[0262] And / or, the pixel circuit also includes an initialization transistor electrically connected between the initialization signal line and the first pole of the light-emitting element. In the first stage, the display driver chip does not provide an initialization voltage to the initialization signal line, and in the display stage, the display driver chip provides an initialization voltage to the initialization signal line.

[0263] In some alternative implementations, the pixel circuit has multiple data refresh frequencies during the display phase, where f is the maximum value among the multiple data refresh frequencies.

[0264] The display device provided in this application embodiment can be a mobile phone, wearable product, computer, television, vehicle display device, or other display device with display function. This application does not impose any specific limitations on it.

[0265] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A display device, characterized in that, include: The display panel includes multiple rows of pixel circuits. Each pixel circuit includes a light-emitting control transistor and a driving transistor. The light-emitting control transistor is used to control the light-emitting element to enter the light-emitting stage, and the driving transistor is used to provide driving current to the light-emitting element. The driving process of the display panel includes a first stage and a display stage, wherein the first stage is present at least one before and after the display stage; In the first stage, at least one of the light-emitting control transistor and the driving transistor in each row of pixel circuits is turned off; The duration of the first stage is t, and the data refresh frequency of the pixel circuit in the display stage is f, where t < 1 / f; The pixel circuit further includes a bias transistor and a threshold compensation transistor. The first terminal of the bias transistor is electrically connected to a bias signal line, the second terminal of the bias transistor is electrically connected to the first terminal of the driving transistor, the first terminal of the threshold compensation transistor is electrically connected to the second terminal of the driving transistor, and the second terminal of the threshold compensation transistor is electrically connected to the gate of the driving transistor. In the first stage, the bias transistors and threshold compensation transistors in each row of pixel circuits are all turned on; the display device further includes a display driver chip, which provides a first voltage to the bias signal line in the first stage, the first voltage being greater than or equal to the voltage of the first power line in the display stage, to turn off the driving transistors in each row of pixel circuits; wherein, the display panel further includes a plurality of cascaded first scan shift circuits, the first scan shift circuits being electrically connected to the gates of the bias transistors, and in the first stage, the duration of the enable level output by all the first scan shift circuits is less than the duration of a data refresh frame; the display panel further includes a plurality of cascaded second scan shift circuits, the second scan shift circuits being electrically connected to the gates of the threshold compensation transistors, and in the first stage, the duration of the enable level output by all the second scan shift circuits is less than the duration of a data refresh frame; Alternatively, the pixel circuit may further include a reset transistor electrically connected between the gate of the driving transistor and a reset signal line; in the first stage, the reset transistors in each row of the pixel circuits are turned on; the display driver chip provides the first voltage to the reset signal line to turn off the driving transistors in each row of the pixel circuits, wherein the display panel further includes multiple cascaded third scan shift circuits electrically connected to the gate of the reset transistors, and in the first stage, the duration of the enable level output by all the third scan shift circuits is less than the duration of a data refresh frame.

2. The display device according to claim 1, characterized in that, The display panel also includes multiple cascaded emitter shifting circuits. The emitter shifting circuits are electrically connected to the gate of the light-emitting control transistor via a light-emitting control signal line. The emitter shifting circuit includes a first emitter shifting circuit, which is electrically connected to the emitter start signal line. The first emission shifting circuit includes a first input transistor, a first set transistor, and a first output transistor. The first input transistor is electrically connected between the emission start signal line and the gate of the first output transistor. The first terminal of the first output transistor is electrically connected to the first potential signal line, and the second terminal of the first output transistor is electrically connected to the light emission control signal line. The gate of the first set transistor is electrically connected to the first control signal line, the first terminal of the first set transistor is electrically connected to the second potential signal line, and the second terminal of the first set transistor is electrically connected to the gate of the first output transistor. The first potential signal line is used to provide the enable voltage of the light-emitting control transistor, and the second potential signal line is used to provide the disable voltage of the light-emitting control transistor; The display device further includes a display driver chip. In the first stage, the display driver chip provides an enable voltage for the first output transistor to the transmit start signal line to which it is connected, and provides an enable voltage for the first set transistor to the first control signal line.

3. The display device according to claim 1, characterized in that, The first voltage is less than or equal to the black state voltage.

4. The display device according to claim 1, characterized in that, In the first stage, when both the bias transistor and the threshold compensation transistor in each row of the pixel circuit are turned on... The first scan shift circuit is electrically connected to the gate of the bias transistor through the first scan line. The first scan shift circuit includes a first A scan shift circuit, which is electrically connected to the first A scan start signal line. The first A-scan shift circuit includes a second A-input transistor and a second A-output transistor. The second A-input transistor is electrically connected between the first A-scan start signal line and the gate of the second A-output transistor. The first terminal of the second A-output transistor is electrically connected to the first A-potential signal line, and the second terminal of the second A-output transistor is electrically connected to the first scan line. The first potential signal line is used to provide the enable voltage of the bias transistor; The display device further includes a display driver chip, which provides the enable voltage of the second A output transistor to the first A scan start signal line during the first stage.

5. The display device according to claim 4, characterized in that, The first A-scan shift circuit further includes a second A-set transistor, the gate of the second A-set transistor is electrically connected to the second A-control signal line, the first terminal of the second A-set transistor is electrically connected to the second A-potential signal line, and the second terminal of the second A-set transistor is electrically connected to the gate of the second A-output transistor. The second potential signal line is used to provide the disable voltage of the bias transistor; In the first stage, the display driver chip provides the second A set transistor's de-enable voltage to the second A control signal line.

6. The display device according to claim 1, characterized in that, In the first stage, when both the bias transistor and the threshold compensation transistor in the pixel circuit of each row are turned on, the threshold compensation transistor is an N-type transistor. The second scan shift circuit is electrically connected to the gate of the threshold compensation transistor via the second scan line. The second scan shift circuit includes a second B scan shift circuit, which is electrically connected to the second B scan start signal line. The second B scan shift circuit includes a second B input transistor, a second B set transistor, and a second B output transistor. The second B input transistor is electrically connected between the second B scan start signal line and the gate of the second B output transistor. The first terminal of the second B output transistor is electrically connected to the first B potential signal line, and the second terminal of the second B output transistor is electrically connected to the second scan line. The gate of the second B set transistor is electrically connected to the second B control signal line, the first terminal of the second B set transistor is electrically connected to the second B potential signal line, and the second terminal of the second B set transistor is electrically connected to the gate of the second B output transistor. The first potential signal line is used to provide the de-enable voltage of the threshold compensation transistor, and the second potential signal line is used to provide the enable voltage of the threshold compensation transistor. The display device further includes a display driver chip. In the first stage, the display driver chip provides the second B scan start signal line with the de-enable voltage of the second B output transistor and provides the second B set transistor with the enable voltage of the second B control signal line.

7. The display device according to claim 1, characterized in that, In the first stage, when both the bias transistor and the threshold compensation transistor in the pixel circuit of each row are turned on, the threshold compensation transistor is a P-type transistor. The second scan shift circuit is electrically connected to the gate of the threshold compensation transistor via the second scan line. The second scan shift circuit includes a second B scan shift circuit, which is electrically connected to the second B scan start signal line. The second B scan shift circuit includes a second B input transistor and a second B output transistor. The second B input transistor is electrically connected between the second B scan start signal line and the gate of the second B output transistor. The first terminal of the second B output transistor is electrically connected to the first B potential signal line, and the second terminal of the second B output transistor is electrically connected to the second scan line. The first potential signal line is used to provide the enable voltage of the threshold compensation transistor; The display device further includes a display driver chip, which, in the first stage, provides the enable voltage of the second output transistor to the second scan start signal line.

8. The display device according to claim 1, characterized in that, In the first stage, when both the bias transistor and the threshold compensation transistor in each row of the pixel circuit are turned on, In the first stage, the reset transistors of the pixel circuits in each row are all turned off.

9. The display device according to claim 8, characterized in that, In the first stage, the display driver chip does not provide a reset voltage to the reset signal line; in the display stage, the display driver chip provides a reset voltage to the reset signal line.

10. The display device according to claim 1, characterized in that, In the first stage, when all the reset transistors in the pixel circuits of each row are turned on, the reset transistors are N-type transistors; The third scan shift circuit is electrically connected to the gate of the reset transistor through the third scan line. The third scan shift circuit includes a third C scan shift circuit, which is electrically connected to the third C scan start signal line. The third C scan shift circuit includes a third C input transistor, a third C set transistor, and a third C output transistor. The third C input transistor is electrically connected between the third C scan start signal line and the gate of the third C output transistor. The first terminal of the third C output transistor is electrically connected to the first C potential signal line, and the second terminal of the third C output transistor is electrically connected to the third scan line. The gate of the third C-position transistor is electrically connected to the third C-control signal line, the first terminal of the third C-position transistor is electrically connected to the second C-potential signal line, and the second terminal of the third C-position transistor is electrically connected to the gate of the third C-output transistor. The first C-potential signal line is used to provide the de-enable voltage of the reset transistor, and the second C-potential signal line is used to provide the enable voltage of the reset transistor; The display device further includes a display driver chip. In the first stage, the display driver chip provides the third C output transistor with an enable voltage to the third C scan start signal line and the third C set transistor with an enable voltage to the third C control signal line.

11. The display device according to claim 1, characterized in that, In the first stage, when all the reset transistors in the pixel circuits of each row are turned on, the reset transistors are P-type transistors. The third scan shift circuit is electrically connected to the gate of the reset transistor through the third scan line. The third scan shift circuit includes a third C scan shift circuit, which is electrically connected to the third C scan start signal line. The third C scan shift circuit includes a third C input transistor and a third C output transistor. The third C input transistor is electrically connected between the third C scan start signal line and the gate of the third C output transistor. The first terminal of the third C output transistor is electrically connected to the first C potential signal line, and the second terminal of the third C output transistor is electrically connected to the third scan line. The first C-potential signal line is used to provide the enable voltage of the reset transistor; The display device further includes a display driver chip, which, in the first stage, provides the enable voltage of the third C output transistor to the third C scan start signal line.

12. The display device according to claim 10 or 11, characterized in that, The threshold compensation transistors and reset transistors in different rows share the same third scan shift circuit; Alternatively, in the first stage, all the threshold compensation transistors in each row are turned off.

13. The display device according to claim 1, characterized in that, The pixel circuit also includes a data writing transistor, which is electrically connected between the first electrode of the driving transistor and the data line. The display panel also includes multiple cascaded fourth scan shift circuits. The fourth scan shift circuits are electrically connected to the gate of the data writing transistor via a fourth scan line. The fourth scan shift circuit includes a fourth scan shift circuit, which is electrically connected to the fourth scan start signal line. The fourth scan shift circuit includes a fourth input transistor and a fourth output transistor. The fourth input transistor is electrically connected between the fourth scan start signal line and the gate of the fourth output transistor. The first terminal of the fourth output transistor is electrically connected to the clock signal line, and the second terminal of the fourth output transistor is electrically connected to the fourth scan line. The clock signal line is used to alternately provide the enable voltage and disable voltage of the data write transistor; The display device further includes a display driver chip, which provides the fourth output transistor with an enable voltage to the fourth scan start signal line during the first stage.

14. The display device according to claim 1, characterized in that, In the first stage, the display driver chip provides a reference voltage to the data line connected to the pixel circuit.

15. The display device according to claim 1, characterized in that, The light-emitting control transistor, the driving transistor, and the light-emitting element are connected in series between the first power line and the second power line. The display device further includes a display driver chip. In the first stage, the display driver chip does not provide power voltage to the first power line and the second power line. In the display stage, the display driver chip provides power voltage to the first power line and the second power line. And / or, the pixel circuit further includes an initialization transistor electrically connected between the initialization signal line and a first electrode of the light-emitting element, wherein in the first stage, the display driver chip does not provide an initialization voltage to the initialization signal line, and in the display stage, the display driver chip provides an initialization voltage to the initialization signal line.

16. The display device according to claim 1, characterized in that, The pixel circuit has multiple data refresh frequencies during the display phase, where f is the maximum value among the multiple data refresh frequencies.

17. A driving method for a display device, characterized in that, The display device includes a display panel, the display panel includes multiple rows of pixel circuits, the pixel circuits include light-emitting control transistors and driving transistors, the light-emitting control transistors are used to control the light-emitting element to enter the light-emitting stage, and the driving transistors are used to provide driving current to the light-emitting element; The driving process of the display panel includes a first stage and a display stage, wherein the first stage is present at least one before and after the display stage; The driving method includes: In the first stage, at least one of the light-emitting control transistor and the driving transistor in each row of pixel circuits is turned off; The duration of the first stage is t, and the data refresh frequency of the pixel circuit in the display stage is f, where t < 1 / f; The pixel circuit further includes a bias transistor and a threshold compensation transistor. The first terminal of the bias transistor is electrically connected to a bias signal line, the second terminal of the bias transistor is electrically connected to the first terminal of the driving transistor, the first terminal of the threshold compensation transistor is electrically connected to the second terminal of the driving transistor, and the second terminal of the threshold compensation transistor is electrically connected to the gate of the driving transistor. In the first stage, the bias transistors and threshold compensation transistors in each row of pixel circuits are all turned on; the method further includes: in the first stage, the display driver chip provides a first voltage to the bias signal line, the first voltage being greater than or equal to the voltage of the first power line in the display stage, to turn off the driving transistors in each row of pixel circuits; wherein, the display panel further includes a plurality of cascaded first scan shift circuits, the first scan shift circuits being electrically connected to the gates of the bias transistors, and in the first stage, the duration of the enable level output by all the first scan shift circuits is less than the duration of a data refresh frame; the display panel further includes a plurality of cascaded second scan shift circuits, the second scan shift circuits being electrically connected to the gates of the threshold compensation transistors, and in the first stage, the duration of the enable level output by all the second scan shift circuits is less than the duration of a data refresh frame; Alternatively, the pixel circuit further includes a reset transistor electrically connected between the gate of the driving transistor and a reset signal line; in the first stage, the reset transistors in each row of the pixel circuits are all turned on; the method further includes: providing the first voltage to the reset signal line to turn off the driving transistors in each row of the pixel circuits, wherein the display panel further includes a plurality of cascaded third scan shift circuits electrically connected to the gate of the reset transistors, and in the first stage, the duration of the enable level output by all the third scan shift circuits is less than the duration of a data refresh frame.

Images