Power control circuit and memory

Abstract

The application provides a power supply control circuit and a memory, including: a control module, coupled to a control end of a transmission module, configured to output a control signal of a first voltage in response to a mode signal being in a first voltage level state, and output a control signal of a second voltage in response to the mode signal being in a second voltage level state; and the transmission module, coupled between a first power signal and a circuit module, configured to transmit the first power signal to the circuit module in response to the control signal of the first voltage, and disconnect the transmission in response to the control signal of the second voltage; wherein the first voltage represents a low voltage level state, and the second voltage is higher than a voltage of the first power signal. The scheme can reduce the leakage current.

Description

Technical Field

[0001] This application relates to memory technology, and more particularly to a power control circuit and a memory. Background Technology

[0002] With the development of memory technology, memory has been widely used in many fields. For example, Dynamic Random Access Memory (DRAM) is widely used.

[0003] In practical applications, memory contains multiple circuit modules. These modules require power signals to operate, such as power supply and ground. To facilitate power management and reduce power consumption, a main power supply is used in some examples. Power control for each circuit module is achieved by controlling the transmission module between the main power supply and the circuit modules. Therefore, it is necessary to consider how to implement effective power control. Summary of the Invention

[0004] Embodiments of this application provide a power control circuit and a memory.

[0005] According to some embodiments, a first aspect of this application provides a power control circuit, comprising: a control module coupled to a control terminal of a transmission module, configured to output a control signal for a first voltage in response to a mode signal being at a first level; and to output a control signal for a second voltage in response to the mode signal being at a second level; the transmission module coupled between a first power signal and a circuit module, configured to transmit the first power signal to the circuit module in response to the control signal for the first voltage; and to disconnect the transmission in response to the control signal for the second voltage; wherein the first voltage represents a low-level state, and the second voltage is higher than the voltage of the first power signal.

[0006] In some embodiments, the transmission module includes: a first PMOS transistor; the source of the first PMOS transistor receives the first power signal, and the drain of the first PMOS transistor is connected to the circuit module; the gate of the first PMOS transistor serves as the control terminal of the transmission module and is connected to the control module.

[0007] In some embodiments, the control module includes: a first switch, a second switch, and a first control unit; a first terminal of the first switch is connected to a second power signal, and a second terminal of the first switch is connected to the control terminal of the transmission module; the voltage of the second power signal is the second voltage; the input terminal of the first control unit is connected to the mode signal, and the output terminal of the first control unit is connected to the control terminal of the first switch; the first control unit is used to control the first switch to turn off when the mode signal switches to the first level state, and to control the first switch to turn on after a first delay when the mode signal switches to the second level state; a first terminal of the second switch is connected to the control terminal of the transmission module, a second terminal of the second switch is grounded, and the control terminal of the second switch is connected to the mode signal; the second switch is used to turn on when the mode signal switches to the first level state, and to turn off when the mode signal switches to the second level state.

[0008] In some embodiments, the control module further includes: a second control unit; the input terminal of the second control unit is connected to the mode signal, and the output terminal of the second control unit is connected to the control terminal of the second switch; the second control unit is used to control the second switch to be turned on after a second delay when the mode signal switches to the first level state, and to control the second switch to be turned off when the mode signal switches to the second level state.

[0009] In some embodiments, the second control unit includes: a first delay unit and an AND gate; the first input terminal of the AND gate is connected to the output terminal of the first delay unit, the second input terminal of the AND gate is connected to the mode signal, and the output terminal of the AND gate is connected to the control terminal of the second switch; the input terminal of the first delay unit is connected to the second input terminal of the AND gate, and the first delay unit is used to transmit the received signal to the first input terminal of the AND gate after the second delay.

[0010] In some embodiments, the first control unit includes: a first logic unit and a first level conversion unit; the input terminal of the first logic unit is connected to the mode signal, and the output terminal of the first logic unit is connected to the input terminal of the first level conversion unit; the first logic unit is configured to output a signal with a level state of the first level state when the received signal switches to the first level state, and to output a signal with a level state of the second level state after a first delay when the received signal switches to the second level state; the output terminal of the first level conversion unit is connected to the control terminal of the first switch; the first level conversion unit is configured to convert the voltage of the received high-level signal into the second voltage.

[0011] In some embodiments, the first logic unit includes: a second delay unit and a first OR gate; the first input terminal of the first OR gate is connected to the mode signal, the second input terminal of the first OR gate is connected to the output terminal of the second delay unit, and the output terminal of the first OR gate is connected to the input terminal of the first level conversion unit; the input terminal of the second delay unit is connected to the first input terminal of the first OR gate; the delay duration of the second delay unit is the first delay.

[0012] In some embodiments, the control module further includes: a third switch and a third control unit; a first terminal of the third switch is connected to the first power signal, and a second terminal of the third switch is connected to the control terminal of the transmission module; an input terminal of the third control unit is connected to the first control unit, and an output terminal of the third control unit is connected to the control terminal of the third switch; the third control unit is used to control the third switch to turn off when the mode signal switches to the first level state, and to control the third switch to turn on and, after a first delay, to turn off when the mode signal switches to the second level state.

[0013] In some embodiments, the third control unit includes: a NOT gate and a second OR gate; the input terminal of the NOT gate is connected to the output terminal of the second delay unit, and the output terminal of the NOT gate is connected to the first input terminal of the second OR gate; the second input terminal of the second OR gate is connected to the input terminal of the second delay unit, and the output terminal of the second OR gate is connected to the control terminal of the third switch.

[0014] In some embodiments, the third control unit further includes: a second level conversion unit; the input terminal of the second level conversion unit is connected to the output terminal of the second OR gate, the output terminal of the second level conversion unit is connected to the control terminal of the third switch, and the delay of the second level conversion unit is consistent with the delay of the first level conversion unit.

[0015] In some embodiments, the first switch includes a second PMOS transistor, and the second switch includes a first NMOS transistor.

[0016] In some embodiments, the third switch includes a third PMOS transistor.

[0017] In some embodiments, the voltage difference between the second voltage and the voltage of the first power signal is within the voltage range of 0.2 to 0.3 volts.

[0018] In some embodiments, the mode signal being in a first level state represents an operating state, and the mode signal being in a second level state represents an idle state.

[0019] According to some embodiments, a second aspect of this application provides a memory, including: a circuit module and a power control circuit as described above; the power control circuit is coupled to the circuit module and is used to provide a first power signal to the circuit module in an operating state, and to stop providing the first power signal to the circuit module in an idle state.

[0020] In the power control circuit and memory provided in this application embodiment, the control module responds to different level states of the mode signal and outputs control signals of different voltages. The transmission module, coupled between the main power supply and the circuit modules, is turned on or off under the control of these different voltage control signals to achieve power control of each circuit module. The voltage of the control signal used to control the transmission module to disconnect is higher than the voltage of the main power supply. In this solution, when it is not necessary to provide a power signal to the circuit modules, a second voltage higher than the main power supply voltage is used to control the transmission module to disconnect. Compared to using a signal with a normal power supply voltage to control the transmission module to disconnect, this effectively reduces leakage current, thereby improving the reliability of power control and further reducing power consumption. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of the embodiments of this application.

[0022] Figure 1 This is an example diagram of the architecture of a memory according to an embodiment of this application;

[0023] Figure 2 This is a structural example diagram of a storage cell shown in one embodiment of this application;

[0024] Figure 3 Here is a structural example diagram of a power control circuit;

[0025] Figure 4 A structural example diagram of a power control circuit provided in one embodiment;

[0026] Figure 5 This is a state example diagram of the power supply control circuit under operating conditions;

[0027] Figure 6 This is a state example diagram of the power control circuit in the idle state;

[0028] Figure 7 A structural example diagram of a power control circuit provided in one embodiment;

[0029] Figure 8 Here is a timing diagram for example;

[0030] Figure 9A structural example diagram of a power control circuit provided in one embodiment;

[0031] Figure 10 A structural example diagram of a power control circuit provided in one embodiment;

[0032] Figure 11 Here is a timing diagram for example;

[0033] Figure 12 A structural example diagram of a power control circuit provided in one embodiment;

[0034] Figure 13 Here is a timing diagram for example.

[0035] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0036] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0037] The terms "comprising" and "having" in this application are used to indicate an open-ended inclusion, meaning that additional elements / components / etc. may exist besides those listed. The terms "first" and "second," etc., are used only as markings or distinctions and are not intended to limit the order or quantity of the objects. Furthermore, the different elements and areas in the accompanying drawings are only schematic and are therefore not limited to the dimensions or distances shown in the drawings.

[0038] The technical solution will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0039] Figure 1 This is an example diagram of the memory architecture shown in one embodiment of this application, such as... Figure 1As shown, taking DRAM as an example, it includes data input / output buffers, row decoders, column decoders, sense amplifiers, and a memory array. The memory array mainly consists of word lines, bit lines, and memory cells. Word lines in the memory array extend along the row direction, and bit lines extend along the column direction. The intersection of word lines and bit lines is the memory cell of the memory array.

[0040] Each storage unit is used to store one bit of data. For example... Figure 2 As shown, Figure 2 This is a structural example diagram of a memory cell according to an embodiment of this application. The memory cell mainly consists of a transistor M and a capacitor C. The capacitor is used to store data, and the transistor is used to turn off or on depending on the word line state.

[0041] Access to a memory cell can be achieved by controlling rows and columns. Taking a read scenario as an example: when data needs to be read from a memory cell, the word line of the row containing that memory cell is selected using a row decoder. Correspondingly, transistor M in the diagram turns on, and the state of capacitor C can be detected by sensing and amplifying the bit line signal. For example, if the data stored in the memory cell is 1, then after transistor M turns on, 1 will be read from the bit line of the memory cell, and vice versa. Furthermore, taking a write scenario as an example: when data needs to be written to a memory cell, such as writing 1, the word line of the row containing that memory cell is selected using a row decoder. The corresponding transistor M in the diagram turns on, and by setting the logic level of the bit line to 1, capacitor C is charged, thus writing 1 to the memory cell. Conversely, to write 0, the logic level of the bit line is set to 0, causing capacitor C to discharge, thus writing 0 to the memory cell.

[0042] Based on the above example, it can be understood that the memory contains multiple different circuit modules, such as data input / output buffers, row decoders, column decoders, and sense amplifiers. These circuit modules work together to realize the memory's functions, such as data writing and reading. Therefore, to facilitate power management and save power, some examples use a main power supply. Between the main power supply and each circuit module, there are transmission modules. By controlling the transmission modules to be turned on or off, the supply of power signals to the circuit modules is controlled. These power signals include, but are not limited to, the power supply VCC and / or the ground power VSS.

[0043] As an example, Figure 3 Here is a structural example diagram of a power control circuit, such as... Figure 3As shown, this example illustrates a power control scheme applied to a memory. Taking the power supply VCC as the main power source for the power control circuit as an example, VCC is a main power source, but it is not directly connected to all circuit modules to provide power. The main power supply VCC supplies power to different circuit modules through one or more transmission modules. By controlling the on and off states of the transmission modules (e.g., by applying a low-level signal or a signal with the voltage of VCC to the control terminal of the transmission module), the power supply to different circuit modules in different operating states of the memory can be controlled. For example, in the figure, VCC generates VCCZ through the transmission module to supply power to the logic circuit. Based on power control, when the memory is in an idle state, if the circuit module in the example does not need to work, the transmission module can be turned off, and VCCZ will not be provided to that circuit module to save power consumption. In actual scenarios, the voltage of VCCZ and the voltage of VCC can be the same, so in some descriptions of the following embodiments, the two terms are not clearly distinguished. In practical applications, when the memory is in an idle state, there are some design parameters that need to be optimized as much as possible, such as the IDD2P current. Specifically, IDD2P current refers to the total current consumed by the memory when it is in an idle state, with the clock enable and chip select signals both inactive, the data lines remaining unchanged, and the command / address lines not receiving command and address signals, thus also remaining unchanged. In practical applications, it is desirable to reduce IDD2P current.

[0044] Some aspects of the embodiments of this application relate to the above considerations. The following describes the solutions with reference to some embodiments of this application.

[0045] Example 1

[0046] Figure 4 A structural example diagram of a power control circuit provided in one embodiment is shown below. Figure 4 As shown, the power control circuit includes:

[0047] The control module 11 is coupled to the control terminal of the transmission module 12 and is used to output a control signal of a first voltage in response to the mode signal being in a first level state; and to output a control signal of a second voltage in response to the mode signal being in a second level state.

[0048] The transmission module 12 is coupled between the first power signal VCC and the circuit module 13, and is used to transmit the first power signal VCC to the circuit module 13 in response to a control signal of the first voltage; and to disconnect the transmission in response to a control signal of the second voltage; wherein the first voltage represents a low level state, and the second voltage is higher than the voltage of the first power signal VCC.

[0049] In practical applications, the chip testing circuit provided in this embodiment can be used in various memories. For example, it can be applied to, but is not limited to, Double Data Rate Synchronous Dynamic Random Access Memory (DDR). The mode signal can be understood as a flag signal used to indicate whether the current state is active or idle. In one example, the mode signal at a first level indicates an active state, and the mode signal at a second level indicates an idle state.

[0050] For example, in the active state, i.e., when the memory is in ACTIVE mode, the mode signal is at a high level; conversely, in the idle state, or when the memory is in IDD2P mode, the mode signal is at a low level. That is, in one example, the first level state is high, and the second level state is low. This embodiment does not limit the way the mode signal is generated.

[0051] Taking DDR as an example, combined with Figure 5 and Figure 6 Example illustration: Figure 5 The diagram illustrates the state of the power control circuit during operation. As shown, when the memory is working normally, the mode signal EN is at a high level. For the circuit module to function properly, the control module 11 responds to the high level of the mode signal EN (represented as "1" in the diagram) by outputting a control signal. The voltage of this control signal is the first voltage, which represents a low-level state (represented as "0" in the diagram). The transmission module 12 is activated under the control of the low-level control signal. The first power signal VCC serves as the main power supply, and the transmission module 12 generates the power supply VCCZ for the circuit module 13, supplying power to the circuit module 13.

[0052] Figure 6The diagram illustrates the state of the power control circuit in the idle state. As shown, when the memory is idle, the mode signal EN is at a low level. The circuit module does not need to operate. Correspondingly, the control module 11 responds to the low level of the mode signal EN (0 in the example diagram) and outputs a control signal. The voltage of this control signal is a second voltage, which represents a high level state (1 in the example diagram), and the second voltage VCCH is higher than the voltage of the first power signal VCC. The transmission module 12 is turned off under the control of the high-level control signal. The transmission module 12 between the first power signal VCC and the circuit module 13 is turned off, and no power is supplied to the circuit module 13. It should be noted that in this embodiment, turning off the transmission module 12 with a control signal whose voltage is higher than that of the first power signal can further reduce the leakage current through the transmission module in the off state, thereby achieving the effect of reducing the IDD2P current. The second voltage is the voltage after the control signal reaches a stable state. In one example, the voltage difference between the second voltage and the voltage of the first power signal VCC is in the range of 0.2 to 0.3 volts.

[0053] In this embodiment, the transmission module is turned on at a low level. In practical applications, the specific structure of the transmission module can be implemented by various circuit structures, and this embodiment does not limit it. In one example, the transmission module 12 includes: a first PMOS transistor; the source of the first PMOS transistor receives a first power supply signal VCC, and the drain of the first PMOS transistor is connected to the circuit module 13; the gate of the first PMOS transistor serves as the control terminal of the transmission module 12 and is connected to the control module 11. In this example, the transmission module is implemented using a single MOS device, which can quickly and timely respond to power control while further simplifying the circuit structure and reducing costs.

[0054] In another example, the transmission module 12 may include a transmission gate and an inverter. Specifically, the structure of the transmission gate is not limited; for example, it can be composed of a symmetrical parallel connection of PMOS and NMOS transistors. The input of the inverter is connected to a control signal, and the output is connected to the control terminal (gate) of the NMOS transistor. In practical applications, the transmission gate has low on-resistance and high off-resistance, thus enabling effective power control.

[0055] In order to provide a control signal with a voltage higher than the first power supply signal, in one example... Figure 7 The diagram illustrates the structure of a power control circuit according to one embodiment. The architecture of the control module 11 is illustrated as follows: the control module 11 includes a first switch 111, a second switch 112, and a first control unit 113.

[0056] The first terminal of the first switch 111 is connected to the second power signal VCCH, and the second terminal of the first switch 111 is connected to the control terminal of the transmission module 12; the voltage of the second power signal VCCH is the second voltage.

[0057] The input terminal of the first control unit 113 is connected to the mode signal EN, and the output terminal of the first control unit 113 is connected to the control terminal of the first switch 111. The first control unit 113 is used to control the first switch 111 to turn off when the mode signal EN switches to the first level state, and to control the first switch 111 to turn on after a first delay t1 when the mode signal EN switches to the second level state.

[0058] The first terminal of the second switch 112 is connected to the control terminal of the transmission module 13, the second terminal of the second switch 112 is grounded, and the control terminal of the second switch 112 is connected to the mode signal EN. The second switch 112 is used to turn on when the mode signal EN switches to the first level state and to turn off when the mode signal EN switches to the second level state.

[0059] Combination Figure 8 Example: Figure 8 Here is an example timing diagram, where KsGate represents the signal at the control terminal of the transmission module, i.e., the control signal; K1Gate represents the signal at the control terminal of the first switch; and K2Gate represents the signal at the control terminal of the second switch.

[0060] When the memory is in working state, the mode signal EN is high. Correspondingly, when the mode signal EN is high, the first control unit 113 controls the first switch 111 to turn off, disconnecting the second power signal VCCH from the control terminal of the transmission module 12. Simultaneously, the second switch 112 is turned on when the mode signal EN is high. Therefore, the control terminal of the transmission module 12 is grounded through the turned-on second switch 112. At this time, the voltage at the control terminal of the transmission module 12 is the ground voltage, i.e., a low-level state. Correspondingly, the transmission module 12 turns on in response to the low-level state of the control terminal, and the first power signal VCC generates VCCZ through the turned-on transmission module 12, which is then supplied to the circuit module.

[0061] In one example, the first switch includes a second PMOS transistor, and the second switch includes a first NMOS transistor. It should be noted that the first and second switches can also be implemented using other structures capable of enabling conduction and turn-off, such as transmission gate structures; no other possible methods are limited here.

[0062] When the memory is in an idle state, the mode signal EN is low. Correspondingly, when the mode signal EN switches to a low state, the first control unit 113 first delays for a period of time (t1) before controlling the first switch 111 to turn on. That is, when the mode signal just switches from a high state to a low state, the first switch 111 remains off for a period of time until after the first delay (t1), when it is turned on under the control of the first control unit 113. This allows the second power signal VCCH and the control terminal of the transmission module 12 to be electrically connected through the turned-on first switch 111. Furthermore, when the mode signal switches from a high state to a low state, the second switch 112 turns off, thus disconnecting the control terminal of the transmission module 12 from the ground signal. The voltage at the control terminal is pulled up to a second voltage by the second power signal VCCH through the turned-on first switch 111, and this second voltage is higher than the voltage of the first power signal VCC. Correspondingly, the transmission module 12 turns off in response to the high-level state of the control terminal, and the first power signal VCC is disconnected from the circuit module 13. It should be noted that the "connection" in this embodiment includes both direct connection and indirect connection.

[0063] In this example, the control module consists of two switches and a first control unit. It can output a control signal representing a low-level state and a control signal with a voltage higher than the first power supply signal in both the working and idle states, thereby achieving power control while reducing leakage current. Furthermore, in this embodiment, an appropriate delay is added to the control strategy. Specifically, when switching from the working state to the idle state, the second switch is first disconnected to break the ground. Only after a first delay is the first switch turned on to pull up the voltage at the control terminal of the control unit. This avoids insufficient charging if the first switch turns on before the second switch is grounded during the voltage pull-up process, thus preventing energy waste and saving energy consumption.

[0064] The implementation structure of the first control unit is not limited. In some examples, Figure 9 A structural example diagram of a power control circuit provided in one embodiment is shown below. Figure 9 As shown, the first control unit 113 includes: a first logic unit 21 and a first level conversion unit 22; wherein,

[0065] The input terminal of the first logic unit 21 is connected to the mode signal EN, and the output terminal of the first logic unit 21 is connected to the input terminal of the first level conversion unit 22. The first logic unit 21 is used to output a signal with a first level state when the received signal is switched to a first level state, and to output a signal with a second level state after a first delay t1 when the received signal is switched to a second level state.

[0066] The output terminal of the first level conversion unit 22 is connected to the control terminal of the first switch 111; the first level conversion unit 22 is used to convert the voltage of the received high-level signal into a second voltage.

[0067] The duration of the first delay t1 can be set according to the situation. In conjunction with the foregoing, the first terminal of the first switch 111 is connected to the second power signal VCCH. The voltage of the second power signal VCCH is a second voltage, which is higher than the voltage of the usual first power signal VCC. Therefore, in order to further ensure the effective conduction and cutoff of the first switch 111, a suitable control voltage is adapted to the first switch 111.

[0068] Specifically, in this example, a first level conversion unit 22 is provided to convert the voltage of the received signal, which is a signal representing a high-level state, into a voltage adapted to the first switch 111, such as a second voltage. As an example, the first level conversion unit 22 may include a level converter.

[0069] Taking a PMOS transistor as an example, when the first switch is to be turned on, the first level conversion unit 22 will receive a signal representing a low-level state. In this case, no voltage conversion is needed because the source of the first switch is connected to the second power supply signal. When the gate of the first switch receives the signal representing a low-level state, a voltage difference is formed between the gate and source of the first switch, and the magnitude of this voltage difference reaches the turn-on threshold voltage of the PMOS transistor, thus the first switch can be turned on promptly. Conversely, when the first switch is to be turned off, the first level conversion unit 22 will receive a signal representing a high-level state (e.g., the voltage of the first power supply signal VCC). The source of the first switch is connected to the second power supply signal, and the voltage of the second power supply signal is a second voltage, higher than the voltage of VCC. The voltage at the gate of the PMOS transistor is still lower than the voltage at the source, resulting in incomplete turn-off. Therefore, in this example, the first level conversion unit 22 is configured to convert the voltage of the received signal when it receives a signal representing a high-level state, obtaining a signal with a voltage magnitude equal to the second voltage, to effectively control the first switch to turn off.

[0070] The first logic unit 21 is mainly used to control the on and off timing of the first switch. Specifically, when the memory switches from an idle state to an operating state, the mode signal EN received by the first logic unit 21 switches from a low level to a high level. In one example, the first logic unit 21 is responsible for responding to the change in the level state by immediately transmitting the changed mode signal EN to the first level conversion unit 22 for voltage conversion, thereby controlling the first switch 111 to turn off. This ensures that when switching from an idle state to an operating state, the voltage at the control terminal of the transmission module is pulled down in a timely manner, controlling the transmission module to turn on. On the other hand, when the memory switches from the working state to the idle state, the mode signal EN received by the first logic unit 21 switches from a high level to a low level. In one example, the first logic unit 21 is responsible for responding to the change in the level state and still maintaining the previous output (the signal in the high level state). Correspondingly, the first level conversion unit 22 still performs voltage conversion, and the first switch 111 remains off. After a first delay t1, the first logic unit 21 transmits the changed mode signal EN (which is now in the low level state) to the first level conversion unit 22. The first level conversion unit 22 does not need to perform voltage conversion and outputs a low level signal to the first switch 111 to control the first switch 111 to turn on. This achieves a delayed pull-up of the voltage at the control terminal of the transmission module when switching from the working state to the idle state, so as to delay the shutdown of the transmission module and improve the reliability of power control.

[0071] As an example, such as Figure 9 As shown, the first logic unit 21 includes: a second delay unit 211 and a first OR gate 212; wherein, the first input terminal of the first OR gate 212 is connected to the mode signal EN, the second input terminal of the first OR gate 212 is connected to the output terminal of the second delay unit 211, and the output terminal of the first OR gate 212 is connected to the input terminal of the first level conversion unit 22; the input terminal of the second delay unit 211 is connected to the first input terminal of the first OR gate 212; the delay duration of the second delay unit 211 is a first delay t1.

[0072] Specifically, when the memory switches from an idle state to an active state, the mode signal EN flips from a low level to a high level. Correspondingly, the first input terminal of the first OR gate 212 and the input terminal of the second delay unit 211 receive the high-level mode signal. Although the second input terminal of the first OR gate 212 has not yet received the high-level signal due to the delay transmission of the second delay unit 211, since the first input terminal of the first OR gate 212 has already received the high-level signal, through OR logic operation, the first OR gate 212 immediately outputs the high-level signal to the first level conversion unit 22 for voltage conversion. The converted high-level signal is transmitted to the first switch 111, and the first switch 111 is turned off. In another scenario, when the memory switches from an active state to an idle state, the mode signal EN flips from a high level to a low level. Correspondingly, the first input of the first OR gate 212 and the input of the second delay unit 211 receive the low-level mode signal. The output of the first OR gate 212 depends on the signal received at the second input. Due to the delayed transmission of the second delay unit 211, the second input of the first OR gate 212 has not yet received the low-level signal after the flip, meaning that the currently received signal is still a high-level signal. Therefore, the first OR gate 212 still outputs a high-level signal, and the first switch 111 remains off. Until the low-level mode signal reaches the second input of the first OR gate 212 after the delayed transmission of the second delay unit 211, after OR logic operation, both inputs are currently low-level signals. Therefore, the output of the first OR gate 212 flips to a low-level signal, and the first switch turns on.

[0073] In the above example, the first logic unit is constructed by using a delay unit and an OR gate, which can realize immediate or delayed control of the first switch according to the switching of the mode signal, and can simplify the circuit and save costs.

[0074] In this example, the first control unit includes a first logic unit and a first level conversion unit. The first logic unit is used to control the on and off timing of the first switch, and the first level conversion unit is used to convert the received high-level signal into voltage to adapt to the control voltage of the first switch, thereby realizing effective control of the first switch and timely and reliable power control.

[0075] Furthermore, considering the delay matching of the entire circuit, in one example, Figure 10 A structural example diagram of a power control circuit provided in one embodiment is shown below. Figure 10 As shown, the control module 11 also includes: a second control unit 114;

[0076] The input terminal of the second control unit 114 is connected to the mode signal EN, and the output terminal of the second control unit 114 is connected to the control terminal of the second switch 112.

[0077] The second control unit 114 is used to control the second switch 112 to turn on after a second delay t2 when the mode signal EN switches to the first level state, and to control the second switch 112 to turn off when the mode signal EN switches to the second level state.

[0078] Combination Figure 11 Example: Figure 11 This is a timing diagram for an example. When the memory switches from an idle state to an active state, the mode signal EN switches from a low level to a high level. The first control unit 113 immediately controls the first switch 111 to turn off, disconnecting the second power signal VCCH from the control terminal of the transmission module 12. Simultaneously, when the mode signal EN switches from a low level to a high level, the second switch 112, under the control of the second control unit 114, remains off until it turns on after a second delay t2. The control terminal of the transmission module 12 is grounded through the on-state second switch 112. The transmission module 12 turns on in response to the low-level state of the control terminal. The first power signal VCC generates VCCZ through the on-state transmission module 12 and provides it to the circuit module, which then begins to operate. When the memory switches from an active state to an idle state, the mode signal EN switches from a high level to a low level. When the mode signal EN switches to a low level, the first control unit 113 first delays for a first time t1, and then controls the first switch 111 to turn on. The second power signal VCCH and the control terminal of the transmission module 12 are electrically connected through the turned-on first switch 111. When the mode signal EN switches from a high level to a low level, the second switch 112 is immediately turned off. Therefore, the control terminal of the transmission module 12 is disconnected from the ground voltage, and the voltage at the control terminal is pulled up to a second voltage, which is higher than the voltage of the first power signal VCC. Correspondingly, the transmission module 12 turns off in response to the high level state of the control terminal, and the first power signal VCC is disconnected from the circuit module 13.

[0079] In some examples, such as Figure 10 As shown, the second control unit 114 includes: a first delay unit 31 and an AND gate 32; wherein, the first input terminal of the AND gate 32 is connected to the output terminal of the first delay unit 31, the second input terminal of the AND gate 32 is connected to the mode signal EN, and the output terminal of the AND gate 32 is connected to the control terminal of the second switch 112; the input terminal of the first delay unit 31 is connected to the second input terminal of the AND gate 32, and the first delay unit 31 is used to transmit the received signal to the first input terminal of the AND gate 32 after a second delay t2.

[0080] The delay of the first delay unit is the second delay t2. The duration of the second delay t2 can be set according to the situation. For example, the durations of the first delay t1 and the second delay t2 can be the same or different. In practical applications, t2 can be set to a smaller value or no delay can be set to ensure timely power supply. Specifically, when the memory switches from an idle state to an active state, the mode signal EN flips from a low level to a high level. Correspondingly, the second input of AND gate 32 and the input of the first delay unit 31 receive the high-level mode signal. The output of AND gate 32 depends on the signal received at the first input. Because of the delay transmission of the first delay unit 31, the first input of AND gate 32 has not yet received the high-level signal after the flip, that is, the currently received signal is still a low-level signal. Therefore, AND gate 32 still outputs a low-level signal, and the second switch 112 remains off. Until the high-level mode signal reaches the first input of AND gate 32 after the delay transmission of the first delay unit 31, after AND logic operation, both inputs are currently high-level signals. Therefore, the output of AND gate 32 flips to a high-level signal, and the second switch 112 turns on.

[0081] In another scenario, when the memory switches from an active state to an idle state, the mode signal EN flips from a high level to a low level. Correspondingly, the second input of AND gate 32 receives the low-level mode signal. Although the first input of AND gate 32 has not yet received the low-level signal due to the delay provided by the first delay unit 31, the second input of AND gate 32 has already received the low-level signal. Through AND logic operation, AND gate 32 immediately outputs a low-level signal to the second switch 112, turning off the second switch 112. In this example, the delay unit and AND gate constitute the second control unit, thereby simplifying the circuit structure.

[0082] In the above example, when switching from idle state to working state, the first switch is first turned off to disconnect the control terminal of the transmission module from the second power signal. After a second delay, the second control unit turns on the second switch to ground the control terminal of the transmission module. This avoids the situation where the second switch turns on too early while the first switch is still connected to the second power signal during the voltage pull-down process of the control terminal of the transmission module, which would lead to an increased discharge. This avoids wasting power, saves energy, and improves the reliability of power control.

[0083] Based on the foregoing, when the memory switches from an active state to an idle state, the transmission module needs to be disconnected to cut off the power supply to the circuit module. In one example, the transmission module is turned on at a low level and turned off at a high level. In this embodiment, the transmission module is turned off by raising the voltage at the control terminal of the transmission module to a stable state to reach a second voltage, wherein the second voltage is higher than the voltage of the first power supply signal.

[0084] In practical applications, a large charging current is required to quickly raise the voltage at the control terminal of the transmission module to the second voltage. Therefore, to save power, in one example, Figure 12 A structural example diagram of a power control circuit provided in one embodiment is shown below. Figure 12 As shown, the control module 11 also includes: a third switch 115 and a third control unit 116;

[0085] The first end of the third switch 115 is connected to the first power signal VCC, and the second end of the third switch 115 is connected to the control end of the transmission module 12.

[0086] The input terminal of the third control unit 116 is connected to the first control unit 113, and the output terminal of the third control unit 116 is connected to the control terminal of the third switch 115. The third control unit 116 is used to control the third switch 115 to turn off when the mode signal EN switches to the first level state, and to control the third switch 115 to turn on and turn off after a first delay t1 when the mode signal EN switches to the second level state.

[0087] Combination Figure 13 The timing diagram shown illustrates the operation of the power supply control circuit: Figure 13 This is an example timing diagram, where KsGate represents the signal at the control terminal of the transmission module, K1Gate represents the signal at the control terminal of the first switch, K2Gate represents the signal at the control terminal of the second switch, and K3Gate represents the signal at the control terminal of the third switch. In one example, the third switch includes a third PMOS transistor. It should be noted that the third switch can also be implemented using other structures capable of turning on and off, such as transmission gate structures, etc., and other possible methods are not limited here.

[0088] Combination Figure 12 and Figure 13As shown, when the memory switches from an idle state to an active state, the mode signal EN flips from a low level to a high level. Correspondingly, the first control unit 113 controls the first switch 111 to open, thus disconnecting the second power signal VCCH from the control terminal of the transmission module 12. Simultaneously, when the mode signal EN flips from a low level to a high level, the third control unit 116 immediately controls the third switch 115 to close, thus disconnecting the first power signal VCC from the control terminal of the transmission module 12. Furthermore, when the mode signal EN flips from a low level to a high level, the second switch 112 remains in the off state before the mode signal EN flipped to a high level until after a second delay t2, at which point the second control unit 114 controls the second switch 112 to open. The voltage at the control terminal of the transmission module 12 is grounded through the open second switch 112, the transmission module 12 is turned on, and the circuit module 13 is powered.

[0089] When the memory switches from an active state to an idle state, the mode signal EN flips from a high level to a low level. Correspondingly, the second control unit 114 immediately controls the second switch 112 to open. Simultaneously, the third control unit 116 first controls the third switch 115 to open, electrically connecting the first power signal VCC and the control terminal of the transmission module 12. The voltage at the control terminal of the transmission module 12 is pulled up by VCC until a first delay t1 has elapsed. During this period, the first switch 111 remains in its previous off state, meaning the second power signal VCCH and the control terminal of the transmission module 12 remain connected. In the disconnected state, the first power signal VCC charges the control terminal of the transmission module 12 until the first delay t1 has elapsed. After the first delay t1, the third control unit 116 controls the third switch 115 to turn off, while the first control unit 113 controls the first switch 111 to turn on. That is, the control terminal of the transmission module 12 disconnects from the first power signal VCC and connects to the second power signal VCCH. The second power signal VCCH continues to charge the control terminal of the transmission module 12 until the second voltage reaches a stable state. The transmission module 12 is then completely turned off, and the circuit module 13 stops supplying power.

[0090] As an example, such as Figure 12 As shown, the third control unit 116 includes: a NOT gate 41 and a second OR gate 42; wherein,

[0091] The input terminal of NOT gate 41 is connected to the output terminal of the second delay unit 211, and the output terminal of NOT gate 41 is connected to the first input terminal of the second OR gate 42.

[0092] The second input terminal of the second OR gate 42 is connected to the input terminal of the second delay unit 211, and the output terminal of the second OR gate 42 is connected to the control terminal of the third switch 115.

[0093] It should be noted that the specific implementation structures of the aforementioned modules and units, such as the control units and switches, can also be other possible structures. The circuit structure shown in the figure is only an example, and this embodiment does not exclude other possible implementation methods.

[0094] Specifically, in combination Figure 12 In the structure shown, when the memory switches from an idle state to an active state, the mode signal EN flips from a low level to a high level. Correspondingly, the first logic unit 21 responds to the received high-level signal and outputs a high-level signal. The first level conversion unit 22 performs voltage conversion on the high-level signal output by the first logic unit 21 and outputs a high-level signal with a voltage of the second voltage, thereby controlling the first switch 111 to open and disconnecting the second power signal VCCH from the control terminal of the transmission module 12. At the same time, when the mode signal EN flips from a low level to a high level, the second input terminal of the second OR gate 42 receives a high-level mode signal and immediately outputs a high-level signal, thereby controlling the third switch 115 to close, that is, disconnecting the first power signal VCC from the control terminal of the transmission module 12. Furthermore, when the mode signal EN flips from a low level to a high level, the second switch 112 remains in the closed state before the mode signal EN flips to a high level until after a second delay t2, at which point the second control unit 114 controls the second switch 112 to open. The voltage at the control terminal of the transmission module 12 is grounded through the conducting second switch 112, the transmission module 12 is turned on, and the circuit module 13 is powered.

[0095] When the memory switches from an active state to an idle state, the mode signal EN flips from a high level to a low level. Correspondingly, the second control unit 114 immediately controls the second switch 112 to open. Simultaneously, because the input of the NOT gate 41 in the second delay unit 211 of the first logic unit 21 has not yet received the low-level mode signal, the NOT gate 41 still outputs a low-level signal to the first input of the second OR gate 42. At this time, the second input of the second OR gate 42 has received the low-level mode signal, so the output of the second OR gate 42 flips from a high level to a low level, turning on the third switch 115. Again, because the second delay unit 211 has not yet received the flipped low-level signal, the second input of the first OR gate 212 still receives a high-level signal, so the first OR gate 212 outputs a high-level signal. The first switch 111 remains in its previous off state, and the first power signal VCC charges the control terminal of the transmission module 12. After the first delay t1 of the second delay unit, the second delay unit 211 outputs a low-level mode signal. After receiving the low-level signal, the input terminal of the NOT gate 41 outputs a high-level signal to the first input terminal of the second OR gate 42. The second OR gate 42 outputs a high-level state, controlling the third switch 15 to open. At the same time, the low-level mode signal output by the second delay unit 211 is also transmitted to the second input terminal of the first OR gate 212. The output of the first OR gate 212 flips to a low-level signal, the first switch 111 is turned on, and the second power signal VCCH charges the control terminal of the transmission module 12 until it stabilizes at the second voltage. The transmission module 12 is then completely turned off, and the circuit module 13 stops supplying power.

[0096] In the above example, the third control unit is constructed using NOT gates and OR gates. It can control the third switch immediately or with a delay according to the switching of the mode signal. Then, with the cooperation of the third switch and the first switch, the voltage at the control terminal of the transmission module is stepped up, thereby realizing power control and saving charging current and power consumption.

[0097] In one example, to match the signal delay, such as Figure 12 As shown, the third control unit 116 further includes a second level conversion unit 43; the input terminal of the second level conversion unit 43 is connected to the output terminal of the second OR gate 42, and the output terminal of the second level conversion unit 43 is connected to the control terminal of the third switch 115. The delay of the second level conversion unit 43 is consistent with the delay of the first level conversion unit 22. Optionally, the second level conversion unit 43 may include a level converter. In this example, by setting the second level conversion unit, the delay generated by the first level conversion unit can be matched, the time difference of the control signals received by the first switch and the third switch can be calibrated, the timing accuracy of the coordinated action of the first switch and the third switch can be improved, and the reliability of power control can be further enhanced.

[0098] In this example, by setting a third control unit and a third switch, the third control unit is used to control the on and off timing of the third switch, thereby achieving a step-by-step increase in the voltage at the control terminal of the transmission module under the combined action of the third switch and the first switch, so as to save charging current and power consumption while realizing power control.

[0099] In the power control circuit provided in this embodiment, the control module responds to different level states of the mode signal and outputs control signals of different voltages. The transmission module, coupled between the main power supply and the circuit modules, is turned on or off under the control of the control signals of different voltages to realize power control of each circuit module. The voltage of the control signal used to control the transmission module to disconnect is higher than the voltage of the main power supply. In this solution, when it is not necessary to provide a power signal to the circuit modules, a second voltage higher than the main power supply voltage is used to control the transmission module to disconnect. Compared with using a signal of ordinary power supply voltage to control the transmission module to disconnect, leakage current can be effectively reduced, thereby improving the reliability of power control and further reducing power consumption.

[0100] Example 2

[0101] Embodiment 2 of this application provides a memory, which includes: a circuit module and a power control circuit as described above; wherein...

[0102] The power control circuit, coupled to the circuit module, is used to provide a first power signal to the circuit module in the working state, and to stop providing the first power signal to the circuit module in the idle state.

[0103] As an example, when the memory is working normally, the mode signal is in a high-level state. For the circuit module to function normally, the control module of the power control circuit responds to the high-level state of the mode signal by outputting a control signal. The voltage of this control signal is a first voltage, which represents a low-level state. The transmission module of the power control circuit is turned on under the control of the low-level control signal. The first power signal serves as the main power supply, and through the transmission module of the power control circuit, it generates power for the circuit module, supplying power to it.

[0104] When the memory is idle, the mode signal is in a low-level state. The circuit module does not need to operate. Correspondingly, the control module of the power control circuit responds to the low-level state of the mode signal and outputs a control signal. The voltage of this control signal is a second voltage, which represents a high-level state and is higher than the voltage of the first power signal. Under the control of the high-level control signal, the transmission module of the power control circuit is turned off, and the transmission module between the first power signal and the circuit module is turned off, thus not supplying power to the circuit module. It should be noted that in this embodiment, turning off the transmission module with a control signal whose voltage is higher than that of the first power signal can further reduce the leakage current through the transmission module in the off state, thereby achieving the effect of reducing the IDD2P current. Here, the second voltage is the voltage after the control signal reaches a stable state.

[0105] In the memory provided in this embodiment, the control module of the power control circuit outputs control signals of different voltages in response to different level states of the mode signal. The transmission module, coupled between the main power supply and the circuit modules, is turned on or off under the control of these different voltage control signals to achieve power control of each circuit module. The voltage of the control signal used to control the transmission module to disconnect is higher than the voltage of the main power supply. In this solution, when it is not necessary to provide a power signal to the circuit modules, a second voltage higher than the main power supply voltage is used to control the transmission module to disconnect. Compared to using a signal with a normal power supply voltage to control the transmission module to disconnect, this effectively reduces leakage current, thereby improving the reliability of power control and further reducing power consumption.

[0106] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0107] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A power supply control circuit, characterized in that, include: The control module, coupled to the control terminal of the transmission module, is used to output a control signal of the first voltage in response to the mode signal being in the first level state; And, in response to the mode signal being in the second level state, a control signal for outputting a second voltage; The transmission module is coupled between the first power signal and the circuit module, and is used to transmit the first power signal to the circuit module in response to the control signal of the first voltage. In addition, in response to a control signal of the second voltage, transmission is disconnected; wherein the first voltage represents a low-level state, and the second voltage is higher than the voltage of the first power supply signal. The transmission module includes: a first PMOS transistor; The source of the first PMOS transistor receives the first power signal, and the drain of the first PMOS transistor is connected to the circuit module; the gate of the first PMOS transistor serves as the control terminal of the transmission module and is connected to the control module. The control module includes: a first switch, a second switch, and a first control unit; The first terminal of the first switch is connected to the second power signal, and the second terminal of the first switch is connected to the control terminal of the transmission module; the voltage of the second power signal is the second voltage. The input terminal of the first control unit is connected to the mode signal, and the output terminal of the first control unit is connected to the control terminal of the first switch; the first control unit is used to control the first switch to turn off when the mode signal switches to the first level state, and to control the first switch to turn on after a first delay when the mode signal switches to the second level state. The first terminal of the second switch is connected to the control terminal of the transmission module, the second terminal of the second switch is grounded, and the control terminal of the second switch is connected to the mode signal; the second switch is used to turn on when the mode signal switches to the first level state and to turn off when the mode signal switches to the second level state.

2. The power control circuit according to claim 1, characterized in that, The control module further includes: a second control unit; The input terminal of the second control unit is connected to the mode signal, and the output terminal of the second control unit is connected to the control terminal of the second switch; The second control unit is configured to control the second switch to turn on after a second delay when the mode signal switches to the first level state, and to control the second switch to turn off when the mode signal switches to the second level state.

3. The power control circuit according to claim 2, characterized in that, The second control unit includes: a first delay unit and an AND gate; The first input terminal of the AND gate is connected to the output terminal of the first delay unit, the second input terminal of the AND gate is connected to the mode signal, and the output terminal of the AND gate is connected to the control terminal of the second switch. The input terminal of the first delay unit is connected to the second input terminal of the AND gate. The first delay unit is used to transmit the received signal to the first input terminal of the AND gate after the second delay.

4. The power control circuit according to claim 1, characterized in that, The first control unit includes: a first logic unit and a first level conversion unit; The input terminal of the first logic unit is connected to the mode signal, and the output terminal of the first logic unit is connected to the input terminal of the first level conversion unit; the first logic unit is used to output a signal with the first level state when the received signal switches to the first level state, and to output a signal with the second level state after the first delay when the received signal switches to the second level state. The output terminal of the first level conversion unit is connected to the control terminal of the first switch; the first level conversion unit is used to convert the voltage of the received high-level signal into the second voltage.

5. The power control circuit according to claim 4, characterized in that, The first logic unit includes: a second delay unit and a first OR gate; The first input terminal of the first OR gate is connected to the mode signal, the second input terminal of the first OR gate is connected to the output terminal of the second delay unit, and the output terminal of the first OR gate is connected to the input terminal of the first level conversion unit. The input terminal of the second delay unit is connected to the first input terminal of the first OR gate; the delay duration of the second delay unit is the first delay.

6. The power control circuit according to claim 5, characterized in that, The control module further includes: a third switch and a third control unit; The first end of the third switch is connected to the first power signal, and the second end of the third switch is connected to the control end of the transmission module; The input terminal of the third control unit is connected to the first control unit, and the output terminal of the third control unit is connected to the control terminal of the third switch. The third control unit is used to control the third switch to turn off when the mode signal switches to the first level state, and to control the third switch to turn on and then turn off after the first delay when the mode signal switches to the second level state.

7. The power control circuit according to claim 6, characterized in that, The third control unit includes: a NOT gate and a second OR gate; The input terminal of the NOT gate is connected to the output terminal of the second delay unit, and the output terminal of the NOT gate is connected to the first input terminal of the second OR gate. The second input terminal of the second OR gate is connected to the input terminal of the second delay unit, and the output terminal of the second OR gate is connected to the control terminal of the third switch.

8. The power control circuit according to claim 7, characterized in that, The third control unit further includes: a second level conversion unit; The input terminal of the second level conversion unit is connected to the output terminal of the second OR gate, the output terminal of the second level conversion unit is connected to the control terminal of the third switch, and the delay of the second level conversion unit is the same as the delay of the first level conversion unit.

9. The power control circuit according to any one of claims 1-8, characterized in that, The first switch includes a second PMOS transistor, and the second switch includes a first NMOS transistor.

10. The power control circuit according to any one of claims 6-8, characterized in that, The third switch includes a third PMOS transistor.

11. The power control circuit according to any one of claims 1-8, characterized in that, The voltage difference between the second voltage and the voltage of the first power signal is within the voltage range of 0.2 to 0.3 volts.

12. The power control circuit according to any one of claims 1-8, characterized in that, The mode signal being in a first level state indicates the working state, and the mode signal being in a second level state indicates the idle state.

13. A memory, characterized in that, include: The circuit module and the power control circuit as described in any one of claims 1-12; The power control circuit, coupled to the circuit module, is used to provide a first power signal to the circuit module in the working state, and to stop providing the first power signal to the circuit module in the idle state.

Images