control circuit

Abstract

The present disclosure provides a control circuit, comprising a random module, a first input end receiving a refresh count signal, a second input end receiving random data, a control end connected to an output end of an output module, for processing the refresh count signal and the random data based on a row hammer refresh signal output by the output module to obtain and output a random signal, an output module, a first input end receiving the refresh count signal, a second input end connected to an output end of the random module, for generating and outputting the row hammer refresh signal according to the random signal and the refresh count signal. Through such a setting, random addition and subtraction on a fixed row hammer refresh frequency is realized, and the risk of row hammer attack is reduced.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, a control circuit. Background Technology

[0002] In memory, when the word line corresponding to a row address in a memory cell is frequently turned on, it may cause the leakage rate of the capacitors at adjacent addresses to be higher than the natural leakage rate. This can lead to data loss due to excessive charge loss of the capacitors at adjacent addresses before the refresh signal arrives. This situation is generally called the "row hammer effect".

[0003] To suppress the row hammer effect, the row hammer address needs to be refreshed promptly to replenish its charge and prevent data errors. This refresh operation is called Row Hammer Refresh (RHR). Since the specification does not define a specific refresh command, RHR can only be implemented using regular refresh operations. Typically, a row hammer refresh is performed after several regular refreshes. Summary of the Invention

[0004] One embodiment of this disclosure provides a control circuit, including: The random module has a first input terminal that receives a refresh count signal, a second input terminal that receives random data, and a control terminal that is connected to the output terminal of the output module. It is used to process the refresh count signal and the random data based on the row hammer refresh signal output by the output module to obtain and output a random signal. The output module has a first input terminal that receives the refresh count signal and a second input terminal that is connected to the output terminal of the random module, and is used to generate and output the row hammer refresh signal based on the random signal and the refresh count signal.

[0005] In some embodiments, the output module includes: A periodic control signal generation unit has a first input terminal that receives the refresh count signal and a second input terminal that is connected to the second output terminal of the hammer refresh signal generation unit. It is used to generate a periodic control signal based on the complementary hammer refresh signal output by the hammer refresh signal generation unit and the refresh count signal. The hammer refresh signal generation unit has a first input terminal connected to the output terminal of the random module and a second input terminal connected to the output terminal of the periodic control signal generation unit. It is used to generate the hammer refresh signal and the complementary hammer refresh signal according to the periodic control signal and the random signal. The hammer refresh signal is output from the first output terminal and the complementary hammer refresh signal is output from the second output terminal. The hammer refresh signal and the complementary hammer refresh signal are out of phase with each other.

[0006] In some embodiments, the start time of the effective state of the periodic control signal is the time when the refresh count signal represents a count value of a set value; the end time of the effective state of the periodic control signal is the end time when the row hammer refresh signal is in an effective state.

[0007] In some embodiments, the periodic control signal generation unit includes: The start trigger circuit receives the refresh count signal at its input terminal and is used to generate a start trigger signal based on the refresh count signal. The start trigger signal determines the start time of the effective state of the periodic control signal. The termination trigger circuit has its input terminal connected to the second output terminal of the row hammer refresh signal generation unit, and is used to generate a termination trigger signal based on the complementary row hammer refresh signal. The termination trigger signal determines the termination time of the effective state of the periodic control signal. The first latch has its first input terminal connected to the output terminal of the start trigger circuit and its second input terminal connected to the output terminal of the stop trigger circuit, and is used to generate the periodic control signal based on the start trigger signal and the stop trigger signal.

[0008] In some embodiments, the refresh count signal includes a plurality of count sub-signals, and the start trigger circuit includes: The OR gate has the same number of input terminals as the number of the counting sub-signals. Each input terminal receives one of the counting sub-signals and is used to perform an OR operation on multiple counting sub-signals to output the start trigger signal.

[0009] In some embodiments, the termination trigger circuit includes: The first delay circuit has its input terminal connected to the first input terminal of the first NAND gate and its output terminal connected to the input terminal of the first inverter. It is used to delay the complementary horizontal hammer refresh signal. The output of the first inverter is connected to the second input of the first NAND gate; The first NAND gate has its first input terminal connected to the second output terminal of the row hammer refresh signal generation unit, and outputs the termination trigger signal.

[0010] In some embodiments, the first latch includes: The second NAND gate has its first input terminal serving as the first input terminal of the first latch, and its second input terminal connected to the output terminal of the third NAND gate, the output terminal of which serves as the output terminal of the first latch. The third NAND gate has its first input terminal connected to the output terminal of the second NAND gate, and its second input terminal serving as the second input terminal of the first latch.

[0011] In some embodiments, the row hammer refresh signal generation unit includes: The fourth NAND gate has its first input connected to the output of the random module, its second input connected to the output of the periodic control signal generation unit, and its output serving as the second output of the row hammer refresh signal generation unit to output the complementary row hammer refresh signal. The third inverter has its input connected to the fourth NAND gate, and its output serves as the first output of the horizontal hammer refresh signal generation unit to output the horizontal hammer refresh signal.

[0012] In some embodiments, after the row hammer refresh signal changes from an active state to an inactive state, the random module updates the random signal at its output.

[0013] In some embodiments, the random module includes: The control unit receives random data at its input terminal and is connected to the output terminal of the output module. It is used to output the random data after the row hammer refresh signal changes from an active state to an inactive state. A random signal generation unit, whose control terminal is connected to the output terminal of the control unit and whose input terminal receives the refresh count signal, is used to generate the random signal according to the refresh count signal under the control of the random data.

[0014] In some embodiments, the control unit includes: The first trigger circuit has its input terminal connected to the output terminal of the output module and is used to generate a first trigger signal based on the row hammer refresh signal. The second latch has its clock terminal connected to the output terminal of the first trigger circuit and its input terminal receiving the random data, and is used to output the random data under the control of the first trigger signal.

[0015] In some embodiments, the first trigger circuit includes: The second delay circuit has its input terminal connected to the first input terminal of the NOR gate and its output terminal connected to the input terminal of the second inverter; it is used to delay the row hammer refresh signal. The output of the second inverter is connected to the second input of the NOR gate; The NOR gate has its first input terminal connected to the output terminal of the output module, and is used to output the first trigger signal.

[0016] In some embodiments, the random signal generation unit includes: The decoder receives the refresh count signal at its input terminal and outputs a first identifier signal and a second identifier signal when the decoder is operating in a first decoding mode. When the refresh count signal is the count value represented by the first identifier signal, the first identifier signal is valid. When the refresh count signal is the count value represented by the second identifier signal, the second identifier signal is valid. The count values ​​represented by the first identifier signal and the count values ​​represented by the second identifier signal are different. The selector, whose input is connected to the output of the decoder and whose control is connected to the output of the control unit, is used to select one output from the first identification signal and the second identification signal based on the random data.

[0017] In some embodiments, the random signal generation unit further includes: a controller; The decoder is also used to output the first identification signal, the second identification signal, and the third identification signal when operating in the second decoding mode; when the refresh count signal is the count value represented by the third identification signal, the third identification signal is in a valid state; the count values ​​represented by the first identification signal, the second identification signal, and the third identification signal are all different; The controller is used to control the selector to select an output from the first identifier signal, the second identifier signal, and the third identifier signal based on the random data when the decoder is operating in the second decoding mode.

[0018] In some embodiments, the difference between the first identification signal characterization count value and the second identification signal characterization count value is 1, 2, or 3; The difference between the count value represented by the first identification signal and the count value represented by the third identification signal is 1, 2 or 3.

[0019] Another embodiment of this disclosure provides a memory including the control circuitry described in the above embodiments.

[0020] The control circuit disclosed herein includes a random module and an output module. The control terminal of the random module is connected to the output terminal of the output module, and the output terminal of the random module is connected to the second input terminal of the output module. The random module processes the refresh count signal and random data based on the row hammer refresh signal output by the output module to obtain and output a random signal. The output module generates and outputs the row hammer refresh signal based on the random signal and the refresh count signal. The refresh count signal determines a fixed row hammer refresh frequency, and the random signal modifies the frequency of the row hammer refresh signal based on the fixed refresh frequency, reducing the risk of hackers using row hammer attacks to alter stored data. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0022] Figure 1 A schematic diagram of a control circuit provided in an embodiment of this disclosure; Figure 2A A schematic diagram of a termination trigger circuit provided in an embodiment of this disclosure; Figure 2B A schematic diagram of another termination trigger circuit provided in an embodiment of this disclosure; Figure 3 A timing diagram of a termination trigger circuit provided in an embodiment of this disclosure; Figure 4 A timing diagram of a first latch circuit provided in an embodiment of this disclosure; Figure 5 A schematic diagram of a random module provided in an embodiment of this disclosure; Figure 6A A schematic diagram of a first trigger circuit provided in an embodiment of this disclosure; Figure 6B A schematic diagram of another first trigger circuit provided in an embodiment of this disclosure; Figure 7 A timing diagram of a first trigger circuit provided in an embodiment of this disclosure; Figure 8 A timing diagram of a control circuit provided in an embodiment of this disclosure.

[0023] Figure label: 100. Output module; 110. Periodic control signal generation unit; 120. Row hammer refresh signal generation unit; 121. Fourth NAND gate; 122. Third inverter; 200. Random module; 210. Control unit; 220. Random signal generation unit; 310. Start trigger circuit; 311. OR gate; 320. Stop trigger circuit; 321. First delay circuit; 322. First inverter; 323. First NAND gate; 324. Fourth inverter; 325. First buffer; 330. First latch; 331. Second NAND gate; 332. Third NAND gate; 410. First trigger circuit; 411. Second delay circuit; 412. Second inverter; 413. NOR gate; 414. Fifth inverter; 415. Second buffer; 420. Second latch; 430. Decoder; 440. Selector.

[0024] The accompanying drawings have illustrated specific embodiments of this disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0025] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0026] Typically, a horizontal hammer refresh occurs after multiple refreshes. The refresh counter's count is monitored, and a horizontal hammer refresh operation is performed when the refresh counter reaches a certain set value. For example, if the refresh counter is a 3-bit counter, and the refresh count signal CBR output by the refresh counter is marked CBR<2:0>, a horizontal hammer refresh operation is performed when the count value of CBR<2:0> is zero. This achieves a horizontal hammer refresh after 8 refreshes, meaning the horizontal hammer refresh frequency is 1 / 8.

[0027] However, the refresh rate of the aforementioned row hammer refresh is fixed, and the risk of row hammer attacks still exists. This disclosure aims to provide a scheme to change the RHR frequency in order to reduce the risk of hackers using row hammer attacks to alter stored data.

[0028] like Figure 1 As shown, one embodiment of this disclosure provides a control circuit, which includes a random module 200 and an output module 100.

[0029] The random module 200 includes a first input terminal, a second input terminal, and a control terminal. The first input terminal of the random module 200 receives the refresh count signal CBR, the second input terminal of the random module 200 receives random data rdmV, and the control terminal of the random module 200 is connected to the output terminal of the output module 100.

[0030] The first input terminal of the output module 100 receives the refresh count signal CBR, and the second input terminal of the output module 100 is connected to the output terminal of the random module 200.

[0031] The random module 200, based on the row hammer refresh signal RHRPre output by the output module 100, processes the refresh count signal CBR and random data rdmV to obtain and output a random signal rdm. The random signal rdm output by the random module 200 is used to change the row hammer refresh frequency. The output module 100 generates and outputs the row hammer refresh signal RHRPre based on the random signal rdm and the refresh count signal CBR, so that the frequency of the output row hammer refresh signal RHRPre varies randomly.

[0032] In some embodiments, the output module 100 generates a periodic control signal Ct when the refresh count signal CBR is a specific value. The output module 100 processes the random signal rdm and the periodic control signal Ct to output a row hammer refresh signal RHRPre, thereby randomly adding or subtracting from the fixed row hammer refresh frequency to change the row hammer refresh frequency and avoid the row hammer refresh frequency becoming too large or too small.

[0033] In some embodiments, after the hammer refresh signal RHRPre changes from an active state to an inactive state, the random module 200 updates the random signal rdm at its output. When the hammer refresh signal RHRPre is active, a hammer refresh operation is performed. As the refresh count value CBR changes, the random signal rdm becomes inactive, and the hammer refresh signal RHRPre, obtained based on the refresh count signal CBR and the random signal rdm, changes from an active state to an inactive state. Simultaneously, the random module 200 updates the random signal rdm at its output based on the random data rdmV, changing the next hammer refresh cycle. This configuration ensures that the random signal rdm is updated promptly after each hammer refresh operation, preparing for the next activation of the hammer refresh signal RHRPre.

[0034] In some embodiments, after the row hammer refresh signal RHRPre changes from an active state to an inactive state, the random module 200 updates the random signal rdm at its output terminal according to the random data rdmV and the refresh count signal CBR.

[0035] After the refresh signal RHRPre changes from an active state to an inactive state, the random module 200 updates the random data rdmV, and under the control of the updated random data rdmV, processes the refresh count signal CBR and outputs the random signal rdm.

[0036] In the above technical solution, the control circuit includes a random module 200 and an output module 100. The control terminal of the random module 200 is connected to the output terminal of the output module 100, and the output terminal of the random module 200 is connected to the second input terminal of the output module 100. The random module 200 processes the refresh count signal CBR and random data rdmV based on the row hammer refresh signal RHRPre output by the output module 100 to obtain and output a random signal rdm. The output module 100 generates and outputs the row hammer refresh signal RHRPre based on the random signal rdm and the refresh count signal CBR. The maximum count value of the refresh count signal CBR is used to determine the fixed row hammer refresh frequency. The random signal rdm changes the frequency of the row hammer refresh signal RHRPre based on the fixed row hammer refresh frequency, reducing the risk of hackers using row hammer attacks to change stored data.

[0037] In some embodiments, continue to refer to Figure 1 The output module 100 includes a periodic control signal generation unit 110 and a horizontal hammer refresh signal generation unit 120. The periodic control signal generation unit 110 includes a first input terminal, a second input terminal, and an output terminal, and the horizontal hammer refresh signal generation unit 120 includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal.

[0038] The first input terminal of the periodic control signal generation unit 110 receives the refresh count signal CBR, and the second input terminal of the periodic control signal generation unit 110 is connected to the second output terminal of the hammer refresh signal generation unit 120. The periodic control signal generation unit 110 generates a periodic control signal Ct based on the complementary hammer refresh signal RHRPreB output by the hammer refresh signal generation unit 120 and the refresh count signal CBR. The refresh count signal CBR controls the periodic control signal Ct to be the start time of the valid state, and the complementary hammer refresh signal RHRPreB controls the periodic control signal Ct to be the end time of the valid state.

[0039] The first input terminal of the hammer refresh signal generation unit 120 is connected to the output terminal of the random module 200, and the second input terminal of the hammer refresh signal generation unit 120 is connected to the output terminal of the periodic control signal generation unit 110. The hammer refresh signal generation unit 120 generates a hammer refresh signal RHRPre and a complementary hammer refresh signal RHRPreB according to the periodic control signal Ct and the random signal rdm. The hammer refresh signal RHRPre is output from the first output terminal, and the complementary hammer refresh signal RHRPreB is output from the second output terminal. The hammer refresh signal RHRPre and the complementary hammer refresh signal RHRPreB are inversely related.

[0040] The effective state of the periodic control signal Ct begins at the moment when the refresh count signal CBR represents the set value. The refresh counter continues to count and outputs the latest refresh count signal CBR. At this time, the periodic control signal Ct remains effective, waiting for the random signal rdm to become effective. When the random signal rdm is effective, the hammer refresh signal RHRPre output by the hammer refresh signal generation unit 120 is also effective. When the random signal rdm changes from effective to ineffective, the hammer refresh signal RHRPre output by the hammer refresh signal generation unit 120 also changes from effective to ineffective. Through this setting, the fixed hammer refresh frequency is determined by the refresh count signal CBR. By controlling the counting time when the random signal is effective, the increment / decrement is controlled. Then, based on the refresh count signal CBR and the random signal rdm, the hammer refresh signal RHRPre is generated to perform random increments and decrements on the fixed hammer refresh frequency, thereby changing the hammer refresh frequency.

[0041] When the hammer refresh signal RHRPre changes from an active state to an inactive state, the control period control signal Ct also changes from an active state to an inactive state. That is, the end time of the active state of the period control signal Ct is the end time of the active state of the hammer refresh signal RHRPre. With this setting, even if the random signal rdm is active between the completion of the current hammer refresh operation and the start time of the next fixed hammer refresh frequency, it still cannot control the hammer refresh signal RHRPre to be active. This avoids the problem of the period control signal Ct remaining high after the hammer refresh operation, leading to multiple random hammer refresh operations within the fixed hammer refresh frequency, further causing the hammer refresh frequency to become excessive.

[0042] In some embodiments, continue to refer to Figure 1 The periodic control signal generation unit 110 includes a start trigger circuit 310, a stop trigger circuit 320, and a first latch 330. The output terminal of the start trigger circuit 310 is connected to the first input terminal of the first latch 330, the output terminal of the stop trigger circuit 320 is connected to the second input terminal of the first latch 330, and the output terminal of the first latch 330 outputs a periodic control signal Ct.

[0043] The input terminal of the start trigger circuit 310 receives the refresh count signal CBR, generates the start trigger signal St based on the refresh count signal CBR, and the start trigger signal St determines the start time of the effective state of the period control signal Ct.

[0044] In some embodiments, when the count value represented by the refresh count signal CBR is set to a set value, the start trigger signal St is made active. By setting it in this way, the start trigger signal St is active at the beginning of the fixed hammer refresh frequency, so that the control period control signal Ct is active at the beginning of the fixed hammer refresh frequency, in preparation for controlling the next hammer refresh frequency.

[0045] In some embodiments, the start trigger signal St is enabled when the count value represented by the refresh count signal CBR is zero.

[0046] The input terminal of the termination trigger circuit 320 is connected to the second output terminal of the horizontal hammer refresh signal generation unit 120. The termination trigger circuit 320 generates a termination trigger signal Sp based on the complementary horizontal hammer refresh signal RHRPreB. The termination trigger signal Sp determines the termination time of the effective state of the periodic control signal Ct.

[0047] In some embodiments, the horizontal hammer refresh signal RHRPre is active when it is high and inactive when it is low. The complementary horizontal hammer refresh signal RHRPreB is active when it is low and inactive when it is high. The termination trigger circuit 320 activates the output termination trigger signal Sp when the complementary horizontal hammer refresh signal RHRPreB is at its rising edge. This configuration ensures that the period control signal Ct is deactivated promptly after the horizontal hammer refresh operation.

[0048] The first latch 330 generates a periodic control signal Ct based on the start trigger signal St and the stop trigger signal Sp. When the start trigger signal St is active, the first latch 330 enables the periodic control signal Ct and continues to enable the periodic control signal Ct when the start trigger signal St is inactive. When the stop trigger signal Sp is active, the first latch 330 disables the periodic control signal Ct and continues to disable the periodic control signal Ct when the stop trigger signal Sp is inactive.

[0049] In the above technical solution, the periodic control signal generation unit 110 includes a start trigger circuit 310, a stop trigger circuit 320, and a first latch 330. The start trigger circuit 310 controls the periodic control signal Ct output by the first latch 330 to be valid when the refresh count signal CBR represents a set value and makes the start trigger signal St active. This enables the preparation stage to begin at the start of the fixed hammer refresh frequency. When the random signal rdm is active, the hammer refresh signal generation unit 120 is controlled to output the hammer refresh signal RHRPre as active.

[0050] In some embodiments, continue to refer to Figure 1 The refresh count signal CBR includes multiple count sub-signals, and the start trigger circuit 310 includes an OR gate 311. The number of inputs of the OR gate 311 is the same as the number of count sub-signals. Each input of the OR gate 311 receives one count sub-signal. The OR gate 311 performs an OR operation on the multiple count sub-signals and outputs the start trigger signal St.

[0051] The start trigger signal St is active when it is low and inactive when it is high. When the refresh count signal CBR indicates a count value of zero, each bit of the refresh count signal CBR is low, and OR gate 311 sets the output start trigger signal St to low. When the refresh count signal CBR indicates a count value of non-zero, at least one bit of the refresh count signal CBR is high, and OR gate 311 sets the output start trigger signal St to high. This configuration ensures that the start trigger signal St is low when the refresh count signal CBR indicates a count value of zero and high when the refresh count signal CBR indicates a count value of non-zero.

[0052] In some embodiments, such as Figure 2A and Figure 2B As shown, the termination trigger circuit 320 includes a first delay circuit 321, a first inverter 322, and a first NAND gate 323.

[0053] The input terminal of the first delay circuit 321 is connected to the first input terminal In1 of the first NAND gate 323, and the output terminal of the first delay circuit 321 is connected to the input terminal of the first inverter 322. The output terminal of the first inverter 322 is connected to the second input terminal In2 of the first NAND gate 323, and the first input terminal In1 of the first NAND gate 323 is connected to the second output terminal of the horizontal hammer refresh signal generation unit 120.

[0054] The first input terminal In1 of the first NAND gate 323 receives the complementary horizontal hammer refresh signal RHRPreB. The first delay circuit 321 delays the complementary horizontal hammer refresh signal RHRPreB, and the first inverter 322 performs a NOT operation on the delayed complementary horizontal hammer refresh signal RHRPreB and outputs the result. The first NAND gate 323 performs a AND-NOT operation on the complementary horizontal hammer refresh signal RHRPreB and the NOT-delayed complementary horizontal hammer refresh signal RHRPreB and outputs a termination trigger signal Sp.

[0055] like Figure 3 As shown, the output of the first NAND gate 323 is high during the first time period T1, the second time period T2, and the fourth time period T4. During the third time period T3, the output of the first NAND gate 323 is low.

[0056] The termination trigger signal Sp is a low-level active signal. The output of the first NAND gate 323 is low during the third time period T3, so that the output termination trigger signal Sp is low when the complementary horizontal hammer refresh signal RHRPreB is rising.

[0057] In some embodiments, the delay amount of the first delay circuit 321 enables the termination trigger signal to switch from an active state to an inactive state in time before the count value represented by the refresh count signal is a set value. By setting it in this way, it is avoided that the start trigger signal St cannot make the period control signal Ct active in time because the termination trigger signal Sp is still active when the refresh count signal CBR represents a preset count value.

[0058] In some embodiments, continue to refer to Figure 2A The first delay circuit 321 includes an even number of fourth inverters 324, which are cascaded together. The input of the first fourth inverter 324 receives the complementary horizontal hammer refresh signal RHRPreB. The output of the first fourth inverter 324 is connected to the input of the second fourth inverter 324, the output of the second fourth inverter 324 is connected to the input of the third fourth inverter 324, and so on. The output of the penultimate fourth inverter 324 is connected to the input of the last fourth inverter 324. The output of the last fourth inverter 324 outputs the delayed complementary horizontal hammer refresh signal RHRPreB.

[0059] In some embodiments, such as Figure 2B The first delay circuit 321 includes multiple first buffers 325, which are cascaded together. The input of the first buffer 325 at the beginning receives the complementary horizontal hammer refresh signal RHRPreB. The output of the first buffer 325 at the beginning is connected to the input of the second first buffer 325, the output of the second first buffer 325 is connected to the input of the third first buffer 325, and so on. The output of the second-to-last first buffer 325 is connected to the input of the first buffer 325 at the end. The output of the first buffer 325 at the end outputs the delayed complementary horizontal hammer refresh signal RHRPreB.

[0060] In some embodiments, continue to refer to Figure 1 The first latch 330 includes a second NAND gate 331 and a third NAND gate 332.

[0061] The first input of the second NAND gate 331 serves as the first input of the first latch 330. The second input of the second NAND gate 331 is connected to the output of the third NAND gate 332, and the output of the second NAND gate 331 serves as the output of the first latch 330. The first input of the third NAND gate 332 is connected to the output of the second NAND gate 331, and the second input of the third NAND gate 332 serves as the second input of the first latch 330.

[0062] Table 1 Truth Table of the First Latch

[0063] As shown in Table 1, the first input terminal of the first latch is marked as R, the second input terminal is marked as S, the state of the output terminal at the previous moment is marked as Q(n-1), and the state of the output terminal at the previous moment is marked as Q(n). "1" represents a high level, and "0" represents a low level.

[0064] like Figure 4 As shown, both the start trigger signal St and the stop trigger signal Sp are active low, while the period control signal Ct is active high. Furthermore, the start trigger signal St goes low earlier than the stop trigger signal Sp goes low.

[0065] During the fifth time period T5, when the start trigger signal St is active, the stop trigger signal Sp is inactive. That is, the first input terminal R of the first latch 330 is low, the second input terminal S is high, and the period control signal Ct output by the first latch 330 is high, indicating that the period control signal Ct is active.

[0066] During the sixth time period T6, when the start trigger signal St becomes invalid and the stop trigger signal Sp remains invalid, that is, when the first input terminal R and the second input terminal S of the first latch 330 are both high, the output terminal of the first latch 330 maintains the previous state and continues to keep the period control signal Ct in an active state.

[0067] During the seventh time period T7, when the termination trigger signal Sp changes from an invalid state to an valid state, the start trigger signal St is in an invalid state. That is, the first input terminal R of the first latch 330 is at a high level, the second input terminal S is at a low level, and the period control signal Ct output by the first latch 330 is at a low level, which means that the period control signal Ct is in an invalid state.

[0068] At the eighth time point T8, when the termination trigger signal Sp becomes invalid and the start trigger signal St remains invalid, that is, when the first input terminal R and the second input terminal S of the first latch 330 are both high, the output terminal of the first latch 330 maintains the previous state and continues to keep the period control signal Ct in an invalid state.

[0069] In some embodiments, reference Figure 5 The random module 200 includes a control unit 210 and a random signal generation unit 220. The control unit 210 has an input terminal, a control terminal, and an output terminal. The random signal generation unit 220 has a control terminal, an input terminal, and an output terminal.

[0070] The input terminal of the control unit 210 receives random data rdmV, the control terminal of the control unit 210 is connected to the output terminal of the output module 100, and the output terminal of the control unit 210 is connected to the control terminal of the random signal generation unit 220.

[0071] After the hammer refresh signal RHRPre changes from an active state to an inactive state, the control unit 210 outputs random data rdmV. Under the control of the random data rdmV, the random signal generation unit 220 generates a random signal rdm based on the refresh count signal CBR. By setting it up in this way, the random signal rdm is updated in a timely manner after a hammer refresh operation is completed, in preparation for the next control of the hammer refresh signal RHRPre to be active. This allows the hammer refresh frequency to be changed by randomly adding or subtracting from a fixed hammer refresh frequency.

[0072] In some embodiments, when the random signal generation unit 220 determines that the count value represented by the refresh count signal CBR is random data rdmV, it makes the output random signal rdm valid. When it determines that the count value represented by the refresh count signal CBR is not random data rdmV, the random signal generation unit 220 makes the output random signal rdm invalid. By setting it in this way, the time when the random signal rdm is valid can be controlled to add or subtract values ​​from the fixed hammer refresh frequency, thereby changing the hammer refresh frequency.

[0073] In some embodiments, reference Figure 5 The control unit 210 includes a first trigger circuit 410 and a second latch 420. The first trigger circuit 410 has an input terminal and an output terminal, and the second latch 420 has a clock terminal, an input terminal, and an output terminal.

[0074] The input terminal of the first trigger circuit 410 is connected to the output terminal of the output module 100, and the output terminal of the first trigger circuit 410 is connected to the clock terminal of the second latch 420. The first trigger circuit 410 generates a first trigger signal latch based on the row hammer refresh signal RHRPre. The input terminal of the second latch 420 receives random data rdmV, and the second latch 420 outputs the received random data rdmV under the control of the first trigger signal latch.

[0075] In some embodiments, the first trigger circuit 410 makes the output first trigger signal latch active after the horizontal hammer refresh signal RHRPre changes from active to inactive. By setting it in this way, the random data rdmV output by the control second latch 410 is updated in a timely manner after a horizontal hammer refresh operation is completed, and the time when the random signal rdm is active is changed, so as to prepare for the next control of the horizontal hammer refresh signal RHRPre to be active.

[0076] In some embodiments, reference Figure 6A and Figure 6B The first trigger circuit 410 includes a second delay circuit 411, a second inverter 412, and a NOR gate 413. The second delay circuit 411 has an input terminal and an output terminal, the second inverter 412 has an input terminal and an output terminal, and the NOR gate 413 has a first input terminal In3, a second input terminal In4, and an output terminal Out2.

[0077] The input terminal of the second delay circuit 411 is connected to the first input terminal In3 of the NOR gate 413, and the output terminal of the second delay circuit 411 is connected to the input terminal of the second inverter 412. The output terminal of the second inverter 412 is connected to the second input terminal In4 of the NOR gate 413.

[0078] The first input of NOR gate 413 is connected to the first output of the horizontal hammer refresh signal generation unit 120, and the second input of NOR gate 413 is connected to the output of the second inverter 412. The first input of NOR gate 413 receives the horizontal hammer refresh signal RHRPre. The second delay circuit 411 delays the horizontal hammer refresh signal RHRPre. The second inverter 412 outputs the horizontal hammer refresh signal RHRPre after delay and NOT operation. NOR gate 413 processes the horizontal hammer refresh signal RHRPre and the horizontal hammer refresh signal RHRPre after delay and NOT operation to output the first trigger signal latch.

[0079] like Figure 7 As shown, the output of NOR gate 413 is low during the ninth time period T9, the tenth time period T10, and the twelfth time period T12. The output of NOR gate 413 is high during the eleventh time period T11.

[0080] The first trigger signal latch is a high-level active signal. The output of the NOR gate 413 is high during the eleventh time period T11, so that the output first trigger signal latch is high when the horizontal hammer refresh signal RHRPre is a falling edge.

[0081] In some embodiments, reference Figure 6A The second delay circuit 411 includes an even number of cascaded fifth inverters 414. The input terminal of the first fifth inverter 414 receives the horizontal hammer refresh signal RHRPre. The output terminal of the first fifth inverter 414 is connected to the input terminal of the second fifth inverter 414. The output terminal of the second fifth inverter 414 is connected to the input terminal of the third fifth inverter 414, and so on. The output terminal of the penultimate fifth inverter 414 is connected to the input terminal of the last fifth inverter 414. The output terminal of the last fifth inverter 414 outputs the delayed horizontal hammer refresh signal RHRPre.

[0082] In some embodiments, reference Figure 6B The second delay circuit 411 includes multiple cascaded second buffers 415. The input terminal of the first second buffer 415 receives the row hammer refresh signal RHRPre. The output terminal of the first second buffer 415 is connected to the input terminal of the second second buffer 415. The output terminal of the second second buffer 415 is connected to the input terminal of the third second buffer 415, and so on. The output terminal of the penultimate second buffer 415 is connected to the input terminal of the last second buffer 415. The output terminal of the last second buffer 415 outputs the delayed row hammer refresh signal RHRPre.

[0083] In some embodiments, continue to refer to Figure 1 The hammer refresh signal generation unit 120 includes a fourth NAND gate 121 and a third inverter 122. The first input of the fourth NAND gate 121 is connected to the output of the random module 200, and the second input is connected to the output of the period control signal generation unit 110. The output of the fourth NAND gate 121 serves as the second output of the hammer refresh signal generation unit 120 to output the complementary hammer refresh signal RHRPreB. The input of the third inverter 122 is connected to the fourth NAND gate 121, and the output of the third inverter 122 serves as the first output of the hammer refresh signal generation unit 120 to output the hammer refresh signal RHRPre.

[0084] The hammer refresh signal RHRPre, the period control signal Ct, and the random signal rdm are all active high-level signals, while the complementary hammer refresh signal RHRPreB is active low-level signal. The period control signal Ct is active high when the refresh count signal CBR represents the set value, and waits for the random signal rdm to go high. When the random signal rdm goes high, the fourth NAND gate 121 outputs a low level, controlling the complementary hammer refresh signal RHRPreB to be active. After a NOT logic operation by the third inverter 122, the hammer refresh signal RHRPre goes high.

[0085] If the random signal rdm is low while the periodic control signal Ct is high, or if the periodic control signal Ct is high, the fourth NAND gate 121 outputs a high level, controlling the complementary horizontal hammer refresh signal RHRPreB output by the fourth NAND gate 121 to be in an invalid state. After the third inverter 122 performs a NOT logic operation, the horizontal hammer refresh signal RHRPre is made low, i.e., in an invalid state. With this setting, the periodic control signal Ct received at the second input terminal of the fourth NAND gate 121 is in an active state. When the random signal rdm received at the first input terminal of the fourth NAND gate 121 is in an active state, the fourth NAND gate 121 controls the horizontal hammer refresh signal RHRPre output by the third inverter 122 to be in an active state.

[0086] In some embodiments, reference Figure 4 The random signal generation unit 220 includes a decoder 430 and a selector 440. The input terminal of the decoder 430 receives the refresh count signal CBR. The output terminal of the decoder 430 is connected to the input terminal of the selector 440, and the control terminal of the selector 440 is connected to the output terminal of the control unit 210.

[0087] When the decoder 430 is operating in the first decoding mode, it decodes the decoding bits of the refresh count signal CBR and outputs the first identification signal and the second identification signal. The selector 440 selects one of the first identification signal and the second identification signal for output based on the random data rdmV.

[0088] The first identifier signal is valid when the count value represented by the decoded bit of the refresh count signal CBR is the same as the count value represented by the first identifier signal. The first identifier signal is invalid when the count value represented by the decoded bit of the refresh count signal CBR is not the same as the count value represented by the first identifier signal. The second identifier signal is valid when the count value represented by the decoded bit of the refresh count signal CBR is the same as the count value represented by the second identifier signal. The second identifier signal is invalid when the count value represented by the decoded bit of the refresh count signal CBR is not the same as the count value represented by the second identifier signal.

[0089] In some embodiments, the first identification signal represents a count value and the second identification signal represents a different count value.

[0090] In some embodiments, the first identification signal, the second identification signal, and the random signal rdm are all active high-level signals.

[0091] In some embodiments, the first identification signal characterization count value is 0. The difference between the first identification signal characterization count value and the second identification signal characterization count value is 1, 2, or 3.

[0092] For example, the refresh count signal CBR includes 3 data bits, labeled CBR<2:0>. The decoded bits of the refresh count signal CBR are the first and second signals ordered from low to high, labeled CBR<1:0>. The first identifier signal represents a count value of 0, and the second identifier signal represents a count value of 1. When the refresh count signal CBR is 000, the first identifier signal output after decoding the refresh count signal CBR is valid. When the refresh count signal CBR is any signal other than 000, the first identifier signal is invalid.

[0093] When the refresh count signal CBR is 001 or 101, the second identifier signal output after decoding the refresh count signal CBR is valid. When the refresh count signal CBR is a signal other than 001 and 101, the second identifier signal is invalid.

[0094] In some embodiments, the random signal generation unit 220 further includes a controller. The decoder 430 also outputs a first identifier signal, a second identifier signal, and a third identifier signal when operating in the second decoding mode. When the decoder 430 is operating in the second decoding mode, the controller controls the selector 440 to select one of the first identifier signal, the second identifier signal, and the third identifier signal for output based on the random data rdmV.

[0095] The third identifier signal is valid when the decoded bit of the refresh count signal CBR represents a count value equal to the count value represented by the third identifier signal. The third identifier signal is invalid when the decoded bit of the refresh count signal CBR represents a count value other than the count value represented by the third identifier signal.

[0096] The count values ​​represented by the first, second, and third identification signals are all different. The difference between the count values ​​represented by the first and third identification signals is 1, 2, or 3.

[0097] In some embodiments, when the decoder 430 is operating in a third decoding mode, it also outputs a first identifier signal, a second identifier signal, a third identifier signal, and a fourth identifier signal. When the decoder 430 is operating in the third decoding mode, the controller controls the selector 440 to select one of the first identifier signal, the second identifier signal, the third identifier signal, and the fourth identifier signal for output based on random data rdmV.

[0098] The fourth identifier signal is valid when the decoded bit of the refresh count signal CBR represents a count value equal to that represented by the fourth identifier signal. The fourth identifier signal is invalid when the decoded bit of the refresh count signal CBR does not represent a count value equal to that represented by the fourth identifier signal. The count values ​​represented by the first, second, third, and fourth identifier signals are all different. The difference between the count values ​​represented by the first and fourth identifier signals is 1, 2, or 3.

[0099] The following example uses a 3-bit refresh counter, with the output refresh count signal CBR labeled CBR<2:0>, to illustrate... Figure 1 and Figure 4 The principle of the control circuit shown: The decoder operates in the second decoding mode. The decoded bits of the refresh count signal CBR are the first and second bits, ordered from low to high, and are marked as CBR<1:0>. The first identifier signal represents a count value of 0, the second identifier signal represents a count value of 1, and the third identifier signal represents a count value of 2.

[0100] like Figure 7 As shown, when the refresh count signal CBR is 000, the start trigger circuit 310 outputs the start trigger signal St at a low level, and the first latch 330 outputs the period control signal Ct at a high level.

[0101] For example: when the second latch 420 outputs random data rdmV of 1, the selector 440 selects the second identifier signal output. When the refresh count signal CBR increases to 001, the second identifier signal is high, the random signal rdm output by the selector 440 is high, the horizontal hammer refresh signal RHRPre is high, and the complementary horizontal hammer refresh signal RHRPreB is low.

[0102] When the refresh count signal CBR is 010, the second identifier signal is low, the random signal rdm output by selector 440 is low, the horizontal hammer refresh signal RHRPre changes from high to low, the first trigger circuit 410 outputs the first trigger signal latch as active, the second latch 420 updates the random data rdmV to 0, and selector 440 selects the first identifier signal output. When the complementary horizontal hammer refresh signal RHRPreB changes from low to high, the termination trigger circuit 320 outputs the termination trigger signal Sp as active, and the first latch 330 outputs the period control signal Ct as low.

[0103] When the refresh count signal CBR increases to 100, the first identifier signal is high, and the random signal rdm output by selector 440 is high. However, at this time, the period control signal Ct is low, the horizontal hammer refresh signal RHRPre is low, and the complementary horizontal hammer refresh signal RHRPreB is high.

[0104] When the refresh count signal CBR changes back to 000, the first latch 330 outputs a period control signal Ct at a high level, the first identifier signal is at a high level, the selector 440 outputs a random signal rdm at a high level, the horizontal hammer refresh signal RHRPre is at a low level, and the complementary horizontal hammer refresh signal RHRPreB is at a high level.

[0105] That is, when the random data rdmV output by the second latch 420 is 1, the selector 440 selects the second identifier signal output, and when the refresh count signal CBR is 001, the horizontal hammer refresh signal RHRPre is high. When the random data rdmV output by the second latch 420 becomes 0, the selector 440 selects the first identifier signal output, and when the refresh count signal CBR is 000, the horizontal hammer refresh signal RHRPre is high, the horizontal hammer refresh frequency becomes 1 / 7, and the horizontal hammer refresh frequency is 1 / 8 of the fixed refresh frequency minus 1.

[0106] For example, when the random data rdmV output by the second latch 420 is 0, the selector 440 selects the first identifier signal output, and when the refresh count signal CBR is 000, the horizontal hammer refresh signal RHRPre is high. When the random data rdmV output by the second latch 420 becomes 1, the selector 440 selects the second identifier signal output, and when the refresh count signal CBR is 001, the horizontal hammer refresh signal RHRPre is high, the horizontal hammer refresh frequency becomes 1 / 9, and the horizontal hammer refresh frequency is 1 / 8 of the fixed refresh frequency plus 1.

[0107] For example, when the random data rdmV output by the second latch 420 is 2, the selector 440 selects the third identifier signal output, and when the refresh count signal CBR is 010, the horizontal hammer refresh signal RHRPre is high. When the random data rdmV output by the second latch 420 becomes 0, the selector 440 selects the first identifier signal output, and when the refresh count signal CBR is 000, the horizontal hammer refresh signal RHRPre is high, the horizontal hammer refresh frequency becomes 1 / 6, and the horizontal hammer refresh frequency is 1 / 8 of the fixed refresh frequency minus 2.

[0108] For example, when the random data rdmV output by the second latch 420 is 0, the selector 440 selects the first identifier signal output, and when the refresh count signal CBR is 000, the horizontal hammer refresh signal RHRPre is high. When the random data rdmV output by the second latch 420 becomes 2, the selector 440 selects the third identifier signal output, and when the refresh count signal CBR is 010, the horizontal hammer refresh signal RHRPre is high, the horizontal hammer refresh frequency becomes 1 / 10, and the horizontal hammer refresh frequency is 1 / 8 of the fixed refresh frequency plus 2.

[0109] For example, when the random data rdmV output by the second latch 420 is 2, the selector 440 selects the third identifier signal output, and when the refresh count signal CBR is 010, the horizontal hammer refresh signal RHRPre is high. When the random data rdmV output by the second latch 420 changes to 2, the selector 440 selects the third identifier signal output, and when the refresh count signal CBR is 010, the horizontal hammer refresh signal RHRPre is high, the horizontal hammer refresh frequency changes to 1 / 8, and the horizontal hammer refresh frequency remains unchanged.

[0110] In the above technical solution, by setting the count values ​​represented by the first to third identifier signals when they are in an active state to be 0, 1 and 2 respectively, and by using random data rdmV to select any one of the first, second and third identifier signals for output, the random increment or decrement can be controlled to be 0, 1 and 2.

[0111] Accordingly, the count values ​​represented by the first to third identifier signals when they are in an active state are set to 0, 1, 2 and 3 respectively. By using random data rdmV to select any one of the first, second, third and fourth identifier signals for output, the random increment or decrement can be controlled to be 0, 1, 2 and 3.

[0112] Accordingly, the count values ​​represented by the first and second identifier signals when they are in an active state are set to 0 and 2, respectively. By using the random data rdmV to select any one of the first, second, third, and fourth identifier signals for output, the random increment or decrement can be controlled to be 0 and 2.

[0113] In the above technical solution, by setting the count value represented when the first to fourth identification signals are in an active state, and using random data rdmV to select any one of the first, second, third, or fourth identification signals for output, the random increment or decrement can be controlled.

[0114] An embodiment of this disclosure also provides a memory including the control circuitry described in the above embodiments.

[0115] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0116] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A control circuit, characterized in that, include: The random module has a first input terminal that receives a refresh count signal, a second input terminal that receives random data, and a control terminal that is connected to the output terminal of the output module. It is used to process the refresh count signal and the random data based on the row hammer refresh signal output by the output module to obtain and output a random signal. The output module has a first input terminal that receives the refresh count signal and a second input terminal that is connected to the output terminal of the random module, and is used to generate and output the row hammer refresh signal based on the random signal and the refresh count signal.

2. The control circuit according to claim 1, characterized in that, The output module includes: A periodic control signal generation unit has a first input terminal that receives the refresh count signal and a second input terminal that is connected to the second output terminal of the hammer refresh signal generation unit. It is used to generate a periodic control signal based on the complementary hammer refresh signal output by the hammer refresh signal generation unit and the refresh count signal. The hammer refresh signal generation unit has a first input terminal connected to the output terminal of the random module and a second input terminal connected to the output terminal of the periodic control signal generation unit. It is used to generate the hammer refresh signal and the complementary hammer refresh signal according to the periodic control signal and the random signal. The hammer refresh signal is output from the first output terminal and the complementary hammer refresh signal is output from the second output terminal. The hammer refresh signal and the complementary hammer refresh signal are out of phase with each other.

3. The control circuit according to claim 2, characterized in that, The start time of the effective state of the periodic control signal is the time when the refresh count signal represents the count value as the set value; the end time of the effective state of the periodic control signal is the end time when the row hammer refresh signal is in the effective state.

4. The control circuit according to claim 3, characterized in that, The periodic control signal generation unit includes: The start trigger circuit receives the refresh count signal at its input terminal and is used to generate a start trigger signal based on the refresh count signal. The start trigger signal determines the start time of the effective state of the periodic control signal. The termination trigger circuit has its input terminal connected to the second output terminal of the row hammer refresh signal generation unit, and is used to generate a termination trigger signal based on the complementary row hammer refresh signal. The termination trigger signal determines the termination time of the effective state of the periodic control signal. The first latch has its first input terminal connected to the output terminal of the start trigger circuit and its second input terminal connected to the output terminal of the stop trigger circuit, and is used to generate the periodic control signal based on the start trigger signal and the stop trigger signal.

5. The control circuit according to claim 4, characterized in that, The refresh counting signal includes multiple counting sub-signals, and the start trigger circuit includes: The OR gate has the same number of input terminals as the number of the counting sub-signals. Each input terminal receives one of the counting sub-signals and is used to perform an OR operation on multiple counting sub-signals to output the start trigger signal.

6. The control circuit according to claim 4, characterized in that, The termination trigger circuit includes: The first delay circuit has its input terminal connected to the first input terminal of the first NAND gate and its output terminal connected to the input terminal of the first inverter. It is used to delay the complementary horizontal hammer refresh signal. The output of the first inverter is connected to the second input of the first NAND gate; The first NAND gate has its first input terminal connected to the second output terminal of the row hammer refresh signal generation unit, and outputs the termination trigger signal.

7. The control circuit according to claim 4, characterized in that, The first latch includes: The second NAND gate has its first input terminal serving as the first input terminal of the first latch, and its second input terminal connected to the output terminal of the third NAND gate, the output terminal of which serves as the output terminal of the first latch. The third NAND gate has its first input terminal connected to the output terminal of the second NAND gate, and its second input terminal serving as the second input terminal of the first latch.

8. The control circuit according to claim 2, characterized in that, The hammer refresh signal generation unit includes: The fourth NAND gate has its first input connected to the output of the random module, its second input connected to the output of the periodic control signal generation unit, and its output serving as the second output of the row hammer refresh signal generation unit to output the complementary row hammer refresh signal. The third inverter has its input connected to the fourth NAND gate, and its output serves as the first output of the horizontal hammer refresh signal generation unit to output the horizontal hammer refresh signal.

9. The control circuit according to claim 1, characterized in that, After the row hammer refresh signal changes from an active state to an inactive state, the random module updates the random signal at its output terminal.

10. The control circuit according to claim 9, characterized in that, The random module includes: The control unit receives random data at its input terminal and is connected to the output terminal of the output module. It is used to output the random data after the row hammer refresh signal changes from an active state to an inactive state. A random signal generation unit, whose control terminal is connected to the output terminal of the control unit and whose input terminal receives the refresh count signal, is used to generate the random signal according to the refresh count signal under the control of the random data.

11. The control circuit according to claim 10, characterized in that, The control unit includes: The first trigger circuit has its input terminal connected to the output terminal of the output module and is used to generate a first trigger signal based on the row hammer refresh signal. The second latch has its clock terminal connected to the output terminal of the first trigger circuit and its input terminal receiving the random data, and is used to output the random data under the control of the first trigger signal.

12. The control circuit according to claim 11, characterized in that, The first trigger circuit includes: The second delay circuit has its input terminal connected to the first input terminal of the NOR gate and its output terminal connected to the input terminal of the second inverter; it is used to delay the row hammer refresh signal. The second inverter has its output terminal connected to the second input terminal of the NOR gate, and its first input terminal connected to the output terminal of the output module, for outputting the first trigger signal.

13. The control circuit according to claim 10, characterized in that, The random signal generation unit includes: The decoder receives the refresh count signal at its input terminal and outputs a first identifier signal and a second identifier signal when the decoder is operating in a first decoding mode. When the refresh count signal is the count value represented by the first identifier signal, the first identifier signal is valid. When the refresh count signal is the count value represented by the second identifier signal, the second identifier signal is valid. The count values ​​represented by the first identifier signal and the count values ​​represented by the second identifier signal are different. The selector, whose input is connected to the output of the decoder and whose control is connected to the output of the control unit, is used to select one output from the first identification signal and the second identification signal based on the random data.

14. The control circuit according to claim 13, characterized in that, The random signal generation unit further includes: a controller; The decoder is also used to output the first identification signal, the second identification signal, and the third identification signal when operating in the second decoding mode; when the refresh count signal is the count value represented by the third identification signal, the third identification signal is in a valid state; the count values ​​represented by the first identification signal, the second identification signal, and the third identification signal are all different; The controller is used to control the selector to select an output from the first identifier signal, the second identifier signal, and the third identifier signal based on the random data when the decoder is operating in the second decoding mode.

15. The control circuit according to claim 14, characterized in that, The difference between the count value represented by the first identification signal and the count value represented by the second identification signal is 1, 2, or 3; The difference between the count value represented by the first identification signal and the count value represented by the third identification signal is 1, 2 or 3.

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