A row address decoding circuit and memory

Abstract

The embodiment of the present disclosure discloses a row address decoding circuit and a memory. The row address decoding circuit comprises N storage address control circuits, and N is greater than or equal to 1. Each storage address control circuit comprises a control signal generation module. The control signal generation module is configured to receive at least one address pre-decoding signal, and generate an address control signal according to the address pre-decoding signal. The control signal generation module comprises a low-threshold voltage transistor. The embodiment of the present disclosure can shorten the time of row decoding and improve the efficiency.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, a row address decoding circuit and a memory. Background Technology

[0002] To improve memory performance, faster read and write speeds are required for memory cells. Row address decoding circuitry is essential in memory circuitry, used for decoding and gating row addresses. The row address decoding circuitry directly affects the memory's read speed and the load on the charge pump. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a row address decoding circuit and a memory that can shorten the row decoding time and improve efficiency.

[0004] The technical solution of this disclosure embodiment is implemented as follows:

[0005] This disclosure provides a row address decoding circuit, which includes N memory address control circuits, where N is greater than or equal to 1; each memory address control circuit includes a control signal generation module, used to receive at least one address pre-decoding signal and generate an address control signal based on the address pre-decoding signal; the control signal generation module includes a low threshold voltage transistor.

[0006] In the above scheme, the storage address control circuit further includes: a power control module, which is connected to the control signal generation module and the power supply terminal respectively, for receiving the running pulse signal and the address control signal, and transmitting the power supply voltage of the power supply terminal to the control signal generation module according to the running pulse signal and the address control signal, so as to enable the control signal generation module to operate.

[0007] In the above scheme, the power control module includes: a power control signal generation unit, used to receive the running pulse signal and the address control signal, and generate a power control signal according to the running pulse signal and the address control signal; and a power switch unit, connected to the power control signal generation unit, the control signal generation module and the power supply terminal respectively, used to receive the power control signal and, in response to the power control signal, transmit the power supply voltage to the control signal generation module.

[0008] In the above scheme, the power control signal generation unit includes an OR gate, the first input terminal of the OR gate receives the running pulse signal, the second input terminal of the OR gate receives the address control signal, and the OR gate outputs the power control signal.

[0009] In the above scheme, the control signal generation module includes a decoding module; the address control signal includes a row address decoding signal; the decoding module is used to receive at least one of the address pre-decoding signals and generate a row address decoding signal based on the address pre-decoding signals.

[0010] In the above scheme, the control signal generation module further includes other control signal generation modules; the address control signal further includes other control signals; the other control signal generation module is used to receive at least one of the address pre-decoding signals and generate the other control signals according to the address pre-decoding signals.

[0011] In the above scheme, the row address decoding circuit further includes: a running pulse generation module, used to receive an initial running signal and generate a running pulse signal based on the initial running signal.

[0012] In the above scheme, the initial running signal is an activation command signal.

[0013] In the above scheme, the running pulse generation module includes: an inverter, the input of which receives the initial running signal; a delay, the input of which is connected to the output of the inverter; and an AND gate, the first input of which receives the initial running signal, the second input of which is connected to the output of the delay, and the AND gate outputs the running pulse signal.

[0014] This disclosure also provides a memory, which includes the row address decoding circuit described in the above scheme.

[0015] In the above scheme, the memory further includes: at least one storage bank; at least one of the storage banks is disposed on at least one side of the row address decoding circuit on opposite sides along a first direction.

[0016] In the above scheme, each of the memory banks includes N memory segments; the row address decoding circuit includes N memory address control circuits; and each of the N memory segments receives an address control signal output by one of the N memory address control circuits.

[0017] In the above scheme, the memory further includes a pre-decoding module, which is used to receive an initial running signal and a row address encoding signal, and pre-decode the row address encoding signal according to the initial running signal to obtain at least one address pre-decoding signal.

[0018] In the above scheme, the pre-decoding module includes: a combinational logic circuit, a row fuse matching circuit, and a row address pre-decoding circuit; the combinational logic circuit is used to receive an initial running signal and an initial address signal, and generate a pre-decoding drive signal corresponding to the initial address signal; the row fuse matching circuit is used to receive the initial address signal, perform fuse address matching and replacement on the initial address signal, and transmit the matched and replaced address signal to the row address pre-decoding circuit; the row address pre-decoding circuit is connected to the combinational logic circuit and the row fuse matching circuit respectively, and is used to receive the pre-decoding drive signal and the matched and replaced address signal, perform pre-decoding on the address signal, and generate an address pre-decoding signal.

[0019] In the above scheme, the memory is a dynamic random access memory (DRAM).

[0020] Therefore, this disclosure provides a row address decoding circuit and a memory. The row address decoding circuit includes N memory address control circuits, where N is greater than or equal to 1. Each memory address control circuit includes a control signal generation module. The control signal generation module receives at least one address pre-decoding signal and generates an address control signal based on the address pre-decoding signal. The control signal generation module includes a low threshold voltage transistor. Since transistors with lower threshold voltages have stronger current capabilities and thus lower delays, forming low threshold voltage transistors in the control signal generation module can shorten the row decoding time and improve efficiency. Attached Figure Description

[0021] Figure 1 A schematic diagram of the row address decoding circuit provided in the embodiments of this disclosure. Figure 1 ;

[0022] Figure 2 A schematic diagram of the row address decoding circuit provided in the embodiments of this disclosure. Figure 2 ;

[0023] Figure 3 A diagram illustrating the threshold voltage of a transistor;

[0024] Figure 4 A schematic diagram of the row address decoding circuit provided in the embodiments of this disclosure. Figure 3 ;

[0025] Figure 5 A schematic diagram of the row address decoding circuit provided in the embodiments of this disclosure. Figure 4 ;

[0026] Figure 6 A schematic diagram of the row address decoding circuit provided in the embodiments of this disclosure. Figure 5 ;

[0027] Figure 7 A schematic diagram of the row address decoding circuit provided in the embodiments of this disclosure. Figure 6 ;

[0028] Figure 8 Signal diagram of the row address decoding circuit provided in the embodiments of this disclosure Figure 1 ;

[0029] Figure 9 A schematic diagram of the row address decoding circuit provided in the embodiments of this disclosure. Figure 7 ;

[0030] Figure 10 A schematic diagram of the row address decoding circuit provided in the embodiments of this disclosure. Figure 8 ;

[0031] Figure 11 Signal diagram of the row address decoding circuit provided in the embodiments of this disclosure Figure 2 ;

[0032] Figure 12 Schematic diagram of the memory structure provided in the embodiments of this disclosure Figure 1 ;

[0033] Figure 13 Schematic diagram of the memory structure provided in the embodiments of this disclosure Figure 2 . Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0035] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0036] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0038] Figure 1 This is an optional structural diagram of the row address decoding circuit provided in the embodiments of this disclosure, such as... Figure 1 As shown, the row address decoding circuit 10 includes N memory address control circuits 20, where N is greater than or equal to 1.

[0039] Combination Figure 1 and Figure 2 Each memory address control circuit 20 includes a control signal generation module 201. The control signal generation module 201 receives at least one address pre-decoding signal Ra_pre and generates an address control signal Ra_En based on the address pre-decoding signal Ra_pre. The control signal generation module 201 includes a low threshold voltage transistor.

[0040] In this embodiment of the disclosure, the number N of storage address control circuits 20 can be set according to the number of storage segments in the memory. In some embodiments, the number N of storage address control circuits 20 is set to 32, 64, 65, 66, or 128, etc. Each storage address control circuit 20 can control a plurality of storage addresses; for example, each storage address control circuit 20 controls 4096 storage addresses. Each storage address stores 1 bit of data.

[0041] In this embodiment, the address pre-decoding signal Ra_pre is obtained by pre-decoding the encoded address signal. For example, the encoded address signal contains 17 bits, denoted as Ra<16:0>, i.e., bits 0 to 16. Some address bits can be multiplexed row and column; Ra_pre is used as an example below. <16> Take reuse as an example.

[0042] When Ra <16> When used to represent column addresses, the row address pre-decoding signal Ra_pre can include signals such as R210<7:0>, R543<7:0>, R876<7:0>, R9<1:0>, R121110<7:0>, and R151413<7:0>. These signals represent the pre-decoding results of a portion of the bits in the memory address. Specifically, R210<7:0> represents the pre-decoding result of bits 0 to 2 of the memory address, and <7:0> indicates that there are 8 bits of data in the pre-decoding result. That is, 3 bits (bits 0 to 2) of the encoded memory address are pre-decoded into 8 bits (i.e., 2... 3 The pre-decoding result of the 8-bit data. Similarly, R543<7:0> is the pre-decoding result of bits 3 to 5 of the memory address, containing 8 bits (i.e., 2^34 bits). 3R876<7:0> represents the pre-decoding result of bits 6 to 8 of the memory address, containing 8 bits (i.e., 2^6 bits). 3 R9<1:0> is the pre-decoding result of the 9th bit at the storage address, containing 2 bits (i.e., 2 bits). 1 R121110<7:0> is the pre-decoding result of bits 10 to 12 of the storage address, containing 8 bits (i.e., 2 bits). 3 R151413<7:0> is the pre-decoding result of bits 13 to 15 of the storage address, containing 8 bits (i.e., 2 bits). 3 (bit) data.

[0043] When Ra <16> When used to represent a row address, the row address pre-decoding signal Ra_pre can include signals such as R210<7:0>, R543<7:0>, R876<7:0>, R109<3:0>, R131211<7:0>, and R161514<7:0>. Among these, R210<7:0> represents the pre-decoding result of bits 0 to 2 of the storage address, containing 8 bits (i.e., 2...). 3 R543<7:0> represents the pre-decoding result of bits 3 to 5 of the storage address, containing 8 bits (i.e., 2 bits). 3 R876<7:0> represents the pre-decoding result of bits 6 to 8 of the memory address, containing 8 bits (i.e., 2^6 bits). 3 R109<3:0> represents the pre-decoding result of bits 9-10 at the memory address, containing 4 bits (i.e., 2 bits). 2 R131211<7:0> is the pre-decoding result of bits 11 to 13 of the storage address, containing 8 bits (i.e., 2 bits). 3 R161514<7:0> represents the pre-decoding result of bits 14 to 16 of the memory address, containing 8 bits (i.e., 2^34 bits). 3 (bit) data.

[0044] Furthermore, the aforementioned address pre-decoding signal Ra_pre is input to each control signal generation module 201. After receiving the address pre-decoding signal Ra_pre, the control signal generation module 201 can decode the address pre-decoding signal Ra_pre to obtain the address control signal Ra_En. In this way, the encoded address signal is decoded into the address control signal Ra_En only after undergoing "pre-decoding-decoding". This process is called step-by-step decoding. It should be noted that the embodiments of this disclosure are not limited to the two-step decoding mode of "pre-decoding-decoding". That is to say, the embodiments of this disclosure can also directly decode without pre-decoding, and the embodiments of this disclosure can also perform multiple pre-decodings before decoding.

[0045] It should be noted that the gate-source voltage V corresponding to the critical point between the on and off states of an NMOS transistor is usually defined as... GS This is called the threshold voltage. Figure 3 The transfer characteristic curve of the NMOS transistor, i.e., the drain current I, is illustrated. D With gate-source voltage V GS The following explanation uses an NMOS transistor as an example to illustrate the variation curve.

[0046] refer to Figure 3 In an NMOS transistor, when the device transitions from depletion to inversion, it needs to pass through a state where the electron concentration equals the hole concentration. At this point, the device is in a critical conduction state, and the corresponding gate-source voltage Vo is... GS This is the threshold voltage Vt. If the gate-source voltage V GS If the threshold voltage Vt is less than the threshold voltage, a channel cannot be formed in the NMOS transistor, and the NMOS transistor will not conduct. On the other hand, the threshold voltage of an NMOS transistor also affects its current capability. That is, for two NMOS transistors with different threshold voltages, under the same input gate-source voltage, the NMOS transistor with the smaller threshold voltage can carry a larger current. The stronger the current capability of an NMOS transistor, the faster its signal transmission speed; in other words, the smaller the threshold voltage, the less delay it introduces. It should be noted that PMOS transistors can be understood in the same way as NMOS transistors.

[0047] In this embodiment of the disclosure, the control signal generation module 201 includes a low threshold voltage transistor. Here, the threshold voltage of the low threshold voltage transistor is lower than that of a conventional transistor; a conventional transistor refers to a transistor manufactured using typical processes. For example, for a DDR (Double Data Rate Synchronous Dynamic Random Access Memory), the threshold voltage of a conventional transistor is between 0.5V and 0.7V, while the threshold voltage of the low threshold voltage transistor is 100mV to 200mV lower than that of a conventional transistor. Similarly, for an LPDDR (Low Power Double Data Rate Synchronous Dynamic Random Access Memory), the threshold voltage of a conventional transistor is between 0.3V and 0.6V, while the threshold voltage of the low threshold voltage transistor is 100mV to 200mV lower than that of a conventional transistor.

[0048] It should be noted that the threshold voltage of a low threshold voltage transistor can vary depending on the product, manufacturing process, or application. The values ​​exemplified above are merely some possible scenarios for low threshold voltage transistors and are not intended to limit the embodiments of this disclosure.

[0049] Furthermore, in combination Figure 1 and Figure 2The row address decoding circuit 10 performs row address decoding on the address pre-decoding signal Ra_pre. The control signal generation module 201 uses a low threshold voltage transistor, which reduces the delay in the control signal generation module 201, thereby shortening the row decoding time.

[0050] In this embodiment, the threshold voltage of the transistor can be influenced and controlled by factors such as the doping of the back gate, the gate material, or the thickness of the gate dielectric. For example, by controlling the doping of the back gate, inversion on the semiconductor surface is made easier, thereby reducing the threshold voltage. Similarly, the threshold voltage can be reduced by decreasing the thickness of the gate dielectric. Thus, a low threshold voltage transistor can be fabricated in the control signal generation module 201.

[0051] It is understandable that since transistors with smaller threshold voltages have stronger current capabilities and thus less delay, forming transistors with low threshold voltages in the control signal generation module can shorten the line decoding time and improve efficiency.

[0052] In some embodiments of this disclosure, such as Figure 4 As shown, the storage address control circuit 20 further includes a power control module 202. The power control module 202 is connected to the control signal generation module 201 and the power supply terminal. Figure 4 (Not shown in the image). The power control module 202 receives the running pulse signal ActPls and the address control signal Ra_En, and transmits the power supply voltage P at the power supply terminal to the control signal generation module 201 according to the running pulse signal ActPls and the address control signal Ra_En, so that the control signal generation module 201 can operate.

[0053] It should be noted that the power supply voltage P at the power supply terminal can be a constant voltage or a changing voltage signal, which will be understood in the following text and will not be elaborated further.

[0054] In the above embodiments, the power supply terminal refers only to the input power supply of the row address decoding circuit, and not the input power supply at the pin or terminal. However, this disclosure is not limited to this. In other embodiments, the power supply terminal may also be the input power supply of the row address decoding circuit directly input at the pin or terminal.

[0055] It should be noted that the control signal generation module 201 contains static current. Static current refers to the current present in a device when there is no signal input; all components in a chip have static current. Taking DDR (Double Data Rate Synchronous Dynamic Random Access Memory) as an example, DDR includes operating states such as Precharge, Active, Read, Write, and Refresh. Static current may exist in DDR under different operating states; for example, I... DD2P I is the quiescent current in the pre-charge state. DD3N This refers to the quiescent current during the active state. The presence of quiescent current causes static power consumption of the chip, meaning that the chip consumes power even when it is in the idle state.

[0056] In this embodiment of the disclosure, reference is made to Figure 4 The power control module 202 can control whether the power supply voltage P is transmitted to the control signal generation module 201 based on the running pulse signal ActPls and the address control signal Ra_En. Thus, when the control signal generation module 201 is idle, the power control module 202 can cut off the transmission of the power supply voltage P to the control signal generation module 201, thereby preventing the generation of static current in the control signal generation module 201 (since the device is not connected to the power supply voltage P, there is no voltage difference between its terminals, and no static current is generated inside).

[0057] On the other hand, the control signal generation module 201 includes a low threshold voltage transistor. Compared to ordinary transistors, low threshold voltage transistors have stronger current capability. That is, for two MOSFETs with different threshold voltages, under the same gate-source voltage input, the MOSFET with the smaller threshold voltage can carry a larger current. Therefore, low threshold voltage transistors tend to generate a larger quiescent current.

[0058] It is understandable that the power control module 202 controls the transmission of power supply voltage. When the control signal generation module 201 is in an idle state, it cuts off the transmission of power supply voltage to the control signal generation module 201. In this way, it can avoid the low threshold voltage transistor in the control signal generation module 201 from generating a large static current, thereby reducing static power consumption.

[0059] Furthermore, the row address decoding circuit provided in this embodiment can be applied to LPDDR (Low Power Double Data Rate Synchronous Dynamic Random Access Memory) to further reduce the power consumption of LPDDR.

[0060] In some embodiments of this disclosure, such as Figure 5As shown, the power control module 202 includes a power control signal generation unit 203 and a power switch unit 204. The power control signal generation unit 203 receives the running pulse signal ActPls and the address control signal Ra_En, and generates a power control signal Sc_En based on the running pulse signal ActPls and the address control signal Ra_En. The power switch unit 204 is connected to the power control signal generation unit 203, the control signal generation module 201, and the power supply terminal. Figure 5 (Not shown in the image). The power switch unit 204 is used to receive the power control signal Sc_En and, in response to the power control signal Sc_En, transmit the power supply voltage P to the control signal generation module 201.

[0061] In some embodiments of this disclosure, reference is made to Figure 6 The power switch unit 204 may include an AND gate AND1. The first input of AND gate AND1 receives a power control signal Sc_En; the second input of AND gate AND1 is connected to the power supply terminal, i.e., receives the power supply voltage P; the output of AND gate AND1 is connected to a control signal generation module. Thus, when the power control signal Sc_En is high, AND gate AND1 outputs the power supply voltage P to the control signal generation module; when the power control signal Sc_En is low, the output of AND gate AND1 is also low, i.e., it does not output the power supply voltage P.

[0062] It should be noted that, Figure 6 Only one optional structure of the power switch unit 204 is shown. The power switch unit 204 can also be composed of a separate transistor or a complementary MOSFET (CMOS transistor). That is, the power control signal Sc_En is connected to the control terminal of a separate transistor or complementary MOSFET to control the output of the power supply voltage P. No limitation is made here.

[0063] Further reference Figure 5 The power switch unit 204 may also include circuits such as a level shifter and an inverter. The level shifter is used to convert the power supply voltage P to a suitable level. The inverter is used to improve the driving capability of the power switch unit 204 and avoid signal attenuation.

[0064] In some embodiments of this disclosure, such as Figure 7 As shown, the power control signal generation unit 203 includes an OR gate OR1. The first input of the OR gate OR1 receives the running pulse signal ActPls, the second input of the OR gate OR1 receives the address control signal Ra_En, and the OR gate OR1 outputs the power control signal Sc_En.

[0065] Figure 8It is an optional waveform diagram of the running pulse signal ActPls, the address control signal Ra_En, and the power control signal Sc_En.

[0066] In this embodiment of the disclosure, combined with Figure 7 and Figure 8 The running pulse signal ActPls is active high after being activated by the initial running signal. This initial running signal can be a multiplexed activation command signal (active) or an independent control signal. The invalid (low) address control signal Ra_En and the active (high) running pulse signal ActPls are logically ORed (by an OR gate OR1) to obtain the active power control signal Sc_En. Then, the address control signal Ra_En remains active, which in turn keeps the power control signal Sc_En active. In other words, the running pulse signal ActPls activates the active state of the power control signal Sc_En, and then the address control signal Ra_En maintains the active state of the power control signal Sc_En.

[0067] In this embodiment of the disclosure, combined with Figure 5 and Figure 8 When the power control signal Sc_En is high, the control signal generation module 201 can run and output the address control signal Ra_En. Here, since the running pulse signal ActPls is earlier in timing, it can activate the effective state of the power control signal Sc_En earlier. Therefore, the power switch unit 204 can quickly transmit the power supply voltage P to the control signal generation module 201, enabling the signal generation module 201 to run. This reduces delay and facilitates control.

[0068] In some embodiments of this disclosure, such as Figure 9 As shown, the control signal generation module 201 includes a decoding module 205, and the address control signal includes a row address decoding signal Sec_En. The decoding module 205 is used to receive at least one address pre-decoding signal Ra_pre, and generate the row address decoding signal Sec_En based on the address pre-decoding signal Ra_pre.

[0069] In some embodiments of this disclosure, such as Figure 9 As shown, the control signal generation module 201 also includes an additional control signal generation module 206, and the address control signal further includes an additional control signal Oth_En. The additional control signal generation module 206 is used to receive at least one address pre-decoding signal Ra_pre, and generate the additional control signal Oth_En based on the address pre-decoding signal Ra_pre.

[0070] It should be noted that, Figure 4The address control signal Ra_En shown can be Figure 9 The row address decoding signal Sec_En and / or other control signal Oth_En are shown. In some embodiments, the row address decoding signal Sec_En is transmitted to the power control module 202 to control the transmission of the power supply voltage, i.e., as shown... Figure 9 As shown. In other embodiments, other control signals Oth_En are transmitted to the power control module 202 to control the transmission of power supply voltage.

[0071] In this embodiment of the disclosure, reference is made to Figure 9 The decoding module 205 can generate the row address decoding signal Sec_En based on the address pre-decoding signal Ra_pre. In other words, the decoding module 205 can decode the linking and storage sections of the row address program. The other control signal generation module 206 can generate other control signals Oth_En based on the address pre-decoding signal Ra_pre. In other words, the other control signal generation module 206 can generate other control signals for the memory array.

[0072] In this embodiment of the disclosure, other control signals Oth_En include: phase driving signal, main word line driving signal, and sense amplifier controlling signal, etc. That is, other control signals Oth_En include, but are not limited to, drive signals and control signals in the memory.

[0073] In some embodiments, such as Figure 9 As shown, the row address decoding signal Sec_En generated by the decoding module 205 is transmitted to the power control module 202. The power control module 202, based on the running pulse signal ActPls and the row address decoding signal Sec_En, transmits the power supply voltage P at the power supply terminal to the decoding module 205 and other control signal generation modules 206 to enable their operation. In other embodiments, other control signals Oth_En generated by the other control signal generation module 206 are transmitted to the power control module 202. The power control module 202, based on the running pulse signal ActPls and other control signals Oth_En, transmits the power supply voltage P at the power supply terminal to the decoding module 205 and other control signal generation modules 206 to enable their operation.

[0074] In some embodiments of this disclosure, Figure 1The row address decoding circuit 10 shown also includes a running pulse generation module. The running pulse generation module is used to receive an initial running signal and generate a running pulse signal based on the initial running signal.

[0075] In some embodiments of this disclosure, the initial running signal is an active command signal, that is, the active command signal is reused as the initial running signal. Since the active command signal is the first command signal during memory read / write, it is the earliest in timing; therefore, the running pulse signal generated based on the initial running signal also has an earlier timing.

[0076] In other embodiments of this disclosure, the initial running signal may also be an independently transmitted control signal or other multiplexed signal, which also has an earlier timing sequence, thereby enabling the running pulse signal to have an earlier timing sequence.

[0077] In some embodiments of this disclosure, such as Figure 10 As shown, the running pulse generation module 101 includes: an inverter INV1, a delay unit DEL, and an AND gate AND2. The input of the inverter INV1 receives the initial running signal Act. The input of the delay unit DEL is connected to the output of the inverter INV1. The first input of the AND gate AND2 receives the initial running signal Act, and the second input of the AND gate AND2 is connected to the output of the delay unit DEL. The AND gate AND2 outputs the running pulse signal ActPls.

[0078] In this embodiment, the delay unit DEL can be constructed using an even number of inverters, or it can be constructed using inverters and CMOS capacitors, etc. It should be noted that delay units are common structures in the art; any structure that can perform the delay function is acceptable, and no specific limitation is made here.

[0079] Figure 11 for Figure 10 The corresponding signal diagram. Combined with... Figure 10 and Figure 11 The initial running signal Act, after passing through inverter INV1, delay unit DEL, and AND gate AND2, yields the running pulse signal ActPls. Both the initial running signal Act and the running pulse signal ActPls are active high, but the effective pulse width of the running pulse signal ActPls is shorter than that of the initial running signal Act. It should be noted that due to the physical delay of inverter INV1, delay unit DEL, and AND gate AND2, the running pulse signal ActPls is delayed relative to the initial running signal Act; the leading edge of the running pulse signal ActPls lags behind the leading edge of the initial running signal Act.

[0080] Understandably, since the initial running signal Act is the first among all signals in the memory, meaning it's earlier in timing than other signals, the running pulse signal ActPls, derived from Act, is also earlier in timing. The running pulse signal ActPls is used by the power switching unit as a control signal to transmit the power supply voltage to the control signal generation module. This allows the power switching unit to transmit the power supply voltage to the control signal generation module more quickly, enabling the signal generation module to operate, thereby reducing latency and even minimizing the impact on the chip's parameter tRCD (row select cycle).

[0081] This disclosure also provides a memory, referenced in embodiments thereof. Figure 12 The memory 80 includes a row address decoding circuit 10.

[0082] In some embodiments of this disclosure, reference is made to Figure 12 The memory 80 also includes at least one bank, each bank may include two half-banks 30 located on either side of the row address decoding circuit 10.

[0083] In other embodiments, the memory 80 may further include at least one bank, each bank being disposed on at least one of the opposite sides of the row address decoding circuit 10 along the first direction X.

[0084] In some embodiments of this disclosure, combined with Figure 1 , Figure 2 and Figure 12 Each memory bank 30 includes N memory segments 40. The row address decoding circuit 10 includes N memory address control circuits 20. Each of the N memory segments 40 receives the address control signal Ra_En output by the N memory address control circuits 20 in a one-to-one correspondence.

[0085] In this embodiment, the address decoding circuit (including row address decoding circuit 10) can direct the input binary address to the corresponding physical space in the memory 80. In the memory 80, to read data from a specific cell, the addressing process first determines which bank is being used, and then performs row and column addressing within that selected bank. During the operation of the memory 80, the bank address and the corresponding row address are issued simultaneously; this command is called "row active" or "row enabled." After this, the column address addressing command and the specific operation command (read or write) are sent simultaneously, so the column addressing is represented by a "read / write command." Row and column addresses can be reused. The interval between row active and the issuance of the read / write command is defined as tRCD (row strobe cycle), i.e., RAS to CAS Delay (RAS to CAS delay, where RAS is the row address strobe pulse and CAS is the column address strobe pulse).

[0086] In some embodiments of this disclosure, Figure 12 The illustrated memory 80 further includes a pre-decoding module. The pre-decoding module receives an initial running signal and a row address encoding signal, and pre-decodes the row address encoding signal according to the initial running signal to obtain at least one address pre-decoding signal.

[0087] In some embodiments of this disclosure, such as Figure 13 As shown, the pre-decoding module 50 includes: a combinational logic circuit 501, a row fuse matching circuit 502, and a row address pre-decoding circuit 503. The combinational logic circuit 501 receives the initial running signal Act and the initial address signal Ra, and generates a pre-decoding drive signal corresponding to the initial address signal Ra. The row fuse matching circuit 502 receives the initial address signal Ra, performs fuse address matching and replacement on the initial address signal Ra, and then transmits the matched and replaced address signal to the row address pre-decoding circuit 503. The row address pre-decoding circuit 503 is connected to both the combinational logic circuit 501 and the row fuse matching circuit 502, and receives the pre-decoding drive signal and the matched and replaced address signal, performs pre-decoding on the matched and replaced address signal, and generates an address pre-decoding signal Ra_pre.

[0088] In this embodiment of the disclosure, reference is made to Figure 13The combinational logic circuit 501 processes the received initial operation signal Act and initial address signal Ra to output a pre-decoding drive signal. In memory, opening a storage row requires multiple signals to drive it, such as a phase driving signal and a mainword line driving signal. The pre-decoding drive signal, along with other drive signals, can control various operations (such as read / write operations) on the storage row.

[0089] In this embodiment of the disclosure, since the storage cells in the memory may malfunction during the manufacturing or use process, i.e., fail to store data correctly, a fuse circuit is provided in the memory to record the address of the malfunctioning storage cell in the storage array. The fuse circuit includes a fuse array, a broadcast circuit, a latch, and a fuse matching circuit. The fuse matching circuit includes row fuse matching circuits and column fuse matching circuits. (Reference) Figure 13 After receiving the initial address signal Ra, the row fuse matching circuit 502 matches the initial address signal Ra with the error address information recorded in the fuse array to determine whether the initial address signal Ra includes an error address. If the initial address signal Ra successfully matches the error address information, meaning the initial address signal Ra includes an error address, then the address of a redundant memory cell in the memory array area is used to replace the error address, activating the intact memory cells in the redundant array.

[0090] In this embodiment, the address pre-decoding signal Ra_pre is obtained by pre-decoding the matched and replaced address signals. For example, the initial address signal Ra contains 17 bits, denoted as Ra<16:0>, i.e., bits 0 to 16. Some address bits can be multiplexed row and column. Ra is used as an example below. <16> Take reuse as an example.

[0091] When Ra <16> When used to represent column addresses, the row address pre-decoding signal Ra_pre can include signals such as R210<7:0>, R543<7:0>, R876<7:0>, R9<1:0>, R121110<7:0>, and R151413<7:0>. These signals represent the pre-decoding results of a portion of the bits in the memory address. Specifically, R210<7:0> represents the pre-decoding result of bits 0 to 2 of the memory address, and <7:0> indicates that there are 8 bits of data in the pre-decoding result. That is, 3 bits (bits 0 to 2) of the encoded memory address are pre-decoded into 8 bits (i.e., 2... 3 The pre-decoding result of the 8-bit data. Similarly, R543<7:0> is the pre-decoding result of bits 3 to 5 of the memory address, containing 8 bits (i.e., 2^34 bits). 3R876<7:0> represents the pre-decoding result of bits 6 to 8 of the memory address, containing 8 bits (i.e., 2^6 bits). 3 R9<1:0> is the pre-decoding result of the 9th bit at the storage address, containing 2 bits (i.e., 2 bits). 1 R121110<7:0> is the pre-decoding result of bits 10 to 12 of the storage address, containing 8 bits (i.e., 2 bits). 3 R151413<7:0> is the pre-decoding result of bits 13 to 15 of the storage address, containing 8 bits (i.e., 2 bits). 3 (bit) data.

[0092] When Ra <16> When used to represent a row address, the row address pre-decoding signal Ra_pre can include signals such as R210<7:0>, R543<7:0>, R876<7:0>, R109<3:0>, R131211<7:0>, and R161514<7:0>. Among these, R210<7:0> represents the pre-decoding result of bits 0 to 2 of the storage address, containing 8 bits (i.e., 2...). 3 R543<7:0> represents the pre-decoding result of bits 3 to 5 of the storage address, containing 8 bits (i.e., 2 bits). 3 R876<7:0> represents the pre-decoding result of bits 6 to 8 of the memory address, containing 8 bits (i.e., 2^6 bits). 3 R109<3:0> represents the pre-decoding result of bits 9-10 at the memory address, containing 4 bits (i.e., 2 bits). 2 R131211<7:0> is the pre-decoding result of bits 11 to 13 of the storage address, containing 8 bits (i.e., 2 bits). 3 R161514<7:0> represents the pre-decoding result of bits 14 to 16 of the memory address, containing 8 bits (i.e., 2^34 bits). 3 (bit) data.

[0093] Furthermore, the address pre-decoding signal Ra_pre is input to each control signal generation module for decoding. This "pre-decoding-decoding" process is called step-by-step decoding. It should be noted that the embodiments of this disclosure are not limited to the two-step decoding mode of "pre-decoding-decoding". That is to say, the embodiments of this disclosure can also directly decode without pre-decoding, and the embodiments of this disclosure can also perform pre-decoding multiple times before decoding.

[0094] In some embodiments of this disclosure, the memory is a dynamic random access memory (DRAM). The memory may be LPDDR4 (fourth-generation low-power double-rate synchronous dynamic random access memory), LPDDR5 (fifth-generation low-power double-rate synchronous dynamic random access memory), or LPDDR6 (sixth-generation low-power double-rate synchronous dynamic random access memory). Alternatively, the memory may be DDR4 (fourth-generation double-rate synchronous dynamic random access memory), DDR5 (fifth-generation double-rate synchronous dynamic random access memory), or DDR6 (sixth-generation double-rate synchronous dynamic random access memory).

[0095] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0096] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments without conflict.

[0097] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A row address decoding circuit, characterized in that, The row address decoding circuit includes N memory address control circuits, where N is greater than or equal to 1; each memory address control circuit includes: A control signal generation module is configured to receive at least one address pre-decoding signal and generate an address control signal based on the address pre-decoding signal; the control signal generation module includes a low threshold voltage transistor. The storage address control circuit further includes: The power control module is connected to the control signal generation module and the power supply terminal respectively. It is used to receive the running pulse signal and the address control signal, and transmit the power supply voltage of the power supply terminal to the control signal generation module according to the running pulse signal and the address control signal, so as to enable the control signal generation module to operate.

2. The row address decoding circuit according to claim 1, characterized in that, The power control module includes: A power control signal generation unit is used to receive the operating pulse signal and the address control signal, and generate a power control signal based on the operating pulse signal and the address control signal. The power switch unit is connected to the power control signal generation unit, the control signal generation module, and the power supply terminal, respectively, and is used to receive the power control signal and, in response to the power control signal, transmit the power supply voltage to the control signal generation module.

3. The row address decoding circuit according to claim 2, characterized in that, The power control signal generation unit includes: The OR gate receives the running pulse signal at its first input terminal, receives the address control signal at its second input terminal, and outputs the power control signal.

4. The row address decoding circuit according to claim 1, characterized in that, The control signal generation module includes a decoding module; the address control signal includes a row address decoding signal. The decoding module is configured to receive at least one address pre-decoding signal and generate a row address decoding signal based on the address pre-decoding signal.

5. The row address decoding circuit according to claim 4, characterized in that, The control signal generation module further includes other control signal generation modules; the address control signal further includes other control signals; The other control signal generation module is used to receive at least one of the address pre-decoding signals and generate the other control signals based on the address pre-decoding signals.

6. A row address decoding circuit, characterized in that, The row address decoding circuit includes N memory address control circuits, where N is greater than or equal to 1; each memory address control circuit includes: A control signal generation module is configured to receive at least one address pre-decoding signal and generate an address control signal based on the address pre-decoding signal; the control signal generation module includes a low threshold voltage transistor, and the row address decoding circuit further includes: The operation pulse generation module is used to receive the initial operation signal and generate an operation pulse signal based on the initial operation signal.

7. The row address decoding circuit according to claim 6, characterized in that, The initial running signal is the activation command signal.

8. The row address decoding circuit according to claim 6, characterized in that, The operating pulse generation module includes: An inverter, the input of which receives the initial operating signal; A time delay unit, the input of which is connected to the output of the inverter; The AND gate receives the initial running signal at its first input terminal and is connected to the output terminal of the delay unit at its second input terminal. The AND gate outputs the running pulse signal.

9. A memory, characterized in that, The memory includes the row address decoding circuitry as described in any one of claims 1 to 8.

10. The memory according to claim 9, characterized in that, The memory further includes: at least one storage bank; At least one of the memory cells is disposed on at least one of the two opposite sides of the row address decoding circuit along a first direction.

11. The memory according to claim 10, characterized in that, Each of the memory banks includes N memory segments; the row address decoding circuit includes N memory address control circuits; Each of the N storage segments receives an address control signal output by one of the N storage address control circuits.

12. The memory according to claim 9, characterized in that, The memory also includes: The pre-decoding module is used to receive an initial running signal and a row address encoding signal, and pre-decode the row address encoding signal according to the initial running signal to obtain at least one address pre-decoding signal.

13. The memory according to claim 12, characterized in that, The pre-decoding module includes: combinational logic circuit, row fuse matching circuit, and row address pre-decoding circuit; The combinational logic circuit is used to receive an initial running signal and an initial address signal, and generate a pre-decoding drive signal corresponding to the initial address signal; The row fuse matching circuit is used to receive the initial address signal, match and replace the fuse address of the initial address signal, and then transmit the matched and replaced address signal to the row address pre-decoding circuit. The row address pre-decoding circuit is connected to the combinational logic circuit and the row fuse matching circuit, respectively, and is used to receive the pre-decoding drive signal and the matched and replaced address signal, pre-decode the address signal, and generate the address pre-decoding signal.

14. The memory according to claim 9, characterized in that, The memory is a dynamic random access memory (DRAM).

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