A self-aligned double patterning method, semiconductor device and electronic equipment

Abstract

The application discloses a self-alignment double patterning method, a semiconductor device and electronic equipment, and relates to the technical field of semiconductors. The method simplifies the steps of the existing SADP process and reduces the process cost. The self-alignment double patterning method comprises the following steps: sequentially forming a hard mask layer and an electron beam negative resist layer on a substrate. The electron beam negative resist layer is exposed and developed by an electron beam to form a plurality of sacrificial shafts on the electron beam negative resist layer. A photoresist layer is formed on the outer periphery of the plurality of sacrificial shafts. The photoresist layer is subjected to gray-scale lithography processing based on a preset mask to form a plurality of corresponding target sacrificial wall structures on the sidewalls of each sacrificial shaft. The hard mask layer is etched based on the plurality of target sacrificial wall structures to form a target pattern on the hard mask layer. The semiconductor device comprises at least one patterned structure, and the patterned structure is formed by the self-alignment double patterning method.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a method for self-aligned dual patterning, semiconductor devices, and electronic devices. Background Technology

[0002] In semiconductor device manufacturing, double patterning, also known as double exposure or two-time exposure, works by dividing the data of the same pattern layer into two separate images or two separate photomasks.

[0003] With the development of integrated circuit manufacturing technology, photolithography technology faces enormous challenges, and the requirements for layout design are becoming more stringent. For example, to ensure the quality of pattern transfer, design rules tend to arrange lines of the same layer in one direction. Nevertheless, when the pitch of lines arranged in the same direction approaches 80nm, it reaches the limit of a single exposure in a 193nm immersion lithography machine; if the pitch is less than 80nm, dual or multiple patterning techniques must be adopted before more advanced lithography machines can be used for mass production.

[0004] Currently, in the traditional Self-Aligned Double Patterning (SADP) process, reactive ion etching is required to etch back the deposited spacer material, making the double patterning process quite cumbersome. Summary of the Invention

[0005] The purpose of this invention is to provide a self-aligned dual patterning method, semiconductor device, and electronic device to simplify the steps of existing SADP processes and reduce process costs.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] In a first aspect, the present invention provides a method for self-aligned dual-graphics, comprising:

[0008] A hard mask layer and an electron beam negative adhesive layer are sequentially formed on the substrate.

[0009] Multiple sacrificial mandrels are formed on the electron beam negative resist layer by exposure and development using an electron beam.

[0010] A photoresist layer is formed on the outer periphery of multiple sacrificial mandrels.

[0011] Grayscale photolithography is performed on the photoresist layer based on a preset mask to form multiple corresponding target sacrificial wall structures on the sidewall of each sacrificial mandrel.

[0012] The hard mask layer is etched based on a multi-target sacrificial wall structure to form target patterns on the hard mask layer.

[0013] Compared with existing technologies, the self-aligned dual patterning method provided by this invention utilizes the characteristic that electron beam negative resist transforms into a silicon oxide-like substance in the electron beam exposure area. Electron beam negative resist can be used to replace the CVD material in existing technologies as the photoresist layer, allowing multiple sacrificial mandrels to be formed on the electron beam negative resist layer during electron beam lithography. After forming a photoresist layer around the periphery of the multiple sacrificial mandrels, grayscale lithography can be performed on the photoresist layer using a preset mask. This etches away the photoresist layer at the top of each sacrificial mandrel and the excess photoresist layer between the sidewalls of every two sacrificial mandrels, forming multiple corresponding target sacrificial wall structures on the sidewalls of each sacrificial mandrel. Finally, based on the multiple formed target sacrificial wall structures, the hard mask layer is etched to form the target pattern on the hard mask layer. Therefore, since this invention eliminates the need for reactive ion etching (RIE) to re-etch the photoresist layer, it achieves the formation of the target sacrificial wall structure, simplifying the steps of existing SADP processes and reducing process costs to a certain extent. Meanwhile, since the reactive ion etching step is eliminated, the self-aligned dual patterning method provided in this embodiment of the invention can be completed entirely within photolithography, which can also improve the efficiency of self-aligned dual patterning.

[0014] In one possible implementation, the preset mask includes a first region having a first transmittance and a second region having a second transmittance, wherein the first transmittance is less than the second transmittance.

[0015] Grayscale photolithography is performed on the photoresist layer based on a pre-set mask to form multiple corresponding target sacrificial wall structures on the sidewalls of each sacrificial mandrel, including:

[0016] Grayscale photolithography is performed on the photoresist layer within the orthographic projection of the first region based on the first transmittance, and grayscale photolithography is performed on the photoresist layer within the orthographic projection of the second region based on the second transmittance, forming multiple corresponding target sacrificial wall structures on the sidewall of each sacrificial mandrel.

[0017] In one possible implementation, before etching the hard mask layer based on the target sacrificial wall structure to form the target pattern on the hard mask layer, the method further includes removing the sacrificial mandrel.

[0018] In one possible implementation, forming a photoresist layer on the outer periphery of a plurality of sacrificial mandrels includes: applying photoresist to the outer periphery of the plurality of sacrificial mandrels to form a photoresist layer.

[0019] In one possible implementation, the first transmittance is 50%, and the second transmittance is 100%.

[0020] In one possible implementation, the material of the electron beam negative adhesive layer includes a hydrogen silsesquioxane polymer.

[0021] In one possible implementation, the thickness of the electron beam negative adhesive layer ranges from 80 nm to 120 nm.

[0022] In one possible implementation, the material of the hard mask layer includes any one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, tantalum nitride, or titanium nitride.

[0023] In a second aspect, the present invention also provides a semiconductor device comprising at least one patterned structure, the patterned structure being fabricated using a self-aligned dual patterning method described in the first aspect or any possible implementation thereof.

[0024] Compared with the prior art, the beneficial effects of the semiconductor device provided by the present invention are the same as those of the self-aligned dual patterning method described in the above technical solutions, and will not be repeated here.

[0025] Thirdly, the present invention also provides an electronic device comprising the semiconductor device described in the second aspect.

[0026] Compared with the prior art, the beneficial effects of the electronic device provided by the present invention are the same as those of the self-aligned dual patterning method described in the above technical solutions, and will not be repeated here. Attached Figure Description

[0027] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0028] Figures 1(a) to 1(f) Existing technology features self-aligned dual-graphic process flow diagrams.

[0029] Figure 2 A flowchart of a self-aligned dual graphical method provided in an embodiment of the present invention;

[0030] Figure 3 A flowchart illustrating another self-aligned dual graphical method provided in this embodiment of the invention;

[0031] Figures 4-8 This is a process flow diagram using the self-aligned dual-graphics method provided in the embodiments of the present invention.

[0032] Figure label:

[0033] 11-Substrate, 12-Existing hard mask layer,

[0034] 13-Sacrificial material layer, 14-Bottom anti-reflective coating,

[0035] 15 - Existing photoresist layer; 16 - Isolation material;

[0036] 21 - Substrate, 22 - Hard mask layer

[0037] 231 - Sacrificial mandrel, 24 - Photoresist layer,

[0038] 241 - Target sacrificial wall structure; 25 - Preset mask.

[0039] 251 - First area, 252 - Second area. Detailed Implementation

[0040] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0041] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0042] In this invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0043] Self-aligned Double Patterning (SADP) refers to the spatial frequency multiplication of a photolithographic pattern by using non-photolithography processes (thin film deposition, etching, etc.) after a single photolithography step.

[0044] Figures 1(a) to 1(f) An example of an existing SADP process flow is shown. As shown in Figure 1(a), a sacrificial material layer 13 is deposited on an existing hard mask layer 12 on the surface of substrate 11. This sacrificial material is typically a chemical vapor deposition (CVD) material, i.e., a ceramic or polymer is deposited. A bottom anti-reflective coating 14 and an existing photoresist layer 15 are formed on the sacrificial material layer 13. As shown in Figure 1(b), the sacrificial material layer 13 is photolithographically etched based on the mask formed by the photoresist, transferring the pattern on the mask to the sacrificial material layer 13. The pattern on the sacrificial material layer 13 is also called the "sacrificial mandrel" or "core". As shown in Figure 1(c), an atomic layer deposition (ALD) technique is used to deposit a relatively uniform thin film (called the "spacer") on the surface and sides of the "mandrel". As shown in Figure 1(d), a portion of the deposited isolation material 16 is etched away using reactive ion etching, a step known as "etch back". Due to the geometric effect of the "mandrel" sidewalls, material deposited on both sides of the pattern remains, forming what is called a "spacer". As shown in Figure 1(e), a highly selective etchant is used to remove the "mandrel", leaving only the "spacer" on the surface of the substrate 11. Since the period of the "spacer" pattern is half that of the photolithographic pattern, the spatial pattern density is doubled. Finally, as shown in Figure 1(f), plasma etching is used to transfer the "spacer" pattern onto the existing hard mask layer 12 in the substrate 11.

[0045] In the existing SADP process, reactive ion etching is also required to etch back the deposited spacer material, which makes the dual patterning process more complicated.

[0046] In view of this, such as Figure 2 As shown, this embodiment of the invention provides a self-aligned dual-graphics method, comprising:

[0047] Step 101: A hard mask layer 22 and an electron beam negative adhesive layer are sequentially formed on the substrate 21.

[0048] In this application, the specific structure of the substrate 21 can be set according to the actual application scenario, and is not specifically limited here. Specifically, the substrate 21 can be a silicon substrate, indium phosphide (InP) substrate, gallium arsenide (GaAs) substrate, germanium substrate, germanium silicon substrate, germanium substrate, silicon-on-insulator (SOI) substrate, or germanium-on-insulator (GOI) substrate, etc., where no structure is formed on it, or it can be a substrate 21 with some structure formed on it. For example, the substrate 21 mentioned above can be a common silicon substrate.

[0049] After the substrate 21 is formed, a hard mask layer 22 is formed on the surface of the substrate 21. The material of the hard mask layer 22 includes any one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, tantalum nitride, or titanium nitride. For example, the hard mask layer 22 can be silicon oxide.

[0050] After forming the hard mask layer 22, an electron beam negative resist layer is formed on the surface of the hard mask layer 22 by spin coating. The material of the electron beam negative resist layer includes hydrogen silsesquioxane polymers (HSQ), and the thickness of the electron beam negative resist layer ranges from 80 nm to 120 nm. For example, the thickness of the electron beam negative resist layer can be 80 nm, 82 nm, 85 nm, 90 nm, 100 nm, or 120 nm, and this embodiment of the invention does not specifically limit this. It is understood that when the thickness of the electron beam negative resist layer is less than 80 nm, the electron beam negative resist layer cannot act as a barrier layer for pattern transfer due to its thinness, and the formed pattern cannot be transferred to the hard mask layer 22. At the same time, when the electron beam negative resist layer is thicker, it will also increase the etching difficulty. Therefore, selecting an electron beam negative resist layer of appropriate thickness can not only reduce the etching difficulty in the subsequent exposure and development process, but also enable the electron beam negative resist layer to act as a barrier layer for pattern transfer.

[0051] Step 102: Expose and develop the electron beam negative resist layer with an electron beam to form multiple sacrificial mandrels 231 on the electron beam negative resist layer.

[0052] It should be understood that when HSQ negative adhesive is used as the material for the electron beam negative adhesive layer, based on the properties of HSQ negative adhesive, the area exposed by the electron beam can form a silicon oxide-like substance, thereby forming multiple sacrificial mandrels 231. In practice, the size of each sacrificial mandrel 231 can be the same or different, and can be set according to the pattern to be etched. This embodiment of the invention does not specifically limit this.

[0053] Step 103: Form a photoresist layer 24 on the outer periphery of the plurality of sacrificial mandrels 231.

[0054] In this application, photoresist can be applied to the outer periphery of each sacrificial mandrel 231 to form a photoresist layer 24 on the hard mask layer 22.

[0055] Step 104: Perform grayscale photolithography on the photoresist layer 24 based on the preset mask 25 to form multiple corresponding target sacrificial wall structures 241 on the sidewall of each sacrificial mandrel 231.

[0056] In this application, the preset mask 25 includes a first region 251 with a first transmittance and a second region 252 with a second transmittance, wherein the first transmittance is less than the second transmittance. For example, the first transmittance can be 50% and the second transmittance can be 100%. Since the transmittance of different regions is different, when grayscale photolithography is performed on the photoresist layer 24 based on the preset mask, the photolithography etching speed of the photoresist layer 24 is also different. Based on this, by setting the transmittance of different regions, the photoresist layer 24 can be etched into the required pattern, thereby forming multiple corresponding target sacrificial wall structures 241 on the sidewall of each sacrificial core 231. This eliminates the need for the reactive ion etching process to etch back the deposited spacer material in the prior art, further simplifying the steps of the existing SADP process.

[0057] Step 105: Based on the multiple target sacrificial wall structures 241, the hard mask layer 22 is etched to form the target pattern on the hard mask layer 22.

[0058] In this application, the hard mask layer 22 is etched based on multiple formed target sacrificial wall structures 241 to form a target pattern on the hard mask layer 22. It is understood that since each sacrificial mandrel 231 has two sidewalls, the number of formed target sacrificial wall structures 241 should be twice the number of sacrificial mandrels 231. When the hard mask layer 22 is etched based on the target sacrificial wall structures 241, the resulting target pattern, compared to the sacrificial mandrels 231, effectively doubles the spatial pattern density.

[0059] In summary, the self-aligned dual patterning method provided by this invention utilizes the characteristic that electron beam negative resist becomes a silicon oxide-like material in the electron beam exposure area. Electron beam negative resist can be used to replace the CVD material in the prior art as the photoresist layer 24, allowing the formation of multiple sacrificial mandrels 231 on the electron beam negative resist layer during electron beam lithography. After forming the photoresist layer 24 around the multiple sacrificial mandrels 231, grayscale lithography can be performed on the photoresist layer 24 using a preset mask 25. This etches away the photoresist layer 24 at the top of each sacrificial mandrel 231 and the excess photoresist layer 24 between the sidewalls of every two sacrificial mandrels 231, forming multiple corresponding target sacrificial wall structures 241 on the sidewalls of each sacrificial mandrel 231. Finally, based on the multiple formed target sacrificial wall structures 241, the hard mask layer 22 is etched to form the target pattern on the hard mask layer 22. Therefore, since the embodiments of the present invention do not require the photoresist layer 24 to be etched back using reactive ion etching, the purpose of forming the target sacrificial wall structure 241 is achieved, which can simplify the steps of the existing SADP process to a certain extent and reduce the process cost. At the same time, since the reactive ion etching step is eliminated, the self-aligned dual patterning method provided by the embodiments of the present invention can be completed entirely within photolithography, which can also improve the efficiency of self-aligned dual patterning.

[0060] Figure 3 Another method for self-aligned dual graphing is illustrated, including:

[0061] Step 201: A hard mask layer 22 and an electron beam negative adhesive layer are sequentially formed on the substrate 21.

[0062] The specific structure of the substrate 21 can be referred to the previous text and will not be repeated here. The material of the hard mask layer 22 includes any one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, tantalum nitride, or titanium nitride. For example, the hard mask layer 22 can be silicon oxide.

[0063] After forming the hard mask layer 22, an electron beam negative resist layer is formed on the surface of the hard mask layer 22 by spin coating. The material of the electron beam negative resist layer includes HSQ, and the thickness of the electron beam negative resist layer ranges from 80nm to 120nm. For example, the thickness of the electron beam negative resist layer can be 80nm, 82nm, 85nm, 90nm, 100nm, or 120nm, and this embodiment of the invention does not specifically limit this. It is understood that when the thickness of the electron beam negative resist layer is less than 80nm, the electron beam negative resist layer cannot act as a barrier layer for pattern transfer due to its thinness, and the formed pattern cannot be transferred to the hard mask layer 22. At the same time, when the electron beam negative resist layer is thicker, it will also increase the etching difficulty. Therefore, selecting an electron beam negative resist layer of appropriate thickness can not only reduce the etching difficulty in the subsequent exposure and development process, but also enable the electron beam negative resist layer to act as a barrier layer for pattern transfer.

[0064] Step 202: As Figure 4 As shown, the electron beam negative resist layer is exposed and developed by an electron beam to form multiple sacrificial mandrels 231 on the electron beam negative resist layer.

[0065] It should be understood that when HSQ negative adhesive is used as the material for the electron beam negative adhesive layer, based on the properties of HSQ negative adhesive, the area exposed by the electron beam can form a silicon oxide-like substance, thereby forming multiple sacrificial mandrels 231. In practice, the size of each sacrificial mandrel 231 can be the same or different, and can be set according to the pattern to be etched. This embodiment of the invention does not specifically limit this.

[0066] Step 203: As Figure 5 As shown, photoresist is coated on the outer periphery of multiple sacrificial mandrels 231 to form a photoresist layer 24.

[0067] In this application, ordinary photoresist can be used as the photoresist layer 24, and the photoresist layer 24 is formed on the outer periphery of each sacrificial mandrel 231 by spin coating. Thin film growth is not required, and all self-aligned dual patterning process steps can be completed inside the photolithography process, which can improve the efficiency of self-aligned dual patterning to a certain extent.

[0068] Step 204: As Figure 6 As shown, grayscale photolithography is performed on the photoresist layer 24 in the orthographic projection of the first region 251 based on the first transmittance, and grayscale photolithography is performed on the photoresist layer 24 in the orthographic projection of the second region 252 based on the second transmittance, forming multiple corresponding target sacrificial wall structures 241 on the sidewall of each sacrificial mandrel 231.

[0069] In this application, the preset mask 25 includes a first region 251 with a first transmittance and a second region 252 with a second transmittance, wherein the first transmittance is less than the second transmittance. For example, the first transmittance is 50% and the second transmittance is 100%. Based on this, the etching rate and the degree of etching of the photoresist layer 24 in the orthographic projection of the first region 251 are much less than those in the orthographic projection of the second region 252. Therefore, only a portion of the photoresist layer 24 in the orthographic projection of the first region 251 is etched away, while the photoresist layer 24 in the orthographic projection of the second region 252 is completely etched away. This etches the photoresist layer 24 into the required pattern to form multiple corresponding target sacrificial wall structures 241 on the sidewall of each sacrificial mandrel 231. This eliminates the need for the reactive ion etching process to etch back the deposited spacer material in the prior art, further simplifying the steps of the existing SADP process.

[0070] Step 205: As Figure 7 As shown, the sacrificial mandrel 231 is removed.

[0071] In practice, a highly selective etchant can be used to etch away the sacrificial mandrel 231, or other methods can be used to remove the sacrificial mandrel 231. This embodiment of the invention does not specifically limit the method used.

[0072] Step 206: As Figure 8 As shown, the hard mask layer 22 is etched based on multiple target sacrificial wall structures 241 to form target patterns on the hard mask layer 22.

[0073] In this application, the hard mask layer 22 is etched based on multiple formed target sacrificial wall structures 241 to form a target pattern on the hard mask layer 22. It is understood that since each sacrificial mandrel 231 has two sidewalls, the number of formed target sacrificial wall structures 241 should be twice the number of sacrificial mandrels 231. When the hard mask layer 22 is etched based on the target sacrificial wall structures 241, the resulting target pattern, compared to the sacrificial mandrels 231, effectively doubles the spatial pattern density.

[0074] This invention also provides a semiconductor device, which includes at least one patterned structure, the patterned structure being fabricated using the self-aligned dual patterning method provided in the above embodiments.

[0075] Compared with the prior art, the beneficial effects of the semiconductor device provided by the embodiments of the present invention are the same as the beneficial effects of the self-aligned dual patterning method described in the above embodiments, and will not be repeated here.

[0076] This invention also provides an electronic device, which includes the semiconductor device described in the above embodiments.

[0077] Compared with the prior art, the beneficial effects of the electronic device provided by the embodiments of the present invention are the same as the beneficial effects of the self-aligned dual patterning method described in the above embodiments, and will not be repeated here.

[0078] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0079] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for self-aligned dual-graphics, characterized in that, include: A hard mask layer and an electron beam negative adhesive layer are sequentially formed on the substrate; The electron beam negative resist layer is exposed and developed by an electron beam to form multiple sacrificial mandrels on the electron beam negative resist layer. A photoresist layer is formed on the outer periphery of the plurality of sacrificial mandrels; The photoresist layer is subjected to grayscale photolithography based on a preset mask to form multiple corresponding target sacrificial wall structures on the sidewall of each sacrificial mandrel. Remove the sacrificial mandrel; The hard mask layer is etched based on multiple target sacrificial wall structures to form target patterns on the hard mask layer.

2. The self-aligned dual-graphics method according to claim 1, characterized in that, The preset mask includes a first region with a first light transmittance and a second region with a second light transmittance, wherein the first light transmittance is less than the second light transmittance; The grayscale photolithography process performed on the photoresist layer based on a preset mask forms multiple corresponding target sacrificial wall structures on the sidewalls of each sacrificial mandrel, including: Based on the first transmittance, grayscale photolithography is performed on the photoresist layer within the orthographic projection of the first region, and simultaneously based on the second transmittance, grayscale photolithography is performed on the photoresist layer within the orthographic projection of the second region, forming multiple corresponding target sacrificial wall structures on the sidewall of each sacrificial mandrel.

3. The self-aligned dual-graphics method according to claim 1, characterized in that, The process of forming a photoresist layer on the outer periphery of the plurality of sacrificial mandrels includes: Photoresist is applied to the outer periphery of the plurality of sacrificial mandrels to form the photoresist layer.

4. The self-aligned dual-graphics method according to claim 2, characterized in that, The first light transmittance is 50%, and the second light transmittance is 100%.

5. The self-aligned dual-graphics method according to claim 1, characterized in that, The electron beam negative adhesive layer is made of a hydrogen silsesquioxane polymer.

6. The self-aligned dual-graphics method according to claim 1, characterized in that, The thickness of the electron beam negative adhesive layer ranges from 80 nm to 120 nm.

7. The self-aligned dual-graphics method according to claim 1, characterized in that, The material of the hard mask layer includes any one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, tantalum nitride, or titanium nitride.

8. A semiconductor device, characterized in that, The semiconductor device includes at least one patterned structure, which is formed using the self-aligned dual patterning method according to any one of claims 1 to 7.

9. An electronic device, characterized in that, The electronic device includes the semiconductor device as described in claim 8.

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