A method of double patterning, semiconductor device and electronic equipment

Abstract

The application discloses a double patterning method, a semiconductor device and electronic equipment, and relates to the technical field of semiconductors. The method is used for simplifying the steps of an existing LELE process and reducing the process cost. The double patterning method comprises the following steps: sequentially forming a pattern transfer layer and an electron beam negative resist layer on a substrate. The electron beam negative resist layer is exposed and developed by an electron beam to form a first pattern on the electron beam negative resist layer. A mask material layer formed on the pattern transfer layer is subjected to a patterning process to form a second pattern on the mask material layer. The pattern transfer layer is etched in combination with the first pattern and the second pattern to form a target pattern on the pattern transfer layer. The semiconductor device comprises at least one patterning structure, and the patterning structure is formed by using the double patterning method.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a dual patterning method, semiconductor device, and electronic device. Background Technology

[0002] In semiconductor device manufacturing, double patterning, also known as double exposure or two-time exposure, works by dividing the data of the same pattern layer into two separate images or two separate photomasks.

[0003] With the development of integrated circuit manufacturing technology, photolithography technology faces enormous challenges, and the requirements for layout design are becoming more stringent. For example, to ensure the quality of pattern transfer, design rules tend to arrange lines of the same layer in one direction. Nevertheless, when the pitch of lines arranged in the same direction approaches 80nm, it reaches the limit of a single exposure in a 193nm immersion lithography machine; if the pitch is less than 80nm, dual or multiple patterning techniques must be adopted before more advanced lithography machines can be used for mass production.

[0004] Currently, in the traditional Litho-Eich-Litho-Etch (LELE) dual patterning process, thin films made of materials such as silicon oxide and silicon nitride are often used as hard mask layers. After the first photolithography, the etched hard mask layer also needs to be cured, making the existing dual patterning process quite complicated. Summary of the Invention

[0005] The purpose of this invention is to provide a dual patterning method, semiconductor device, and electronic device to simplify the steps of the existing LELE process and reduce process costs.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] In a first aspect, the present invention provides a dual-graphics method, comprising:

[0008] A pattern transfer layer and an electron beam negative adhesive layer are sequentially formed on the substrate.

[0009] The electron beam negative photoresist layer is exposed and developed using an electron beam to form the first pattern on the electron beam negative photoresist layer.

[0010] The mask material layer formed on the pattern transfer layer is patterned to form a second pattern on the mask material layer.

[0011] By combining the first and second graphics, the graphics transfer layer is etched to form the target graphics.

[0012] Compared to existing technologies, the dual patterning method provided by this invention utilizes the characteristic that the electron beam negative resist transforms into a silicon oxide-like substance in the electron beam exposure area. After the first pattern etching of the dual patterning is completed using electron beam lithography, the curing step can be omitted, allowing for direct second optical etching to form the second pattern. Simultaneously, forming the first pattern solely through electron beam direct writing on the electron beam negative resist layer not only improves the efficiency of electron beam direct writing to a certain extent but also avoids the problem of electron beam proximity effect preventing the achievement of patterns below 10nm. Furthermore, compared to optical etching, using electron beam etching to etch the first pattern can improve its resolution. Therefore, the dual patterning method provided by this invention not only improves the resolution of the formed first pattern and avoids the problem of electron beam proximity effect preventing the achievement of patterns below 10nm, but also simplifies the steps of existing LELE processes, saving time and process costs in forming dual patterns to a certain extent.

[0013] In one possible implementation, before exposing and developing the electron beam negative photoresist layer with an electron beam to form the first pattern on the electron beam negative photoresist layer, the method further includes:

[0014] The etched pattern is segmented according to its size to determine a first pattern and a second pattern; wherein the size of the first pattern is smaller than the size of the second pattern.

[0015] In one possible implementation, a pattern transfer layer and an electron beam negative adhesive layer are sequentially formed on a substrate, including:

[0016] A pattern transfer layer is formed on the substrate; an electron beam spin coat is then performed on the pattern transfer layer to form an electron beam negative adhesive layer.

[0017] In one possible implementation, the mask material layer formed on the pattern transfer layer is patterned to form a second pattern on the mask material layer, including:

[0018] An anti-reflective coating and a photoresist layer are sequentially formed on the pattern transfer layer;

[0019] The photoresist layer is exposed and developed to form a mask;

[0020] Based on the mask, the anti-reflective coating is etched to form a second pattern on the anti-reflective coating.

[0021] In one possible implementation, the size of the first pattern is less than 40 nm, and the size of the second pattern is greater than or equal to 40 nm.

[0022] In one possible implementation, the material of the electron beam negative adhesive layer includes a hydrogen silsesquioxane polymer.

[0023] In one possible implementation, the thickness of the electron beam negative adhesive layer ranges from 40 nm to 60 nm.

[0024] In one possible implementation, the material of the pattern transfer layer includes any one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, tantalum nitride, or titanium nitride.

[0025] In a second aspect, the present invention also provides a semiconductor device comprising at least one patterned structure, the patterned structure being fabricated using a dual patterning method described in the first aspect or any possible implementation thereof.

[0026] Compared with the prior art, the beneficial effects of the semiconductor device provided by the present invention are the same as those of the dual patterning method described in the above technical solution, and will not be repeated here.

[0027] Thirdly, the present invention also provides an electronic device comprising the semiconductor device described in the second aspect.

[0028] Compared with the prior art, the beneficial effects of the electronic device provided by the present invention are the same as those of the dual-graphics method described in the above technical solutions, and will not be repeated here. Attached Figure Description

[0029] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0030] Figures 1(a) to 1(e) Existing technology features dual graphical process flow diagrams;

[0031] Figure 2 A flowchart of a dual-graphical method provided in an embodiment of the present invention;

[0032] Figure 3 This is a flowchart of another dual-graphical method provided in an embodiment of the present invention;

[0033] Figures 4-7 This is a dual-graphical process flow diagram provided by an embodiment of the present invention.

[0034] Figure label:

[0035] 1-Base layer, 2-Graphics transfer layer

[0036] 3-Electron beam negative adhesive layer, 4-Mask material layer,

[0037] 41-Anti-reflective coating, 42-Photoresist layer,

[0038] 01' - Hard mask layer, 02' - First mask,

[0039] 03' - Second mask template. Detailed Implementation

[0040] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0041] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0042] In this invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0043] The existing LELE dual patterning process requires splitting the pattern into two layers according to a certain algorithm and making masks for each layer separately, so that each layer of pattern can be within the limitations of photolithography capabilities. Figures 1(a) to 1(e)The existing LELE process flow is illustrated in Figure 1(a). First, a first exposure is performed using a first mask. As shown in Figure 1(b), the hard mask layer 01' is etched based on the first mask 02'. As shown in Figure 1(c), a second exposure is performed using a second mask 03'. As shown in Figure 1(d), the photoresist formed during the second exposure and the hard mask layer 01' formed during the first etching are used as a barrier layer for the second etching. As shown in Figure 1(e), the patterns of the first mask 02' and the second mask 03' are simultaneously transferred to the target wafer. In the existing LELE process, because thin films made of materials such as silicon oxide and silicon nitride are used as the hard mask layer 01', a curing process is required after the first photolithography step, making the existing dual-patterning process quite cumbersome.

[0044] In view of this, such as Figure 2 As shown, this embodiment of the invention provides a dual-graphics method, including:

[0045] Step 101: A pattern transfer layer 2 and an electron beam negative adhesive layer 3 are sequentially formed on substrate 1.

[0046] In this application, the specific structure of substrate 1 can be set according to the actual application scenario, and is not specifically limited here. Specifically, substrate 1 can be a silicon substrate, indium phosphide (InP) substrate, gallium arsenide (GaAs) substrate, germanium substrate, germanium silicon substrate, germanium substrate, silicon-on-insulator (SOI) substrate, or germanium-on-insulator (GOI) substrate, etc., where no structure is formed on it, or it can be a substrate 1 with some structure formed on it. For example, the aforementioned substrate 1 can be a common silicon substrate.

[0047] After forming the substrate 1, a pattern transfer layer 2 is formed on the surface of the substrate 1. The material of the pattern transfer layer 2 includes any one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, tantalum nitride, or titanium nitride. For example, the pattern transfer layer 2 can be silicon oxide.

[0048] After forming the pattern transfer layer 2, an electron beam negative resist layer 3 is formed on the surface of the pattern transfer layer 2. The material of the electron beam negative resist layer 3 includes hydrogen silsesquioxane polymers (HSQ), and the thickness of the electron beam negative resist layer 3 ranges from 40 nm to 60 nm. For example, the thickness of the electron beam negative resist layer 3 can be 40 nm, 41 nm, 45 nm, 50 nm, 56 nm, or 60 nm, and this embodiment of the invention does not specifically limit this. It is understood that when the thickness of the electron beam negative resist layer 3 is less than 40 nm, the electron beam negative resist layer 3 is too thin, which will cause it to be unable to act as a barrier layer for pattern transfer, and the formed pattern cannot be transferred to the pattern transfer layer 2. At the same time, when the electron beam negative resist layer 3 is thicker, it will also increase the etching difficulty. Therefore, selecting an electron beam negative resist layer 3 of appropriate thickness can not only reduce the etching difficulty in the subsequent exposure and development process, but also enable the electron beam negative resist layer 3 to act as a barrier layer for pattern transfer.

[0049] Step 102: Expose and develop the electron beam negative photoresist layer 3 with an electron beam to form a first pattern on the electron beam negative photoresist layer 3.

[0050] It should be understood that electron beam lithography is a photolithography technique that uses an electron beam to directly draw or project patterns onto a wafer coated with electron resist. Compared with traditional optical lithography, although electron beam lithography has a higher resolution, when the pattern size reaches below 10nm, electron beam lithography is affected by the electron beam proximity effect, making it difficult to form patterns. In this application, due to the use of a dual patterning technique, the pattern to be etched is divided into a first pattern and a second pattern, which can further expand the pitch of the lines in the pattern to be etched. Based on this, the first pattern is formed by direct electron beam writing on the electron beam negative resist layer 3, which not only improves the efficiency of direct electron beam writing to a certain extent, but also avoids the problem of not being able to achieve patterns below 10nm due to the electron beam proximity effect.

[0051] Furthermore, when HSQ negative adhesive is used as the material for electron beam negative adhesive layer 3, based on the properties of HSQ negative adhesive, the area exposed by electron beam can form a silicon oxide-like substance, which can avoid the influence of the second photolithography. Therefore, after the first etching process using electron beam, no additional curing process is required, and the second photolithography process can be performed directly, which simplifies the steps of the existing dual patterning process and saves process flow and time for forming dual patterns to a certain extent.

[0052] Step 103: The mask material layer 4 formed on the pattern transfer layer 2 is patterned to form a second pattern on the mask material layer 4.

[0053] In this application, the mask material layer 4 includes a photoresist layer 42 and an anti-reflective coating 41. After forming the first pattern on the electron beam negative resist layer 3, the anti-reflective coating 41 and the photoresist layer 42 need to be formed sequentially on the pattern transfer layer 2. The pattern of the photoresist layer 42 is used as a mask to perform optical etching on the anti-reflective coating 41, and finally a second pattern is formed on the anti-reflective coating 41.

[0054] Step 104: Combine the first and second graphics to perform etching on the graphic transfer layer 2 to form the target graphic.

[0055] In this application, a first pattern is formed on the electron beam negative adhesive layer 3, and a second pattern is formed on the mask material layer 4. Based on the formed first and second patterns, the pattern transfer layer 2 is etched to form a target pattern on the pattern transfer layer 2, so as to etch the target pattern onto the target wafer.

[0056] In summary, the dual patterning method provided by this invention utilizes the characteristic that the electron beam negative resist transforms into a silicon oxide-like substance in the electron beam exposure area. After the first pattern etching of the dual patterning is completed using electron beam lithography, the curing step can be omitted, allowing for direct second optical etching to form the second pattern. Simultaneously, forming the first pattern solely through direct electron beam writing on the electron beam negative resist layer 3 not only improves the efficiency of direct electron beam writing to a certain extent but also avoids the problem of electron beam proximity effect preventing the achievement of patterns below 10nm. Furthermore, compared to optical etching, using electron beam etching to etch the first pattern can improve its resolution. Therefore, the dual patterning method provided by this invention not only improves the resolution of the formed first pattern and avoids the problem of electron beam proximity effect preventing the achievement of patterns below 10nm, but also simplifies the steps of existing LELE processes, saving time and process costs in forming dual patterns to a certain extent.

[0057] Figure 3 Another dual-graphics approach is illustrated, including:

[0058] Step 201: A pattern transfer layer 2 and an electron beam negative adhesive layer 3 are sequentially formed on substrate 1.

[0059] Specifically, step 201 includes the following sub-steps:

[0060] Sub-step A1: Form a pattern transfer layer 2 on substrate 1. The specific structure of substrate 1 can be referred to the previous text and will not be repeated here. The material of pattern transfer layer 2 includes any one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, tantalum nitride, or titanium nitride. For example, pattern transfer layer 2 can be silicon oxide.

[0061] Sub-step A2: Electron beam spin coating is performed on the pattern transfer layer 2 to form an electron beam negative adhesive layer 3. After forming the pattern transfer layer 2, an electron beam negative adhesive layer 3 is formed on the surface of the pattern transfer layer 2 by electron beam spin coating. The material of the electron beam negative adhesive layer 3 includes hydrogen silsesquioxane polymers (HSQ), and the thickness of the electron beam negative adhesive layer 3 ranges from 40 nm to 60 nm. For example, the thickness of the electron beam negative adhesive layer 3 can be 40 nm, 41 nm, 45 nm, 50 nm, 56 nm, or 60 nm. This embodiment of the invention does not specifically limit this. It is understood that when the thickness of the electron beam negative adhesive layer 3 is less than 40 nm, due to the very thin thickness of the electron beam negative adhesive layer 3, it will be unable to act as a barrier layer for pattern transfer, and the formed pattern cannot be transferred to the pattern transfer layer 2. Meanwhile, a thicker electron beam negative resist layer 3 will also increase the etching difficulty. Therefore, selecting an electron beam negative resist layer 3 of appropriate thickness can not only reduce the etching difficulty in the subsequent exposure and development process, but also enable the electron beam negative resist layer 3 to act as a barrier layer for pattern transfer.

[0062] Step 202: Perform graphic segmentation on the graphic to be etched according to the graphic size to determine the first graphic and the second graphic; wherein the graphic size of the first graphic is smaller than the graphic size of the second graphic.

[0063] Specifically, the size of the first pattern is less than 40nm, and the size of the second pattern is greater than or equal to 40nm.

[0064] In this application, the pattern to be etched can be segmented according to the pattern size. On the one hand, the line pitch in the pattern can be expanded, which can avoid the problem that the electron beam proximity effect cannot achieve patterns below 10nm. On the other hand, only electron beam direct writing is used to complete the etching process of patterns below 40nm, while patterns above 40nm are all completed by optical etching. This can improve the efficiency of electron beam etching while improving the pattern resolution.

[0065] Step 203: As Figure 4 As shown, the electron beam negative photoresist layer 3 is exposed and developed by an electron beam to form a first pattern on the electron beam negative photoresist layer 3.

[0066] It should be understood that electron beam lithography has higher resolution compared to traditional optical lithography. Furthermore, when HSQ negative resist is used as the material for the electron beam negative resist layer 3, based on the properties of HSQ negative resist, the area exposed by the electron beam can form a silicon oxide-like substance, avoiding the influence of the second lithography step. Therefore, after the first etching process using an electron beam, no additional curing process is required, and the second lithography process can be performed directly. This simplifies the steps of the existing dual patterning process and saves time in the process flow and the time required to form the dual pattern.

[0067] Step 204: The mask material layer 4 formed on the pattern transfer layer 2 is patterned to form a second pattern on the mask material layer 4.

[0068] Specifically, step 204 includes the following sub-steps:

[0069] Sub-step B1: An anti-reflective coating 41 and a photoresist layer 42 are sequentially formed on the pattern transfer layer 2.

[0070] Sub-step B2: such as Figure 5 As shown, the photoresist layer 42 is exposed and developed to form a mask.

[0071] Sub-step B3: such as Figure 6 As shown, based on the mask, the anti-reflective coating 41 is etched to form a second pattern on the anti-reflective coating 41.

[0072] Step 205: As Figure 7 As shown, the first and second graphics are combined to perform etching on the graphics transfer layer 2, forming the target graphic on the graphics transfer layer 2.

[0073] In this application, a first pattern is formed on a hard mask layer, and a second pattern is formed on a second mask material layer 4. Based on the formed first and second patterns, the pattern transfer layer 2 is etched to form a target pattern on the pattern transfer layer 2, so that the target pattern can be etched onto the target wafer.

[0074] This invention also provides a semiconductor device, which includes at least one patterned structure, the patterned structure being fabricated using the dual patterning method provided in the above embodiments.

[0075] Compared with the prior art, the beneficial effects of the semiconductor device provided by the embodiments of the present invention are the same as the beneficial effects of the dual patterning method described in the above embodiments, and will not be repeated here.

[0076] This invention also provides an electronic device, which includes the semiconductor device described in the above embodiments.

[0077] Compared with the prior art, the beneficial effects of the electronic device provided by the embodiments of the present invention are the same as the beneficial effects of the dual graphical method described in the above embodiments, and will not be repeated here.

[0078] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0079] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A dual-graphics method, characterized in that, include: A pattern transfer layer and an electron beam negative adhesive layer are sequentially formed on the substrate; The electron beam negative resist layer is exposed and developed by an electron beam to form a first pattern on the electron beam negative resist layer. The mask material layer formed on the pattern transfer layer is patterned to form a second pattern on the mask material layer; By combining the first pattern and the second pattern, the pattern transfer layer is etched to form the target pattern on the pattern transfer layer; The mask material layer formed on the pattern transfer layer is patterned to form a second pattern on the mask material layer, including: An anti-reflective coating and a photoresist layer are sequentially formed on the pattern transfer layer; The photoresist layer is exposed and developed to form a mask; Based on the mask, the anti-reflective coating is etched to form a second pattern on the anti-reflective coating; The electron beam negative adhesive layer is made of a hydrogen silsesquioxane polymer.

2. The dual-graphics method according to claim 1, characterized in that, Before the electron beam negative resist layer is exposed and developed using an electron beam to form a first pattern on the electron beam negative resist layer, the method further includes: The etched pattern is segmented according to its size to determine the first pattern and the second pattern; wherein the size of the first pattern is smaller than the size of the second pattern.

3. The dual-graphics method according to claim 1, characterized in that, The process of sequentially forming a pattern transfer layer and an electron beam negative adhesive layer on a substrate includes: The pattern transfer layer is formed on the substrate; Electron beam spin coating is performed on the pattern transfer layer to form the electron beam negative adhesive layer.

4. The dual-graphics method according to claim 2, characterized in that, The size of the first pattern is less than 40 nm, and the size of the second pattern is greater than or equal to 40 nm.

5. The dual-graphics method according to claim 1, characterized in that, The thickness of the electron beam negative adhesive layer ranges from 40 nm to 60 nm.

6. The dual-graphics method according to claim 1, characterized in that, The material of the pattern transfer layer includes any one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, tantalum nitride, or titanium nitride.

7. A semiconductor device, characterized in that, The semiconductor device includes at least one patterned structure, which is formed using the dual patterning method according to any one of claims 1 to 6.

8. An electronic device, characterized in that, The electronic device includes the semiconductor device as described in claim 7.

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